A control circuit for a three-level Buck DC converter

Abstract

The present invention provides a control circuit for a three-level Buck DC converter, comprising: a power circuit and a control circuit, the power circuit and the control circuit being used to adjust the phase shift angle and duty cycle of the switch tube drive signal of the three-level Buck DC converter to achieve midpoint potential balance and output voltage regulation; the control circuit comprising a midpoint potential error regulator, a phase shift angle generation circuit, a synchronization pulse generation circuit, an output voltage closed-loop feedback circuit, and a drive signal generation circuit; the midpoint potential error regulator being used to generate a midpoint potential adjustment signal; the phase shift angle generation circuit being used to generate a phase shift angle signal; the synchronization pulse generation circuit being used to generate the leading edge of the synchronization drive signal; the output voltage closed-loop feedback circuit being used to output a voltage adjustment signal; and the drive signal generation circuit being used to implement loop control of the three-level Buck DC converter. Through the power circuit and the control circuit, a converter with high efficiency, high power density, and high reliability is provided.

Description

Technical Field

[0001] The present invention relates to the technical field, and in particular to a control circuit of a three-level Buck DC converter. Background Art

[0002] High efficiency, high power density, and high reliability are the development trends of power electronic converters. Compared to traditional two-level Buck DC converters, three-level Buck DC converters introduce an additional midpoint potential, reducing voltage stress on power devices and the high-frequency AC component of the voltage across the filter inductor. This facilitates converter miniaturization and is therefore gaining increasing popularity.

[0003] However, the asymmetry of circuit parameters will lead to unbalanced midpoint potential and unbalanced voltage across the input voltage divider capacitor, which will increase the voltage stress of power devices and the pulsating component of the filter inductor current. In severe cases, the device will fail due to overvoltage and the converter will be damaged.

[0004] While control methods for three-level Buck DC converters have been studied both domestically and internationally, none can guarantee neutral potential balance under full-load conditions. Furthermore, most control methods are complex to implement and lack the feasibility of conventional analog devices. They are only suitable for digital control, which suffers from drawbacks such as discrete time delay, quantization error, and poor noise immunity.

[0005] Therefore, it is necessary to adopt a new analog control method to balance the midpoint potential. Summary of the Invention

[0006] In view of this, the embodiments of this specification provide a control circuit for a three-level Buck DC converter, so as to achieve phase shift adjustment and duty cycle adjustment of the three-level Buck DC converter through an analog circuit, thereby controlling the midpoint potential balance and output voltage regulation, so that the midpoint potential is half of the input voltage, reducing the switching tube voltage stress and filter inductor current pulsation component of the three-level Buck DC converter, and improving the efficiency, power density and reliability of the converter.

[0007] The embodiments of this specification provide the following technical solutions:

[0008] A control circuit for a three-level Buck DC converter, comprising:

[0009] The power circuit and control circuit are used for power conversion, and the control circuit is used to adjust the phase shift angle and duty cycle of the switch drive signal of the three-level Buck DC converter to achieve midpoint potential balance and output voltage regulation;

[0010] The control circuit includes a midpoint potential error regulator, a phase shift angle generating circuit, a synchronization pulse generating circuit, an output voltage closed-loop feedback circuit and a drive signal generating circuit;

[0011] The midpoint potential error regulator is used to adjust the upper voltage divider capacitor voltage V in1 and the lower divider capacitor voltage V in2 Sampling is performed to generate a midpoint potential adjustment signal V inerr ;

[0012] The phase shift angle generating circuit is used to generate the phase shift angle signal

[0013] The synchronization pulse generation circuit is used to generate the phase-shifted angle signal Generate the first synchronization pulse S ync1 and the second synchronization pulse S ync2 and used for the leading edge of the first synchronous drive signal G1 and the second synchronous drive signal G2;

[0014] The output voltage closed-loop feedback circuit is used to output the voltage regulation signal V oerr ;

[0015] The driving signal generating circuit is used to adjust the signal V according to the midpoint potential inerr , voltage regulation signal V oerr , the first synchronous drive signal G1 and the second synchronous drive signal G2, to realize the loop control of the three-level Buck DC converter.

[0016] Furthermore, the power circuit includes:

[0017] Input voltage source V in , upper input voltage divider capacitor C in1 , lower input voltage divider capacitor C in2 , first switch tube Q1, second switch tube Q2, first switch component, second switch component, output filter inductor L, output filter capacitor C out and the output load resistor R out ; Input voltage source V in The positive terminal is connected to the upper input voltage divider capacitor C in1 The upper end and the drain of the first switch tube Q1, the input voltage source V in The negative terminal is connected to the lower input voltage divider capacitor C in2 The lower end of the switch is connected to the source of the second switch tube Q2, the source of the first switch tube Q1 is connected to the cathode of the first switch component and one end of the output filter inductor L, and the anode of the first switch component is connected to the upper input voltage divider capacitor C in1 The lower end of the input voltage divider capacitor C in2The connection point of the upper end and the cathode of the second switching component, the anode of the second switching component is connected to the drain of the second switching tube Q2, the output filter capacitor C out The first end and the output load resistor R out The second end of the output filter capacitor C out The second end and the output load resistor R out The first end of the phase is connected to the other end of the output filter inductor L.

[0018] Furthermore, in the power circuit, the first switching component is a first diode D1 or a first replacement switching tube, and the second switching component is a second diode D2 or a second replacement switching tube;

[0019] The switch tube driving signal of the first replacement switch tube is complementary to the driving signal of the first switch tube Q1 , and the driving signal of the second replacement switch tube is complementary to the driving signal of the second switch tube Q2 .

[0020] Furthermore, the driving signal generating circuit includes a first PWM controller U1, a second PWM controller U2, a third comparator Comp3 and a fourth comparator Comp4;

[0021] The first synchronization signal S ync1 The first PWM controller U1 is connected to the input end of the first internal oscillator synchronization circuit, and the output end of the first internal oscillator synchronization circuit is connected to the first sawtooth wave signal V saw1 The inverting input terminal of the third comparator Comp3 of the first internal oscillator synchronization circuit is connected to the first modulation signal V mod1 , the output end of the third comparator Comp3 is connected to the first driving signal G1;

[0022] The second synchronization signal S ync2 The input end of the second internal oscillator synchronization circuit is connected to the second PWM controller U2, and the output end of the second internal oscillator synchronization circuit is connected to the second sawtooth wave signal V saw2 The inverting input terminal of the fourth comparator Comp4 of the first internal oscillator synchronization circuit and the non-inverting input terminal of the fourth comparator Comp4 are connected to the second modulation signal V mod2 , the output end of the fourth comparator Comp4 is connected to the second driving signal G2.

[0023] Further, the phase shift angle generating circuit includes a comparator;

[0024] The phase shift angle generation circuit is used to adjust the signal V using the midpoint potential. inerr and sawtooth wave signal V saw Perform delivery and generate phase shift angle signal

[0025] The positive input of the comparator is connected to the output signal V of the midpoint potential error regulator inerr , the negative input of the comparator is connected to the sawtooth wave signal V saw , the output of the comparator is connected to the phase shift angle signal

[0026] Furthermore, the synchronization pulse generating circuit includes:

[0027] A first logic NOT gate NOT1, a second logic NOT gate NOT2, a first logic AND gate AND1, a second logic AND gate AND2, a first delay resistor R and a second delay capacitor C;

[0028] The synchronization pulse generation circuit is used to generate the phase-shifted angle signal Generate the first synchronization pulse S ync1 and the second synchronization pulse S ync2 and the first synchronization pulse S ync1 and the second synchronization pulse S ync2 for the leading edge of the first synchronous drive signal G1 and the second synchronous drive signal G2;

[0029] The input terminal of the first logic NOT gate NOT1 is connected to the phase shift angle signal The output end of the first logic NOT gate NOT1 is connected to one input end of the first logic AND gate AND1, the other input end of the first logic AND gate AND1 is connected to one end of the first delay resistor R and one end of the second delay capacitor C, and the output end of the first logic AND gate AND1 is connected to the first synchronization pulse S ync1 The input end of the second logic NOT gate NOT2 is connected to the connection point of the first delay resistor R and the second delay capacitor C, the output end of the second logic NOT gate NOT2 is connected to one input end of the second logic AND gate AND2, and the other input end of the second logic AND gate AND2 is connected to the phase shift angle signal The output terminal of the second logic AND gate AND2 is connected to the second synchronization pulse S ync2 .

[0030] Furthermore, the midpoint potential error regulator includes: a first operational amplifier OPA1 and a first compensation network;

[0031] The midpoint potential error regulator is used to adjust the upper voltage divider capacitor voltage V in1 and the lower divider capacitor voltage V in2 Sampling and dividing the voltage of the upper voltage divider capacitor V in1 and the lower divider capacitor voltage V in2 The error signal compensation feedback generates the midpoint potential adjustment signal V inerr ;

[0032] The non-inverting input terminal of the first operational amplifier OPA1 is connected to the lower input voltage divider capacitor C in2 The voltage across the terminals V in2 The inverting input of the first operational amplifier OPA1 is connected to the upper input voltage divider capacitor C in1 The voltage across the terminals V in1 and the input of the first compensation network, the output of the first operational amplifier OPA1 is connected to the output of the first compensation network and V inerr Signal.

[0033] Furthermore, the output voltage closed-loop feedback circuit is a single voltage loop error regulator;

[0034] The single voltage loop error adjustment includes a second operational amplifier OPA2 and a second compensation network;

[0035] The non-inverting input terminal of the second operational amplifier OPA2 is connected to the output voltage reference V ref The inverting input terminal of the second operational amplifier OPA2 is connected to the output voltage signal V out The output of the operational amplifier OPA2 is connected to the output of the second compensation network and V oerr Signal.

[0036] Compared with the prior art, the at least one technical solution adopted in the embodiments of this specification can achieve the following beneficial effects:

[0037] The control method of the embodiment of the present invention is simple and feasible, easy to implement in analog circuits, has strong scalability and portability, and can achieve the control purposes of midpoint potential balance and output voltage stabilization, thereby achieving high efficiency, high power density and high reliability of the converter. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0039] Figure 1 This is a power circuit of a control circuit of a three-level Buck DC converter provided by an embodiment of the present invention;

[0040] Figure 2 It is the key waveform when only the duty cycle of the switch tube Q2 is adjusted to perform midpoint potential balance control;

[0041] Figure 3It is the key waveform when midpoint potential balance control is performed by adjusting the phase shift angle;

[0042] Figure 4 It is a control circuit part in a control circuit of a three-level Buck DC converter provided by an embodiment of the present invention;

[0043] Figure 5 is a control circuit portion provided by another embodiment of the present invention;

[0044] Figure 6 yes Figure 5 Schematic diagram of the midpoint potential error regulator of the control circuit;

[0045] Figure 7 yes Figure 5 Schematic diagram of the phase shift angle generating circuit in the control circuit;

[0046] Figure 8 yes Figure 5 A schematic diagram of a synchronous pulse generating circuit in a control circuit;

[0047] Figure 9 yes Figure 5 Schematic diagram of a single voltage loop error regulator in a control circuit;

[0048] Figure 10 yes Figure 5 Schematic diagram of the drive signal generating circuit in the control circuit. DETAILED DESCRIPTION

[0049] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0050] It should be noted that, in the absence of conflict, the embodiments and features of the embodiments in this application can be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0051] The control circuit of the three-level Buck DC converter includes a power circuit and a control circuit.

[0052] like Figure 1 As shown, the power circuit includes: input voltage source V in , upper input voltage divider capacitor C in1 , lower input voltage divider capacitor C in2 , first switch tube Q1, second switch tube Q2, first diode D1, second diode D2, output filter inductor L, output filter capacitor C out and the output load resistor R out .

[0053] Input voltage source V in The positive terminal is connected to the upper input voltage divider capacitor C in1The upper end and the drain of the first switch tube Q1, the input voltage source V in The negative terminal is connected to the lower input voltage divider capacitor C in2 The lower end of the switch tube Q1 is connected to the source of the second switch tube Q2, the source of the first switch tube Q1 is connected to the cathode of the first diode D1 and one end of the output filter inductor L, and the anode of the first diode D1 is connected to the input voltage source V in The positive terminal is connected to the upper input voltage divider capacitor C in1 The lower end of the lower input voltage divider capacitor C in2 The upper end of the second diode D2 and the cathode of the second diode D2, the anode of the second diode D2 is connected to the drain of the second switch tube Q2, the output filter capacitor C out and the output load resistor R out The lower end of the output filter capacitor C out and the output load resistor R out The upper end of the phase is connected to the other end of the output filter inductor L.

[0054] Upper input voltage divider capacitor C in1 and the lower input voltage divider capacitor C in2 Connect the upper input voltage divider capacitor C in1 and the lower input voltage divider capacitor C in2 The phase connection point is the midpoint, and the upper input voltage divider capacitor C in1 The voltage across the terminals is V in1 , the lower input voltage divider capacitor C in2 The voltage across the terminals is V in2 , output filter capacitor C out and the output load resistor R out The voltage across the terminals is the output voltage V out .

[0055] In other embodiments, the first diode D1 and the second diode D2 can also be replaced by switching tubes, and the switching tube driving signal of the first diode D1 is complementary to the driving signal of the first switching tube Q1, and the switching tube driving signal of the second diode D2 is complementary to the driving signal of the second switching tube Q2, and the analog control method proposed in the present invention is also applicable.

[0056] The general control method of the three-level Buck DC converter is to stagger the driving signals of the first switch Q1 and the second switch Q2 by 180 degrees and have the same duty cycle. In actual operation, due to the asymmetry of the parasitic parameters of the power circuit and the control circuit, the upper input voltage divider capacitor C in1 Voltage across both ends V in1 and the lower input voltage divider capacitor C in2 Voltage across both ends V in2If the voltages are different, the midpoint potential is unbalanced. In this case, the midpoint potential balance can be controlled by adjusting the duty cycle of the first switch Q1 and the second switch Q2. The duty cycles of the first and second switches Q1 and Q2 can be adjusted simultaneously, or individually.

[0057] PWM (Pulse Width Modulation) pulse width modulation methods include leading edge pulse width modulation, trailing edge pulse width modulation and dual edge pulse width modulation. Generally, analog PWM controllers use trailing edge pulse width modulation to generate drive signals. To meet the universality of the control method, the analog control method in the present invention also uses trailing edge pulse width modulation to generate drive signals. The following takes the example of adjusting the duty cycle of the second switch Q2 to illustrate the principle and defects of adjusting the duty cycle to achieve midpoint potential balance control. The waveform of the key signal is Figure 2 Given in.

[0058] Figure 2 Where G1 and G2 are the driving signals of the first switch tube Q1 and the second switch tube Q2 respectively. L is the inductor current. Assume that the upper input voltage divider capacitor C in1 Voltage across both ends V in1 Lower than the input voltage divider capacitor C in2 Voltage across both ends V in2 At this time, the duty cycle of the second switch tube Q2 should be increased to perform additional discharge on the second switch tube Q2, that is, the conduction time of the second switch tube Q2 is t on ( Figure 2 To simplify the calculation process, the voltage across the input voltage divider capacitor is assumed to be And Δt is much smaller than t on It can be calculated that in the current cycle, due to the increase in the conduction time of the second switch tube Q2, the lower input voltage divider capacitor C in2 The amount of charge that changes is:

[0059] In formula 1, I vally is the valley value of the inductor current.

[0060] Since the driving signal is generated by trailing-edge pulse width modulation, the conduction time of the second switch tube Q2 increases, while the turn-on time of the first switch tube Q1 remains unchanged, resulting in a reduction in the demagnetization time of the filter inductor L. Therefore, when the first switch tube Q1 is turned on, the inductor current value increases. The conduction time of the first switch tube Q1 in the current cycle remains unchanged, so the upper input voltage divider capacitor C in1 The change in charge can be calculated as:

[0061]

[0062] By subtracting Equation 1 from Equation 2, we can obtain the charge difference between the upper and lower voltage divider capacitors within one cycle:

[0063]

[0064] From formula 3, we can see that when When ΔQ>0, the duty cycle of the switch tube Q2 is increased, and the input voltage divider capacitor C is lowered. in2 than the input voltage divider capacitor C i n1 discharges more, the lower input voltage divider capacitor C in2 The voltage at both ends will drop, and the midpoint potential balance can be achieved.

[0065] when When ΔQ≤0, it means that even if the duty cycle of the second switch tube Q2 is increased, the voltage across the lower voltage-dividing capacitor cannot be reduced, that is, the midpoint potential balance cannot be achieved.

[0066] It should be noted that the analysis method and conclusion are also applicable to two duty cycle adjustment methods: adjusting only the duty cycle of the first switch Q1 or adjusting the duty cycle of the first switch Q1 and the first switch Q2 simultaneously.

[0067] Therefore, the present invention introduces an additional control variable, namely the driving leading edge phase shift angle of the switch tube Q1 and the switch tube Q2, on the basis of duty cycle regulation to achieve midpoint potential balance in the full load range.

[0068] The following describes the regulation effect of phase shift control on the midpoint potential balance. The waveform of the key signal is Figure 3 Given in.

[0069] Figure 3 Middle D φ To reflect the duty cycle of the control signal of the phase shift angle, D φ The relationship between φ and the phase shift angle is:

[0070]

[0071] φ1 and φ2 are driving leading edge phase shift angles of the first switching tube Q1 and the second switching tube Q2 before and after phase shift adjustment, respectively.

[0072] When phase shift control is used, assuming that the leading edge of the first switch tube Q1 is fixed, the phase shift angle can be adjusted by adjusting the leading edge of the second switch tube Q2. in1 Voltage across both ends V in1 Lower than the input voltage divider capacitor C in2 Voltage across both ends V in2 At this time, it is necessary to reduce the phase shift angle φ of the first switch tube Q1 and the second switch tube Q2.

[0073] Lower input voltage divider capacitor C before phase shift in2The amount of charge discharged in the current cycle is:

[0074]

[0075] After phase shift, the lower input voltage divider capacitor C in2 The amount of charge discharged in the current cycle is:

[0076]

[0077] The difference between Equation 6 and Equation 5 can be obtained before and after adjusting the phase shift angle, and the lower input voltage divider capacitor C in2 The charge change in one cycle is:

[0078]

[0079] The charge change is always greater than 0, that is, under the full load range, the midpoint potential balance control can be achieved by adjusting the phase shift angle.

[0080] It should be noted that the mechanisms of duty cycle adjustment and phase shift angle adjustment in the present invention are explained based on the assumption that the three-level Buck DC converter is in continuous conduction mode and the switch tube driving duty cycle is less than 50%. When the three-level Buck DC converter is in discontinuous conduction mode or the duty cycle is greater than 50%, the above analysis conclusions can also be obtained, and the three-level Buck DC converter and analog control method proposed in the present invention are also effective.

[0081] Adjusting the phase shift angle will increase the inductor current pulsation, increase circuit loss and output voltage ripple. Therefore, the control part of the present invention adopts a combination of phase shift and duty cycle adjustment to achieve midpoint potential balance and output voltage stabilization.

[0082] In the first embodiment, the control circuit includes a midpoint potential error regulator, a phase shift angle generating circuit, a synchronization pulse generating circuit, an output voltage closed-loop feedback circuit and a drive signal generating circuit. Figure 4 shown.

[0083] The output voltage closed-loop feedback circuit is used to achieve output voltage regulation control. This feedback control can adopt common closed-loop control methods of power electronic converters, such as single voltage loop control, peak current control, average current control, inductor current damping control, etc. The input signal of the output voltage closed-loop feedback circuit includes but is not limited to the output voltage V out , inductor current i L , output voltage reference V ref The input signal is regulated by the loop to generate the output voltage regulation signal V oerr .

[0084] In the second embodiment, the control circuit includes a midpoint potential error regulator, a phase shift angle generating circuit, a synchronization pulse generating circuit, a single voltage loop error regulator (because the single voltage loop error regulator is a type of output voltage closed-loop feedback circuit, the second embodiment uses a single voltage loop error regulator) and a drive signal generating circuit, such as Figure 5 shown.

[0085] The midpoint potential error regulator is connected to the upper voltage divider capacitor voltage V in1 and the lower divider capacitor voltage V in2 Sampling is performed, and the error signal is compensated and fed back to generate the midpoint potential adjustment signal V inerr .

[0086] like Figure 6 As shown, the midpoint potential error regulator includes: a first operational amplifier OPA1 and a first compensation network;

[0087] The non-inverting input of the second operational amplifier OPA2 is connected to the lower input voltage divider capacitor C in2 Voltage across both ends V in2 The inverting input of the second operational amplifier OPA2 is connected to the output voltage signal V out The output of the operational amplifier OPA2 is connected to the input of the second compensation network and V oerr Signal. The midpoint potential error regulator samples the upper input voltage divider capacitor C in1 Voltage across both ends V in1 and the lower input voltage divider capacitor C in2 Voltage across both ends V in2 , V in1 and V in2 The error is amplified and fed back by the compensation network to generate the midpoint potential error regulator output signal V inerr The compensation network of the regulator can be a classic proportional-integral-differential resistor-capacitor network.

[0088] The phase shift angle generation circuit uses the midpoint potential to adjust the signal V inerr Interchange with the sawtooth wave to obtain the driving signal D that reflects the phase shift angle φ .

[0089] like Figure 7 As shown, the phase shift angle generating circuit includes a comparator;

[0090] The positive input of the comparator is connected to the output signal V of the midpoint potential error regulator inerr , the negative input of the comparator is connected to the sawtooth wave signal V saw , the output of the comparator is connected to the signal

[0091] Vinerr and sawtooth wave V saw After delivery, the driving signal D reflecting the phase shift angle is obtained φ Considering a three-level Buck DC converter, when the driving signals of the first switch Q1 and the second switch Q2 are staggered by 180°, the inductor current i L The AC pulsation component is the smallest. Generally, it is designed to be in a state of midpoint potential balance when the power circuit is in a state of midpoint potential balance. inerr Equal to V saw half of the amplitude, at this time D φ The duty cycle of the first switch tube Q1 and the second switch tube Q2 is 50%, that is, the driving signals of the first switch tube Q1 and the second switch tube Q2 are staggered by 180 degrees.

[0092] D φ It is the input signal of the synchronous pulse generating circuit. In order to ensure that the synchronous pulse generating circuit can work normally, it is also necessary to φ The duty cycle of the signal is limited, otherwise the synchronization signal will be disordered and the driving signals of the first switch tube Q1 and the second switch tube Q2 will not be synchronized.

[0093] The synchronous pulse generating circuit generates the driving signal D φ Take the leading edge and trailing edge to generate the first synchronization pulse S ync1 and the second synchronization pulse S ync2 , used to synchronize the leading edges of the first synchronous drive signal G1 and the second synchronous drive signal G2, thereby achieving phase shift of the drive signal.

[0094] like Figure 8 As shown, the synchronization pulse generating circuit includes:

[0095] A first logic NOT gate NOT1, a second logic NOT gate NOT2, a first logic AND gate AND1, a second logic AND gate AND2, a first delay resistor R and a second delay capacitor C;

[0096] The input terminal of the first logic NOT gate NOT1 is connected to signal, the output end of the first logic NOT gate NOT1 is connected to one input end of the first logic AND gate AND1, the other input end of the first logic AND gate AND1 is connected to one end of the first delay resistor R and one end of the second delay capacitor C, and the output end of the first logic AND gate AND1 is connected to the synchronization pulse S ync1 The input end of the second logic NOT gate NOT2 is connected to the connection point of the first delay resistor R and the second delay capacitor C, the output end of the second logic NOT gate NOT2 is connected to one input end of the second logic AND gate AND2, and the other input end of the second logic AND gate AND2 is connected to signal, the output end of the second logic AND gate AND2 is connected to the second synchronization pulse S ync2 .

[0097] like Figure 9 As shown, the output voltage closed-loop feedback circuit includes a second operational amplifier OPA2 and a second compensation network;

[0098] The non-inverting input terminal of the second operational amplifier OPA2 is connected to the output voltage reference V ref The inverting input of the second operational amplifier OPA2 is connected to the output voltage signal V out The output of the operational amplifier OPA2 is connected to the input of the second compensation network and the output voltage regulation signal V oerr . V out and V ref The error is compensated and fed back to generate the output voltage regulation signal V oerr The compensation network in this circuit can be compensated by using the classic proportional-integral-differential resistor-capacitor network.

[0099] The driving signal generating circuit is based on the output signal V of the midpoint potential error regulator. inerr , the output signal V of the single voltage loop error regulator oerr and the synchronization signal S ync1 、S ync2 Generates a first drive signal G1 and a second drive signal G2 for implementing loop control of a three-level Buck DC converter.

[0100] like Figure 10 As shown, the driving signal generating circuit includes a first PWM controller U1, a second PWM controller U2 and peripheral circuits (a third comparator Comp3 and a fourth comparator Comp4).

[0101] The first synchronization signal S ync1 The first PWM controller 1 is connected to the input end of the first internal oscillator synchronization circuit, and the output end of the first internal oscillator synchronization circuit is connected to the first sawtooth wave signal V saw1 The inverting input terminal of the first comparator Comp3 of the first internal oscillator synchronization circuit is connected to the first modulation signal V mod1 The output terminal of the first comparator Comp3 is connected to the first drive signal G1. The second synchronization signal S ync2 The input end of the second internal oscillator synchronization circuit of the second PWM controller U2 is connected to the output end of the second oscillator synchronization circuit. The output end of the second oscillator synchronization circuit is connected to the second sawtooth wave signal V saw2 The inverting input terminal of the second comparator Comp4 of the first internal oscillator synchronization circuit and the non-inverting input terminal of the second comparator Comp4 are connected to the second modulation signal V mod2The output terminal of the second comparator Comp4 is connected to the second drive signal G2. The first PWM controller U1 is used to generate the first drive signal G1, and the second PWM controller U2 is used to generate the second drive signal G2. The sawtooth wave V saw1 By S ync1 Synchronous triggering generates the sawtooth wave V of the second PWM controller U2 saw2 By S ync2 Synchronous trigger generation, V saw1 and V saw2 The amplitude is the same, V saw1 and V saw2 The phase shift angle is the phase shift angle of the first drive signal G1 and the second drive signal G2, and the corresponding drive signal is obtained after the modulation signal and the sawtooth wave are exchanged.

[0102] The PWM controllers for the first switch tube Q1 and the second switch tube Q2 use S ync1 and S ync2 The controller performs pulse width modulation to generate a first drive signal G1 and a second drive signal G2 to drive the first switch tube Q1 and the second switch tube Q2 respectively, thereby achieving midpoint potential balance control and output voltage stabilization.

[0103] The driving signal generating circuit is based on the output signal V of the midpoint potential error regulator. inerr , the output signal V of the single voltage loop error regulator oerr and the first synchronization signal S ync1 , Second S ync2 Generates a first drive signal G1 and a second drive signal G2 for implementing loop control of a three-level Buck DC converter.

[0104] The modulation signal of the first PWM controller U1 is the first modulation signal V mod1 By the DC bias signal V bias and V oerr The signal superposition is composed of the following expressions:

[0105] V mod1 =k1·V bias +k2·V oerr (Formula 8);

[0106] In formula 8, k1 is V mod1 The superimposed V bias The signal's proportional coefficient k2 is V mod1 The superimposed V oerr The scale factor of the signal.

[0107] In this embodiment, the modulation signal V mod2 By Vinerr signal and V oerr The signal superposition is composed of the following expressions:

[0108] V mod2 =k3·V inerr +k4·V oerr (Formula 9);

[0109] In formula 9, k3 is V mod2 The superimposed V inerr The proportional coefficient of the signal, k4 is V mod2 The superimposed V oerr The signal proportional coefficients, k3 and k4, need to be designed according to the DC operating point of the circuit and the imbalance of the midpoint potential. If the natural voltage balancing characteristics of the circuit are poor, then it is necessary to increase V inerr The signal adjustment ratio ensures the control circuit's ability to adjust the midpoint potential imbalance.

[0110] In order to ensure that the duty cycle of the first drive signal G1 and the second drive signal G2 are the same when the three-level Buck DC converter is in the natural equilibrium state of the midpoint potential, V bias When the midpoint potential is naturally balanced, V inerr The value of , and k1 is equal to k3, k2 is equal to k4.

[0111] Beneficial effects of the embodiments of the present invention:

[0112] A simple analog circuit can achieve midpoint potential balance and output voltage regulation of a three-level Buck DC converter under the full load range, reducing circuit losses and the size of passive filter components, thereby achieving high efficiency, high power density and high reliability of the converter. The control method of the three-level Buck converter is simple and feasible, easy to implement with analog circuits, and has strong scalability and portability. It can also achieve the control purposes of midpoint potential balance and output voltage regulation, thereby achieving high efficiency, high power density and high reliability of the converter.

[0113] The above description is merely a specific embodiment of the present invention and should not be construed as limiting the scope of the invention. Therefore, substitutions of equivalent components, or equivalent changes and modifications made within the scope of patent protection, should still fall within the scope of this patent. Furthermore, the technical features of the present invention may be freely combined with one another, with other technical solutions, and with other technical solutions.

Claims

1. A control circuit for a three-level Buck DC converter, characterized in that: include: A power circuit and a control circuit, wherein the power circuit is used for power conversion, and the control circuit is used to adjust the phase shift angle and duty cycle of the switch tube drive signal of the three-level Buck DC converter to achieve midpoint potential balance and output voltage regulation; The control circuit includes a midpoint potential error regulator, a phase shift angle generating circuit, a synchronization pulse generating circuit, an output voltage closed-loop feedback circuit and a drive signal generating circuit; The midpoint potential error regulator is used to adjust the voltage of the upper voltage divider capacitor V in1 and the lower divider capacitor voltage V in2 Sampling to generate midpoint potential adjustment signal V inerr ; The phase shift angle generating circuit is used to generate a phase shift angle signal D φ ; The phase shift angle generating circuit includes a comparator; The phase shift angle generating circuit is used to adjust the signal using the midpoint potential V inerr and sawtooth signal V saw Perform delivery and generate the phase shift angle signal D φ ; The positive input terminal of the comparator is connected to the output signal of the midpoint potential error regulator V inerr , the negative input of the comparator is connected to the sawtooth wave signal V saw , the output of the comparator is connected to the phase shift angle signal D φ ; The synchronization pulse generating circuit is used to generate the phase shift angle signal D φ Generate the first sync pulse S ync1 and the second sync pulse S ync2 And used for the first synchronous drive signal G 1 and the second synchronous drive signal G 2's leading edge; The output voltage closed-loop feedback circuit is used to output a voltage regulation signal V oerr ; The driving signal generating circuit is used to adjust the signal according to the midpoint potential V inerr , the voltage regulation signal V oerr , the first synchronous driving signal G 1 and the second synchronous drive signal G 2. Implement loop control of three-level Buck DC converter; The driving signal generating circuit includes a first PWM controller U 1. Second PWM controller U 2. The third comparator Comp 3 and the fourth comparator Comp 4; First synchronization signal S ync1 Phase connected to the first PWM controller U 1 is connected to the input end of the first internal oscillator synchronization circuit, and the output end of the first internal oscillator synchronization circuit is connected to the first sawtooth wave signal V saw1 and the third comparator of the first internal oscillator synchronization circuit Comp 3, the inverting input of the third comparator Comp The non-inverting input terminal of 3 is connected to the first modulation signal V mod1 , the third comparator Comp The output terminal of 3 is connected to the first drive signal G 1; Second synchronization signal S ync2 Phase connected to the second PWM controller U 2 is connected to the input end of the second internal oscillator synchronization circuit, and the output end of the second internal oscillator synchronization circuit is connected to the second sawtooth wave signal V saw2 and the fourth comparator of the first internal oscillator synchronization circuit Comp 4, the inverting input terminal of the fourth comparator Comp The non-inverting input terminal of 4 is connected to the second modulation signal V mod2 , the fourth comparator Comp The output terminal of 4 is connected to the second drive signal G 2.

2. The control circuit of the three-level Buck DC converter according to claim 1, characterized in that: The power circuit includes: Input voltage source V in , Upper input voltage divider capacitor C in1 , lower input voltage divider capacitor C in2 , the first switch tube Q 1. Second switch tube Q 2. First switch component, second switch component, output filter inductor L , output filter capacitor C out and output load resistance R out ; The input voltage source V in The positive terminal is connected to the upper input voltage divider capacitor C in1 The upper end and the first switch tube Q 1's drain, the input voltage source V in The negative phase is connected to the lower input voltage divider capacitor C in2 The lower end and the second switch tube Q 2 source, the first switch tube Q The source of 1 is connected to the cathode of the first switching component and the output filter inductor L One end of the first switching element, the anode is connected to the upper input voltage divider capacitor C in1 The lower end of the input voltage divider capacitor C in2 The connection point of the upper end of the second switching element and the cathode of the second switching element, the anode of the second switching element is connected to the second switching tube Q 2 drain, the output filter capacitor C out The first end and the output load resistor R out The second end of the output filter capacitor C out The second end and the output load resistor R out The first end of the phase is connected to the output filter inductor L the other end.

3. The control circuit of the three-level Buck DC converter according to claim 2, characterized in that: In the power circuit, the first switching component is a first diode D 1 or the first replacement switch tube, the second switch component is a second diode D 2 or the second replacement switch tube.

4. The control circuit of the three-level Buck DC converter according to claim 1, characterized in that: The synchronization pulse generating circuit comprises: First logical NOT gate NOT 1. Second logical NOT gate NOT 2. The first logic AND gate AND 1. Second logic AND gate AND 2. The first delay resistor R and the second delay capacitor C ; The synchronization pulse generating circuit is used to generate the phase shift angle signal D φ Generate the first sync pulse S ync1 and the second sync pulse S ync2 and the first sync pulse S ync1 and the second sync pulse S ync2 For the first synchronous driving signal G 1 and the second synchronous drive signal G 2's leading edge; The first logical NOT gate NOT 1 is connected to the phase-shift angle signal D φ , the first logical NOT gate NOT 1 is connected to the output of the first logic AND gate AND 1, one input of the first logic AND gate AND The other input terminal of 1 is connected to the first delay resistor R One end and the second delay capacitor C One end of the first logic AND gate AND The output of phase 1 is connected to the first sync pulse S ync1 , the second logical NOT gate NOT The input terminal of phase 2 is connected to the first delay resistor R and the second delay capacitor C The second logical NOT gate NOT The output of 2 is connected to the second logic AND gate AND 2, one input of the second logic AND gate AND The other input terminal of phase 2 is connected to the phase shift angle signal D φ , the second logic AND gate AND The output of phase 2 is connected to the second sync pulse S ync2 .

5. The control circuit of the three-level Buck DC converter according to claim 1, characterized in that: The midpoint potential error regulator includes: a first operational amplifier OPA 1 and the first compensation network; The midpoint potential error regulator is used to adjust the voltage of the upper voltage divider capacitor V in1 and the lower divider capacitor voltage V in2 Sampling and converting the upper divider capacitor voltage V in1 and the lower divider capacitor voltage V in2 The error signal compensation feedback generates the midpoint potential adjustment signal V inerr ; The first operational amplifier OPA The non-inverting input of 1 is connected to the lower input voltage divider capacitor C in2 The voltage across the V in2 , the first operational amplifier OPA The inverting input of 1 is connected to the upper input voltage divider capacitor C in1 The voltage across the V in1 and the input of the first compensation network, the first operational amplifier OPA 1 output is connected to the output of the first compensation network and V inerr Signal.

6. The control circuit of the three-level Buck DC converter according to claim 1, characterized in that: The output voltage closed-loop feedback circuit is a single voltage loop error regulator; The single voltage loop error regulator includes a second operational amplifier OPA 2 and the second compensation network; The second operational amplifier OPA The non-inverting input of the 2 phase is connected to the output voltage reference V ref , the second operational amplifier OPA The inverting input of 2 is connected to the output voltage signal V out and the input of the second compensation network, the operational amplifier OPA The output terminals of the two phases are connected to the output of the second compensation network and V oerr Signal.

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