Analog-to-digital converter and analog-to-digital conversion method

Abstract

An analog-to-digital converter and analog-to-digital conversion method, the analog-to-digital converter comprising a capacitor array circuit, a comparison circuit, and a logic circuit. The Nth-stage capacitor array unit in the capacitor array circuit comprises a first capacitor, a first switch unit, a second capacitor, and a second switch unit. The active terminal of the first switch unit is selectively connectable to a power supply voltage, a second reference voltage, and a ground terminal, and the second terminal of the first switch unit is coupled to the first terminal of the first capacitor; the active terminal of the second switch unit is selectively connectable to a power supply voltage, a second reference voltage, and a ground terminal; the comparison circuit has a second input terminal inputted with the first reference voltage and an output terminal coupled to the logic circuit; the logic circuit is adapted to convert the output result of the comparison circuit into a corresponding digital signal. The above scheme can improve the accuracy of the analog-to-digital conversion value output by the analog-to-digital converter.

Description

Technical Field

[0001] The present invention relates to the technical field of analog-to-digital conversion, and in particular to an analog-to-digital converter and an analog-to-digital conversion method. Background Art

[0002] Analog to Digital Converter (ADC) is an important component in communication systems that can convert analog signals into digital signals.

[0003] An analog-to-digital converter typically includes a sample-and-hold circuit, a capacitor array circuit, a comparator circuit, and a logic circuit. The capacitor array circuit typically consists of N stages of capacitor array units. Conventional analog-to-digital converters can only output an N+1-bit analog-to-digital conversion value, resulting in low output accuracy. Summary of the Invention

[0004] An object of the present invention is at least to provide an analog-to-digital converter and an analog-to-digital conversion method, which can improve the output accuracy of the analog-to-digital converter.

[0005] In a first aspect, the present invention provides an analog-to-digital converter, adapted to convert an input target voltage into an N+2-bit analog-to-digital conversion value and output it; the analog-to-digital converter comprises: a capacitor array circuit, a comparison circuit, and a logic circuit, wherein the capacitor array circuit comprises N-level capacitor array units; wherein: the i-th level capacitor array unit in the N-level capacitor array unit comprises 2 N-i unit capacitors; the i-th level capacitor array unit is coupled to the output end of the capacitor array circuit; i is a positive integer and 1≤i≤N-1; the N-th level capacitor array unit among the N-level capacitor array units includes a first subunit and a second subunit, wherein: the first subunit includes a first capacitor and a first switch unit, the active end of the first switch unit is selectively connected to a power supply voltage, a second reference voltage and a ground end, and the second end of the first switch unit is coupled to the first end of the first capacitor; the second end of the first capacitor is coupled to the output end of the capacitor array circuit; the second subunit includes a second capacitor and a second switch unit, the active end of the second switch unit is selectively connected to the power supply voltage, the second reference voltage and the ground end, and the second end of the second switch unit is coupled to the first end of the second capacitor; the second end of the second capacitor is coupled to the output end of the capacitor array circuit; the comparison circuit has a second input end inputting the first reference voltage and an output end coupled to the logic circuit; the logic circuit is suitable for converting the output result of the comparison circuit into a corresponding digital signal.

[0006] Optionally, the i-th level capacitor array unit includes a first subunit and a second subunit, the first subunit includes a first capacitor array and a first switch unit, the second subunit includes a second capacitor array and a second switch unit, wherein: the first switch unit has a moving end that can be selectively connected to the power supply voltage and the ground end, and a fixed end that is coupled to the first end of the first capacitor array; the first capacitor array has a second end coupled to the output end of the capacitor array circuit, including 2 N-i-1 The second switch unit has a moving end selectively connected to the power supply voltage and the ground end, and a fixed end coupled to the first end of the second capacitor array; the second end of the second capacitor array is coupled to the output end of the capacitor array circuit, including 2 N-i-1 A unit capacitor.

[0007] Optionally, in the sampling and holding state of the capacitor array circuit, the active end of the first comparison unit of any one level of the N-level capacitor array units is connected to the power supply voltage, and the active end of the second comparison unit of any one level of the N-level capacitor array units is connected to the ground end.

[0008] Optionally, the power supply voltage is twice the first reference voltage.

[0009] Optionally, the second reference voltage is associated with the first reference voltage, that is, the second reference voltage can be determined by the first reference voltage. Specifically, the second reference voltage can be any voltage value within a preset voltage range, where the minimum value of the voltage range is the difference between the first reference voltage and a preset threshold value, and the maximum value of the voltage range is the sum of the first reference voltage and the preset threshold value.

[0010] In a second aspect, the present invention provides an analog-to-digital conversion method, which is suitable for controlling the analog-to-digital converter provided above to perform analog-to-digital conversion on the input target voltage; the method includes: comparing the output voltage of the capacitor array circuit with the first reference voltage for the jth time, and determining the value of the jth bit in the analog-to-digital conversion value based on the jth comparison result; 1≤j≤N; after comparing the output voltage of the capacitor array circuit with the first reference voltage for the Nth time, updating the output voltage of the capacitor array circuit to the first voltage; comparing the first voltage with the first reference voltage, and determining the value of the N+1th bit in the analog-to-digital conversion value based on the comparison result of the first voltage with the first reference voltage, and updating the output voltage of the capacitor array circuit to the second voltage; comparing the second voltage with the first reference voltage, and determining the value of the N+2th bit in the analog-to-digital conversion value based on the comparison result of the second voltage with the first reference voltage.

[0011] Optionally, updating the output voltage of the capacitor array circuit to a first voltage includes: if the output voltage of the capacitor array circuit after the Nth comparison is greater than the first reference voltage, connecting the active end of the first switch unit of the Nth level capacitor array unit to a second reference voltage; if the output voltage of the capacitor array circuit after the Nth comparison is less than the first reference voltage, connecting the active end of the second switch unit of the Nth level capacitor array unit to the second reference voltage.

[0012] Optionally, updating the output voltage of the capacitor array circuit to a second voltage includes: if the output voltage of the capacitor array circuit is greater than the first reference voltage during the Nth comparison, and the first voltage is greater than the first reference voltage, connecting the fixed end of the first switch unit of the N-level capacitor array unit to the second reference voltage; if the output voltage of the capacitor array circuit is greater than the first reference voltage during the Nth comparison, and the first voltage is less than the first reference voltage, connecting the fixed end of the second switch unit of the N-level capacitor array unit to the second reference voltage; if the output voltage of the capacitor array circuit is less than the first reference voltage during the Nth comparison, and the first voltage is greater than the first reference voltage, connecting the fixed end of the second switch unit of the N-level capacitor array unit to the ground; if the output voltage of the capacitor array circuit is less than the first reference voltage during the Nth comparison, and the first voltage is less than the first reference voltage, connecting the fixed end of the first switch unit of the N-level capacitor array unit to the second reference voltage.

[0013] Compared with the prior art, the technical solution provided by the present invention has at least the following beneficial effects:

[0014] By setting a second reference voltage, based on the magnitude relationship between the output voltage of the capacitor array circuit after the Nth comparison and the first reference voltage, it is determined whether the active terminal of the first switch unit / the active terminal of the second switch unit of the Nth level capacitor array unit is connected to the second reference voltage. Furthermore, the output voltage of the capacitor array circuit is updated to the first voltage. Based on the magnitude relationship between the first voltage and the first reference voltage, the active terminal of the first switch unit / the second switch unit connected to the second reference voltage is adjusted, the output voltage of the capacitor array circuit is adjusted from the first voltage to the second voltage, and the value of the N+1th bit in the analog-to-digital conversion value is obtained. Furthermore, by comparing the second voltage with the first reference voltage, the N+2th bit in the analog-to-digital conversion value can be obtained. By using a capacitor array circuit including N levels of capacitor array units, the output of an N+2-bit analog-to-digital conversion value is achieved, thereby improving the accuracy of the analog-to-digital converter. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 1 is a schematic structural diagram of an analog-to-digital converter according to an embodiment of the present invention;

[0016] Figure 2 is a flow chart of an analog-to-digital conversion method in an embodiment of the present invention;

[0017] Figure 3 is a structural schematic diagram of a capacitor array circuit in an embodiment of the present invention;

[0018] Figure 4 FIG. 4 is a schematic diagram of a P portion layout of a capacitor array circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0019] In the prior art, a capacitor array circuit in an analog-to-digital converter may include N stages of capacitor array units, capable of outputting an N+1-bit analog-to-digital conversion value.

[0020] In an embodiment of the present invention, by setting a second reference voltage, based on the magnitude relationship between the output voltage of the capacitor array circuit after the Nth comparison and the first reference voltage, it is determined whether the active terminal of the first switch unit / the active terminal of the second switch unit of the Nth level capacitor array unit is connected to the second reference voltage. Furthermore, the output voltage of the capacitor array circuit is updated to the first voltage. Based on the magnitude relationship between the first voltage and the first reference voltage, the active terminal of the first switch unit / the second switch unit connected to the second reference voltage is adjusted, the output voltage of the capacitor array circuit is adjusted from the first voltage to the second voltage, and the value of the N+1th bit in the analog-to-digital conversion value is obtained. Furthermore, by comparing the second voltage with the first reference voltage, the N+2th bit in the analog-to-digital conversion value can be obtained. By using a capacitor array circuit including N levels of capacitor array units, the output of an N+2-bit analog-to-digital conversion value is achieved, thereby improving the accuracy of the analog-to-digital converter.

[0021] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0022] An embodiment of the present invention provides an analog-to-digital converter suitable for converting an input target voltage into an N+2-bit analog-to-digital conversion value and outputting the converted value.

[0023] In an embodiment of the present invention, the analog-to-digital converter may include a capacitor array circuit, a comparison circuit, and a logic circuit.

[0024] In a specific implementation, the capacitor array circuit may include N levels of capacitor array units. For the i-th level of capacitor array units in the N levels of capacitor array units, it includes 2 N-i The i-th capacitor array unit is coupled to the output terminal of the capacitor array circuit; i is a positive integer and 1≤i≤N-1.

[0025] That is, the first-level capacitor array unit includes 2 N-1Unit capacitors, the second-level capacitor array includes 2 N-2 Unit capacitors, and so on, the N-1th level capacitor array unit includes 2 unit capacitors.

[0026] That is, the equivalent capacitance value of the i-th capacitor array unit is twice the equivalent capacitance value of the (i+1)-th capacitor array unit.

[0027] like Figure 1 As shown in FIG, in the capacitor array circuit, the first-level capacitor array unit is located at the leftmost side of the capacitor array circuit, and the second-level capacitor array unit is adjacent to the first-level capacitor array unit and is located to the right of the first-level capacitor array unit. Similarly, the Nth-level capacitor array unit is located at the rightmost side of the capacitor array circuit.

[0028] The i-th level capacitor array unit may include a first subunit and a second subunit. The first subunit includes a first switch unit and a first capacitor array. The second subunit includes a second switch unit and a second capacitor array.

[0029] Specifically, in the i-th level capacitor array unit, the active end of the first switch unit is selectively connected to the power supply voltage VDD and the ground terminal GND, and the fixed end of the first switch unit is coupled to the first end of the first capacitor array; the first capacitor array includes 2 N-i-1 unit capacitors, and the second end of the first capacitor array is coupled to the output end of the capacitor array circuit;

[0030] The active end of the second switch unit is selectively connected to the power supply voltage VDD and the ground terminal GND, and the fixed end of the second switch unit is coupled to the first end of the second capacitor array; the second capacitor array includes 2 N-i-1 The second end of the second capacitor array is coupled to the output end of the capacitor array circuit. In the i-th capacitor array unit, the total number of capacitors of the first capacitor and the second capacitor array is 2 N-i A unit capacitor.

[0031] For example, if N=11, the first-level capacitor array unit includes 1024 unit capacitors. In the first-level capacitor array unit, the first capacitor array and the second capacitor array each include 512 unit capacitors.

[0032] In the embodiment of the present invention, the N-th level capacitor array unit also includes a first sub-unit and a second sub-unit, wherein:

[0033] A first subunit in the Nth stage capacitor array unit includes a first capacitor and a first switch unit; a moving end of the first switch unit is selectively connected to a power supply voltage VDD, a second reference voltage Vref2, and a ground terminal GND; a second end of the first switch unit is coupled to a first end of the first capacitor; and a second end of the first capacitor is coupled to an output end of the capacitor array circuit;

[0034] The second subunit of the Nth-stage capacitor array unit includes a second capacitor and a second switch unit. The active terminal of the second switch unit is selectively connected to a power supply voltage VDD, a second reference voltage Vref2, and a ground terminal GND. The second terminal of the second switch unit is coupled to the first terminal of the second capacitor. The second terminal of the second capacitor is coupled to the output terminal of the capacitor array circuit. The first and second capacitors are both unit capacitors.

[0035] In a specific implementation, the first reference voltage Vref1 may be 1 / 2 of the power supply voltage VDD, that is, Vref1 = 1 / 2×VDD.

[0036] The second reference voltage Vref2 can be determined based on the first reference voltage Vref1. In other words, the second reference voltage Vref2 is correlated with the first reference voltage Vref1. The second reference voltage Vref2 can be less than the first reference voltage Vref1, greater than the first reference voltage Vref1, or equal to Vref1. Both the first reference voltage Vref1 and the second reference voltage Vref2 are less than the power supply voltage VDD.

[0037] In some embodiments, the second reference voltage can be any voltage value within a preset voltage range, the minimum value of the voltage range is the difference between the first reference voltage and the preset threshold, and the maximum value of the voltage range is the sum of the first reference voltage and the preset threshold.

[0038] For example, if the power supply voltage VDD is set to 1.2 V, the first reference voltage Vref1 is 0.6 V. If the preset threshold is 0.3 V, the second reference voltage Vref2 can be between 0.3 V and 0.9 V.

[0039] In an embodiment of the present invention, a first input terminal of the comparison circuit is coupled to an output terminal of the capacitor array circuit. The analog-to-digital converter may further include a sample-and-hold circuit to sample and hold an input target voltage. A first reference voltage Vref1 may be input to a second input terminal of the comparator. The comparator may compare the first reference voltage Vref1 with the output voltage of the capacitor array circuit and output the comparison result between the first reference voltage Vref1 and the output voltage of the capacitor array circuit to the logic circuit.

[0040] The logic circuit may convert the comparison result between the first reference voltage Vref1 and the output voltage of the capacitor array circuit into a corresponding digital signal, thereby obtaining an N+2-bit analog-to-digital conversion value.

[0041] In a specific implementation, the specific circuit structures and working processes of the above-mentioned sampling and holding circuit, comparison circuit, and logic circuit can refer to existing analog-to-digital converters and are not described in detail here.

[0042] In an embodiment of the present invention, after the sample-and-hold circuit completes the sample-and-hold state, in the sample-and-hold state of the capacitor array circuit, for any one level of the N levels of capacitor array units: the active terminal of the first comparison unit therein is connected to the power supply voltage VDD, and the active terminal of the second comparison unit therein is connected to the ground terminal GND.

[0043] The working process of the analog-to-digital converter provided above is described below. Figure 2 , a flowchart of an analog-to-digital conversion method in an embodiment of the present invention is given. Figure 2 The analog-to-digital conversion method provided in can control the analog-to-digital converter provided above.

[0044] In a specific implementation, the following steps 201 to 204 may be executed by a controller. The controller may be independent of the analog-to-digital converter, or located in the analog-to-digital converter.

[0045] Step 201 : performing a j-th comparison on the output voltage of the capacitor array circuit and the first reference voltage, and determining a value of the j-th bit in the analog-to-digital conversion value based on the j-th comparison result.

[0046] In a specific implementation, j is a positive integer and 1≤j≤N.

[0047] In an embodiment of the present invention, the controller may control the comparison of the output voltage of the capacitor array circuit with the first reference voltage. After performing the j-th comparison of the output voltage of the capacitor array circuit, a j-th comparison result may be obtained, and the value of the j-th bit in the analog-to-digital conversion value may be determined based on the j-th comparison result.

[0048] When the output voltage of the capacitor array circuit is compared with the first reference voltage for the jth time, the output voltage of the capacitor array circuit is Vout j. When the output voltage of the capacitor array circuit is compared with the first reference voltage for the j+1th time, the output voltage of the capacitor array circuit is Vout j+1, which is different from Vout j.

[0049] That is, after one comparison, the output voltage of the capacitor array circuit will change. In other words, the output voltage of the capacitor array circuit will change as the number of comparisons with the first reference voltage changes.

[0050] Specifically, the controller first controls the output voltage of the capacitor array circuit to perform a first comparison with the first reference voltage. During the first comparison, the output voltage Vout1 of the capacitor array circuit is compared with the first reference voltage Vref1.

[0051] If Vout1>Vref1, the value of the first bit in the analog-to-digital conversion value is 1; and in the first-stage capacitor array unit, the active terminal of the first switch unit is switched to be connected to the ground terminal, and the active terminal of the second switch unit remains connected to the ground terminal;

[0052] If Vout1>Vref1, the value of the first bit in the analog-to-digital conversion value is 0; and in the first-level capacitor array unit, the active end of the first switch unit remains connected to the power supply voltage, and the active end of the second switch unit is switched to be connected to the power supply voltage.

[0053] The first bit in the above analog-to-digital conversion value is the most significant bit of the analog-to-digital conversion value.

[0054] Since the active terminal of the first switch unit in the first-stage capacitor array unit changes / the active terminal of the second switch unit changes after the first comparison, the output voltage of the capacitor array circuit will change accordingly, from Vout1 to Vout2. Vout2 is the output voltage of the capacitor array circuit during the second comparison.

[0055] After obtaining the value of the first bit in the analog-to-digital conversion value, the controller controls to compare Vout2 with the first reference voltage Vref1. Similarly:

[0056] If Vout2>Vref1, the value of the second bit in the analog-to-digital conversion value is 1; and in the second-stage capacitor array unit, the active terminal of the first switch unit is switched to be connected to the ground terminal, and the active terminal of the second switch unit remains connected to the ground terminal;

[0057] If Vout2>Vref1, the value of the second bit in the analog-to-digital conversion value is 0; and, in the second-stage capacitor array unit, the active end of the first switch unit remains connected to the power supply voltage, and the active end of the second switch unit is switched to be connected to the power supply voltage.

[0058] After the second comparison, the active terminal of the first switch unit in the second-stage capacitor array unit changes / the active terminal of the second switch unit changes, so the output voltage of the capacitor array circuit changes accordingly, from Vout2 to Vout2, where Vout2 is the output voltage of the capacitor array circuit during the second comparison.

[0059] Similarly, the controller controls the output voltage of the capacitor array circuit to compare with the first reference voltage Vref1 for the Nth time to obtain the value of the Nth bit in the analog-to-digital conversion value. When performing the Nth comparison, the output voltage of the capacitor array circuit is updated to VoutN.

[0060] Step 202 : After comparing the output voltage of the capacitor array circuit with the first reference voltage for the Nth time, update the output voltage of the capacitor array circuit to the first voltage.

[0061] In an embodiment of the present invention, after obtaining the comparison result of VoutN and Vref1, the controller can determine the connection mode of the active end of the first comparison unit and the connection mode of the active end of the second comparison unit in the Nth level capacitor array unit based on the comparison result of VoutN and Vref1.

[0062] Specifically, if VoutN>Vref1, the active end of the first switch unit in the Nth stage capacitor array unit is switched to be connected to the second reference voltage, and the active end of the second switch unit remains connected to the ground;

[0063] If VoutN<Vref1, then in the Nth stage capacitor array unit, the active end of the first switch unit is kept connected to the power supply voltage, and the active end of the second switch unit is connected to the second reference voltage.

[0064] After the first adjustment is performed on the active end of the first switch unit / the active end of the second switch unit in the Nth stage capacitor array unit, the output voltage of the capacitor array circuit changes and is updated from VoutN to the first voltage VoutN+1.

[0065] Step 203 : Compare the first voltage with a first reference voltage, determine the value of the N+1th bit in the analog-to-digital conversion value based on the comparison result of the first voltage and the first reference voltage, and update the first voltage to a second voltage.

[0066] In a specific implementation, the controller may control the comparison between the first voltage VoutN+1 and the first reference voltage Vref1 .

[0067] If VoutN>Vref1 and VoutN+1>Vref1, the value of the N+1th bit in the analog-to-digital conversion value is 1, and the active terminal of the first switch unit in the Nth stage capacitor array unit is switched to be connected to the ground terminal, and the active terminal of the second switch unit remains connected to the ground terminal;

[0068] If VoutN>Vref1, and VoutN+1<Vref1, the value of the N+1th bit in the analog-to-digital conversion value is 0, and the active end of the first switch unit in the Nth stage capacitor array unit remains connected to the second reference voltage, and the active end of the second switch unit is switched to be connected to the second reference voltage;

[0069] If VoutN<Vref1, and VoutN+1>Vref1, the value of the N+1th bit in the analog-to-digital conversion value is 1, and the active terminal of the first switch unit in the Nth stage capacitor array unit remains connected to the second reference voltage, and the active terminal of the second switch unit is switched to be connected to the ground terminal;

[0070] If VoutN<Vref1, and VoutN+1<Vref1, the value of the N+1th bit in the analog-to-digital conversion value is 0, and the active end of the first switch unit in the Nth level capacitor array unit is switched to be connected to the second reference voltage, and the active end of the second switch unit is switched to be connected to the second reference voltage.

[0071] After the controller adjusts the active end of the first switch unit / the active end of the second switch unit in the Nth level capacitor array unit for the second time, the output voltage of the capacitor array circuit changes, and the output voltage of the capacitor array circuit is updated from the first voltage VoutN+1 to the second voltage VoutN+2.

[0072] Step 204 : Compare the second voltage with the first reference voltage, and determine the value of the N+2th bit in the analog-to-digital conversion value based on the comparison result of the second voltage and the first reference voltage.

[0073] In a specific implementation, the controller controls the comparison between the second voltage VoutN+2 and the first reference voltage Vref1 to determine the value of the N+2th bit in the analog-to-digital conversion value.

[0074] Specifically, if VoutN+2>Vref1, the value of the N+2th bit in the analog-to-digital conversion value is 1; if VoutN+2<Vref1, the value of the N+2th bit in the analog-to-digital conversion value is 0.

[0075] As can be seen from the above, through steps 201 to 204 , an N+2-bit analog-to-digital conversion value can be obtained.

[0076] In some embodiments, the N+2th bit may also be referred to as a redundant bit.

[0077] The analog-to-digital conversion method and the analog-to-digital converter provided in the above embodiments are described below through specific examples.

[0078] Reference Figure 3 , a structural schematic diagram of a capacitor array circuit in an embodiment of the present invention is given. Figure 3 In the embodiment, the capacitor array circuit is in the initialization state.

[0079] Figure 3In the embodiment, the capacitor array circuit includes 11 levels of capacitor array units. The analog-to-digital converter can output a 12-bit analog-to-digital conversion value, and adds one redundant bit to the 12-bit analog-to-digital conversion value. In other words, the analog-to-digital converter can output a 13-bit analog-to-digital conversion value. Figure 3 In the circuit, the capacitor array circuit is in the initialization state.

[0080] The i-th level capacitor array unit includes a first switch unit Sip and a second switch unit Sin. The first capacitor array and the second capacitor array in the i-th level capacitor array unit both include 2 N-i-1 A unit capacitor.

[0081] Specifically, if Figure 3 As shown, the first-level capacitor array unit includes a first switch unit S1p and a second switch unit S1n, and the first capacitor array includes 512 unit capacitors C lsb The second capacitor array also includes 512 unit capacitors C lsb .

[0082] The second-level capacitor array unit includes a first switch unit S2p, a first capacitor array, a second switch unit S2n, and a second capacitor array. The first capacitor array includes 256 unit capacitors C lsb The second capacitor array also includes 256 unit capacitors C lsb .

[0083] Similarly, the 10th level capacitor array unit includes a first switch unit S10p and a second switch unit S10n, and the first capacitor array includes one unit capacitor C lsb The second capacitor array also includes 1 unit capacitor C lsb .

[0084] The 11th stage capacitor array unit includes a first switch unit S11p, a second switch unit S12p, and capacitors C respectively connected to the second end of the first switch unit S11p. lsb , capacitor C connected to the second switch unit S12p lsb .

[0085] The active terminal of S11p can be selectively connected to the power supply voltage, the second reference voltage and the ground terminal, and the active terminal of S11n can be selectively connected to the power supply voltage, the second reference voltage and the ground terminal. The second reference voltage is 1 / 2 times the first reference voltage.

[0086] The controller can compare the output voltage of the capacitor array circuit with the first reference voltage for the first time to obtain the value of the first bit in the analog-to-digital conversion value (i.e., the most significant bit in the analog-to-digital conversion value). Similarly, the controller can compare the output voltage of the capacitor array circuit with the first reference voltage for the second time to obtain the value of the second bit in the analog-to-digital conversion value. Similarly, the controller can compare the output voltage of the capacitor array circuit with the first reference voltage for the second time to obtain the value of the Nth bit in the analog-to-digital conversion value.

[0087] In the sample-and-hold state of the capacitor array circuit, the active terminal of the first switch unit of the j-th capacitor array unit is connected to the power supply voltage, and the active terminal of the second switch unit is connected to the ground terminal. In this state, the controller compares the output voltage of the capacitor array circuit with the first reference voltage for the first time.

[0088] For the first-level capacitor array unit:

[0089] The first capacitor array of the first subunit includes 512 unit capacitors connected in parallel, and the second capacitor array of the second subunit includes 512 unit capacitors connected in parallel.

[0090] The controller controls the output voltage of the capacitor array circuit to be compared with the first reference voltage Vref1 for the first time. At this time, the output voltage of the capacitor array circuit is Vout1. If Vout1 < Vref1, the active terminal of the first switch unit of the first-stage capacitor array unit remains connected to the power supply voltage, and the active terminal of the second switch unit is switched from the ground terminal to the power supply voltage. At this time, the first bit of the analog-to-digital conversion value is 0.

[0091] If Vout1>Vref1, the active terminal of the first switch unit of the first-stage capacitor array unit is switched from the power supply voltage to the ground, and the active terminal of the second switch unit remains connected to the ground; at this time, the value of the first bit in the analog-to-digital conversion value is 1.

[0092] For the second-level capacitor array unit:

[0093] The first capacitor array of the first sub-unit includes 256 unit capacitors connected in parallel, and the second capacitor array of the second sub-unit includes 256 unit capacitors connected in parallel.

[0094] The controller controls the output voltage of the capacitor array circuit to be compared with Vref1 for a second time. The output voltage of the capacitor array circuit during the second comparison is Vout2. If Vout2 < Vref1, the active terminal of the first switch unit of the second-stage capacitor array unit remains connected to the power supply voltage, and the active terminal of the second switch unit is switched from the ground terminal to the power supply voltage. At this time, the value of the second bit in the analog-to-digital conversion value is 0.

[0095] If Vout2>Vref1, the active terminal of the first switch unit of the second-stage capacitor array unit is switched from the power supply voltage to the ground, and the active terminal of the second switch unit remains connected to the ground; at this time, the value of the second bit in the analog-to-digital conversion value is 1.

[0096] By analogy, for the 10th level capacitor array unit:

[0097] The first capacitor array of the first sub-unit includes one unit capacitor, and the second capacitor array of the second sub-unit includes one unit capacitor.

[0098] The controller controls and compares the output voltage value Vout10 of the capacitor array circuit with Vref1. If Vout10 < Vref1, the active terminal of the first switch unit of the 10th stage capacitor array remains connected to the power supply voltage, and the active terminal of the second switch unit is switched from the ground terminal to the power supply voltage. At this time, the value of the 10th bit in the analog-to-digital conversion value is 0.

[0099] If Vout10>Vref1, the active terminal of the first switch unit of the 10th level capacitor array is switched from the power supply voltage to the ground, and the active terminal of the second switch unit remains connected to the ground; at this time, the value of the 10th bit in the analog-to-digital conversion value is 1.

[0100] The structure of the 11th-level capacitor array unit is the same as that of the 10th-level capacitor array unit. The 11th-level capacitor array unit includes a first subunit and a second subunit. The first subunit includes a first capacitor and a first switch unit, and the second subunit includes a second capacitor and a second switch unit. Both the first capacitor and the second capacitor are unit capacitors.

[0101] The controller controls the output voltage value of the capacitor array circuit to be compared with Vref1 for the 11th time. The output voltage value of the capacitor array circuit during the 11th comparison is Vout11. If Vout11 < Vref1, the active terminal of the first switch unit in the 11th level of capacitor array units is connected to the power supply voltage, and the active terminal of the second switch unit is connected to the second reference voltage. The value of the 11th bit in the analog-to-digital conversion value is 0;

[0102] If Vout11>Vref1, the active terminal of the first switch unit in the 11th level capacitor array unit is connected to the second reference voltage, and the active terminal of the second switch unit is connected to the second reference voltage; at this time, the value of the 11th bit in the analog-to-digital conversion value is 1.

[0103] After comparing Vout11 with Vref1, the output voltage of the capacitor array circuit changes and is set to Vout12.

[0104] Compare Vout12 to Vref1.

[0105] If Vout11<Vref1 and Vout12<Vref1, the active terminal of the first switch unit in the 11th capacitor array unit is connected to the second reference voltage, and the active terminal of the second switch unit is connected to the second reference voltage. The value of the 12th bit in the analog-to-digital conversion value is 0.

[0106] If Vout11 < Vref1 and Vout12 > Vref1, the active terminal of the first switch unit in the 11th capacitor array unit is connected to the power supply voltage, and the active terminal of the second switch unit is connected to the ground terminal. The value of the 12th bit in the analog-to-digital conversion value is 1.

[0107] If Vout11>Vref1 and Vout12<Vref1, the active terminal of the first switch unit in the 11th capacitor array unit is connected to the second reference voltage, and the active terminal of the second switch unit is connected to the second reference voltage. The value of the 12th bit in the analog-to-digital conversion value is 0.

[0108] If Vout11>Vref1 and Vout12>Vref1, the active terminal of the first switch unit in the 11th capacitor array unit is connected to the ground terminal, and the active terminal of the second switch unit is connected to the ground terminal. The value of the 12th bit in the analog-to-digital conversion value is 1.

[0109] After comparing Vout12 with Vref1 , the output voltage of the capacitor array circuit is updated to Vout13 .

[0110] Compare Vout13 to Vref1.

[0111] If Vout13<Vref1, the value of the 13th bit in the analog-to-digital conversion value is 0; if Vout13>Vref1, the value of the 13th bit in the analog-to-digital conversion value is 1.

[0112] As can be seen from the above, in the process of obtaining a 13-bit analog-to-digital conversion value, the value of the most significant bit (i.e., the first bit of the analog-to-digital conversion value) is first obtained, followed by the value of the second most significant bit (i.e., the second bit of the analog-to-digital conversion value), and so on, ultimately obtaining the value of the 13th bit (i.e., the least significant bit of the analog-to-digital conversion value). Furthermore, the capacitor array circuit includes only 11 levels of capacitor array units, which can achieve 1-bit redundancy and a 12-bit analog-to-digital conversion value (essentially a total of 13 bits of analog-to-digital conversion value).

[0113] Reference Figure 4 , a schematic diagram of a P-part layout of a capacitor array circuit according to an embodiment of the present invention is provided. The P-part layout includes the first subunits of the 1st to 11th levels of capacitor array units, that is, the first subunits of the 11th level of capacitor array units.

[0114] The schematic diagram of the N-part layout of the capacitor array circuit can be referred to as the schematic diagram of the P-part layout, and the two are mirror images. The above-mentioned N-part layout includes the second sub-units in the 1st to 11th level capacitor array units, that is, the second sub-units of the 11th level capacitor array units.

[0115] Depend on Figure 4 It can be seen that the capacitors in the P part of the layout can be completely covered, realizing full utilization of the layout. Correspondingly, the N part of the layout can also achieve full utilization of the layout.

[0116] In summary, by setting the second reference voltage, based on the magnitude relationship between the output voltage of the capacitor array circuit after the Nth comparison and the first reference voltage, it is determined that the active end of the first switch unit / the active end of the second switch unit of the N-th capacitor array unit is connected to the second reference voltage. Then, the output voltage of the capacitor array circuit is updated to the first voltage. Based on the magnitude relationship between the first voltage and the first reference voltage, the active end of the first switch unit / the second switch unit connected to the second reference voltage is adjusted, the output voltage of the capacitor array circuit is adjusted from the first voltage to the second voltage, and the value of the N+1th bit in the analog-to-digital conversion value is obtained. Further, by comparing the second voltage with the first reference voltage, the N+2th bit in the analog-to-digital conversion value can be obtained. By using a capacitor array circuit including N-level capacitor array units, the output of an N+2-bit analog-to-digital conversion value is achieved, thereby improving the accuracy of the analog-to-digital converter.

[0117] Those skilled in the art will understand that all or part of the steps in the various methods of the above embodiments can be completed by instructing the relevant hardware through a program, and the program can be stored in a computer-readable storage medium, which may include: ROM, RAM, disk or CD, etc.

[0118] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. An analog-to-digital converter, characterized in that Suitable for converting the input target voltage into an N+2-bit analog-to-digital conversion value and outputting it; the analog-to-digital converter includes: a capacitor array circuit, a comparison circuit and a logic circuit, the capacitor array circuit includes N levels of capacitor array units; wherein: The i-th level capacitor array unit in the N-level capacitor array unit includes 2 N-i unit capacitors; the i-th capacitor array unit is coupled to the output end of the capacitor array circuit; i is a positive integer and 1≤i≤N-1; The N-th level capacitor array unit in the N-level capacitor array unit includes a first subunit and a second subunit, wherein: The first subunit includes a first capacitor and a first switch unit, wherein a moving end of the first switch unit is selectively connected to a power supply voltage, a second reference voltage, and a ground end, a second end of the first switch unit is coupled to a first end of the first capacitor, and a second end of the first capacitor is coupled to an output end of the capacitor array circuit; The second subunit includes a second capacitor and a second switch unit, wherein a movable end of the second switch unit is selectively connected to the power supply voltage, the second reference voltage, and the ground end, a second end of the second switch unit is coupled to the first end of the second capacitor, and a second end of the second capacitor is coupled to the output end of the capacitor array circuit; The comparison circuit has a second input terminal inputting a first reference voltage and an output terminal coupled to the logic circuit; The logic circuit is adapted to convert the output result of the comparison circuit into a corresponding digital signal.

2. The analog-to-digital converter according to claim 1, wherein The i-th level capacitor array unit includes a first subunit and a second subunit, the first subunit includes a first capacitor array and a first switch unit, and the second subunit includes a second capacitor array and a second switch unit, wherein: the first switch unit has a moving end selectively connected to the power supply voltage and the ground end, and a fixed end coupled to the first end of the first capacitor array; The second end of the first capacitor array is coupled to the output end of the capacitor array circuit, including 2 N-i-1 Unit capacitance; The second switch unit has a moving end selectively connected to the power supply voltage and the ground, and a fixed end coupled to the first end of the second capacitor array; The second capacitor array, whose second end is coupled to the output end of the capacitor array circuit, includes 2 N-i-1 A unit capacitor.

3. The analog-to-digital converter according to claim 2, wherein: In the sampling and holding state of the capacitor array circuit, the active end of the first comparison unit of any one level of the N-level capacitor array units is connected to the power supply voltage, and the active end of the second comparison unit of any one level of the N-level capacitor array units is connected to the ground.

4. The analog-to-digital converter according to claim 1, wherein The power supply voltage is twice the first reference voltage.

5. The analog-to-digital converter according to claim 1, wherein The second reference voltage is correlated to the first reference voltage.

6. An analog-to-digital conversion method, characterized in that: The method is suitable for performing analog-to-digital conversion on an input target voltage based on the analog-to-digital converter provided by any one of claims 1 to 5; the method comprising: performing a j-th comparison of the output voltage of the capacitor array circuit with the first reference voltage, and determining a value of the j-th bit in the analog-to-digital conversion value based on the j-th comparison result, where j is a positive integer and 1≤j≤N; after performing an N-th comparison of the output voltage of the capacitor array circuit with the first reference voltage, updating the output voltage of the capacitor array circuit to the first voltage; comparing the first voltage with the first reference voltage, determining a value of the (N+1)th bit in the analog-to-digital conversion value based on a result of the comparison between the first voltage and the first reference voltage, and updating the output voltage of the capacitor array circuit to a second voltage; The second voltage is compared with the first reference voltage, and based on the comparison result of the second voltage and the first reference voltage, a value of the N+2th bit in the analog-to-digital conversion value is determined.

7. The analog-to-digital conversion method according to claim 6, wherein: Updating the output voltage of the capacitor array circuit to a first voltage includes: If the output voltage of the capacitor array circuit is greater than the first reference voltage during the Nth comparison, the active end of the first switch unit of the N-level capacitor array unit is connected to the second reference voltage; if the output voltage of the capacitor array circuit is less than the first reference voltage during the Nth comparison, the active end of the second switch unit of the N-level capacitor array unit is connected to the second reference voltage.

8. The analog-to-digital conversion method according to claim 7, wherein: Updating the output voltage of the capacitor array circuit to a second voltage includes: If the output voltage of the capacitor array circuit is greater than the first reference voltage during the Nth comparison, and the first voltage is greater than the first reference voltage, connecting the fixed end of the first switch unit of the Nth stage capacitor array unit to the second reference voltage; If the output voltage of the capacitor array circuit is greater than the first reference voltage during the Nth comparison, and the first voltage is less than the first reference voltage, connecting the fixed end of the second switch unit of the Nth stage capacitor array unit to the second reference voltage; If the output voltage of the capacitor array circuit is less than the first reference voltage during the Nth comparison, and the first voltage is greater than the first reference voltage, connecting the fixed terminal of the second switch unit of the Nth stage capacitor array unit to the ground terminal; If the output voltage of the capacitor array circuit is less than the first reference voltage during the Nth comparison, and the first voltage is less than the first reference voltage, the fixed end of the first switch unit of the Nth stage capacitor array unit is connected to the second reference voltage.

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