FPGA-based fast decoding design method for polar code DJSCC

Abstract

The application discloses a design method of a fast decoding of a polar code DJSCC based on FPGA from the commonality of the DJSCC based on the polar code and the SC decoding of the traditional polar code. Based on the distribution characteristics of the frozen bits and the information bits of the polar code, the code word of the polar code is divided into four sub-codes, and the decoding mode can be converted from the decoding of each bit to the parallel decoding of each sub-code. Meanwhile, based on the parallel characteristics of the FPGA, the operation units in the same decoding tree are iterated in parallel. The simulation result shows that, compared with the SC decoding under the same hardware framework, the application can effectively reduce the iteration times of the decoding, thereby improving the throughput of the decoding, under the premise that the error code performance is almost not lost and the resource consumption is not excessively increased.

Description

Technical Field

[0001] This invention belongs to the field of source coding technology, specifically involving a fast decoding design method for DJSCC polar codes based on FPGA. Background Technology

[0002] With the rapid development of the Internet of Things (IoT), wireless sensor networks have been widely applied in various fields. Against the backdrop of continuously increasing device and data volumes, wireless sensor devices are increasingly trending towards low power consumption and miniaturization. To address the high complexity and high power consumption issues of traditional discrete source-channel coding frameworks, Slepian-Wolf and Wyner-Ziv theories demonstrate that joint decoding can be performed using the correlation between sources, thereby shifting the complexity from the transmitter to the receiver. This is the theoretical basis of Distributed Source Coding (DSC). Distributed Joint Source-Channel Coding (DJSCC) is a special case of DSC that considers channel conditions, effectively compressing the source while possessing a certain degree of anti-interference capability.

[0003] In 2009, Professor Arikan of Turkey proposed polar codes based on channel polarization. Polar codes are a type of channel coding that has been rigorously proven in theory to reach the Shannon limit. Subsequently, Arikan extended polar codes to source coding based on source polarization. The emergence of polar codes has provided a new research direction for DJSCC.

[0004] Successive Cancellation (SC) decoding of polar codes is a serial decoding scheme, thus SC decoders suffer from high latency. To address this latency issue, many scholars have conducted meaningful research, one approach being to study the distribution characteristics of information bits and frozen bits in polar codes. Unlike polar codes used for channel codes, DJSCC based on polar codes aims to achieve high compression performance while maintaining good error resilience; the different transmitted codewords determine their different decoding methods. Currently, no research results have been published on how to reduce the time complexity of DJSCC decoding based on polar codes, or on corresponding FPGA design schemes. Summary of the Invention

[0005] The purpose of this invention is to research a high-throughput polar code decoding scheme. This invention leverages the similarity in decoding iteration structure between polar codes within the DJSCC framework and traditional polar codes, extending the Fast Simplified Successive Cancellation (Fast-SSC) decoding scheme of traditional polar codes to the DJSCC framework, supplementing the original four-seed code decoding method of Fast-SSC. Compared to the original SC decoding, the method of this invention effectively reduces the number of decoding iterations, thereby improving decoding throughput.

[0006] For ease of explanation, the following concepts are introduced:

[0007] Distributed Joint Source-Channel Coding (DJSCC): DJSCC takes channel conditions into account while simultaneously using Distributed Source Coding (DSC).

[0008] Fast Simplified Successive Cancellation (Fast-SSC) Decoding: Fast-SSC decoding is based on SC decoding. It divides the codewords of the polar code and performs parallel decoding on the subcodes of the polar code, thereby reducing the number of iterations in SC decoding.

[0009] Rate-0 code: A zero-rate code with a code length of N, where all bits of this polar code subcode are frozen bits.

[0010] SPC (Single Parity Check) code: A polar code of length N, where only the first bit u0 is a frozen bit, and the remaining bits u1 to u2 are frozen bits. N-1 For information bits, the characteristic of this codeword is that the sum of all bits modulo 2 is 0, and the receiving end verifies the result as 1, indicating that there is an error in the transmission.

[0011] The basic idea of ​​this invention is to utilize a specific combination of frozen bits and information bits in polar codes to form a new decoding method. The polar code is divided into four sub-codes, and parallel decoding of the sub-code nodes reduces the number of decoding iterations, thereby improving decoding efficiency. The DJSCC decoding based on polar codes can be divided into two processes: first, SC decoding is performed using the side information and syntactic equations obtained at the receiving end to recover the information lost due to compression at the encoding end; finally, a polar code encoding is performed to reverse-engineer the source. Specifically, the main process steps are as follows:

[0012] (1) Division of polar code subcodes: After the code length and code rate of the polar code are selected, the distribution of its frozen bits and information bits is determined. According to its distribution characteristics, the codeword of the polar code is divided into 4 subcodes, namely Rate-0 code, Rate-1 code, SPC-0 code and SPC-1 code. The code length, position and subcode type of each subcode are stored in the ROM memory for use in the decoding process.

[0013] (2) Polar code encoding: Polar code encoding is performed on a binary codeword sequence of length N. The frozen bit set is taken as the compressed codeword. The compressed codeword and related information source are transmitted to the receiving end through the channel for joint decoding. This is also the basic framework of DJSCC.

[0014] (3) Polar code iterative decoding: The process can be divided into two different directions of iteration, namely the iteration of the log-likelihood ratio from top to bottom and the iteration of the intermediate bit value from bottom to top. The decoding process can be summarized as first iterating the log-likelihood ratio and then iterating the intermediate bit value. When performing the log-likelihood ratio iteration operation from top to bottom, different parallel decoding schemes are selected according to the type of the subcode after iterating to the subcode node.

[0015] (4) Rate-0 code decoding: Rate-0 code is a code rate zero code, which is composed of frozen bits. Under the DJSCC framework, the frozen bits are compressed codewords. Different sources generate different Rate-0 code sequences, which are different from the original Rate-0 code which is a fixed value. Therefore, the receiver needs to iterate the bit values ​​from bottom to top according to the received syntactic to finally obtain the estimated value of the Rate-0 codeword.

[0016] (5) SPC code decoding: SPC code is a single even parity code. Only the first bit of the code is a frozen bit, and the rest are information bits. Under the DJSCC framework, the SPC code is extended to SPC-0 code and SPC-1 code according to the actual value of the frozen bit, and the parity is divided into odd parity and even parity.

[0017] (6) Secondary polar code encoding: The decoding result of the Fast-SSC iteration of the Fast Simplified Serial Cancellation needs to be encoded by polar code once to recover the information lost by compression. The combination of this result and the syntactic is the encoding result of the polar code at the transmitting end. After another polar code encoding, the source can be recovered, and the final decoding result is obtained.

[0018] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0019] (1) The iterative decoding process of this invention is general to the iterative decoding process of SC decoding. The algorithm proposed in this invention can be used without modifying the overall decoding framework. At the same time, it ensures that the application of this invention will not lead to more resource consumption.

[0020] (2) The present invention proposes that the resources required for parallel decoding of subcodes can be reused from the log-likelihood ratio iteration processing unit PE and the intermediate bit value iteration processing unit CE of the original decoding framework, thereby saving resources.

[0021] (3) The fast decoding scheme under the DJSCC framework proposed in this invention greatly improves the decoding rate of polar codes under the DJSCC framework through parallel decoding of subcodes. At the same time, the decoding scheme proposed in this invention ensures the robustness of the system and almost does not lose the error resistance performance while improving the decoding rate. Attached Figure Description

[0022] Figure 1 This is the overall framework of the present invention.

[0023] Figure 2 This is the algorithm flowchart of the present invention.

[0024] Figure 3 This is a graph showing the BER performance comparison test results of the present invention.

[0025] Figure 4 This is a simulation time result diagram of the improved Fast-SSC decoding in this invention.

[0026] Figure 5 This is a graph showing the FPGA resource consumption results in this invention. Detailed Implementation

[0027] The present invention will be further described in detail below with reference to the embodiments. It should be noted that the following embodiments are only used to further illustrate the present invention and should not be construed as limiting the scope of protection of the present invention. Those skilled in the art can make some non-essential improvements and adjustments to the present invention based on the above-described invention, and these improvements and adjustments should still fall within the scope of protection of the present invention.

[0028] 1. Overall decoding framework and processing procedure

[0029] The decoding framework proposed in this invention is as follows: Figure 1 As shown, the decoding module stores the received side information and syntactic expression in RAM. Upon receiving a complete code segment, decoding begins. The processing unit PE iterates the log-likelihood ratio, and after iterating to a specific layer, selects the corresponding sub-code decoding method based on the sub-node type. Subsequently, the processing unit CE iterates the intermediate bit values. The specific decoding process can be summarized as follows:

[0030] (1) Subcode division: After the code length and code rate of the polar code are selected, the distribution of its frozen bits and information bits is determined. According to its distribution characteristics, the codeword of the polar code is divided into 4 subcodes, namely Rate-0 code, Rate-1 code, SPC-0 code and SPC-1 code. The code length, position and subcode type of each subcode are stored in the ROM memory for use in the decoding process.

[0031] (2) Iterative decoding can be divided into two iterations in different directions: top-down log-likelihood ratio iteration and bottom-up intermediate bit value iteration. The decoding process can be summarized as first performing log-likelihood ratio iteration, and then performing intermediate bit value iteration as needed. Decoding can be performed after the side information and syntagmatic matrix of a complete code segment are input into the buffer. When performing top-down log-likelihood ratio iteration, different parallel decoding schemes are selected according to the type of sub-code after iterating to the sub-code node;

[0032] (3) Polar code encoding: The iterative decoding result in step (2) needs to be encoded by polar code once to recover the information that was compressed and lost. Then, the sequence is combined with the symptom, that is, the encoding result of the polar code at the sending end, and finally, the source information is recovered by polar code encoding once more.

[0033] 2. Rate-0 code decoding

[0034] This invention proposes a fast decoding design method for polar codes using the DJSCC framework based on FPGA. The decoding of Rate-0 codes differs from that of traditional polar codes. In the DJSCC framework, the frozen bits of the polar codes are no longer fixed, known sequences, but compressed codewords. This means that different information sources produce different Rate-0 code sequences, thus requiring additional iterative decoding. Leveraging the parallel characteristics of FPGAs, the iteration of Rate-0 codes can be independent of the log-likelihood ratio and intermediate bit value iteration in the decoding process. Furthermore, by reusing intermediate bit values, the resources of the iteration computation unit can be utilized. Therefore, the Rate-0 code decoding proposed in this invention, based on the DJSCC framework, can also be performed in parallel, achieving improved decoding throughput without increasing resource consumption.

[0035] 3. SPC code decoding

[0036] This invention proposes a fast decoding design method for Polar Codes (SPCs) based on FPGA (FPGA-based JavaScript Code Centering). The SPC code has only one frozen bit located at the leftmost end of the codeword. Within the JavaScript Code Centering framework, this frozen bit is a compressed codeword. Based on its actual value, its parity can be divided into odd parity and even parity. An SPC code with a frozen bit value of 0 is designated as an SPC-0 code, which satisfies even parity. An SPC code with a frozen bit value of 1 is designated as an SPC-1 code, which satisfies odd parity. The decoding principle for both is as follows: when the parity condition is not met, the bit value at the index position with the smallest absolute value of the log-likelihood ratio is inverted. The frozen bit of the SPC-0 code is 0, satisfying even parity. The SPC-0 code decoding method is the same as the original SPC code. The frozen bits of the SPC-1 code are 1, satisfying odd parity. set up This is the hard decision result for the log-likelihood ratio (LLR) of the decoded child node. The decision formula for the SPC-1 code is as follows:

[0037]

[0038] When the SPC-0 or SPC-1 code check condition is not met, the index with the smallest absolute value of the log-likelihood ratio needs to be addressed. The f function in the decoding iteration unit includes a comparison operation of the absolute value of the log-likelihood ratio. Therefore, by reusing the f function, the resource consumption of this type of subcode decoding method can be reduced. The f function is expressed as follows:

[0039] f(L1,L2)=sgn(L1)sgn(L2)min(|L1|,|L2|)

[0040] 4. Polar code encoding

[0041] The decoding scheme proposed in this invention includes two non-overlapping polar code encoding operations, which reduces resource consumption by reusing the same encoder. The polar code encoding process can be equivalent to multiplying a binary sequence by a binary two-dimensional matrix and then taking the modulo 2 result. The polar code encoding matrix is ​​unique for different code lengths. In FPGA circuit design, this invention can fix the encoding matrix in the form of N N-dimensional wire vectors, which correspond to the N columns of the binary encoding matrix. When the encoder input sequence is operated on with each column of the encoding matrix, the encoded bit sequence can be obtained. In the above matrix multiplication process, AND operation is used instead of multiplication, XOR reduction operator is used instead of summation and modulo 2 operation, and the encoding result is obtained within one clock cycle.

[0042] 5. Performance Testing

[0043] This invention presents a fast decoding design method for DJSCC polar codes based on FPGA. To verify the effectiveness of this invention, a comparison is made with the SC decoding algorithm under the same hardware framework, as follows:

[0044] (1) Error Rate Testing. In MATLAB, the code length was set to N = 256, the source crossover probability to 0.01, and the compression ratio to approximately 0.3. After determining the compression ratio, the polar codewords were divided, and the edge information generated by the source and the encoded codeword sequence were analyzed. The compressed codewords were then modulated using BPSK and passed through an AWGN channel. The receiver employed both SC decoding and improved Fast-SSC decoding. Figure 2 As shown, the error curves of the two algorithms almost overlap, which proves that the improved Fast-SSC decoding algorithm has similar error resistance to the SC decoding algorithm.

[0045] (2) Vivado Functional Verification Simulation. To verify the correctness of the design function and the specific delay, the simulation was performed using the simulation tool that comes with Vivado. Figure 3 The figures show the minimum number of clock cycles required for the improved Fast-SSC decoding. Table 1 compares the decoding time of the improved Fast-SSC decoding and SC decoding. It can be seen that within the DJSCC framework, the improved Fast-SSC algorithm proposed in this paper has a higher throughput compared to traditional SC decoding.

[0046] (3) Synthesis results of VC707. The quantization method of the log-likelihood ratio is fixed-point quantization, set to a 5-bit signed integer. According to the synthesis results, on the VC707 hardware development platform, under the framework of similar decoding numbers, the resource consumption LUT and FF of the Fast-SSC decoder designed in this invention are within a reasonable range compared with the SC decoder;

[0047] On the VC707 hardware development platform, the resource consumption LUT and FF of the Fast-SSC decoder designed in this invention, the number of clock cycles required for decoding, and the maximum clock frequency F are all considered. m As shown in Table 1 below. To verify the effectiveness of the algorithm and design, Table 1 provides relevant data for the SC decoding module under the same hardware framework. Table 1 shows that, within the DJSCC framework, the improved Fast-SSC algorithm proposed in this invention achieves a higher throughput rate compared to traditional SC decoding while reasonably increasing resource consumption.

[0048] Table 1 Comparison of the implementation results of the present invention's scheme and the SC decoding scheme

[0049] Decoding Algorithm LUT FF Fmax / MHz Number of clocks SC 7693 3529 134 1016 Fast-SSC 10531 5116 113 185

[0050] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A fast decoding design method for DJSCC polar codes based on FPGA, characterized in that... The main process steps include the following: (1) Division of polar code subcodes: After the code length and code rate of the polar code are selected, the distribution of its frozen bits and information bits is determined. According to its distribution characteristics, the codeword of the polar code is divided into 4 subcodes, namely Rate-0 code, Rate-1 code, SPC-0 code and SPC-1 code. The code length, position and subcode type of each subcode are stored in the ROM memory for use in the decoding process. (2) Polar code coding: Polar code coding is performed on a binary codeword sequence of length N. The frozen bit set is taken as the compressed codeword. The compressed codeword and related information source are transmitted to the receiving end through the channel for joint decoding. This is also the basic framework of Distributed Joint Source-Channel Coding (DJSCC). (3) Polar code iterative decoding: The process can be divided into two different directions of iteration, namely the iteration of the log-likelihood ratio from top to bottom and the iteration of the intermediate bit value from bottom to top. The decoding process can be summarized as first iterating the log-likelihood ratio and then iterating the intermediate bit value. When performing the log-likelihood ratio iteration operation from top to bottom, different parallel decoding schemes are selected according to the type of the subcode after iterating to the subcode node. (4) Rate-0 code decoding: Rate-0 code is a code rate zero code, which is composed of frozen bits. Under the framework of Distributed Joint Source-Channel Coding (DJSCC), the frozen bits are compressed codewords. Different sources generate different Rate-0 code sequences, which are different from the original Rate-0 code which is a fixed value. Therefore, the receiver needs to iterate the bit values ​​from bottom to top according to the received syntactic to finally obtain the estimated value of the Rate-0 codeword. (5) SPC code decoding: SPC code is a single even parity code. Only the first bit of the code is a frozen bit, and the rest are information bits. Under the DJSCC framework, the SPC code is extended to SPC-0 code and SPC-1 code according to the actual value of the frozen bit, and the parity is divided into odd parity and even parity. (6) Secondary polar code encoding: The decoding result of Fast Simplified Successive Cancellation (Fast-SSC) iteration needs to be encoded with polar code once to recover the information lost by compression. The combination of this result and the syntagmatic expression is the encoding result of the polar code at the transmitting end. After another polar code encoding, the source can be recovered, which is the final decoding result.

2. The FPGA-based fast decoding design method for DJSCC polar codes as described in claim 1, characterized in that... The Rate-0 code in step (4) and its decoding scheme: The Rate-0 code is composed of frozen bits. The codeword sequence of the Rate-0 code under the DJSCC framework is an uncertain value. The frozen bits are the codewords after encoding and compression. Additional iterative decoding is required for the Rate-0 code. Based on the parallel characteristics of FPGA, the iteration of the Rate-0 subcode can be independent of the log-likelihood ratio and the iteration of intermediate bit values ​​in the decoding process. At the same time, by reusing the resources of the intermediate bit value iteration operation unit, the subcode can improve the decoding efficiency without increasing resource consumption.

3. The FPGA-based fast decoding design method for DJSCC polar codes as described in claim 1, characterized in that... In step (5), the SPC code is extended and its decoding scheme is as follows: only the leftmost bit of the SPC code is a frozen bit. Under the DJSCC framework, the frozen bit is the compressed codeword. According to its actual value, its verification method can be divided into odd parity and even parity. The SPC code with a frozen bit value of 0 is defined as the SPC-0 code that needs to satisfy even parity, and the SPC code with a frozen bit value of 1 is defined as the SPC-1 code that needs to satisfy odd parity. The decoding principle of the two is as follows: when the SPC-0 or SPC-1 code verification condition is not met, the index with the smallest absolute value of the log-likelihood ratio needs to be addressed and the bit value is inverted. The f function in the decoding iteration operation unit contains the comparison operation of the absolute value of the log-likelihood ratio. Therefore, by reusing the f function, the resource consumption of this type of subcode decoding method can be reduced.

4. The FPGA-based fast decoding design method for DJSCC polar codes as described in claim 1, characterized in that... In step (6), the two polar code encodings are non-overlapping in time. By reusing the same encoder, resource consumption is reduced. In the circuit design of the FPGA, the encoding matrix is ​​fixed in the form of N N-dimensional wire vectors, where N is the code length. These N vectors correspond to the N columns of the binary encoding matrix. When the sequence input by the encoder is operated on with each column of the encoding matrix, the encoded bit sequence can be obtained. At the same time, in the matrix multiplication process, AND operation is used to replace multiplication, XOR reduction operator is used to replace summation and modulo 2 operation, and the encoding result is obtained within one clock cycle.

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