Ultrasonic equipment clock synchronization system and method

Abstract

The present invention is applicable to the technical field of medical equipment, and provides a system and method for synchronizing the clock of an ultrasonic device. The system includes a main system board and multiple subsystem boards connected to the main system board and performing clock synchronization; the main system board includes a control module, a clock distribution module and a first FPGA module, and each subsystem board includes a phase-locked loop circuit and a second FPGA module; the first FPGA module includes a pulse synchronization unit, a clock calibration enabling unit and a phase information reading unit, and the second FPGA module includes a clock phase information latching unit. The present invention solves the problem that the additional jitter noise caused by the existing use of a low-frequency receiving clock as a reference for clock synchronization affects the system performance.

Description

Technical Field

[0001] The present invention relates to the technical field of medical equipment, and in particular to a clock synchronization system and method for ultrasonic equipment. Background Art

[0002] As an important diagnostic device in modern medicine, the core technology of medical ultrasound imaging system includes the generation and reception of ultrasound waves, and the imaging of collected ultrasound signals through digital signal processing. Similar to radar and communication equipment, ultrasound system also relies on transceiver modules to complete the transmission and reception of signals. However, there are significant differences in technical requirements between medical ultrasound system and radar and communication equipment. Among them, the transceiver module of ultrasound system has more stringent requirements for timing synchronization, especially in large desktop medical ultrasound equipment, the integration and synchronization of multiple subsystems are crucial to the overall performance of the system. Accurate timing synchronization is crucial to the imaging quality, diagnostic accuracy and overall performance of the system. The transceiver module of the ultrasound system must ensure strict timing alignment between the transmitted signal and the received signal. Any timing deviation will have a significant impact on image quality and system performance.

[0003] With the improvement of electronic integration, some handheld or portable ultrasound systems can realize the synchronous transmission and reception functions through a single board. This design is suitable for small equipment scenarios, with a compact structure and high integration. However, in large desktop ultrasound imaging systems, it is usually necessary to integrate multiple subsystems to realize the transmission and reception processing of multi-channel signals. Although this multi-subsystem architecture design can support more complex signal processing and higher imaging resolution, it also introduces the problem of timing synchronization between subsystems. In this case, clock synchronization between subsystems becomes a key technical challenge in system design. The synchronization performance between subsystems directly affects key indicators such as the overall imaging effect and signal-to-noise ratio of the system. Therefore, how to ensure accurate timing synchronization between subsystems has become the core criterion for evaluating system design.

[0004] In existing medical ultrasound systems, two main clocks are usually used: the transmit clock and the receive clock. In order to obtain a higher precision transmit signal, the frequency of the transmit clock is generally higher, usually set between 200MHz and 250MHz, depending on the performance of the chip interface in the system. The frequency of the receive clock is relatively low, usually between 40MHz and 60MHz, which is mainly due to the limitation of the sampling frequency of the analog-to-digital converter (ADC) in the receive channel. Traditional system synchronization schemes usually use a lower-frequency receive clock as the inter-board synchronization clock, which is distributed to each transceiver board through the backplane. The subsystem locks the receive clock through a phase-locked loop circuit (PLL) to achieve timing synchronization between the subsystems.

[0005] However, this synchronization scheme has obvious limitations. First, the low-frequency receiving clock is easily interfered by noise during the generation, transmission and distribution process, especially during the transmission between the backplane or circuit boards. Secondly, during the phase-locked loop synchronization process, the noise may also be synchronized to the receiving clock of each subsystem, resulting in increased clock jitter. At this time, when the low-frequency receiving clock is used as a synchronization reference clock, it is easily affected by noise interference and jitter, resulting in a decrease in the system's clock synchronization accuracy, thereby increasing the system's jitter noise. This jitter noise has a negative impact on the system's performance, especially the precise imaging and signal processing of ultrasound equipment, and thus affects the system's signal-to-noise ratio and imaging quality. Therefore, the decline in the receiving clock performance will directly affect the system's key performance indicators such as the signal-to-noise ratio, which is unacceptable for ultrasound systems that require high-precision imaging. Summary of the invention

[0006] Based on this, the purpose of the present invention is to provide an ultrasound equipment clock synchronization system and method, so as to fundamentally solve the problem that the additional jitter noise caused by the existing use of a low-frequency receiving clock as a reference for clock synchronization affects the system performance.

[0007] A clock synchronization system for ultrasound equipment according to an embodiment of the present invention includes a main system board and a plurality of subsystem boards connected to the main system board and performing clock synchronization;

[0008] The main system board includes a control module, a clock distribution module and a first FPGA module, and each subsystem board includes a phase-locked loop circuit and a second FPGA module;

[0009] The first FPGA module includes a pulse synchronization unit, a clock calibration enabling unit and a phase information reading unit, and the second FPGA module includes a clock phase information latching unit;

[0010] The clock distribution module is connected to the clock calibration enabling unit and the phase-locked loop circuit in each subsystem board, and is used to provide a high-frequency transmission clock signal as a synchronization reference;

[0011] The pulse synchronization unit is connected to the control module and the phase-locked loop circuit in each subsystem board respectively, and is used to generate a synchronization pulse signal according to the synchronization control signal output by the control module and send it to the phase-locked loop circuit;

[0012] The clock calibration enabling unit is respectively connected to the control module, the clock distribution module and the clock phase information latching unit in each subsystem board, and is used to generate a low-frequency pulse enabling signal according to the clock calibration signal output by the control module and send it to the clock phase information latching unit;

[0013] The phase information reading unit is connected to the control module and the clock phase information latch unit in each subsystem board respectively, and is used to sequentially obtain the clock phase information stored in the clock phase information latch unit in each subsystem board according to the control of the control module and transmit it to the control module;

[0014] The phase-locked loop circuit is connected to the clock distribution module, the pulse synchronization unit and the clock phase information locking module respectively, and is used to synchronize the high-frequency transmission clock provided by the clock distribution module to the local transmission clock according to the synchronization pulse signal sent by the pulse synchronization unit, and generate a local receiving clock and output it to the clock phase information latch unit;

[0015] The clock phase information latch unit is connected to the phase-locked loop circuit, the clock calibration enable unit and the phase information reading unit respectively, and is used to lock the clock phase information related to the local receiving clock according to the low-frequency pulse enable signal output by the clock calibration enable unit, and the local transmitting clock and the local receiving clock output by the phase-locked loop circuit, and send it to the phase information reading unit;

[0016] The control module is respectively connected with the pulse synchronization unit, the clock calibration enabling unit and the phase information reading unit, and is used to generate a synchronization control signal to the pulse synchronization unit to control the clock synchronization of each subsystem board, and generate a clock calibration signal to the clock calibration enabling unit to receive the clock phase information stored in the clock phase information latch unit in each subsystem board sequentially acquired by the phase information reading unit, and judge whether each subsystem board achieves clock synchronization according to the clock phase information of each subsystem board, and continue to generate the synchronization control signal and the clock calibration signal when it is judged that the clock synchronization is not achieved, until each subsystem board achieves clock synchronization.

[0017] In addition, the ultrasound equipment clock synchronization system according to the above embodiment of the present invention may also have the following additional technical features:

[0018] Furthermore, the clock distribution module includes:

[0019] A clock source, used to generate a high-frequency transmit clock signal;

[0020] And a clock driver connected to the clock source and the phase-locked loop circuit of each subsystem board respectively, for distributing the high-frequency transmission clock signal generated by the clock source to the phase-locked loop circuit of each subsystem board.

[0021] Furthermore, the pulse synchronization unit comprises:

[0022] a first register connected to the control module, and configured to receive a synchronization control signal generated by the control module;

[0023] And a synchronization circuit connected to the first register and the phase-locked loop circuit in each subsystem board respectively, for generating a synchronization pulse signal and sending it to the phase-locked loop circuit when acquiring the synchronization control signal received by the first register.

[0024] Further, the clock calibration enabling unit includes:

[0025] A frequency division circuit connected to the clock distribution module, used for dividing the high-frequency transmission clock signal provided by the clock distribution module into a low-frequency clock signal;

[0026] a second register connected to the control module, and configured to receive a clock calibration signal generated by the control module;

[0027] And a pulse generating circuit respectively connected to the frequency dividing circuit, the second register, and the clock phase information latch unit in each subsystem board, for generating a low-frequency pulse enable signal according to the low-frequency clock signal and sending it to the clock phase information latch unit when the clock calibration signal received by the second register is obtained.

[0028] Furthermore, the reference clock end of the phase-locked loop circuit is connected to the clock distribution module, the feedback clock end of the phase-locked loop circuit is connected to the local transmission clock end, the control signal end of the phase-locked loop circuit is connected to the pulse synchronization unit, and the local transmission clock end and the local reception clock end of the phase-locked loop circuit are respectively connected to the clock phase information latch unit.

[0029] Furthermore, the clock phase information latch unit includes:

[0030] A clock phase information locking subunit connected to the phase-locked loop circuit and the clock calibration enabling unit, used to lock the clock phase information related to the local receiving clock according to the low-frequency pulse enabling signal output by the clock calibration enabling unit, and the local transmitting clock and the local receiving clock output by the phase-locked loop circuit;

[0031] And a phase information storage subunit connected to the clock phase information locking subunit and the phase information reading unit respectively, used for storing the clock phase information output by the clock phase information locking subunit and sending it to the phase information reading unit.

[0032] Furthermore, the clock phase information locking subunit includes a shift register, an input data signal terminal of the shift register is connected to a local receiving clock terminal of the phase-locked loop circuit, a clock signal terminal of the shift register is connected to a local transmitting clock terminal of the phase-locked loop circuit, an enable signal terminal of the shift register is connected to the clock calibration enable unit, and an output data terminal of the shift register is connected to the phase information reading unit.

[0033] Furthermore, the control module is connected to the first FPGA module via a communication bus, the phase information reading unit and the phase information storage module in each subsystem board are connected via a communication bus, the pulse synchronization unit and the phase-locked loop circuit in each subsystem board are connected via a PCB connection, and the clock calibration enabling unit and the clock phase information latch unit in each subsystem board are connected via a PCB connection.

[0034] Furthermore, the phase information reading unit includes a third register, and the phase information storage subunit includes a fourth register.

[0035] Another embodiment of the present invention aims to provide an ultrasound device clock synchronization method, which is applied to the ultrasound device clock synchronization system described above. The method includes:

[0036] The control module of the main system board generates a synchronization control signal to the pulse synchronization unit, so that the pulse synchronization unit generates a synchronization pulse signal according to the synchronization control signal and sends it to the phase-locked loop circuit in each subsystem board;

[0037] The phase-locked loop circuit in each subsystem board synchronizes the high-frequency transmission clock provided by the clock distribution module of the main system board to the local transmission clock according to the synchronization pulse signal, and generates a local receiving clock and outputs it to the clock phase information latch unit;

[0038] The control module of the main system board generates a clock calibration signal to the clock calibration enabling unit, so that the clock calibration enabling unit generates a low-frequency pulse enabling signal according to the clock calibration signal and sends it to the clock phase information latching unit in each subsystem board;

[0039] The clock phase information latch unit in each subsystem board locks the clock phase information related to the local receiving clock according to the low-frequency pulse enable signal and the local transmitting clock and the local receiving clock output by the phase-locked loop circuit, and outputs it to the phase information storage subunit;

[0040] The control module of the main system board receives the clock phase information stored in the clock phase information latch unit of each subsystem board sequentially acquired by the phase information reading unit, and determines whether each subsystem board realizes clock synchronization according to the clock phase information of each subsystem board;

[0041] When the control module of the main system board determines that each subsystem board has not achieved clock synchronization, it continues to generate synchronization control signals to the pulse synchronization unit and generates clock calibration signals to the clock calibration enabling unit until it is determined that each subsystem board has achieved clock synchronization.

[0042] The ultrasound equipment clock synchronization system provided by the embodiment of the present invention adopts a high-frequency transmission clock as a reference signal and uses a pulse synchronization unit to generate a synchronization pulse signal, thereby ensuring that the local transmission clock generated by each subsystem board is synchronized with the high-frequency transmission clock, thereby improving the accuracy of clock synchronization and avoiding the phase offset error caused by the low-frequency signal. At the same time, the high-frequency transmission clock signal has higher stability and a shorter period, and can effectively reduce the accumulation of jitter errors. By using the high-frequency signal as a reference in the clock synchronization process, the jitter noise introduced when the low-frequency receiving clock is traditionally used as a reference is avoided, the noise caused by clock inconsistency is effectively reduced, and the performance stability of the system is improved. The control module uses the clock calibration signal The signal and the synchronization control signal coordinate the synchronous operation of each subsystem board, and obtain the clock phase information of each board through the phase information reading unit, which can detect the synchronization state in real time and automatically continue the synchronization process when asynchronism is detected, so that the clock phase of each subsystem board is gradually calibrated to ensure that all subsystem boards are finally synchronized, which greatly reduces the noise interference caused by clock asynchronism; at the same time, by combining the clock calibration enabling unit with the phase information reading unit, the complexity of additional hardware circuit design is reduced, which is convenient for the control module to uniformly manage and regulate the entire system; it solves the problem that the additional jitter noise caused by the existing use of low-frequency receiving clock as a reference for clock synchronization affects the system performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 It is a module schematic diagram of the ultrasound equipment clock synchronization system in the first embodiment of the present invention;

[0044] Figure 2 is a circuit diagram of a clock synchronization system for ultrasound equipment in a first embodiment of the present invention;

[0045] Figure 3 is a flow chart of a method for synchronizing a clock of an ultrasonic device in a second embodiment of the present invention;

[0046] The following specific implementations will further illustrate the present invention in conjunction with the above-mentioned drawings. DETAILED DESCRIPTION

[0047] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. Several embodiments of the present invention are given in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thorough and comprehensive.

[0048] It should be noted that when an element is referred to as being "fixed to" another element, it may be directly on the other element or there may be a central element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a central element at the same time. The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are for illustrative purposes only.

[0049] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present invention belongs. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0050] Embodiment 1

[0051] See also Figure 1 , which shows a clock synchronization system for ultrasound equipment in a first embodiment of the present invention. For the sake of convenience, only the parts related to the embodiment of the present invention are shown. The clock synchronization system for ultrasound equipment provided by the embodiment of the present invention includes a main system board 1, and a plurality of subsystem boards 2 connected to the main system board and performing clock synchronization;

[0052] The main system board includes a control module 11, a clock distribution module 12 and a first FPGA module 13, and each subsystem board includes a phase-locked loop circuit 21 and a second FPGA module 22;

[0053] The first FPGA module includes a pulse synchronization unit 131, a clock calibration enabling unit 132 and a phase information reading unit 133, and the second FPGA module includes a clock phase information latching unit 221;

[0054] The clock distribution module is connected to the clock calibration enabling unit and the phase-locked loop circuit in each subsystem board to provide a high-frequency transmission clock signal as a synchronization reference;

[0055] The pulse synchronization unit is respectively connected to the control module and the phase-locked loop circuit in each subsystem board, and is used to generate a synchronization pulse signal according to the synchronization control signal output by the control module and send it to the phase-locked loop circuit;

[0056] The clock calibration enabling unit is respectively connected to the control module, the clock distribution module and the clock phase information latching unit in each subsystem board, and is used to generate a low-frequency pulse enabling signal according to the clock calibration signal output by the control module and send it to the clock phase information latching unit;

[0057] The phase information reading unit is connected to the control module and the clock phase information latch unit in each subsystem board respectively, and is used to sequentially obtain the clock phase information stored in the clock phase information latch unit in each subsystem board according to the control of the control module and transmit it to the control module;

[0058] The phase-locked loop circuit is respectively connected to the clock distribution module, the pulse synchronization unit and the clock phase information locking module, and is used to synchronize the high-frequency transmission clock provided by the clock distribution module to the local transmission clock according to the synchronization pulse signal sent by the pulse synchronization unit, and generate a local receiving clock and output it to the clock phase information latch unit;

[0059] The clock phase information latch unit is connected to the phase-locked loop circuit, the clock calibration enable unit and the phase information reading unit respectively, and is used to lock the clock phase information related to the local receiving clock according to the low-frequency pulse enable signal output by the clock calibration enable unit, and the local transmitting clock and the local receiving clock output by the phase-locked loop circuit, and send it to the phase information reading unit;

[0060] The control module is respectively connected to the pulse synchronization unit, the clock calibration enabling unit and the phase information reading unit, and is used to generate a synchronization control signal to the pulse synchronization unit to control the clock synchronization of each subsystem board, and to generate a clock calibration signal to the clock calibration enabling unit to receive the clock phase information stored in the clock phase information latch unit in each subsystem board sequentially acquired by the phase information reading unit, and to judge whether each subsystem board achieves clock synchronization according to the clock phase information of each subsystem board, and to continue to generate the synchronization control signal and the clock calibration signal when it is judged that the clock synchronization is not achieved, until each subsystem board achieves clock synchronization.

[0061] Further, see Figure 2 As shown, in one embodiment of the present invention, the clock distribution module includes:

[0062] A clock source, used to generate a high-frequency transmit clock signal;

[0063] And a clock driver connected to the clock source and the phase-locked loop circuit of each subsystem board respectively, for distributing the high-frequency transmission clock signal generated by the clock source to the phase-locked loop circuit of each subsystem board.

[0064] Further, see Figure 2 As shown, in one embodiment of the present invention, the pulse synchronization unit includes:

[0065] A first register connected to the control module, used to receive a synchronization control signal generated by the control module;

[0066] And a synchronization circuit connected to the first register and the phase-locked loop circuit in each subsystem board respectively, for generating a synchronization pulse signal and sending it to the phase-locked loop circuit when acquiring the synchronization control signal received by the first register.

[0067] Further, see Figure 2 As shown, in one embodiment of the present invention, the clock calibration enabling unit includes:

[0068] A frequency dividing circuit connected to the clock distribution module, used to divide the high-frequency transmission clock signal provided by the clock distribution module into a low-frequency clock signal;

[0069] A second register connected to the control module, used to receive a clock calibration signal generated by the control module;

[0070] And a pulse generating circuit respectively connected to the frequency dividing circuit, the second register, and the clock phase information latch unit in each subsystem board, is used to generate a low-frequency pulse enable signal according to the low-frequency clock signal and send it to the clock phase information latch unit when the clock calibration signal received by the second register is obtained.

[0071] Further, see Figure 2 As shown, in one embodiment of the present invention, the reference clock terminal of the phase-locked loop circuit is connected to the clock distribution module, the feedback clock terminal of the phase-locked loop circuit is connected to the local transmission clock terminal, the control signal terminal of the phase-locked loop circuit is connected to the pulse synchronization unit, and the local transmission clock terminal and the local receiving clock terminal of the phase-locked loop circuit are respectively connected to the clock phase information latch unit.

[0072] Further, see Figure 2 As shown, in one embodiment of the present invention, the clock phase information latch unit includes:

[0073] A clock phase information locking subunit connected to the phase-locked loop circuit and the clock calibration enabling unit, used to lock the clock phase information related to the local receiving clock according to the low-frequency pulse enabling signal output by the clock calibration enabling unit, and the local transmitting clock and the local receiving clock output by the phase-locked loop circuit;

[0074] And a phase information storage subunit connected to the clock phase information locking subunit and the phase information reading unit respectively, for storing the clock phase information output by the clock phase information locking subunit and sending it to the phase information reading unit.

[0075] Further, see Figure 2As shown, in one embodiment of the present invention, the clock phase information locking subunit includes a shift register, the input data signal terminal of the shift register is connected to the local receiving clock terminal of the phase-locked loop circuit, the clock signal terminal of the shift register is connected to the local transmitting clock terminal of the phase-locked loop circuit, the enable signal terminal of the shift register is connected to the clock calibration enable unit, and the output data terminal of the shift register is connected to the phase information reading unit.

[0076] Furthermore, in one embodiment of the present invention, the control module is connected to the first FPGA module via a communication bus, the phase information reading unit and the phase information storage module in each subsystem board are connected via a communication bus, the pulse synchronization unit and the phase-locked loop circuit in each subsystem board are connected via a PCB connection, and the clock calibration enabling unit and the clock phase information latch unit in each subsystem board are connected via a PCB connection.

[0077] Further, see Figure 2 As shown, in one embodiment of the present invention, the phase information reading unit includes a third register, and the phase information storage subunit includes a fourth register.

[0078] Specifically, in one embodiment of the present invention, the ultrasound equipment clock synchronization system includes a main system board and multiple subsystem boards, which are used to realize clock synchronization of each subsystem board in the ultrasound equipment, wherein the main system board generates and distributes a high-frequency transmission clock signal, and controls the clock phase adjustment of each subsystem board through synchronization pulse control and calibration signals, thereby ensuring that the transmission clock and receiving clock of each subsystem board are synchronized.

[0079] Specifically, in one embodiment of the present invention, the clock distribution module includes a clock source and a clock driver, wherein the clock source, as the core clock signal source of the entire clock synchronization system, can provide a stable high-frequency transmission clock signal (tx_clk), wherein the high-frequency transmission clock signal is used for all boards in the clock synchronization system to ensure that each subsystem board and the main system board in the clock synchronization system share a unified clock reference. The clock source generally includes a crystal oscillator circuit, an oscillation control circuit, and an oscillation amplifier circuit, wherein the crystal oscillator circuit provides a stable reference clock signal based on the frequency of the quartz crystal oscillation; the oscillation control circuit is used to adjust and stabilize the output frequency to ensure the frequency of the clock source is accurate; and the oscillation amplifier circuit is used to amplify the crystal oscillation signal to meet the level required by the system. In specific use, its clock source generally adopts a crystal oscillator (Crystal Oscillator) or a MEMS oscillator, which is set according to actual use needs and is not specifically limited here. Furthermore, the clock driver is respectively connected to the clock source and the phase-locked loop circuit of each subsystem board, responsible for the distribution and driving of the clock signal, ensuring that the signal will not be distorted or interfered during transmission, and used to distribute the high-frequency transmission clock signal generated by the clock source to each subsystem board, ensuring that each subsystem board receives the same high-frequency transmission clock signal, and uses the high-frequency transmission clock signal for synchronization in the subsequent synchronization process. The clock driver usually includes an input buffer, a driver amplifier, and a distribution network, wherein the input buffer is used to receive the high-frequency transmission clock signal from the clock source to prevent reflection and signal attenuation; the driver amplifier is used to amplify the clock signal to ensure that multiple output ends have stable clock signals; and the distribution network is used to distribute the clock signal to multiple destination devices (i.e., subsystem boards) to ensure that each destination device receives a consistent clock signal. In specific use, its clock driver usually uses a clock buffer (Clock Buffer) or a clock distribution chip.

[0080] Further, in one embodiment of the present invention, the pulse synchronization unit includes a first register and a synchronization circuit, wherein the first register is respectively connected to the control module and the synchronization circuit, and is used to store and transmit data or control signals generated by the control module to the synchronization circuit, wherein the first register can be any one of a D flip-flop register (D Flip-Flop Register), a multi-bit register (Multi-bit Register), a latch (Latch) and an internal register of an FPGA. Specifically, in the embodiment of the present invention, the first register adopts a register block integrated inside the first FPGA module. It can be understood that in other embodiments of the present invention, the first register can also adopt other, which is set according to actual use needs and is not specifically limited here. The synchronization circuit is respectively connected to the first register and the phase-locked loop circuit in each subsystem board, and is used to generate a synchronization pulse signal according to the synchronization control signal transmitted by the first register to coordinate the clock synchronization operation between the main system board and each subsystem board, wherein the synchronization circuit can adopt a D flip-flop (D Flip-Flop), which is used to trigger data synchronization at the clock edge to ensure that the output signal changes at a predetermined time.

[0081] Specifically, the control module is connected to the first register through a communication bus, wherein the communication bus is used to transmit address signals, data signals and control signals, wherein the address signal is used to determine the location of the specific register or storage unit to be accessed by the control module, wherein the register may have different addresses, and the control module selects the register to be operated by specifying a specific address, such as the first register. The data signal is used to transmit the value actually to be written into the register, and the control module sends a specific data to the register through the communication bus, and this data may be control data or timing information or configuration information. The control signal is used to control the read and write operations, wherein the control signal tells the register whether to perform a read operation or a write operation, so that the register knows whether to receive data or send data. Therefore, the communication bus brings these signals together to provide address signals, data signals and control signals, so that the control module can locate a specific register (such as the first register) according to the address, and then transmit data and control commands to complete the data write or read operation, thereby realizing that the control module communicates with the first register through the communication bus.

[0082] Furthermore, when the control module needs to perform clock synchronization at a specific moment of system operation or when a specific event occurs, the control module writes data to the first register according to the synchronization requirement. For example, when the control module needs to start the synchronization operation of the phase-locked loop circuit, it writes a specific value to the first register at an appropriate time to trigger the operation, wherein the specific value can be a simple numerical value, such as 1 represents starting synchronization, 0 represents stopping; or its specific value can also be a control code or timing information, etc., which is set according to actual needs. The above-mentioned writing process specifically includes the control module first sending the address of the first register through the communication bus, and the communication bus transmits this address signal to the first FPGA module so that the first FPGA module determines that the target to be operated is the first register. Then the control module sends the data value to be written through the communication bus, and the control module also sends a control signal through the communication bus to prompt the first FPGA module that the operation is a "write operation". After the first FPGA module receives the above signal, it will store the data transmitted by the communication bus in the first register. Once the data is successfully written to the first register, the communication bus will also return a confirmation signal to inform the control module that the write operation has been completed. At this time, when the first register receives the value written by the control module (i.e., the synchronization control signal), the synchronization circuit detects the change of the first register and responds according to the written value. The synchronization circuit is usually a circuit designed based on a state machine, which decodes the change in the first register and generates a synchronization pulse signal according to the timing logic. Specifically, the synchronization circuit usually determines whether to generate a synchronization pulse signal according to the new value in the first register. For example, if the value in the first register is "1", it means starting the synchronization operation; if the value is "0", the synchronization operation is stopped. At this time, the synchronization circuit outputs a corresponding control signal by decoding the value of the first register. There are usually two implementation methods for the synchronization circuit to detect the value of the first register. One implementation method is that the synchronization circuit can continuously monitor the first register, and when it is found that the value of the first register changes (for example, from 0 to 1), the subsequent operation is immediately triggered. Another implementation method is that the change of the first register will directly notify the synchronization circuit. For example, when the value of the first register is written, it immediately sends a signal to notify the synchronization circuit to respond. Therefore, once the first register changes, the synchronization circuit decides whether to generate a synchronization pulse signal according to the new value in the first register. The synchronization pulse signal is a short pulse signal, which usually lasts for one or more clock cycles and is used to notify the phase-locked loop circuit to enter the synchronization mode to start the synchronization process of the phase-locked loop circuit.The synchronization pulse signal is usually a pulse signal triggered by the edge of a high or low level change, such as a short rising edge pulse from a low level to a high level or a falling edge pulse from a high level to a low level. The pulse width of the synchronization pulse signal is determined by the synchronization circuit, usually one clock cycle or several clock cycles. Since the main function of the synchronization pulse signal is to trigger the phase-locked loop circuit to enter the synchronization mode, its pulse duration does not need to be very long. It should also be pointed out that the synchronization pulse signal is a single-shot trigger control signal. Unlike the above-mentioned continuous clock signal, the synchronization pulse signal is only generated when synchronization is required.

[0083] Further, in one embodiment of the present invention, the clock calibration enabling unit includes a frequency division circuit, a second register, and a pulse generating circuit, wherein the frequency division circuit is connected to the clock source of the clock distribution module and the pulse generating circuit, and is used to divide the high-frequency transmission clock generated by the clock source to generate a low-frequency clock signal to drive the subsequent pulse generating circuit, wherein the frequency division circuit generally includes a frequency divider chip or a programmable logic device (such as the frequency division logic in the first FPGA module). The second register is respectively connected to the control module and the pulse generating circuit, and is used to store and transmit the data or control signal generated by the control module to the pulse generating circuit. The second register can be specifically referred to the first register mentioned above, and will not be described in detail here. The pulse generating circuit is respectively connected to the frequency division circuit, the second register, and the clock phase information locking module in each subsystem board, and is used to generate a low-frequency pulse enable signal according to the clock calibration signal written into the second register by the control module, as the enable signal of the clock phase information latch unit, so as to control the shift register of each subsystem board to work.

[0084] Specifically, when the first FPGA module receives the high-frequency transmission clock generated by the clock source, the first FPGA module uses an internal frequency division circuit to divide the high-frequency transmission clock into a low-frequency clock, wherein the generation process of the low-frequency clock is usually implemented by a simple counter. Specifically, the frequency division circuit generates a clock signal with a lower frequency by counting the high-frequency transmission clock pulses. For example, if the frequency of the high-frequency transmission clock is 200MHz, and the frequency division circuit divides it to 40MHz, it means that the frequency division circuit will output 1 low-frequency clock cycle for every 5 high-frequency transmission clock cycles. The low-frequency clock generated at this time is used to drive the pulse generation circuit, which is responsible for generating a low-frequency pulse enable signal under specific conditions. The control module is connected to the second register through a communication bus, and its specific implementation can refer to the working principle of the aforementioned control module and the first register. The pulse generating circuit is respectively connected to the frequency dividing circuit, the second register, and the clock phase information latch unit in each subsystem board, wherein the low-frequency pulse generating circuit is used to generate a low-frequency pulse enable signal according to the low-frequency clock signal output by the frequency dividing circuit when the control module writes a specific value to the second register, wherein the low-frequency pulse enable signal will be used as the enable signal of the shift register in each subsystem board. Specifically, when the control module writes a specific value to the second register, the pulse generating circuit determines whether a low-frequency pulse needs to be generated by detecting the change of the second register. Once it is determined to generate a pulse, the pulse generating circuit will generate a short pulse signal when the next low-frequency clock edge arrives. The low-frequency pulse usually has a width of only one clock cycle. At this time, the low-frequency pulse is used as an enable signal and is transmitted to the shift register in each subsystem board to control the operation of the shift register. Furthermore, since the high-frequency transmission clock frequency generated by the clock source is relatively high, and the system's shift register usually does not need to perform data shift operations frequently, the use of the low-frequency clock obtained by dividing the high-frequency transmission clock frequency by the frequency division circuit as the enable signal has the following advantages. First, the operation of the shift register is usually consistent with the time period of data processing, while the high-frequency transmission clock may cause unnecessary high-frequency triggering, increasing the synchronization burden of the shift register, and the low-frequency clock is obtained by dividing the high-frequency transmission clock, and its phase is consistent with the phase of the high-frequency transmission clock. At this time, using a lower clock frequency can ensure that the shift register is only operated when needed, avoiding multiple unnecessary shifts introduced by the high-frequency clock and reducing the synchronization burden. Second, the high-frequency transmission clock will make it easy for the synchronization pulse signal to cause timing conflicts or jitters when it is transmitted between different subsystem boards, while the use of a low-frequency clock reduces the complexity of timing operations, while ensuring that the operation of the shift register is synchronized with other clocks, reducing timing conflicts and jitters.Third, by using a high-frequency transmission clock signal as an enable signal, the shift register may be triggered frequently, while most data processing operations in the system may not require such a high clock frequency. Using a low-frequency clock will only trigger the shift operation when needed, thereby reducing the power consumption of the system.

[0085] Further, in one embodiment of the present invention, the phase information reading unit is connected to the control module and the clock phase information latch unit in each subsystem board through a communication bus, wherein the phase information reading unit includes a third register, the clock phase information latch unit includes a clock phase information locking subunit and a phase information storage subunit, wherein the clock phase information locking subunit includes a shift register, and the phase information storage subunit includes a fourth register, wherein the fourth register stores the clock phase information output by the shift register, wherein the clock phase information indicates the synchronization state between the local receiving clock of the subsystem board and the high-frequency transmitting clock, at this time, the third register is connected to the control module and the fourth register of each subsystem board through a communication bus, wherein the third register is used to read the content of the fourth register in each subsystem board, specifically, at the beginning of each reading operation, the control module sends a selection signal or address to the communication bus, indicating the subsystem board to be read by the third register (i.e., the selection of the fourth register). At this time, the control module triggers the third register to read data from the fourth register of the currently selected subsystem board through a specific control signal (such as a "read enable" signal). At this time, the third register latches the clock phase information transmitted from the fourth register of the subsystem board through the communication bus under the instruction of the control module. The clock phase information is transmitted to the third register of the main system board and temporarily saved until the control module reads the data from the third register. Then the control module updates the selection signal according to the preset polling mechanism, points to the fourth register of the next subsystem board, and repeats the above process. The control module polls different subsystem boards and selects to communicate with them one by one, so that the value of the fourth register of each subsystem board can be read sequentially. At this time, the control module stores the value of the fourth register of each subsystem board read by the third register in the internal cache respectively. Then, whenever the control module reads the value of the fourth register, it compares the values ​​of the fourth registers of different subsystem boards to determine whether they are synchronized. If the values ​​of the fourth registers of all subsystem boards are consistent, it means that the clocks of each subsystem board have been synchronized; if they are inconsistent, it means that the clocks of some subsystem boards have not been synchronized. At this time, the control module will continue to issue control instructions to correct the inconsistent clocks through the phase-locked loop circuit of each subsystem board.

[0086] Furthermore, in one embodiment of the present invention, the phase-locked loop circuit in each subsystem board is respectively connected to the clock distribution module, the pulse synchronization unit and the clock phase information locking module, and is specifically responsible for synchronizing the local transmission clock of each subsystem board with the high-frequency transmission clock of the main system board to ensure that the clock on the subsystem board is consistent with the clock on the main system board. The phase-locked loop circuit (PLL) dynamically adjusts the phase and frequency of the local clock to match the reference clock (i.e., the high-frequency transmission clock), thereby achieving clock synchronization.

[0087] Specifically, the phase-locked loop circuit includes various input terminals and output terminals, wherein the input terminals include a reference clock terminal (tx_clk), a feedback clock terminal (fb_clk) and a control signal terminal (pll_sync), wherein the output terminals include a local transmit clock terminal (tx_clk_local) and a local receive clock terminal (rx_clk_local), wherein the reference clock terminal of the phase-locked loop circuit is connected to a clock driver, the feedback clock terminal is connected to a local transmit clock terminal, the control signal terminal is connected to a synchronization circuit in a pulse synchronization unit, and the local transmit clock terminal and the local receive clock terminal are respectively connected to a clock phase information latch unit, specifically, the reference clock terminal, the feedback clock terminal and the control signal terminal respectively input a reference clock, a feedback clock and a control signal, and the local transmit clock terminal and the local receive clock terminal respectively output a local transmit clock and a local receive clock, wherein the reference clock is the main input signal of the phase-locked loop circuit, generated by a clock source and distributed to each subsystem board through a clock driver, wherein the high-frequency transmit clock is the reference clock to be synchronized by all subsystem boards in the system. The feedback clock is the local transmission clock of the subsystem board that is fed back to the phase-locked loop circuit as a reference, where the phase-locked loop circuit compares the feedback clock with the high-frequency transmission clock to detect the phase difference between the two. The control signal is the synchronization pulse signal generated by the control module on the main system board through the pulse synchronization unit, which is used to control the phase-locked loop circuit to start the synchronization process. The local transmission clock is a clock signal adjusted and synchronized by the phase-locked loop circuit. The local transmission clock is used to drive the core circuits such as high-speed digital logic, data processing and transmission modules inside the subsystem board, especially in the transmission link (such as signal modulation, transmission, etc.). Since the processing speed of the transmitter usually needs to be kept high, the local transmission clock is designed to be synchronized with the high-frequency transmission clock of the main system board to ensure that the system's transmission link has a consistent time reference and high frequency. The local receiving clock is also generated by the phase-locked loop circuit and used as the reference clock of the receiving end ADC (analog-to-digital converter) and the clock signal of the second FPGA module. The local receiving clock is designed to be synchronized with the local transmitting clock, but may have different frequency adjustments according to different system requirements. The specific local receiving clock usually uses a low-frequency clock after the high-frequency transmitting clock is divided. Since the ADC (analog-to-digital converter) usually requires a lower frequency clock signal to match the signal bandwidth and sampling accuracy requirements, the local receiving clock is designed as a low-frequency clock, so that when the sampling rate of the ADC matches the signal bandwidth, the low-frequency clock can provide the ADC with better signal integrity and sampling accuracy. That is, the reason for setting up the local transmitting clock and the local receiving clock is that different hardware modules have different clock frequency requirements. The transmitting end (such as modulation, transmitter) requires a high-frequency clock to ensure the data transmission rate, while the ADC at the receiving end requires a lower frequency clock for accurate signal sampling.The two clock signals are generated by the phase-locked loop circuit to ensure that the transmitting and receiving links in the system can operate at different frequencies, while maintaining the clock synchronization between the subsystem board and the main system board. Although the local transmitting clock and the local receiving clock have different frequencies, they are phase-synchronized through the phase-locked loop circuit to ensure that the time bases between different clocks in the system are consistent, thereby ensuring that there is no delay or phase deviation between the receiving and transmitting signals. It should be pointed out that in a communication system with multiple subsystems or multiple subsystem boards, the asynchronization of the transmitting and receiving clocks will lead to phase inconsistency in data transmission. This inconsistency may cause errors in data reception, signal loss, and even system crash. At this time, the clock is dynamically adjusted by the phase-locked loop circuit so that the output local transmitting clock and the local receiving clock are synchronized with the phase of the reference clock, which can ensure that during the data transmission process, the operations between the subsystem boards are performed under the same time base, thereby avoiding errors caused by clock asynchrony.

[0088] The phase-locked loop circuit includes a phase detector (PD), a loop filter (LF), a voltage-controlled oscillator (VCO), and a divider. The phase detector is used to compare the phase difference between the input reference clock signal and the feedback clock and generate an error signal. The loop filter is used to low-pass filter the error signal and smooth the output signal to reduce jitter and high-frequency noise. The voltage-controlled oscillator is used to adjust the oscillation frequency according to the voltage output by the loop filter so that the output clock and the reference clock are in phase. The divider is used to reduce the high-frequency clock signal to the desired frequency. Specifically, the phase detector in the phase-locked loop circuit compares the phase difference between the input reference clock (that is, the high-frequency transmission clock) and the feedback clock (local transmission clock) in real time. If the phase of the feedback clock is ahead of or behind the reference clock, the phase detector will generate a corresponding error signal (called phase error). At this time, the phase error signal is sent to the loop filter, which filters out the high-frequency noise and leaves a smooth control signal, which is used to adjust the frequency of the voltage-controlled oscillator. The voltage-controlled oscillator adjusts the clock frequency of its output according to the filtered control signal, and the output signal of the voltage-controlled oscillator is also the local transmit clock of the phase-locked loop circuit. At this time, the frequency of the voltage-controlled oscillator will change dynamically until the frequency and phase of the local transmit clock are completely consistent with the reference clock (that is, the high-frequency transmit clock). The local transmit clock generated at the same time is fed back to the phase detector as a feedback clock for continuous comparison with the reference clock to ensure continuous synchronization. If the phase difference still exists, the phase-locked loop circuit will continue to adjust the local transmit clock, through continuous feedback and adjustment, until the two are completely synchronized. Therefore, the phase-locked loop circuit synchronizes the local transmit clock of each subsystem board with the high-frequency transmit clock generated by the clock source through real-time phase comparison and dynamic frequency adjustment of the voltage-controlled oscillator. At the same time, the phase-locked loop circuit reduces the high-frequency transmit clock to the required receive clock frequency according to a specific division ratio through the internal frequency division circuit. Then, referring to the above, the phase detector compares the phase of the divided low-frequency clock with the input reference clock (that is, the high-frequency transmit clock), and adjusts the output frequency of the voltage-controlled oscillator through the error signal, so that the local receive clock is gradually synchronized with the reference clock, and finally generates a lower frequency local receive clock.

[0089] Furthermore, referring to the above, when the control module outputs a synchronization control signal to the pulse synchronization unit so that the pulse synchronization unit generates a synchronization pulse signal and sends it to the phase-locked loop circuit, the phase-locked loop circuit will immediately enter the synchronization mode after receiving the synchronization pulse signal and start to perform the clock synchronization operation. In the synchronization mode, the phase-locked loop circuit will recalibrate its local transmission clock to ensure that the local transmission clock is synchronized with the high-frequency transmission clock signal as a synchronization reference in phase and frequency. Specifically, the internal circuit of the phase-locked loop circuit usually monitors the synchronization control signal from the outside. When the synchronization pulse signal is transmitted to the control signal end of the phase-locked loop circuit, the phase-locked loop circuit detects the rising edge or falling edge of the synchronization pulse signal (depending on the design) and identifies it as a synchronization trigger signal. After receiving the synchronization pulse signal, the phase-locked loop circuit enters a reset or recalibration mode. At this time, the phase-locked loop circuit clears the previous phase lock state and restarts to capture the phase information of the high-frequency transmission clock. The phase comparator inside the phase-locked loop circuit will adjust the output frequency and phase of the voltage-controlled oscillator according to the new round of phase comparison results, so that the local transmission clock output by it is synchronized with the reference clock again. When the phase-locked loop circuit reduces the phase difference between the local transmission clock and the reference clock to an acceptable range through adjustment, the phase-locked loop circuit re-enters the locked state, indicating that the clocks have been synchronized.

[0090] Furthermore, the synchronization pulse signal generated by the pulse synchronization unit is transmitted to the phase-locked loop circuit of each subsystem board through the PCB connection. If there is uneven delay in the transmission path, or jitter occurs during signal transmission (jitter refers to the instability of the phase of the clock signal in time), the synchronization pulse signals received by the phase-locked loop circuits of different subsystem boards may have slight time differences, resulting in asynchrony when the phase-locked loop circuit is adjusted. Or there may be slight manufacturing differences in the hardware implementation of each subsystem board, such as differences in parameters such as capacitance and inductance in the circuit, and the response speed of the phase-locked loop circuit. These hardware differences will cause the phase-locked loop circuits on different subsystem boards to adjust the frequency and phase at different speeds after the synchronization pulse signal arrives, so that during the initial clock synchronization, the local receiving clock of some subsystem boards may not be completely synchronized with the local transmitting clock. At the same time, the adjustment of the phase-locked loop circuit is a dynamic process. The phase-locked loop circuit generates an error signal according to the phase difference and gradually adjusts the output local receiving clock through the feedback mechanism. This adjustment process takes a certain amount of time. If the phase-locked loop adjustment speed of some sub-boards is relatively slow or the adjustment process is not completely stable, it may cause the local receiving clock and the local transmitting clock to be not completely consistent during the initial synchronization. Therefore, in order to determine whether the clocks of each subsystem board are completely synchronized, a clock calibration mechanism is also designed to determine whether the clocks of each subsystem board are completely synchronized.

[0091] Further, in one embodiment of the present invention, the clock phase information latch unit is connected to the phase-locked loop circuit, the clock calibration enabling unit and the phase information reading unit respectively, wherein the clock phase information latch unit includes a clock phase information locking subunit and a phase information storage subunit, and the specific clock phase information locking subunit includes a shift register (Shift Register), wherein the shift register includes an input data signal terminal (shift_in), a clock signal terminal (clk), an enable signal terminal (enable) and a data output terminal (data_out), the input data signal terminal, the clock signal terminal and the enable signal terminal respectively input the above-mentioned input data signal, the clock signal and the enable signal, the data output terminal outputs the captured or processed information related to the input data signal, the specific input data signal terminal and the clock signal terminal of the shift register are respectively connected to the local receiving clock terminal and the local transmitting clock terminal of the phase-locked loop circuit, the enable signal terminal of the shift register is connected to the pulse generating circuit, and the data output terminal of the shift register is connected to the fourth register, at this time, the shift register is used to capture and lock the clock phase information related to the local receiving clock, wherein the specific working principle of the shift register is: the local transmitting clock is used as the clock signal of the shift register, the register is controlled to shift each cycle, and the input data signal (that is, the phase information of the local receiving clock) input by the input data signal terminal is gradually stored in the shift register, which is similar to the FIFO (first in first out) queue operation. When the shift register receives the low-frequency pulse enable signal output from the pulse generating circuit, the shift operation is activated, that is, the shift register will start to capture and process the phase information of the local receiving clock in each clock cycle of the local transmitting clock, and shift and store it. At this time, the shift register is continuously shifted by the local transmitting clock under the control of the low-frequency pulse enable signal until the phase information related to the local receiving clock is captured and locked. When the low-frequency pulse enable signal ends, the shift operation stops, and the shift register locks the stored phase information and outputs it to the fourth register. It should be pointed out that in the embodiment of the present invention, a low-frequency pulse enable signal is used to control the operation of the shift register, rather than directly relying on the high-frequency transmitting clock signal, mainly because the low-frequency pulse enable signal can accurately control when the shift register starts working, avoiding the shift register from being frequently triggered in unnecessary clock cycles. At the same time, the use of a low-frequency pulse enable signal reduces unnecessary energy consumption and reduces the unstable effects caused by clock jitter. In addition, under the control of the low-frequency pulse enable signal, the shift register can have sufficient time to capture stable data and avoid phase confusion caused by the high-frequency clock.

[0092] Further, in one embodiment of the present invention, the control module is connected to the first FPGA module via a communication bus. Specifically, the communication bus is used to transmit digital control signals and relatively low-speed data exchange, and is suitable for low-speed, non-time-sensitive data, such as control commands and feedback information. This communication bus connection is usually for flexibly processing complex control logic and data exchange, and has the advantage of good scalability and supports parallel or serial communication between multiple signals, protocols and devices. The phase information reading unit and the phase information storage module in each subsystem board are connected via a communication bus. Specifically, reading and transmitting phase information is usually based on the exchange of data signals, and the transmission rate can be slightly slower than the real-time control signal. This connection method is more suitable for using a communication bus, because the reading and storage of phase information does not require very high real-time performance, but requires reliability and flexibility. The communication bus allows multiple devices to transmit information through a shared channel, which can reduce the complexity of wiring and support remote reading and control. The pulse synchronization unit is connected to the phase-locked loop circuit in each subsystem board via a PCB connection. Specifically, the synchronization pulse signal requires high real-time performance and low latency. In the clock synchronization system, the timing requirements of the synchronization pulse signal are very strict, and it is used to directly control the phase-locked loop circuit to achieve synchronization. Therefore, the use of PCB wiring is to reduce the delay and jitter in signal transmission, thereby ensuring the synchronization accuracy and reliability of the clock signal. In addition, the pulse signal is usually a high-frequency signal, and the use of PCB wiring can avoid the delay and potential signal integrity problems caused by the communication bus. The transmission path of the PCB wiring is more direct, which is conducive to maintaining the phase consistency and stability of the signal. The clock calibration enable unit is connected to the clock phase information latch unit in each subsystem board through a PCB connection. Specifically, the low-frequency pulse enable signal also has extremely high requirements for time accuracy and synchronization control. The use of PCB wiring can ensure the minimization of signal transmission delay and high-precision transmission. Since the low-frequency pulse enable signal directly affects the synchronization correction of the clock, the low-frequency pulse enable signal must be synchronously transmitted to the clock phase information latch unit in each subsystem board as quickly as possible to ensure the accuracy and real-time performance of the calibration operation. At the same time, although the processing speed of the communication bus is very fast, it will still introduce a certain transmission delay and protocol overhead, which is not suitable for these time-sensitive signal transmissions, which will affect the precise control of the timing. Direct, low-latency transmission methods such as PCB wiring can avoid these problems and achieve higher synchronization accuracy. Therefore, in the embodiment of the present invention, the communication bus is used for the transmission of digital data and control signals, which is suitable for low-speed, non-time-sensitive data. For synchronization pulse signals and low-frequency pulse enable signals, which are usually high-frequency, high-precision control signals, using PCB wiring can avoid signal integrity problems that may be caused by the communication bus.

[0093] Further, in one embodiment of the present invention, the control module is connected to the first register, the second register and the third register through the communication bus, respectively, and is used to generate a synchronization control signal to the first register to control the clock synchronization of each subsystem board, and to generate a clock calibration signal to the second register, and to determine whether clock synchronization is achieved according to the clock phase information of each subsystem board obtained in sequence by the third register, and to continue to generate a synchronization control signal and a clock calibration signal to the first register and the second register respectively when it is determined that clock synchronization is not achieved, until each subsystem board achieves clock synchronization. The control module can be a control device with the function of controlling and processing signals, such as a single-chip microcomputer, a DSP (Digital Signal Processing), etc., which is set according to the actual use requirements of the user and is not limited here.

[0094] Specifically, when the control module of the main system board needs to start clock synchronization for each subsystem board in the initial state, the control module generates a synchronization control signal to the first register (that is, writes a specific value to the first register). At this time, the value of the first register changes (for example, from 0 to 1), wherein the synchronization circuit generates a synchronization pulse signal (such as a rising edge pulse or a falling edge pulse) according to the change of the first register, and sends it to the phase-locked loop circuit of each subsystem board through the PCB connection, so that the phase-locked loop circuit of each subsystem board starts the synchronization process according to the received synchronization pulse signal. After the synchronization of the phase-locked loop circuits of each subsystem board is completed, the control module generates a clock calibration signal to the second register (that is, writes a specific value to the second register), and at the same time, the frequency division circuit divides the high-frequency transmission clock pulse generated by the clock source into a low-frequency clock signal, wherein the pulse generation circuit generates a low-frequency pulse enable signal according to the change of the second register and the low-frequency clock signal output by the frequency division circuit, and outputs it to each subsystem board The enable signal end of the shift register of the card, and the input data signal end and the clock signal end of the shift register are respectively connected to the local receiving clock end and the local transmitting clock end of the phase-locked loop circuit. At this time, the clock phase information related to the local receiving clock is locked under the shift operation of the shift register and output to the fourth register. At this time, the third register latches the clock phase information transmitted from the fourth register through the communication bus according to the order of each subsystem board card until the control module reads the data from the third register. At this time, the control module can store the clock phase information of the fourth register in each subsystem board card in the internal cache, and compare the clock phase information to determine whether they are consistent. If the values ​​of the fourth registers of all subsystem boards are consistent, it means that the clocks of each subsystem board card have been synchronized; if they are inconsistent, it means that the clocks of some subsystem boards have not been synchronized. At this time, the control module will continue to send the above-mentioned synchronization control signal and clock calibration signal to the first register and the second register until each subsystem board card achieves clock synchronization. Among them, when the control module detects that the values ​​of the fourth registers on different subsystem boards are inconsistent and determines that the local receiving clock has not been fully synchronized, the control module can control the synchronization circuit to send a new synchronization pulse signal, and continue to drive the phase-locked loop circuit of each subsystem board to make adjustments to restart the synchronization operation of the phase-locked loop circuit until it is detected that the values ​​of the fourth registers of all subsystem boards are completely consistent and it is determined that each subsystem board has completed clock synchronization.

[0095] In summary, the ultrasonic equipment clock synchronization system in the above-mentioned embodiment of the present invention adopts a high-frequency transmission clock as a reference signal and uses a pulse synchronization unit to generate a synchronization pulse signal to ensure that the local transmission clock generated by each subsystem board is synchronized with the high-frequency transmission clock, thereby improving the accuracy of clock synchronization and avoiding the phase offset error caused by the low-frequency signal. At the same time, the high-frequency transmission clock signal has higher stability and a shorter period, which can effectively reduce the accumulation of jitter errors. By using a high-frequency signal as a reference in the clock synchronization process, the jitter noise introduced by the traditional use of a low-frequency receiving clock as a reference is avoided, the noise caused by clock inconsistency is effectively reduced, and the performance stability of the system is improved. The control module uses the clock calibration The calibrated signal and the synchronization control signal coordinate the synchronous operation of each subsystem board, and obtain the clock phase information of each board through the phase information reading unit, which can detect the synchronization state in real time and automatically continue the synchronization process when asynchrony is detected, so that the clock phase of each subsystem board is gradually calibrated to ensure that all subsystem boards are finally synchronized, which greatly reduces the noise interference caused by clock asynchrony; at the same time, by combining the clock calibration enabling unit with the phase information reading unit, the complexity of additional hardware circuit design is reduced, which facilitates the unified management and regulation of the entire system by the control module; it solves the problem that the additional jitter noise caused by the existing use of low-frequency receiving clock as a reference for clock synchronization affects the system performance.

[0096] Embodiment 2

[0097] See also Figure 3 , is a flow chart of a method for synchronizing a clock of an ultrasonic device provided by a second embodiment of the present invention. For the sake of convenience, only the part related to the embodiment of the present invention is shown. The method for synchronizing a clock of an ultrasonic device is a system for synchronizing a clock of an ultrasonic device as described in the foregoing embodiment. The method comprises:

[0098] Step S10, the control module of the main system board generates a synchronization control signal to the pulse synchronization unit, so that the pulse synchronization unit generates a synchronization pulse signal according to the synchronization control signal and sends it to the phase-locked loop circuit in each subsystem board;

[0099] Step S20, the phase-locked loop circuit in each subsystem board synchronizes the high-frequency transmission clock provided by the clock distribution module of the main system board to a local transmission clock according to the synchronization pulse signal, and generates a local receiving clock and outputs it to the clock phase information latch unit;

[0100] Step S30, the control module of the main system board generates a clock calibration signal to the clock calibration enabling unit, so that the clock calibration enabling unit generates a low-frequency pulse enabling signal according to the clock calibration signal and sends it to the clock phase information latching unit in each subsystem board;

[0101] Step S40, the clock phase information latch unit in each subsystem board locks the clock phase information related to the local receiving clock according to the low-frequency pulse enable signal and the local transmitting clock and the local receiving clock output by the phase-locked loop circuit, and outputs it to the phase information storage subunit;

[0102] Step S50, the control module of the main system board receives the clock phase information stored in the clock phase information latch unit of each subsystem board sequentially acquired by the phase information reading unit, and determines whether each subsystem board achieves clock synchronization according to the clock phase information of each subsystem board;

[0103] Step S60, when the control module of the main system board determines that each subsystem board has not achieved clock synchronization, it continues to generate a synchronization control signal to the pulse synchronization unit and a clock calibration signal to the clock calibration enabling unit until it is determined that each subsystem board has achieved clock synchronization.

[0104] The implementation principle and technical effects of the ultrasonic equipment clock synchronization method provided in the embodiment of the present invention are the same as those of the aforementioned device embodiment. For the sake of brief description, for matters not mentioned in the method embodiment, reference may be made to the corresponding contents in the aforementioned device embodiment.

[0105] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0106] The above-described embodiments only express several implementation methods of the present invention, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the scope of the present invention. It should be pointed out that, for a person of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the attached claims.

Claims

1. An ultrasonic equipment clock synchronization system, characterized in that: It includes a main system board and a plurality of subsystem boards connected to the main system board and performing clock synchronization; The main system board includes a control module, a clock distribution module and a first FPGA module, and each subsystem board includes a phase-locked loop circuit and a second FPGA module; The first FPGA module includes a pulse synchronization unit, a clock calibration enabling unit and a phase information reading unit, and the second FPGA module includes a clock phase information latching unit; The clock distribution module is connected to the clock calibration enabling unit and the phase-locked loop circuit in each subsystem board, and is used to provide a high-frequency transmission clock signal as a synchronization reference; The pulse synchronization unit is connected to the control module and the phase-locked loop circuit in each subsystem board respectively, and is used to generate a synchronization pulse signal according to the synchronization control signal output by the control module and send it to the phase-locked loop circuit; The clock calibration enabling unit is respectively connected to the control module, the clock distribution module and the clock phase information latching unit in each subsystem board, and is used to generate a low-frequency pulse enabling signal according to the clock calibration signal output by the control module and send it to the clock phase information latching unit; The phase information reading unit is connected to the control module and the clock phase information latch unit in each subsystem board respectively, and is used to sequentially obtain the clock phase information stored in the clock phase information latch unit in each subsystem board according to the control of the control module and transmit it to the control module; The phase-locked loop circuit is connected to the clock distribution module, the pulse synchronization unit and the clock phase information latch unit respectively, and is used to synchronize the high-frequency transmission clock signal provided by the clock distribution module to a local transmission clock according to the synchronization pulse signal sent by the pulse synchronization unit, and generate a local receiving clock and output it to the clock phase information latch unit; The clock phase information latch unit is connected to the phase-locked loop circuit, the clock calibration enable unit and the phase information reading unit respectively, and is used to lock the clock phase information related to the local receiving clock according to the low-frequency pulse enable signal output by the clock calibration enable unit, and the local transmitting clock and the local receiving clock output by the phase-locked loop circuit, and send it to the phase information reading unit; The control module is respectively connected to the pulse synchronization unit, the clock calibration enabling unit and the phase information reading unit, and is used to generate a synchronization control signal to the pulse synchronization unit to control the clock synchronization of each subsystem board, and to generate a clock calibration signal to the clock calibration enabling unit, and to receive the clock phase information stored in the clock phase information latch unit in each subsystem board acquired in sequence by the phase information reading unit, and to judge whether each subsystem board achieves clock synchronization according to the clock phase information of each subsystem board, and to continue to generate a synchronization control signal and a clock calibration signal when it is judged that clock synchronization is not achieved, until each subsystem board achieves clock synchronization.

2. The ultrasound equipment clock synchronization system according to claim 1, characterized in that: The clock distribution module comprises: A clock source, used to generate a high-frequency transmit clock signal; And a clock driver connected to the clock source and the phase-locked loop circuit of each subsystem board respectively, for distributing the high-frequency transmission clock signal generated by the clock source to the phase-locked loop circuit of each subsystem board.

3. The ultrasound equipment clock synchronization system according to claim 1, characterized in that: The pulse synchronization unit comprises: a first register connected to the control module, and configured to receive a synchronization control signal generated by the control module; And a synchronization circuit connected to the first register and the phase-locked loop circuit in each subsystem board respectively, for generating a synchronization pulse signal and sending it to the phase-locked loop circuit when acquiring the synchronization control signal received by the first register.

4. The ultrasound equipment clock synchronization system according to claim 1, characterized in that: The clock calibration enabling unit comprises: A frequency division circuit connected to the clock distribution module, used for dividing the high-frequency transmission clock signal provided by the clock distribution module into a low-frequency clock signal; a second register connected to the control module, and configured to receive a clock calibration signal generated by the control module; And a pulse generating circuit respectively connected to the frequency dividing circuit, the second register, and the clock phase information latch unit in each subsystem board, for generating a low-frequency pulse enable signal according to the low-frequency clock signal and sending it to the clock phase information latch unit when the clock calibration signal received by the second register is obtained.

5. The ultrasound equipment clock synchronization system according to claim 1, characterized in that: The reference clock end of the phase-locked loop circuit is connected to the clock distribution module, the feedback clock end of the phase-locked loop circuit is connected to the local transmission clock end, the control signal end of the phase-locked loop circuit is connected to the pulse synchronization unit, and the local transmission clock end and the local reception clock end of the phase-locked loop circuit are respectively connected to the clock phase information latch unit.

6. The ultrasound equipment clock synchronization system according to claim 5, characterized in that: The clock phase information latch unit comprises: A clock phase information locking subunit connected to the phase-locked loop circuit and the clock calibration enabling unit, used to lock the clock phase information related to the local receiving clock according to the low-frequency pulse enabling signal output by the clock calibration enabling unit, and the local transmitting clock and the local receiving clock output by the phase-locked loop circuit; And a phase information storage subunit connected to the clock phase information locking subunit and the phase information reading unit respectively, used for storing the clock phase information output by the clock phase information locking subunit and sending it to the phase information reading unit.

7. The ultrasound equipment clock synchronization system according to claim 6, characterized in that: The clock phase information locking subunit includes a shift register, an input data signal terminal of the shift register is connected to a local receiving clock terminal of the phase-locked loop circuit, a clock signal terminal of the shift register is connected to a local transmitting clock terminal of the phase-locked loop circuit, an enable signal terminal of the shift register is connected to the clock calibration enable unit, and an output data terminal of the shift register is connected to the phase information reading unit.

8. The ultrasound equipment clock synchronization system according to claim 1, characterized in that: The control module is connected to the first FPGA module via a communication bus, the phase information reading unit is connected to the phase information storage module in each subsystem board via a communication bus, the pulse synchronization unit is connected to the phase-locked loop circuit in each subsystem board via a PCB connection, and the clock calibration enabling unit is connected to the clock phase information latch unit in each subsystem board via a PCB connection.

9. The ultrasound equipment clock synchronization system according to claim 8, characterized in that: The phase information reading unit includes a third register, and the phase information storage subunit includes a fourth register.

10. A method for synchronizing a clock of an ultrasonic device, characterized in that: The method applied to the ultrasound equipment clock synchronization system according to any one of claims 1 to 9 comprises: The control module of the main system board generates a synchronization control signal to the pulse synchronization unit, so that the pulse synchronization unit generates a synchronization pulse signal according to the synchronization control signal and sends it to the phase-locked loop circuit in each subsystem board; The phase-locked loop circuit in each subsystem board synchronizes the high-frequency transmission clock provided by the clock distribution module of the main system board to the local transmission clock according to the synchronization pulse signal, and generates a local receiving clock and outputs it to the clock phase information latch unit; The control module of the main system board generates a clock calibration signal to the clock calibration enabling unit, so that the clock calibration enabling unit generates a low-frequency pulse enabling signal according to the clock calibration signal and sends it to the clock phase information latching unit in each subsystem board; The clock phase information latch unit in each subsystem board locks the clock phase information related to the local receiving clock according to the low-frequency pulse enable signal and the local transmitting clock and the local receiving clock output by the phase-locked loop circuit, and outputs it to the phase information storage subunit; The control module of the main system board receives the clock phase information stored in the clock phase information latch unit of each subsystem board sequentially acquired by the phase information reading unit, and determines whether each subsystem board realizes clock synchronization according to the clock phase information of each subsystem board; When the control module of the main system board determines that each subsystem board has not achieved clock synchronization, it continues to generate synchronization control signals to the pulse synchronization unit and generates clock calibration signals to the clock calibration enabling unit until it is determined that each subsystem board has achieved clock synchronization.

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