Data transmission method and device, network card, network card chip and computer

Abstract

The invention provides a data transmission method and device, a network card, a network card chip and a computer. In an embodiment, a first network card receives a plurality of data requests, the plurality of data requests are respectively from different virtual processors in a first processor, and destination nodes of the data requests are different; the first network card adds the plurality of data requests into core queues, each virtual processor corresponds to one core queue, and the data requests from different virtual processors enter different core queues; the first network card extracts the plurality of data requests from the core queue and adds the plurality of data requests into the shared queues according to the destination node of each data request in the plurality of data requests, each destination node corresponds to one shared queue, and the data requests with the same destination node enter the same shared queue; and the first network card takes out the plurality of data requests from the shared queue, and sends the plurality of data requests to a destination computer system where the corresponding destination node is located. Therefore, the time delay of data transmission is reduced, and the occupation of CPU resources in the nodes is reduced.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a data transmission method, device, network card, network card chip and computer. Background Art

[0002] With the rapid development of cloud computing, big data, the Internet of Things, artificial intelligence and other related industries, the requirements of network communications for data transmission delay are also increasing.

[0003] The Remote Direct Memory Access OverConverged Ethernet (RoCE) protocol provides a remote memory access capability from Internet Protocol (IP) to IP. Based on the RoCE protocol, processes transmit data through queue pairs (QP) established between nodes. Among them, QP only supports one-to-one service, that is, a message in a QP can only reach another certain node from one node, and data transmission cannot meet the needs of network communication.

[0004] Therefore, there is an urgent need for a data transmission method based on the RoCE protocol to meet current network communication needs. Summary of the invention

[0005] The embodiments of the present application provide a data transmission method, device, network card, network card chip and computer, which can reduce the delay of data transmission.

[0006] In a first aspect, an embodiment of the present application provides a data transmission method, wherein a first computer system includes a first node and a first network card, the first node includes a first processor, the first node communicates with the first network card through a bus, and the first node communicates with multiple computer systems through the first network card, the method comprising:

[0007] The first network card receives multiple data requests, the multiple data requests are respectively from different virtual processors in the first processor, and the destination node of each data request is different;

[0008] The first network card adds the multiple data requests to the core queues respectively, wherein each virtual processor corresponds to a core queue, and the data requests from different virtual processors enter different core queues;

[0009] The first network card takes out multiple data requests from the core queue, and adds the multiple data requests to the shared queue respectively according to the destination nodes of each of the multiple data requests, wherein each destination node corresponds to a shared queue, and data requests with the same destination node enter the same shared queue;

[0010] The first network card takes out multiple data requests from the shared queue, and sends the multiple data requests to a destination computer system where the corresponding destination nodes are located.

[0011] According to this solution, through the two-layer QP architecture in the network card, the two-layer QP architecture includes multiple core QPs in the first layer and multiple shared QPs in the second layer. Among them, each core QP corresponds to a virtual processor in the node one by one, so that the virtual processor in the node can monopolize the core QP, and then data requests from different virtual processors are added to different core queues. Each shared QP corresponds to a node in the network one by one, and a single shared QP supports data transmission of multiple core QPs.

[0012] Taking sending data requests as an example, if the processor sending the data request is called the source processor, the node receiving the data request is called the destination node (generally, the destination virtual processor in the destination node is the final recipient of the data). For multiple data requests from different source virtual processors and sent to the same destination node, they first arrive at the core QP corresponding to each source virtual processor, and then arrive at the shared QP corresponding to the destination node. In this way, the virtual processor can monopolize the core QP, meeting the demand for the virtual processor to monopolize the QP; and a single shared QP can support data transmission of multiple core QPs, reducing the CPU overhead in the node.

[0013] In a possible implementation, the first network card is configured with first mapping relationship information, the first mapping relationship information is used to indicate a mapping relationship between an identity of a node and an identity of a shared queue, and according to a destination node of each of the multiple data requests, the multiple data requests are added to the shared queue respectively, including:

[0014] According to the identity of the destination node, determine the identity of the shared queue corresponding to the destination node from the first mapping relationship information;

[0015] According to the identity of the shared queue corresponding to the destination node, the data request is added to the shared queue.

[0016] In this way, nodes in the network can monopolize the shared queue, so that multiple virtual processors can transmit data with multiple nodes, reducing data transmission latency.

[0017] In a possible implementation, the first network card is configured with second mapping relationship information, the second mapping relationship information is used to indicate a mapping relationship between an identity of a virtual processor and an identity of a core queue, the data request includes the identity of the virtual processor from which the data request comes, and multiple data requests are added to the core queue respectively, including:

[0018] According to the identity of the virtual processor from which each of the multiple data requests comes, determining the identity of the core queue to which each of the data requests is to be added from the second mapping relationship information;

[0019] According to the identity identifier of the core queue, multiple data requests are added to the core queue respectively.

[0020] In this way, the virtual processors in the node can monopolize the core QP without the need to preempt resources in the CPU, thus reducing CPU resource usage.

[0021] In a second aspect, an embodiment of the present application provides a data transmission method, wherein a second computer system includes a second node and a second network card, the second node includes a second processor, the second node communicates with the second network card through a bus, and the second node communicates with multiple computer systems through the second network card, the method comprising:

[0022] The second network card receives multiple data requests, where the multiple data requests come from different nodes;

[0023] The second network card adds the multiple data requests to the shared queue respectively, wherein each node corresponds to a core queue, and the data requests from the same node enter the same shared queue;

[0024] The second network card takes out multiple data requests from the shared queue, and adds the multiple data requests to the core queue respectively according to the destination virtual processor of each of the multiple data requests, wherein the data requests with different destination virtual processors enter different core queues;

[0025] The second network card takes out multiple data requests from the core queue and sends the multiple data requests to corresponding destination virtual processors.

[0026] According to this solution, through the two-layer QP architecture in the network card, the two-layer QP architecture includes multiple core QPs in the first layer and multiple shared QPs in the second layer. Among them, each core QP corresponds to a virtual processor in the node one by one, so that the virtual processor in the node can monopolize the core QP, and then the data requests of different destination virtual processors are added to different core queues. Each shared QP corresponds to a node in the network one by one, and a single shared QP supports data transmission of multiple core QPs.

[0027] Taking receiving data requests as an example, if the node sending the data request is called the source node, the virtual processor receiving the data request is the destination virtual processor (generally, the destination virtual processor is the final recipient of the data request). For multiple data requests from the same source node and sent to different destination virtual processors, the multiple data requests can be added to the shared QP corresponding to the source node, and then reach the core QP corresponding to each destination virtual processor. In this way, the virtual processor can monopolize the core QP, meeting the demand for the virtual processor to monopolize the QP; and a single shared QP can support data transmission of multiple core QPs, reducing the CPU overhead in the node.

[0028] In a possible implementation manner, the second network card includes first mapping relationship information, where the first mapping relationship information is used to indicate a mapping relationship between an identity of a node and an identity of a shared queue, the data request includes an identity of a node from which the data request comes, and the multiple data requests are added to the shared queue respectively, including:

[0029] According to the identity of the node in each data request in the multiple data requests, determine the identity of the shared queue corresponding to the node from the first mapping relationship information;

[0030] According to the identity identifier of the shared queue, multiple data requests are added to the corresponding shared queue respectively.

[0031] In this way, nodes in the network can monopolize the shared queue, so that multiple virtual processors can transmit data with multiple nodes, reducing data transmission latency.

[0032] In a possible implementation, the second network card includes second mapping relationship information, the second mapping relationship information is used to indicate a mapping relationship between an identity of a virtual processor and an identity of a core queue, the data request includes an identity of a destination virtual processor of the data request, and according to the destination virtual processor of each of the multiple data requests, the multiple data requests are respectively added to the core queue, including:

[0033] According to the identity of the destination virtual processor of each data request, determining the identity of the core queue corresponding to the destination virtual processor from the second mapping relationship information;

[0034] According to the identity of the core queue corresponding to the destination virtual processor, the data request is added to the corresponding core queue.

[0035] In this way, the virtual processors in the node can monopolize the core QP without the need to preempt resources in the CPU, thus reducing CPU resource usage.

[0036] In a third aspect, an embodiment of the present application provides a data transmission device, wherein a first computer system includes a first node and a first network card, the first node includes a first processor, the first node communicates with the first network card through a bus, the first node communicates with multiple computer systems through the first network card, the device is applied to the first network card, and the device includes:

[0037] A receiving module, used for receiving multiple data requests, the multiple data requests are respectively from different virtual processors in the first processor, and the destination node of each data request is different;

[0038] A processing module, used for adding multiple data requests to core queues respectively, wherein each virtual processor corresponds to a core queue, and data requests from different virtual processors enter different core queues;

[0039] The processing module is also used to take out multiple data requests from the core queue, and add the multiple data requests to the shared queue respectively according to the destination nodes of each data request in the multiple data requests, wherein each destination node corresponds to a shared queue, and data requests with the same destination node enter the same shared queue;

[0040] The sending module is used to take out multiple data requests from the shared queue and send the multiple data requests to the destination computer system where the corresponding destination nodes are located.

[0041] According to this solution, through the two-layer QP architecture in the network card, the two-layer QP architecture includes multiple core QPs in the first layer and multiple shared QPs in the second layer. Among them, each core QP corresponds to a virtual processor in the node one by one, so that the virtual processor in the node can monopolize the core QP, and then data requests from different virtual processors are added to different core queues. Each shared QP corresponds to a node in the network one by one, and a single shared QP supports data transmission of multiple core QPs.

[0042] Taking sending data requests as an example, if the processor sending the data request is called the source processor, the node receiving the data request is called the destination node (generally, the destination virtual processor in the destination node is the final recipient of the data). For multiple data requests from different source virtual processors and sent to the same destination node, they first arrive at the core QP corresponding to each source virtual processor, and then arrive at the shared QP corresponding to the destination node. In this way, the virtual processor can monopolize the core QP, meeting the demand for the virtual processor to monopolize the QP; and a single shared QP can support data transmission of multiple core QPs, reducing the CPU overhead in the node.

[0043] In a possible implementation manner, the first network card is configured with first mapping relationship information, where the first mapping relationship information is used to indicate a mapping relationship between an identity of a node and an identity of a shared queue, and the processing module is used to:

[0044] According to the identity of the destination node, determine the identity of the shared queue corresponding to the destination node from the first mapping relationship information;

[0045] According to the identity of the shared queue corresponding to the destination node, the data request is added to the shared queue.

[0046] In this way, nodes in the network can monopolize the shared queue, so that multiple virtual processors can transmit data with multiple nodes, reducing data transmission latency.

[0047] In a possible implementation, the first network card is configured with second mapping relationship information, the second mapping relationship information is used to indicate a mapping relationship between an identity of a virtual processor and an identity of a core queue, the data request includes an identity of the virtual processor from which the data request comes, and the processing module is used to:

[0048] According to the identity of the virtual processor from which each of the multiple data requests comes, determining the identity of the core queue to which each of the data requests is to be added from the second mapping relationship information;

[0049] According to the identity identifier of the core queue, multiple data requests are added to the core queue respectively.

[0050] In this way, the virtual processors in the node can monopolize the core QP without the need to preempt resources in the CPU, thus reducing CPU resource usage.

[0051] In a fourth aspect, an embodiment of the present application provides a data transmission device, wherein a second computer system includes a second node and a second network card, the second node includes a second processor, the second node communicates with the second network card through a bus, the second node communicates with multiple computer systems through the second network card, the device is applied to the second network card, and the device includes:

[0052] A receiving module, used for receiving multiple data requests, where the multiple data requests come from different nodes;

[0053] A processing module, used for adding multiple data requests to a shared queue respectively, wherein each node corresponds to a core queue, and data requests from the same node enter the same shared queue;

[0054] The processing module is also used to take out multiple data requests from the shared queue, and add the multiple data requests to the core queue respectively according to the destination virtual processor of each data request in the multiple data requests, wherein data requests with different destination virtual processors enter different core queues;

[0055] The sending module is used to take out multiple data requests from the core queue and send the multiple data requests to the corresponding destination virtual processors.

[0056] According to this solution, through the two-layer QP architecture in the network card, the two-layer QP architecture includes multiple core QPs in the first layer and multiple shared QPs in the second layer. Among them, each core QP corresponds to a virtual processor in the node one by one, so that the virtual processor in the node can monopolize the core QP, and then the data requests of different destination virtual processors are added to different core queues. Each shared QP corresponds to a node in the network one by one, and a single shared QP supports data transmission of multiple core QPs.

[0057] Taking receiving data requests as an example, if the node sending the data request is called the source node, the virtual processor receiving the data request is the destination virtual processor (generally, the destination virtual processor is the final recipient of the data request). For multiple data requests from the same source node and sent to different destination virtual processors, the multiple data requests can be added to the shared QP corresponding to the source node, and then reach the core QP corresponding to each destination virtual processor. In this way, the virtual processor can monopolize the core QP, meeting the demand for the virtual processor to monopolize the QP; and a single shared QP can support data transmission of multiple core QPs, reducing the CPU overhead in the node.

[0058] In a possible implementation manner, the second network card includes first mapping relationship information, where the first mapping relationship information is used to indicate a mapping relationship between an identity of a node and an identity of a shared queue, the data request includes an identity of a node from which the data request comes, and the multiple data requests are added to the shared queue respectively, including:

[0059] According to the identity of the node in each data request in the multiple data requests, determine the identity of the shared queue corresponding to the node from the first mapping relationship information;

[0060] According to the identity identifier of the shared queue, multiple data requests are added to the corresponding shared queue respectively.

[0061] In this way, nodes in the network can monopolize the shared queue, so that multiple virtual processors can transmit data with multiple nodes, reducing data transmission latency.

[0062] In a possible implementation, the second network card includes second mapping relationship information, where the second mapping relationship information is used to indicate a mapping relationship between an identity of a virtual processor and an identity of a core queue, the data request includes an identity of a destination virtual processor of the data request, and the processing module is used to:

[0063] According to the identity of the destination virtual processor of each data request, determining the identity of the core queue corresponding to the destination virtual processor from the second mapping relationship information;

[0064] According to the identity of the core queue corresponding to the destination virtual processor, the data request is added to the corresponding core queue.

[0065] In this way, the virtual processors in the node can monopolize the core QP without the need to preempt resources in the CPU, thus reducing CPU resource usage.

[0066] In a fifth aspect, an embodiment of the present application provides a network card, a computer system including a network card and a node, the node including a processor, and the network card including:

[0067] Computer bus interface for communicating with nodes;

[0068] Network interfaces for communicating with other computer systems;

[0069] Processors are used to provide core queues and shared queues, and are also used to:

[0070] Obtain multiple data requests from the node through a computer bus interface, and add the multiple data requests to core queues respectively, wherein each virtual processor corresponds to a core queue, and data requests from different virtual processors enter different core queues;

[0071] Taking out multiple data requests from the core queue, and adding the multiple data requests to the shared queue respectively according to the destination nodes of each of the multiple data requests, wherein each destination node corresponds to a shared queue, and data requests with the same destination node enter the same shared queue;

[0072] Multiple data requests are taken out from the shared queue, and sent to the computer system where the corresponding destination nodes are located through the network interface.

[0073] According to this solution, through the two-layer QP architecture in the network card, the two-layer QP architecture includes multiple core QPs in the first layer and multiple shared QPs in the second layer. Among them, each core QP corresponds to a virtual processor in the node one by one, so that the virtual processor in the node can monopolize the core QP, and then data requests from different virtual processors are added to different core queues. Each shared QP corresponds to a node in the network one by one, and a single shared QP supports data transmission of multiple core QPs.

[0074] Taking sending data requests as an example, if the processor sending the data request is called the source processor, the node receiving the data request is called the destination node (generally, the destination virtual processor in the destination node is the final recipient of the data). For multiple data requests from different source virtual processors and sent to the same destination node, they first arrive at the core QP corresponding to each source virtual processor, and then arrive at the shared QP corresponding to the destination node. In this way, the virtual processor can monopolize the core QP, meeting the demand for the virtual processor to monopolize the QP; and a single shared QP can support data transmission of multiple core QPs, reducing the CPU overhead in the node.

[0075] In a sixth aspect, an embodiment of the present application provides a network card chip, a computer system includes a network card and a node, the network card and the node communicate through a computer bus, the node communicates with other nodes through the network card, and the network card includes a network card chip, a computer bus interface, and a network interface;

[0076] The network card chips include:

[0077] A power supply, used to supply power to the network card chip;

[0078] The main body of the network card chip is used to provide core queues and shared queues. The network card chip is also used to:

[0079] Adding multiple data requests to core queues respectively, wherein each virtual processor corresponds to a core queue, and data requests from different virtual processors enter different core queues;

[0080] Taking out multiple data requests from the core queue, and adding the multiple data requests to the shared queue respectively according to the destination nodes of each of the multiple data requests, wherein each destination node corresponds to a shared queue, and data requests with the same destination node enter the same shared queue;

[0081] Multiple data requests are taken out from the shared queue, and sent to the computer system where the corresponding destination nodes are located through the network interface.

[0082] According to this solution, through the two-layer QP architecture in the network card, the two-layer QP architecture includes multiple core QPs in the first layer and multiple shared QPs in the second layer. Among them, each core QP corresponds to a virtual processor in the node one by one, so that the virtual processor in the node can monopolize the core QP, and then data requests from different virtual processors are added to different core queues. Each shared QP corresponds to a node in the network one by one, and a single shared QP supports data transmission of multiple core QPs.

[0083] Taking sending data requests as an example, if the processor sending the data request is called the source processor, the node receiving the data request is called the destination node (generally, the destination virtual processor in the destination node is the final recipient of the data). For multiple data requests from different source virtual processors and sent to the same destination node, they first arrive at the core QP corresponding to each source virtual processor, and then arrive at the shared QP corresponding to the destination node. In this way, the virtual processor can monopolize the core QP, meeting the demand for the virtual processor to monopolize the QP; and a single shared QP can support data transmission of multiple core QPs, reducing the CPU overhead in the node.

[0084] In a seventh aspect, an embodiment of the present application provides a computer, characterized in that it includes a node and a network card, and the network card is used to execute the method of the first aspect, or execute the method of the second aspect.

[0085] In an eighth aspect, an embodiment of the present application provides a data transmission device, comprising: at least one memory for storing programs; and at least one processor for executing the programs stored in the memory. When the program stored in the memory is executed, the processor is used to execute the method of the first aspect, or to execute the method of the second aspect.

[0086] In a ninth aspect, an embodiment of the present application provides a data transmission device, characterized in that the device runs computer program instructions to execute the method of the first aspect, or execute the method of the second aspect. Exemplarily, the device may be a chip or a processor.

[0087] In one example, the device may include a processor, which may be coupled to a memory, read instructions in the memory and execute the method provided in the first aspect according to the instructions, or execute the method provided in the second aspect. The memory may be integrated in a chip or a processor, or may be independent of the chip or the processor.

[0088] In the tenth aspect, an embodiment of the present application provides a computer storage medium, in which instructions are stored. When the instructions are executed on a computer, the computer executes the method described in the first aspect, or executes the method described in the second aspect.

[0089] In the eleventh aspect, an embodiment of the present application provides a computer program product comprising instructions, which, when executed on a computer, enables the computer to execute the method described in the first aspect, or execute the method described in the second aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0090] Figure 1 It is a schematic diagram of inter-process communication based on the RoCE protocol provided in an embodiment of the present application;

[0091] Figure 2 It is a schematic diagram of the architecture of a clustered RDMA network provided in an embodiment of the present application;

[0092] Figure 3 It is a logical schematic diagram of communication between nodes in a network provided by an embodiment of the present application;

[0093] Figure 4 It is a schematic diagram of the architecture of a computer system in which a virtual processor accesses a QP based on a lock provided by an embodiment of the present application;

[0094] Figure 5 It is a schematic diagram of the architecture of a computer system in which a virtual processor exclusively occupies a QP provided in an embodiment of the present application;

[0095] Figure 6a It is a schematic diagram of the architecture of a computer system based on a network card with a double-layer QP architecture provided in an embodiment of the present application;

[0096] Figure 6b It is a schematic diagram of the architecture of another computer system based on a network card with a double-layer QP architecture provided in an embodiment of the present application;

[0097] Figure 6c It is a schematic diagram of the architecture of another computer system based on a network card with a double-layer QP architecture provided in an embodiment of the present application;

[0098] Figure 7 It is a communication schematic diagram of a data transmission method provided in an embodiment of the present application;

[0099] Figure 8 It is a flowchart of a data transmission method provided by an embodiment of the present application;

[0100] Fig. 9 It is a flowchart of another data transmission method provided in an embodiment of the present application;

[0101] Fig.10 It is a flowchart of another data transmission method provided in an embodiment of the present application;

[0102] Fig.11 It is a structural schematic diagram of a data transmission device provided in an embodiment of the present application;

[0103] Fig.12 is a structural schematic diagram of another data transmission device provided in an embodiment of the present application;

[0104] Fig.13 It is a structural diagram of a network card provided in an embodiment of the present application;

[0105] Fig.14 It is a schematic diagram of the structure of a network card chip provided in an embodiment of the present application;

[0106] Fig.15 It is a structural diagram of a computing device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0107] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0108] In the description of the embodiments of the present application, words such as "exemplary", "for example" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary", "for example" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary", "for example" or "for example" is intended to present related concepts in a concrete way.

[0109] In the description of the embodiments of the present application, the term "and / or" is merely a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B may represent: A exists alone, B exists alone, and A and B exist at the same time. In addition, unless otherwise specified, the term "multiple" means two or more. For example, multiple systems refers to two or more systems, and multiple terminals refers to two or more terminals.

[0110] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. The terms "include", "comprises", "has" and their variations all mean "including but not limited to", unless otherwise specifically emphasized.

[0111] The Remote Direct Memory Access Over Converged Ethernet (RoCE) protocol provides an Internet Protocol (IP) to IP remote memory access capability.

[0112] Based on the RoCE protocol, data is transmitted between processes through queue pairs (QP) established between nodes. Among them, QP only supports one-to-one services, that is, a message in a QP can only reach another certain node from one node. For example, Figure 1 As shown, node A and node B communicate through a network, wherein each node can be connected to multiple network ports, and each node has multiple processes, for example, node A includes multiple processes A, and node B includes multiple processes B. Multiple processes A can respectively transmit data to multiple processes B through queues established between node A and node B.

[0113] For example, Figure 1 The clustered RDMA networking shown in the figure includes multiple computer systems, each of which includes a node and a network card. The node and the network card communicate through a bus, and the node communicates with the switch through the network card to transmit data with other nodes. Here, the node and the network card can be regarded as two parts of the computer system. In some embodiments, the network card is an unloadable network card. The computer system can be used as a data sending system and a data receiving system.

[0114] It should be noted that QP includes a sending queue and a receiving queue. For the sake of brevity, the following only uses QP to describe the data receiving process and sending process. However, in actual applications, the sending queue in QP is used to send data, and the receiving queue in QP is used to receive data.

[0115] based on Figure 1 The clustered RDMA networking shown in the figure is Figure 2 A schematic diagram of the logical relationship between nodes in a clustered RDMA network is shown, when each node can communicate with the remaining n-1 nodes through the RDMA protocol. When data is transmitted between two nodes, a QP needs to be established, and the established QP is a QP exclusively shared by the two nodes, so that the nodes transmit data based on the QP.

[0116] In one case, based on Figure 1 and Figure 2In the network shown in FIG. 1 , during the process of QP-based data transmission between nodes, when multiple virtual central processing units (CPUs) in a node need to send data to other nodes at the same time, access to the QP needs to be protected by a lock. Figure 1 The network architecture shown is based on Figure 4 As shown, node n includes virtual processors vCPU1 to vCPU3, node n also includes QP1 to QPn-1, and the network card includes QP1' to QP1n-1'. The QP in the node and the QP in the network card are in a one-to-one correspondence. Among them, when the virtual processors vCPU1 to vCPU3 all send data to node 1, node n needs to establish QP1, and all virtual processors in node n need to send data to node 1 by accessing QP1. Among them, virtual processors vCPU1 to vCPU3 need to obtain lock 10 to protect the access to QP1. If virtual processor vCPU1 obtains lock 10, then virtual processor vCPU1 can access QP1, and then send data to node 1 through QP' in the network card. In the process of virtual processor vCPU1 sending data to node 1 through QP1, virtual processors vCPU2 and virtual processors vCPU3 are both in a waiting state and cannot access QP1. However, protecting the access to the QP in the CPU by locking will cause the preemption of CPU resources between virtual processors, thereby resulting in the occupation of CPU resources and increasing the delay of data transmission.

[0117] In another case, based on Figure 1 and Figure 2 In the network shown in FIG. 1 , in the process of data transmission between nodes based on QP, each virtual processor can exclusively occupy a QP. Figure 1 The network architecture shown is based on Figure 5As shown, the CPU in node n has m cores, that is, the CPU can be divided into m virtual processors vCPU. Node n includes n-1 QP groups (Note: there is no relationship between the node number and the number of QPs), namely QPG1 to QPGn-1, and each QP group includes m QPs. Each QP group is used to send data to the node corresponding to the QP group. For example, the QPs in QPG1 are all used to send data to node 1. The QPs in the QP group have a one-to-one correspondence with the virtual processor vCPU, that is, one virtual processor has exclusive access to one QP. In this way, multiple vCPUs can send data to the same node in parallel, and multiple vCPUs can send data to different nodes in parallel, avoiding the problem of resource preemption. However, each vCPU occupies a QP exclusively, and each node corresponds to a QP group, so the network card corresponding to the node needs to support m*(n-1) QPs, but QP resources are limited, and a large number of QPs easily exceeds the network card specifications. In addition, in the process of reading and writing memory, QP manages and sends and receives data, which consumes memory resources. When the number of QPs is large, a large amount of node memory will be consumed.

[0118] In other words, for a system consisting of n nodes, one of the nodes has m virtual processors. Then, in the prior art, QP has only one layer. For this node with m virtual processors, each virtual processor needs n-1 QPs to communicate with any node in the n-1 nodes. Therefore, its network card needs to provide a total of m*(n-1) QPs to achieve the purpose of each of the m virtual processors being able to communicate with any other node. On the contrary, based on the solution provided by the embodiment of the present invention, the QP structure is divided into a core layer (first layer) and a shared layer (second layer). Since the second layer QP can be shared by multiple virtual processors, the network card of this node only needs to provide m first layer QPs and n-1 second layer QPs, which achieves the purpose of each of the m virtual processors being able to communicate with any other node. The total number of QPs is reduced from m*(n-1) to m+(n-1), saving the QP resources of the network card and reducing the occupation of the network card memory by QP.

[0119] It should be noted that if Figure 4 and Figure 5 The nodes shown in the figure transmit data through RDMA during data transmission, that is, the virtual processor transmits data with the QP in the network card through the user state QP corresponding to the virtual processor. Figure 4 and Figure 5 Here, data transmission includes receiving data or sending data.

[0120] Based on this, the embodiment of the present application provides a data transmission method, device, network card, network card chip and computer. According to the present solution, the method uses a two-layer QP architecture in the network card, and the two-layer QP architecture includes multiple core QPs in the first layer and multiple shared QPs in the second layer. Among them, each core QP corresponds to a virtual processor in the node one by one, so that the virtual processor in the node can monopolize the core QP, and then data requests from different virtual processors are added to different core queues. Each shared QP corresponds to a node in the network one by one, and a single shared QP supports data transmission of multiple core QPs.

[0121] Taking sending data requests as an example, if the processor sending the data request is called the source processor, the node receiving the data request is called the destination node (generally, the destination virtual processor in the destination node is the final recipient of the data). For multiple data requests from different source virtual processors and sent to the same destination node, they first reach the core QP corresponding to each source virtual processor, and then reach the shared QP corresponding to the destination node. In this way, the virtual processor can monopolize the core QP, meeting the demand for the virtual processor to monopolize the QP; and a single shared QP can support data transmission of multiple core QPs, and the number of QPs in the CPU of the node does not need to increase with the increase in the number of nodes in the network, reducing the CPU overhead in the node.

[0122] Next, the computer system in the network provided in the embodiment of the present application is described in detail.

[0123] Figure 6a Schematic diagram of the computer system architecture provided by the embodiment of the present application. Figure 6a As shown, the computer system provided in the embodiment of the present application includes a node 61 and a network card 62. Among them, the node 61 is the i-th node in the network, i=1, 2, ..., n, and n is a positive integer greater than 1. The node 61 communicates with the network through the network card 62, so that multiple nodes can communicate with each other. It should be noted that the network card can be integrated on the node, and the network card can also be a detachable network card. The embodiment of the present application does not specifically limit the form of the network card.

[0124] In the embodiment of the present application, node 61 includes a CPU and a memory. The CPU may be an m-core CPU, which are vCPUi1 to vCPUim. The vCPU reads data from the memory and sends it to the network card through the user state QP. Alternatively, the vCPU receives data from the network card through the user state QP and writes the data to the memory. In the embodiment of the present application, the vCPU corresponds to the user state QP one by one. Figure 6aAs shown, the node includes m user state QPs, namely user state QPyi1 to user state QPyim. Exemplarily, user state QP1 corresponds to vCPU1 one by one. When vCPUi1 and the network card are transmitting data, vCPUi1 puts the data into user state QPyi1 and then sends the data in user state QPyi1 to the network card. Similarly, vCPUi2 corresponds to user state QPyi2 one by one, and so on, vCPUim corresponds to user state QPyim one by one. Here, the data transmission process in the node can be referred to the detailed description of the node in the RDMA protocol, which will not be repeated here.

[0125] The network card 62 includes a data processing unit (DPU) and a physical port. The DPU is used to assemble data into network messages, or parse network messages received by the network card. The physical port is used to communicate with the network, receive network messages sent by the network, or send network messages to the network. The network message carries data transmitted between nodes.

[0126] In order to improve the performance of the entire system during data transmission and reduce the usage of memory, CPU and other resources, a double-layer QP architecture is designed on the network card side during the process of receiving or sending data, so that the network card transmits data through the double-layer QP architecture. Figure 6a As shown in FIG, the dual-layer QP architecture of the network card includes multiple core QPs and multiple shared QPs. The core QPs correspond one-to-one to the user-mode QPs in the node. Figure 6a As shown, the network card includes m core QPs, namely core QPhi1 to core QPhim. Among them, core QPhi1 corresponds to user state QPyi1 in the node one by one, core QPhi2 corresponds to user state QPyi2 in the node one by one, and so on, core QPhim corresponds to user state QPyim in the node one by one. Exemplarily, when vCPUi1 in the node sends data to the network card, vCPUi1 puts the data into user state QPyi1 and sends it to core QPhi1 in the network card.

[0127] The core QP in the network card can communicate with the shared QP, where one shared QP supports data transmission of multiple core QPs. The shared QP corresponds to other nodes in the network one by one, so that the data in the core QP can be transmitted to multiple other nodes in the network. For example, Figure 6a As shown, the network card includes shared QPpi1 to shared QPpin-1, where n is a positive integer and n is greater than 1. The shared QP corresponds to other nodes in the network one by one. Figure 6aThe node shown is node n in the network, and the network also includes nodes 1 to n-1. Therein, shared QPpi1 corresponds to node 1 one-to-one, shared QPpi1 corresponds to node 2 one-to-one, and so on, shared QPpin-1 corresponds to node n-1 one-to-one.

[0128] Exemplarily, when vCPUn1 of node n sends data to node 1, node n reads the data from the memory and puts the data into the user state QPyn1, so as to transmit the data to the core QPhn1 in the network card through the user state QPyn1, and the core QPhn1 sends the data to the shared QPpn1, so as to transmit the data to node 1 through the shared QPpn1. In another exemplary embodiment, when node 1 sends data to vCPUn1 in node n, the network card corresponding to node n receives the data sent by node 1 through the network through the shared QPp11, and the shared QPp11 transmits the data to the core QPhn1, and then transmits the data to the user state QPyn1 in node n, so that the vCPUn1 in node n reads the data sent by node 1 from the user state QPyn1.

[0129] It should be noted that the user QP in the node, the core QP in the network card, and the shared QP in the network card all include paired receive queues and send queues, so that the user QP in the node, the core QP in the network card, and the shared QP in the network card can be used to send data and also to receive data.

[0130] In this way, based on the dual-layer QP architecture in the network card, when the node sends data to the network card, the vCPU does not need to protect the QP access through a lock, avoiding the occupation of CPU resources during resource preemption between vCPUs and reducing the data transmission delay. In addition, the dual-layer QP architecture in the network card can reduce the number of QPs, thereby preventing the number of QPs from exceeding the network card specifications and avoiding a large amount of memory consumption in the node during the QP reading and writing memory.

[0131] In some embodiments, the network card provided by the embodiments of the present application includes multiple core QPs and multiple shared QPs. Among them, the multiple core QPs correspond one-to-one to the multiple virtual processors in the node. In the process of the CPU in the node sending data to the network card, the network card is used to receive multiple data requests, and the multiple data requests come from different virtual processors in the CPU. After receiving the multiple data requests, the network card adds the multiple data requests to the core QP respectively. Among them, the core QP and the virtual processor are in a one-to-one correspondence, and data requests from different virtual processors enter different core queues. For example, Figure 6aAs shown, the NIC adds the data from vCPUi1 to the core QPhi1, the NIC adds the data from vCPUi2 to the core QPhi2, and the NIC adds the data from vCPUim to the core QPhim.

[0132] In the process of the NIC sending data to the CPU in the node, the NIC is used to take out multiple data requests from the shared QP and add the multiple data requests to the core QP respectively. Among them, the target virtual processors of the data requests are different, and the core QPs entered are different. For example, the target virtual processor of data request A is vCPUi1, so the NIC adds data request A to core QPhi1. The target virtual processor of data request B is vCPUi2, so the NIC adds data request B to core QPhi2. The target virtual processor of data request C is vCPUim, so the NIC adds data request C to core QPhim.

[0133] There is a one-to-one correspondence between the shared QP and the nodes in the network. Data requests from different nodes enter different shared QPs, and data requests from the same node enter the same shared QP. Figure 6a As shown, shared QPpi1 corresponds to node 1 one-to-one. When the network card receives a data request from node 1, the network card adds the data request from node 1 to shared QPhi1. Shared QPpi2 corresponds to node 2 one-to-one. When the network card receives a data request from node 2, the network card adds the data request from node 2 to shared QPpi2.

[0134] For example, Figure 6b As shown, the two-layer QP architecture in the network card can include a group of core QPs and n-1 groups of shared QPs, each group of shared QPs includes a shared QP. Among them, the core QP corresponds to the vCPU in the node one by one. The shared QP can communicate with all the core QPs. Among them, the shared QP in QPG1 is used to communicate with node 1, the shared QP in QPG2 is used to communicate with node 2, and so on. The shared QP in QPGn-1 is used to communicate with node n-1.

[0135] exist Figure 6b In the double-sided QP architecture in the node i and the network card i1 shown in FIG. 1 , when the node i is the nth node in the network, the logical relationship among the vCPU, the core QP, the shared QP and the communication between the nodes is shown in Table 1 .

[0136] Table 1

[0137]

[0138] According to this solution, through the dual-layer QP architecture in the network card, the dual-layer QP architecture includes multiple core QPs in the first layer and multiple shared QPs in the second layer. Among them, each core QP corresponds to a virtual processor in the node one by one, so that the virtual processor in the node can monopolize the core QP, then the data requests from different virtual processors are added to different core queues. Each shared QP corresponds to a node in the network one by one, and a single shared QP supports data transmission of multiple core QPs.

[0139] Taking sending data requests as an example, if the processor sending the data request is called the source processor, the node receiving the data request is called the destination node (generally, the destination virtual processor in the destination node is the final recipient of the data). For multiple data requests from different source virtual processors and sent to the same destination node, they first arrive at the core QP corresponding to each source virtual processor, and then arrive at the shared QP corresponding to the destination node. In this way, the virtual processor can monopolize the core QP, meeting the demand for the virtual processor to monopolize the QP; and a single shared QP can support data transmission of multiple core QPs, reducing the CPU overhead in the node.

[0140] In some other embodiments, the dual-layer QP architecture in the network card may include multiple core QP groups P and n-1 shared QP groups, wherein the core QP group includes multiple core QPs and the shared QP group includes multiple shared QPs. The core QP group corresponds one-to-one to the shared QPs in the shared QP group, and the shared QP supports data transmission of multiple core QPs in the same core QP group. Specifically, the network card includes multiple core queue groups and multiple shared queue groups. Each core queue group in the multiple core queue groups includes multiple core queues, and the multiple core queues correspond one-to-one to multiple virtual processors in the node. For example, Figure 6c As shown, the network card includes core QP group G11, core QP group G22 and core QP group G33. Among them, core QP group G11, core QP group G22 and core QP group G33 each include m core QPs. The network card includes shared QP group QP1, shared QP group QP2, ..., shared QP group QPn-1. Shared QP group QPG1 is used for data transmission with node 1, shared QP group QPG2 is used for data transmission with node 2, and so on, shared QP group QPGn-1 is used for data transmission with node n-1. Among them, each shared QP group includes 3 shared QPs, and each shared QP corresponds to a core QP group.

[0141] The network card is used to receive multiple data requests, and the multiple data requests come from different virtual processors. Data requests from the same virtual processor enter different core QP groups. Data requests from different virtual processors enter different core QPs. For example, Figure 6cAs shown, data request A and data request B both come from vCPUi1. The NIC adds data request A to core QPhi1 in core QP group G11, and adds data request B to core QPhi1 in core QP group G22. In this way, the NIC can process multiple data requests from the same virtual processor in parallel, improving data transmission efficiency.

[0142] For example, Figure 6c As shown, the network card includes 3 groups of core QPs, namely G11, G22 and G33. Each group of core QPs includes m core QPs, which correspond to m vCPUs one by one. The network card includes n-1 groups of shared QPs, namely QPG1 to QPGn-1, and each group of shared QPs includes 3 shared QPs, namely G1, G2 and G3. Among them, different shared QPs in each group of shared QPs correspond to different core QP groups. For example, when the core QP in core QP group G11 sends data to node 1, core QP group G11 sends the data to shared QPg1 in the shared QP. Here, shared QPg1 is included in shared QP group QPG1 to shared QP group QPGn-1. Figure 6c Based on the two-tier QP architecture shown in Figure 1, the same vCPU in a node can process different services in parallel. Figure 1 Based on the networking architecture shown, vCPU1 can send data to node 1 and node 2 in parallel, where the data sent by node n to node 1 is data 1, and the data sent by node n to node 2 is data 2. vCPUn1 sends data 1 to core QPhn1 corresponding to vCPUn1 in core QP group G11, and vCPUn1 sends data 2 to core QPhn1 corresponding to vCPUn1 in core QP group G22. Then, the core QP corresponding to vCPUn1 in core QP group G11 sends data 1 to shared QPg1 in shared QP group QPG1, and the core QPhn1 corresponding to vCPUn1 in core QP group G22 sends data 2 to shared QPg2 in shared QP group QPG2.

[0143] exist Figure 6c In the double-sided QP architecture of the node i and the network card i1 shown in FIG. 1 , when the node i is the nth node in the network, the logical relationship among the vCPU, the core QP, the shared QP and the communication between the nodes is shown in Table 2 .

[0144] Table 2

[0145]

[0146]

[0147] According to this solution, through the two-layer QP architecture in the network card, the two-layer QP architecture includes multiple core QPs and multiple shared QPs, wherein the core QP is used for one-to-one correspondence between the virtual processors in the node, so that the virtual processor in the node can monopolize the core QP, without resource preemption, and reduce the resource occupation of the CPU. A shared QP supports the data transmission of multiple core QPs, and the nodes in the network correspond one-to-one to the shared queues, so that the nodes in the network can monopolize the shared queues, so that multiple vCPUs in the node can transmit data with multiple other nodes in the network, reducing the data transmission delay. Moreover, since the virtual processor can monopolize the core QP, and a shared QP supports the data transmission of multiple core QPs, the CPU overhead in the node is reduced. In addition, through the one-to-one correspondence between the shared queues in the core queue group and a shared queue group, and the one-to-one correspondence between the shared queue group and the node, multiple vCPUs can transmit data in parallel with the same node, or the same vCPU can transmit data in parallel with the same node, improving the data transmission efficiency.

[0148] It should be noted that Figure 6b and Figure 6c To illustrate the dual-layer QP architecture in the network card, detailed descriptions of some modules or components are omitted for brevity. Figure 6a Detailed description.

[0149] The above is a detailed description of the architecture of the computer system provided in the embodiment of the present application. Figure 2 , Figures 6a to 6c Based on Figure 7 Taking as an example, the data transmission method provided in the embodiment of the present application is exemplarily described.

[0150] Before describing the data transmission method provided in the embodiment of the present application, Figure 7 The architecture for data transmission between nodes in the provided network is described. Figure 7 As shown, the network includes a transmitting end and a receiving end. The transmitting end includes node 1 and network card 11, and the receiving end includes node n and network card n1. The CPU of node 1 is m cores, that is, node 1 includes m vCPUs, namely vCPU11 to vCPU1m, and node 1 includes m user-state QPs, namely user-state QPy11 to user-state QPy1m. Figure 7 As shown, m user-mode QPs correspond to m vCPUs one by one. The network card 11 includes m core QPs, namely core QPh11 to core QPh12. Figure 7 As shown, the m core QPs correspond one-to-one to the m user-mode QPs in node 1. The network card 11 also includes n-1 shared QPs, and different shared QPs send data to different nodes, such as Figure 7The shared QP t2 shown in the figure indicates that the shared QP is used to send data to node 2, the shared QPt3 indicates that the shared QP is used to send data to node 3, and so on, the shared QPtn indicates that the shared QP is used to send data to node n. The CPU of node n is k cores, that is, node n includes k vCPUs, namely vCPUn1 to vCPUnk, and node n includes k user-state QPs, namely user-state QPn1 to user-state QPnk. Figure 7 As shown in , k user-mode QPs correspond to k vCPUs one by one. Network card n1 includes k core QPs, namely core QPhn1 to core QPhnk. Figure 7 As shown in , the k core QPs correspond one-to-one to the k user-mode QPs in node n. Network card n1 also includes n-1 shared QPs. Different shared QPs are used to receive data from different nodes, such as Figure 7 As shown, shared QPf1 is used to receive data from node 1, shared QPf2 is used to receive data from node 2, and so on, and shared QPfn-1 is used to receive data from node n-1.

[0151] Below Figure 7 Taking the example of node 1 sending data to node n in the example, the data transmission method provided in the embodiment of the present application is exemplarily described.

[0152] Figure 8 is a flow chart of a data transmission method provided in an embodiment of the present application. Figure 2 , Figures 6a to 6c The computer system shown in . Figure 8 As shown, the data transmission method provided in the embodiment of the present application includes S801 to S815.

[0153] S801, vCPU12 in node 1 adds information of service A to user state QP12.

[0154] Node 1 and node n can communicate with each other in multiple services. Different services can use different vCPUs for data transmission. For example, when node 1 and node n transmit data for service A, vCPU 12 in node 1 is used to process data for service A. vCPU 12 can read data from memory ( Figure 7 According to the pre-configured architecture in node 1, vCPU 12 corresponds to user-mode QP 12 one by one, and vCPU 12 accesses the information of service A to user-mode QP 12.

[0155] In the embodiment of the present application, the information of service A includes the data of service A and the identity of the destination node and the identity of the destination vCPU corresponding to the data of service A. The destination node corresponding to the data of service A is node n, so the identity of the destination node is n, and the destination vCPU corresponding to the data of service A is vCPUhnk in node n, so the identity of the destination vCPU is hnk.

[0156] As a possible implementation manner, the information of service A is sent to the network card in the form of a command prompt (CMD).

[0157] S802, vCPU12 sends the data of service A in user state QP12 to network card 11.

[0158] S803, the network card 11 adds the information of service A to the core QPh12.

[0159] According to the pre-configured architecture in the network card, the user state QP12 in node 1 corresponds to the core QP12 in the network card. After receiving the information of service A, the network card adds the information of service A to the core QP12.

[0160] S804, the NPU1 in the network card 11 parses the information of the service A to obtain the identity of the destination node corresponding to the data of the service A.

[0161] S805 , the NPU1 in the network card 11 determines the identity of the shared QP corresponding to the identity of the destination node according to the mapping relationship information.

[0162] The mapping relationship information is pre-configured in the network card, and the mapping relationship information in the network card 11 is used to indicate the mapping relationship between the shared QP in the network card 11 and the destination node. The mapping relationship information includes the identity of the destination node and the identity of the shared QP. NPU1 can determine the identity of the shared QP corresponding to the identity of the destination node from the mapping relationship information. The shared QP corresponding to the destination node is the shared QP used to send data to the destination node.

[0163] Exemplarily, the mapping relationship information in the network card 11 is shown in Table 3. Among them, node 2 corresponds to shared QPt2, node 3 corresponds to shared QPt3, and so on, node n corresponds to shared QPtn.

[0164] Table 3

[0165] node Shared QP corresponding to the node 2 t2 3 t3 4 t4 …… …… n tn

[0166] In this way, when the node sends data to the network card, the vCPU does not need to protect the QP access through a lock, which avoids the occupation of CPU resources during the resource preemption process between vCPUs and reduces the delay in data transmission.

[0167] It should be noted that the node referred to in the mapping relationship information can be used as a destination node or a source node. In different data transmission scenarios, the role of the node referred to in the mapping relationship information is different. In the scenario of the embodiment of the present application, the node referred to in the mapping relationship information refers to the destination node to which the data is to be sent.

[0168] S806 , the NPU1 in the network card 11 adds the information of the service A to the shared QP corresponding to the identity of the shared QP.

[0169] Exemplarily, the destination node of service A is node n. According to the mapping relationship information, the shared QP corresponding to node n is shared QPtn. NPU1 adds the information of service A to the shared QPtn.

[0170] S807, NPU1 in the network card 11 packages the information of service A to obtain a message of service A.

[0171] NPU1 adds an IP message header to the information of service A, thereby assembling the information of service A into a network message.

[0172] S808 , the network card 11 sends the message of the service A in the shared QP to the network card n1 at the receiving end.

[0173] The network card 11 can send the message of service A to the network, thereby transmitting the message of service A to the receiving end through the network. The network card n1 in the receiving end can receive the message of service A from the network through the physical port of the network card n1.

[0174] S809, the network card n1 adds the message of service A to the shared QPf1 in the network card n1.

[0175] The message of service A includes the identity of the source node of the message. In the embodiment of the present application, the source node of the message of service A is node 1, and the shared QPf1 in the network card n1 is used to receive data from node 1. Therefore, after receiving the message of service A, the network card n1 adds the message of service A to the shared QPf1.

[0176] S809, the NPUn in the network card n1 parses the message of the service A, and obtains the data of the service A and the identity of the destination vCPU corresponding to the data of the service A.

[0177] S810 , the NPUn in the network card n1 determines the identity of the core QP corresponding to the identity of the destination vCPU according to the mapping relationship information in the network card n1 .

[0178] The mapping relationship information in the network card n1 is used to indicate the mapping relationship between the destination vCPU and the core QP in the network card n1. The mapping relationship information in the network card n1 includes the identity of the destination vCPU and the identity of the core QP in the network card n1. The NPUn can determine the identity of the core QP corresponding to the identity of the destination vCPU from the mapping relationship information. The core QP corresponding to the destination vCPU is the core QP that sends data to the destination vCPU.

[0179] Exemplarily, the mapping relationship information in the network card n1 is shown in Table 4. Among them, vCPUn1 corresponds to core QPhn1, vCPUn2 corresponds to core QPhn2, and so on, vCPUnk corresponds to core QPnk.

[0180] Table 4

[0181] vCPU vCPU corresponding to the core QP n1 hn1 n2 hn2 …… …… n hnk

[0182] It should be noted that the node referred to in the mapping relationship information can be used as a destination node or a source node. In different data transmission scenarios, the role of the node referred to in the mapping relationship information is different. In the scenario of the embodiment of the present application, the node referred to in the mapping relationship information refers to the destination node to which the data is to be sent.

[0183] S811, network card n1 adds the data of service A in shared QPf1 to the core QP corresponding to the destination vCPU.

[0184] In the embodiment of the present application, the destination vCPU of the data of service A is vCPUnk. According to Table 4, the core QP corresponding to vCPUnk is core QPhnk. Network card n1 adds the data of service A to core QPhnk.

[0185] S812, the network card n1 sends the data of the service A in the core QP to the target storage space corresponding to the vCPUnk.

[0186] In the embodiment of the present application, the node may include a memory, and the memory may include multiple storage spaces, and different vCPUs correspond to different storage spaces. As a possible implementation, the vCPU stores the received data in the target storage space corresponding to the vCPU.

[0187] In this way, when the network card sends data to the node, the vCPU does not need to protect the QP access through a lock, which avoids the occupation of CPU resources during the resource preemption process between vCPUs and reduces the delay in the data reception process.

[0188] According to the solution provided by the embodiment of the present application, according to this solution, through the two-layer QP architecture in the network card, the two-layer QP architecture includes multiple core QPs in the first layer and multiple shared QPs in the second layer. Among them, each core QP corresponds to a virtual processor in the node one by one, so that the virtual processor in the node can monopolize the core QP, then the data requests from different virtual processors are added to different core queues. Each shared QP corresponds to a node in the network one by one, and a single shared QP supports data transmission of multiple core QPs.

[0189] Taking sending data requests as an example, if the processor sending the data request is called the source processor, the node receiving the data request is called the destination node (generally, the destination virtual processor in the destination node is the final recipient of the data). For multiple data requests from different source virtual processors and sent to the same destination node, they first arrive at the core QP corresponding to each source virtual processor, and then arrive at the shared QP corresponding to the destination node. In this way, the virtual processor can monopolize the core QP, meeting the demand for the virtual processor to monopolize the QP; and a single shared QP can support data transmission of multiple core QPs, reducing the CPU overhead in the node.

[0190] Below Figure 2 , Figure 3 , Figures 6a to 6c , Figure 7 and Figure 8 Based on this, the data transmission method provided in the embodiment of the present application is described in detail.

[0191] Fig. 9 is a flow chart of a data transmission method provided in an embodiment of the present application. The data transmission method provided in an embodiment of the present application can be applied to Figure 1 , Figures 6a to 6c In the network card in the computer system shown in the figure, in the embodiment of the present application, the computer system acts as a sender. For the convenience of description, the network card of the sender is called a first network card, and the node of the sender is called a first node. It should be noted that all computer systems in the network can act as a sender. Fig. 9 As shown, the data transmission method provided in the embodiment of the present application includes S901 to S904.

[0192] S901, receiving multiple data requests, where the multiple data requests come from different virtual processors in a first processor.

[0193] The first node includes a first processor, and the first processor can be virtualized into multiple virtual processors. The data request refers to a request for transmitting data. The data request can carry data, so that the data is transmitted to other nodes. The data request can also request data from other nodes.

[0194] The network card can receive multiple data requests, and the multiple data requests come from different virtual processors in the first processor. Figure 6a As shown, the network card 62 receives data request A, data request B and data request C. Among them, data request A comes from vCPUi1, data request B comes from vCPUi2, and data request C comes from vCPUim.

[0195] S902, adding multiple data requests to core queues respectively, wherein each virtual processor corresponds to a core queue, and data requests from different virtual processors enter different core queues.

[0196] The first network card includes multiple core QPs, and the core QPs correspond to the virtual processors in the node one by one, that is, the virtual processor in the node occupies one core QP exclusively. After receiving multiple data requests, the first network card can add the multiple data requests to the core QP respectively. Among them, the data requests from different virtual processors enter different core QPs. For example, Figure 6a As shown, data request A comes from vCPUi1, vCPUi1 corresponds to core QPhi1, so the network card 62 adds data request A to core QPhi1. Data request B comes from vCPUi2, vCPUi2 corresponds to core QPhi2, so the network card 62 adds data request B to core QPhi2. Data request C comes from vCPUim, vCPUim corresponds to core QPhim, so the network card 62 adds data request C to core QPhim.

[0197] In this way, the virtual processor in the node can exclusively access the core QP in the network card, avoiding resource preemption in the node's processor during data transmission and reducing the processor overhead in the node.

[0198] As a possible implementation, the data request includes the identity of the virtual processor from which the data request comes. Figure 7 As shown, the source virtual processor is the virtual processor vCPU12 in node 1, and the identity of the virtual processor is vCPU12, so the service information includes vCPU12. Here, vCPU12 is only used as an example of the identity of the virtual processor. In actual applications, the identity of the virtual processor can be in other forms, such as the address of the virtual processor in the node, which is not specifically limited in the embodiment of the present application.

[0199] The first network card is pre-configured with second mapping relationship information. The second mapping relationship information is used to indicate the mapping relationship between the identity of the virtual processor and the identity of the core QP. For example, Figure 7As shown, vCPU11 in node 1 corresponds to core QPh11, vCPU12 corresponds to core QPh12, and so on, Vcpu1m corresponds to core QPh1m. The second mapping relationship information of the virtual processor in node n to the network card n1 can be found in Table 4 for the description of the mapping information table in network card n1, which will not be repeated here.

[0200] The first network card determines the identity of the core QP corresponding to the identity of the virtual processor from the second mapping relationship information according to the identity of the virtual processor in the data request. According to the identity of the core QP, the data request is added to the core QP. For example, Figure 6a As shown, the second mapping relationship information of node i is shown in Table 5. The identity of the source virtual processor is i1. According to the second mapping relationship, the identity of the core QP corresponding to vCPUi1 is hi1. Therefore, the first core QP is core QPhi1, and the business data from vCPUi1 is added to core QPhi1.

[0201] Table 5

[0202] vCPU vCPU corresponding to the core QP i1 hi1 i2 hi2 …… …… ik hik

[0203] S903, taking out multiple data requests from the core queue, and adding the multiple data requests to the shared queue respectively according to the destination nodes of each of the multiple data requests, wherein each destination node corresponds to a shared queue, and data requests with the same destination node enter the same shared queue.

[0204] The first network card includes multiple shared queues, and the shared queues are used to send data requests to the nodes corresponding to the shared queues. In order to avoid resource competition in the CPU during the process of sending data requests to multiple nodes, the shared queues correspond to the nodes one by one, and the shared queue where the data request is located is the shared queue corresponding to the destination node of the data request. For example, Figure 6a As shown, shared QPpi1 is used to send data requests to node 1, so data requests with the destination node being node 1 can enter shared QPpi1. Shared QPpi2 is used to send data requests to node 2, so data requests with the destination node being node 2 can enter shared QPpi2.

[0205] The first network card can take out multiple data requests from the core queue, and add the multiple data requests to the corresponding shared QPs according to the respective destination nodes of the multiple data requests. Data requests with the same destination node enter the same shared queue. In this way, multiple core QPs can share multiple shared QPs, thereby improving data transmission efficiency while reducing the number of shared QPs in the network card.

[0206] In an embodiment of the present application, the data request includes an identity of a destination node, and the first network card adds the data request to a shared QP corresponding to the destination node according to the identity in the data request. In a possible implementation, the first network card is pre-configured with first mapping relationship information. The first mapping relationship information is used to indicate a mapping relationship between an identity of a virtual processor and an identity of a core queue. The first network card can determine the identity of a shared queue corresponding to the destination node from the first mapping relationship information according to the identity of the destination node in the data request, thereby determining the shared queue corresponding to the destination node. The first network card adds the data request to the shared queue according to the identity of the shared queue.

[0207] For example, Figure 6a As shown, the first mapping relationship information is shown in Table 6. The first node corresponding to the first network card is node 1, and the identity of the destination node of the data request A is n. According to Table 6, the identity of the shared QP corresponding to node n is p1n, that is, the first shared QP is shared QPp1n. The first network card adds the data request A to the shared QPp1n.

[0208] Table 6

[0209] node Shared QP corresponding to the node 2 p12 3 p13 4 p14 …… …… n p1n

[0210] S904, taking out multiple data requests from the shared queue, and sending the multiple data requests to the destination computer system where the corresponding destination nodes are located.

[0211] The first network card can take out multiple data requests from the shared queue, and send the multiple data requests to the destination computer system where the destination node of the data request is located.

[0212] In a possible implementation, the first network card can assemble the data request into a network message, thereby sending the network message to the network, and sending the data request to the destination computer system where the destination node is located through the network.

[0213] Here, illustratively, the process of the first network card performing data transmission can also be referred to as Figure 8 The detailed description of S803 to S807 in the corresponding embodiment will not be repeated here.

[0214] According to an embodiment of the present application, according to this solution, through a two-layer QP architecture in a network card, the two-layer QP architecture includes multiple core QPs in the first layer and multiple shared QPs in the second layer. Among them, each core QP corresponds to a virtual processor in a node one by one, so that the virtual processor in the node can monopolize the core QP, then data requests from different virtual processors are added to different core queues. Each shared QP corresponds to a node in the network one by one, and a single shared QP supports data transmission of multiple core QPs.

[0215] Taking sending data requests as an example, if the processor sending the data request is called the source processor, the node receiving the data request is called the destination node (generally, the destination virtual processor in the destination node is the final recipient of the data). For multiple data requests from different source virtual processors and sent to the same destination node, they first arrive at the core QP corresponding to each source virtual processor, and then arrive at the shared QP corresponding to the destination node. In this way, the virtual processor can monopolize the core QP, meeting the demand for the virtual processor to monopolize the QP; and a single shared QP can support data transmission of multiple core QPs, reducing the CPU overhead in the node.

[0216] Below Figure 2 , Figure 3 , Figures 6a to 6c , Figure 7 and Figure 8 Based on this, the data transmission method provided in the embodiment of the present application is described in detail.

[0217] Fig.10 is a flow chart of a data transmission method provided in an embodiment of the present application. The data transmission method provided in an embodiment of the present application can be applied to Figure 1 , Figures 6a to 6c In the network card in the computer system shown in the figure, in the embodiment of the present application, the computer system is a receiving end. For the convenience of description, the network card of the receiving end is called a second network card, and the node of the receiving end is called a second node. Fig.10 As shown, the data transmission method provided in the embodiment of the present application includes S1001 to S1004.

[0218] S1001, receiving multiple data requests, where the multiple data requests come from different nodes.

[0219] The second network card can receive data requests from different nodes through the network.

[0220] The data request refers to a request for transmitting data. The data request may carry data, so that the data is transmitted to the node where the second network card is located, that is, the second node. The data request may also request data from the second node.

[0221] S1002, adding multiple data requests to shared queues respectively, wherein each node corresponds to a core queue, and data requests from the same node enter the same shared queue.

[0222] The second network card includes multiple shared queues, and different shared queues correspond to different nodes. The second network card can receive data requests from different nodes, wherein the data requests from different nodes enter different shared queues. For example, Figure 6aAs shown, the data request from node 1 enters the shared QPpi1, the data request from node 2 enters the shared QPpi2, and so on, the data request from node n-1 enters the shared QPpin-1.

[0223] As a possible implementation, the second network card is pre-configured with first mapping relationship information, and the first mapping relationship information is used to indicate the mapping relationship between the node identity and the shared queue identity. Exemplarily, the first mapping relationship information may be as shown in Table 3, and specific details may be referred to the detailed description of Table 3 in the above embodiment, which will not be repeated here.

[0224] The second network card can determine the identity of the shared queue corresponding to the identity of the node from the first mapping relationship information, thereby adding the data request to the shared queue.

[0225] For example, Figure 7 As shown, the network card n1 receives the service information from the node 1, the shared QPf1 in the network card n1 corresponds to the node 1 one by one, and the network card n1 adds the service information to the shared QPf1.

[0226] S1003, taking out multiple data requests from the shared queue, and adding the multiple data requests to the core queue respectively according to the destination virtual processor of each of the multiple data requests, wherein data requests with different destination virtual processors enter different core queues.

[0227] The destination virtual processor is the end point of the data request. The destination virtual processors of different data requests can be the same or different. The second network card adds the data request to the core queue according to the destination virtual processor of each data request. Data requests with different destination virtual processors enter different core queues. For example, Figure 6a As shown, the destination virtual processor of data request A is vCPUi1, and the second network card adds data request A to core QPhi1. The destination virtual processor of data request B is vCPUi2, and the second network card adds data request B to core QPhi2.

[0228] In some possible implementations, the data request includes an identity of a destination virtual processor. The second network card can add multiple data requests to a core queue respectively according to the identity of the destination virtual processor. After the second network card adds the data request to the shared queue, it can parse the data request to obtain the identity of the data request. According to the identity of the destination virtual processor, the data request is added to the core queue corresponding to the destination virtual processor.

[0229] As a possible implementation, the second network card is pre-configured with second mapping relationship information, and the second mapping relationship information is used to indicate the mapping relationship between the identity of the virtual processor and the identity of the core queue. For example, the second mapping relationship information may be as shown in Table 4. Figure 8 The detailed description of Table 4 in the corresponding embodiment will not be repeated here.

[0230] For example, Figure 7 As shown, the identity of the destination virtual processor of the data of service A is nk, the identity of the core queue corresponding to vCPUnk is ynk, and the network card n1 adds the service data to the core QPynk.

[0231] The second network card can determine the identity of the core queue corresponding to the destination virtual processor from the second mapping relationship information according to the identity of the destination virtual processor. The second network card adds the service data to the core queue according to the identity of the core queue corresponding to the destination virtual processor.

[0232] S1004, taking out multiple data requests from the core queue, and sending the multiple data requests to corresponding destination virtual processors.

[0233] According to an embodiment of the present application, through a two-layer QP architecture in a network card, the two-layer QP architecture includes multiple core QPs in the first layer and multiple shared QPs in the second layer. Among them, each core QP corresponds to a virtual processor in a node one by one, so that the virtual processor in the node can monopolize the core QP, and then the data requests of different destination virtual processors are added to different core queues. Each shared QP corresponds to a node in the network one by one, and a single shared QP supports data transmission of multiple core QPs.

[0234] Taking receiving data requests as an example, if the node sending the data request is called the source node, the virtual processor receiving the data request is the destination virtual processor (generally, the destination virtual processor is the final recipient of the data request). For multiple data requests from the same source node and sent to different destination virtual processors, the multiple data requests can be added to the shared QP corresponding to the source node, and then reach the core QP corresponding to each destination virtual processor. In this way, the virtual processor can monopolize the core QP, meeting the demand for the virtual processor to monopolize the QP; and a single shared QP can support data transmission of multiple core QPs, reducing the CPU overhead in the node.

[0235] Based on the same concept as the embodiment of the method of the present application, the embodiment of the present application also provides a data transmission device. The data transmission device includes several modules, each of which is used to execute each step in the data transmission method provided in the embodiment of the present application, and the division of the modules is not limited here. The technicians in the relevant field can clearly understand that in practical applications, the various steps in the data transmission method provided in the embodiment of the present application can be assigned to different modules as needed, that is, the internal structure of the device is divided into different modules to complete all or part of the functions described above. Each module in the embodiment can be integrated in a processing unit, or each unit can exist physically separately, or two or more modules can be integrated in one unit, and the above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of each module are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of the present application. The specific working process of the module in the above-mentioned device can refer to the corresponding process in the aforementioned method embodiment, which will not be repeated here.

[0236] For example, Fig.11 The data transmission device 1100 provided in the embodiment of the present application is a schematic diagram of the structure of the data transmission device 1100 provided in the embodiment of the present application. The data transmission device provided in the embodiment of the present application can be applied to Figure 1 , Figures 6a to 6c In the network card in the computer system shown in FIG. Fig. 9 The data transmission method in the corresponding embodiment. For the convenience of description, the computer system is referred to as a first computer system, the first computer system includes a first node and a first network card, the first node includes a first processor, the first node communicates with the first network card through a bus, the first node communicates with multiple computer systems through the first network card, and the device is applied to the first network card, such as Fig.11 As shown, the data transmission device 1100 provided in the embodiment of the present application includes:

[0237] A receiving module 1101 is used to receive multiple data requests, where the multiple data requests come from different virtual processors in the first processor, and the destination node of each data request is different;

[0238] The processing module 1102 is used to add multiple data requests to core queues respectively, wherein each virtual processor corresponds to a core queue, and data requests from different virtual processors enter different core queues;

[0239] The processing module is also used to take out multiple data requests from the core queue, and add the multiple data requests to the shared queue respectively according to the destination nodes of each data request in the multiple data requests, wherein each destination node corresponds to a shared queue, and data requests with the same destination node enter the same shared queue;

[0240] The sending module 1103 is used to take out multiple data requests from the shared queue and send the multiple data requests to the destination computer system where the corresponding destination node is located.

[0241] According to this solution, through the two-layer QP architecture in the network card, the two-layer QP architecture includes multiple core QPs in the first layer and multiple shared QPs in the second layer. Among them, each core QP corresponds to a virtual processor in the node one by one, so that the virtual processor in the node can monopolize the core QP, and then data requests from different virtual processors are added to different core queues. Each shared QP corresponds to a node in the network one by one, and a single shared QP supports data transmission of multiple core QPs.

[0242] Taking sending data requests as an example, if the processor sending the data request is called the source processor, the node receiving the data request is called the destination node (generally, the destination virtual processor in the destination node is the final recipient of the data). For multiple data requests from different source virtual processors and sent to the same destination node, they first arrive at the core QP corresponding to each source virtual processor, and then arrive at the shared QP corresponding to the destination node. In this way, the virtual processor can monopolize the core QP, meeting the demand for the virtual processor to monopolize the QP; and a single shared QP can support data transmission of multiple core QPs, reducing the CPU overhead in the node.

[0243] In a possible implementation manner, the first network card is configured with first mapping relationship information, where the first mapping relationship information is used to indicate a mapping relationship between an identity of a node and an identity of a shared queue, and the processing module is used to:

[0244] According to the identity of the destination node, determine the identity of the shared queue corresponding to the destination node from the first mapping relationship information;

[0245] According to the identity of the shared queue corresponding to the destination node, the data request is added to the shared queue.

[0246] In this way, nodes in the network can monopolize the shared queue, so that multiple virtual processors can transmit data with multiple nodes, reducing data transmission latency.

[0247] In a possible implementation, the first network card is configured with second mapping relationship information, the second mapping relationship information is used to indicate a mapping relationship between an identity of a virtual processor and an identity of a core queue, the data request includes an identity of the virtual processor from which the data request comes, and the processing module is used to:

[0248] According to the identity of the virtual processor from which each of the multiple data requests comes, determining the identity of the core queue to which each of the data requests is to be added from the second mapping relationship information;

[0249] According to the identity identifier of the core queue, multiple data requests are added to the core queue respectively.

[0250] In this way, the virtual processors in the node can monopolize the core QP without the need to preempt resources in the CPU, thus reducing CPU resource usage.

[0251] For example, Fig.12 The data transmission device provided in the embodiment of the present application can be applied to Figure 1 , Figures 6a to 6c In the network card in the computer system shown in FIG. Fig.10 The data transmission method in the corresponding embodiment. In the embodiment of the present application, for the convenience of description, the computer system in the embodiment of the present application is referred to as the second computer system. The second computer system includes a second node and a second network card, the second node includes a second processor, the second node communicates with the second network card through a bus, the second node communicates with multiple computer systems through the second network card, and the device is applied to the second network card. Fig.12 As shown, the data transmission device provided in the embodiment of the present application includes:

[0252] The receiving module 1201 is used to receive multiple data requests, where the multiple data requests come from different nodes;

[0253] The processing module 1202 is used to add multiple data requests to the shared queue respectively, wherein each node corresponds to a core queue, and data requests from the same node enter the same shared queue;

[0254] The processing module 1202 is further used to take out multiple data requests from the shared queue, and add the multiple data requests to the core queue respectively according to the destination virtual processor of each data request in the multiple data requests, wherein data requests with different destination virtual processors enter different core queues;

[0255] The sending module 1203 is used to take out multiple data requests from the core queue and send the multiple data requests to the corresponding destination virtual processor.

[0256] According to this solution, through the two-layer QP architecture in the network card, the two-layer QP architecture includes multiple core QPs in the first layer and multiple shared QPs in the second layer. Among them, each core QP corresponds to a virtual processor in the node one by one, so that the virtual processor in the node can monopolize the core QP, and then the data requests of different destination virtual processors are added to different core queues. Each shared QP corresponds to a node in the network one by one, and a single shared QP supports data transmission of multiple core QPs.

[0257] Taking receiving data requests as an example, if the node sending the data request is called the source node, the virtual processor receiving the data request is the destination virtual processor (generally, the destination virtual processor is the final recipient of the data request). For multiple data requests from the same source node and sent to different destination virtual processors, the multiple data requests can be added to the shared QP corresponding to the source node, and then reach the core QP corresponding to each destination virtual processor. In this way, the virtual processor can monopolize the core QP, meeting the demand for the virtual processor to monopolize the QP; and a single shared QP can support data transmission of multiple core QPs, reducing the CPU overhead in the node.

[0258] In a possible implementation manner, the second network card includes first mapping relationship information, where the first mapping relationship information is used to indicate a mapping relationship between an identity of a node and an identity of a shared queue, the data request includes an identity of a node from which the data request comes, and the multiple data requests are added to the shared queue respectively, including:

[0259] According to the identity of the node in each data request in the multiple data requests, determine the identity of the shared queue corresponding to the node from the first mapping relationship information;

[0260] According to the identity identifier of the shared queue, multiple data requests are added to the corresponding shared queue respectively.

[0261] In this way, nodes in the network can monopolize the shared queue, so that multiple virtual processors can transmit data with multiple nodes, reducing data transmission latency.

[0262] In a possible implementation, the second network card includes second mapping relationship information, where the second mapping relationship information is used to indicate a mapping relationship between an identity of a virtual processor and an identity of a core queue, the data request includes an identity of a destination virtual processor of the data request, and the processing module is used to:

[0263] According to the identity of the destination virtual processor of each data request, determining the identity of the core queue corresponding to the destination virtual processor from the second mapping relationship information;

[0264] According to the identity of the core queue corresponding to the destination virtual processor, the data request is added to the corresponding core queue.

[0265] In this way, the virtual processors in the node can monopolize the core QP without the need to preempt resources in the CPU, thus reducing CPU resource usage.

[0266] Based on the same concept as the method embodiment of the present application, the embodiment of the present application also provides a network card. Fig.13Schematic diagram of the structure of a network card provided in an embodiment of the present application. Fig.13 As shown, the computer system includes a network card and a node, the node includes a processor, and the network card includes:

[0267] A computer bus interface 1301, used to communicate with the node;

[0268] Network interface 1302, for communicating with other computer systems;

[0269] The processor 1303 is used to provide a core queue and a shared queue, and is also used to:

[0270] Acquire multiple data requests from the node through the computer bus interface, and add the multiple data requests to core queues respectively, wherein each virtual processor corresponds to a core queue, and data requests from different virtual processors enter different core queues;

[0271] Taking out the multiple data requests from the core queue, and adding the multiple data requests to the shared queue respectively according to the destination node of each data request in the multiple data requests, wherein each destination node corresponds to a shared queue, and data requests with the same destination node enter the same shared queue;

[0272] The multiple data requests are taken out from the shared queue, and the multiple data requests are sent to the computer system where the corresponding destination nodes are located through the network interface.

[0273] As a possible implementation manner, the processor 1303 provided in the embodiment of the present application may be a DPU.

[0274] The functions of the network card in the embodiment of the present application can be referred to above Figures 6a to 6c , Figures 7 to 12 The detailed description of the network card is not repeated here.

[0275] Based on the same concept as the method embodiment of the present application, the embodiment of the present application also provides a network card chip. Fig.14 Schematic diagram of the structure of a network card chip provided in an embodiment of the present application. Fig.14 As shown, the computer system includes a network card and a node, the network card and the node communicate through a computer bus, the node communicates with other nodes through the network card, and the network card includes a network card chip 1401, a computer bus interface 1402 and a network interface 1403;

[0276] The network card chip 1401 includes:

[0277] A power supply 1411, used to supply power to the main body of the network card chip;

[0278] The main body 1412 of the network card chip is used to provide a core queue and a shared queue, wherein the network card chip is also used to:

[0279] Adding the multiple data requests to core queues respectively, wherein each virtual processor corresponds to a core queue, and data requests from different virtual processors enter different core queues;

[0280] Taking out the multiple data requests from the core queue, and adding the multiple data requests to the shared queue respectively according to the destination node of each data request in the multiple data requests, wherein each destination node corresponds to a shared queue, and data requests with the same destination node enter the same shared queue;

[0281] The multiple data requests are taken out from the shared queue, and the multiple data requests are sent to the computer system where the corresponding destination nodes are located through the network interface.

[0282] The functions of the network card chip in the embodiment of the present application can be referred to above Figures 6a to 6c , Figures 7 to 12 The detailed description of the network card is not repeated here.

[0283] Based on the same concept as the method embodiment of the present application, the embodiment of the present application further provides a computing device, which may be a server, a storage node, etc.

[0284] Fig.14 It is a structural diagram of a computing device provided in an embodiment of the present application.

[0285] like Fig.15 As shown, computing device 1500 includes a processor 1501 , memory 102 , and a network interface 1503 .

[0286] The processor 1501 may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or the processor may be any conventional processor, etc.

[0287] Among them, the non-volatile memory can be a read-only memory (ROM), a programmable ROM (PROM), an erasable PROM (EPROM), an electrically erasable programmable read-only memory (EEPROM) or a flash memory. The volatile memory can be a random access memory (RAM), which is used as an external cache. By way of example but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous connection dynamic random access memory (SLDRAM) and direct memory bus random access memory (DR RAM).

[0288] For example, a computer program may be stored in the memory 1502, and the processor 1501 implements the steps in the above method embodiment when executing the computer program. Alternatively, the processor 1501 implements the functions of each module in the above device embodiment when executing the computer program. For example, the computer program may be divided into one or more modules / units, and the one or more modules / units may be a series of computer program instruction segments that can perform specific functions. The one or more modules / units are stored in the memory 1502 and executed by the processor 1501 to complete the present application. For example, a computer program may be divided into multiple modules, such as the modules in the device described above.

[0289] The network interface 1503 is used to send and receive data, for example, to send data processed by the processor 1501 to other computing devices, or to receive data sent by other computing devices.

[0290] Of course, to simplify, Fig.15Only some of the components of the computing device 1500 related to the present application are shown, and components such as buses, input / output interfaces, etc. are omitted. In addition, according to specific application situations, the computing device 1500 may also include any other appropriate components. In addition, the computing device may be a desktop computer, a notebook, a handheld computer, a cloud server, and other computing devices. Those skilled in the art will understand that Fig.15 This is only an example of the computing device 1500 and does not constitute a limitation of the computing device. It may include more or fewer components than shown in the figure, or combine certain components, or different components. For example, the computing device may also include an input device, an output device, a network access device, a bus, etc. By way of example, the input device may be a microphone array, and may also include, for example, a keyboard, a mouse, etc. By way of example, the output device may output various information to the outside, and may include, for example, a display, a speaker, a printer, a communication network and a remote output device connected thereto, etc.

[0291] In addition to the above methods, devices and electronic devices, embodiments of the present application may also provide a computer program product, which includes computer program instructions, which, when executed by a processor, cause the processor to execute the steps in the methods of various embodiments of the present application described in the "Method" section of this specification. Wherein, the computer program product can be written in any combination of one or more programming languages ​​to write a computer program code for performing the operation of the embodiments of the present application, and the programming language includes an object-oriented programming language, such as Java, C++, etc., and also includes a conventional procedural programming language, such as "C" language or similar programming language. Wherein, the computer program code can be in source code form, object code form, executable file or some intermediate form, etc. The computer program code can be executed completely on the user computing device, partially on the user device, as an independent software package, partially on the user computing device, partially on the remote computing device, or completely on the remote computing device or server.

[0292] In addition, the embodiment of the present application may also provide a computer-readable storage medium on which computer program instructions are stored, and the computer program instructions, when executed by the processor, cause the processor to perform the steps in the display control method according to various embodiments of the present application described in the "Method" section of the present specification. The computer-readable storage medium may adopt any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. The readable storage medium may, for example, include but is not limited to electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or devices, or any combination of the above. More specific examples of readable storage media (non-exhaustive list) include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. It should be noted that the content contained in the computer-readable medium may be appropriately increased or decreased according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media do not include electrical carrier signals and telecommunication signals.

[0293] The method steps in the embodiments of the present application can be implemented by hardware or by a processor executing software instructions. The software instructions can be composed of corresponding software modules, and the software modules can be stored in random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, mobile hard disks, CD-ROMs, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor so that the processor can read information from the storage medium and write information to the storage medium. Of course, the storage medium can also be a component of the processor. The processor and the storage medium can be located in an ASIC.

[0294] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium or transmitted through the computer-readable storage medium. The computer instructions may be transmitted from a website site, computer, server or data center to another website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium may be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrated. The available medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid state disk (SSD)), etc.

[0295] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0296] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0297] The basic principles of the present application are described above in conjunction with specific embodiments. However, it should be noted that the advantages, strengths, effects, etc. mentioned in the present application are only examples and not limitations, and it cannot be considered that these advantages, strengths, effects, etc. are required by each embodiment of the present application. In addition, the specific details disclosed above are only for the purpose of illustration and ease of understanding, not for limitation, and the above details do not limit the present application to being implemented by adopting the above specific details.

[0298] The block diagrams of the devices, apparatuses, equipment, and systems involved in this application are only illustrative examples and are not intended to require or imply that they must be connected, arranged, and configured in the manner shown in the block diagram. As will be appreciated by those skilled in the art, these devices, apparatuses, equipment, and systems can be connected, arranged, and configured in any manner. Words such as "including", "comprising", "having", etc. are open words, referring to "including but not limited to", and can be used interchangeably with them. The words "or" and "and" used here refer to the words "and / or" and can be used interchangeably with them, unless the context clearly indicates otherwise. The words "such as" used here refer to the phrase "such as but not limited to", and can be used interchangeably with them.

[0299] It should also be noted that in the apparatus, device and method of the present application, each component or each step can be decomposed and / or recombined. Such decomposition and / or recombination should be regarded as equivalent solutions of the present application.

[0300] The above description has been given for the purpose of illustration and description. In addition, this description is not intended to limit the embodiments of the present application to the forms disclosed herein. Although multiple example aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, changes, additions and sub-combinations thereof.

[0301] It should be understood that the various numerical numbers involved in the embodiments of the present application are only used for the convenience of description and are not used to limit the scope of the embodiments of the present application.

Claims

1. A data transmission method, characterized in that: The first computer system includes a first node and a first network card, the first node includes a first processor, the first node communicates with the first network card through a bus, and the first node communicates with multiple computer systems through the first network card. The method includes: The first network card receives a plurality of data requests, where the plurality of data requests come from different virtual processors in the first processor respectively; The first network card adds the multiple data requests to core queues respectively, wherein each virtual processor corresponds to a core queue, and data requests from different virtual processors enter different core queues; The first network card takes out the multiple data requests from the core queue, and adds the multiple data requests to a shared queue respectively according to a destination node of each of the multiple data requests, wherein each destination node corresponds to a shared queue, and data requests with the same destination node enter the same shared queue; The first network card takes out the multiple data requests from the shared queue, and sends the multiple data requests to a destination computer system where a corresponding destination node is located.

2. The method according to claim 1, characterized in that The first network card is configured with first mapping relationship information, the first mapping relationship information is used to indicate a mapping relationship between an identity of a node and an identity of a shared queue, and the adding the multiple data requests to the shared queue respectively according to a destination node of each of the multiple data requests comprises: According to the identity of the destination node, determining the identity of the shared queue corresponding to the destination node from the first mapping relationship information; The data request is added to the shared queue according to the identity identifier of the shared queue corresponding to the destination node.

3. The method according to claim 1 or 2, characterized in that: The first network card is configured with second mapping relationship information, the second mapping relationship information is used to indicate a mapping relationship between an identity of a virtual processor and an identity of a core queue, the data request includes the identity of the virtual processor from which the data request comes, and the adding the multiple data requests to the core queues respectively includes: According to the identity of the virtual processor from which each of the multiple data requests comes, determining from the second mapping relationship information the identity of the core queue to which each of the data requests is to be added; According to the identity identifier of the core queue, the multiple data requests are added to the core queue respectively.

4. A data transmission method, characterized in that: The second computer system includes a second node and a second network card, the second node includes a second processor, the second node communicates with the second network card via a bus, and the second node communicates with a plurality of computer systems via the second network card, the method including: The second network card receives multiple data requests, where the multiple data requests come from different nodes; The second network card adds the multiple data requests to a shared queue respectively, wherein each node corresponds to a core queue, and data requests from the same node enter the same shared queue; The second network card takes out the multiple data requests from the shared queue, and adds the multiple data requests to the core queue respectively according to the destination virtual processor of each of the multiple data requests, wherein the data requests with different destination virtual processors enter different core queues; The second network card takes out the multiple data requests from the core queue, and sends the multiple data requests to corresponding destination virtual processors.

5. A data transmission device, characterized in that: The first computer system includes a first node and a first network card, the first node includes a first processor, the first node communicates with the first network card through a bus, the first node communicates with a plurality of computer systems through the first network card, the device is applied to the first network card, and the device includes: A receiving module, configured to receive a plurality of data requests, wherein the plurality of data requests are respectively from different virtual processors in the first processor, and the destination node of each of the data requests is different; A processing module, used for adding the multiple data requests to core queues respectively, wherein each virtual processor corresponds to a core queue, and data requests from different virtual processors enter different core queues; The processing module is further used to take out the multiple data requests from the core queue, and add the multiple data requests to the shared queue respectively according to the destination node of each data request in the multiple data requests, wherein each destination node corresponds to a shared queue, and data requests with the same destination node enter the same shared queue; The sending module is used to take out the multiple data requests from the shared queue and send the multiple data requests to the destination computer system where the corresponding destination node is located.

6. The device according to claim 5, characterized in that The first network card is configured with first mapping relationship information, where the first mapping relationship information is used to indicate a mapping relationship between an identity of a node and an identity of a shared queue, and the processing module is used to: According to the identity of the destination node, determining the identity of the shared queue corresponding to the destination node from the first mapping relationship information; The data request is added to the shared queue according to the identity identifier of the shared queue corresponding to the destination node.

7. The device according to claim 5 or 6, characterized in that The first network card is configured with second mapping relationship information, the second mapping relationship information is used to indicate a mapping relationship between an identity of a virtual processor and an identity of a core queue, the data request includes an identity of a virtual processor from which the data request comes, and the processing module is used to: According to the identity of the virtual processor from which each of the multiple data requests comes, determining from the second mapping relationship information the identity of the core queue to which each of the data requests is to be added; According to the identity identifier of the core queue, the multiple data requests are added to the core queue respectively.

8. A data transmission device, characterized in that: The second computer system includes a second node and a second network card, the second node includes a second processor, the second node communicates with the second network card via a bus, the second node communicates with a plurality of computer systems via the second network card, the device is applied to the second network card, and the device includes: A receiving module, used for receiving multiple data requests, where the multiple data requests come from different nodes; A processing module, used for adding the multiple data requests to a shared queue respectively, wherein each node corresponds to a core queue, and data requests from the same node enter the same shared queue; The second network card takes out the multiple data requests from the shared queue, and adds the multiple data requests to the core queue respectively according to the destination virtual processor of each of the multiple data requests, wherein the data requests with different destination virtual processors enter different core queues; The second network card takes out the multiple data requests from the core queue, and sends the multiple data requests to corresponding destination virtual processors.

9. A network card, characterized in that: The computer system includes a network card and a node, wherein the node includes a processor, and the network card includes: A computer bus interface for communicating with the node; Network interfaces for communicating with other computer systems; Processors are used to provide core queues and shared queues, and are also used to: Acquire multiple data requests from the node through the computer bus interface, and add the multiple data requests to core queues respectively, wherein each virtual processor corresponds to a core queue, and data requests from different virtual processors enter different core queues; The multiple data requests are taken out from the core queue, and the multiple data requests are added to the shared queue respectively according to the destination node of each data request in the multiple data requests, wherein each destination node corresponds to a shared queue, Data requests with the same target node enter the same shared queue; The multiple data requests are taken out from the shared queue, and the multiple data requests are sent to the computer system where the corresponding destination nodes are located through the network interface.

10. A network card chip, characterized in that: The computer system includes a network card and a node, the network card and the node communicate via a computer bus, the node communicates with other nodes via the network card, and the network card includes a network card chip, a computer bus interface and a network interface; The network card chip comprises: A power supply, used to supply power to the main body of the network card chip; The main body of the network card chip is used to provide a core queue and a shared queue, wherein the network card chip is also used to: Adding multiple data requests to core queues respectively, wherein each virtual processor corresponds to a core queue, and data requests from different virtual processors enter different core queues; The multiple data requests are taken out from the core queue, and the multiple data requests are added to the shared queue respectively according to the destination node of each data request in the multiple data requests, wherein each destination node corresponds to a shared queue, Data requests with the same target node enter the same shared queue; The multiple data requests are taken out from the shared queue, and the multiple data requests are sent to the computer system where the corresponding destination nodes are located through the network interface.

11. A computer, characterized in that: The method comprises a node and a network card, wherein the network card is used to execute the method according to any one of claims 1 to 3, or execute the method according to claim 4.

12. A data transmission device, characterized in that: include: at least one memory for storing a program; At least one processor is used to execute the program stored in the memory. When the program stored in the memory is executed, the processor is used to execute the method according to any one of claims 1 to 3, or execute the method according to claim 4.

13. A data transmission device, characterized in that: The device runs computer program instructions to perform the method according to any one of claims 1 to 3, or to perform the method according to claim 4.

14. A computer storage medium, wherein instructions are stored in the computer storage medium, and when the instructions are executed on a computer, the computer executes the method according to any one of claims 1 to 3, or executes the method according to claim 4.

15. A computer program product comprising instructions, which, when executed on a computer, enables the computer to execute the method according to any one of claims 1 to 3, or to execute the method according to claim 4.

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