Memory cell structure, memory cell array structure and manufacturing method thereof

Abstract

The embodiment of the invention relates to the technical field of semiconductors, and provides a memory cell structure, a memory cell array structure and a manufacturing method thereof, and the memory cell structure comprises a grid electrode which comprises a main body part, and a first epitaxial part and a second epitaxial part which are in contact connection with the two ends of the main body part in a first direction respectively, a first annular groove is defined by the grid; the gate dielectric layer covers the inner wall of the first annular groove in a shape-preserving manner, and a second annular groove is defined by the gate dielectric layer; the semiconductor layer covers the inner wall of the second annular groove in a shape-preserving manner, and a third annular groove provided with a first groove and a second groove which are oppositely arranged in a spaced manner in the second direction is defined by the semiconductor layer; the first groove is filled with the first conductive structure; the second groove is filled with the second conductive structure; and the capacitor structure comprises a lower electrode layer, and the lower electrode layer is in contact connection with the second conductive structure. The embodiment of the invention is at least beneficial to improving the electrical performance of the storage unit structure.

Description

Technical Field

[0001] The disclosed embodiments relate to the field of semiconductor technology, and in particular to a memory cell structure, a memory cell array structure, and a method for manufacturing the same. Background Art

[0002] As the integration density of semiconductor structures develops towards a higher direction, while studying the arrangement of transistors in semiconductor structures and how to reduce the size of single functional devices in dynamic semiconductor structures, it is also necessary to improve the electrical performance of small-sized functional devices.

[0003] When a vertical gate-all-around (GAA) transistor structure is used as the access transistor of a semiconductor structure, the area occupied by the transistor can reach 4F. 2 (F: the minimum pattern size obtainable under given process conditions). In principle, higher density efficiency can be achieved, but due to the reduction in the size of the functional device itself, it is more likely to affect the electrical performance of the functional device. Summary of the invention

[0004] The embodiments of the present disclosure provide a memory cell structure, a memory cell array structure and a manufacturing method thereof, which are at least beneficial to improving the electrical performance of the memory cell structure.

[0005] According to some embodiments of the present disclosure, on the one hand, an embodiment of the present disclosure provides a storage unit structure, including: a gate, the gate including a main body, and a first epitaxial part and a second epitaxial part respectively contacting and connected to both ends of the main body in a first direction, the first epitaxial part and the second epitaxial part extending in a plane perpendicular to the first direction in a direction away from the main body, and the gate itself encloses a first annular groove; a gate dielectric layer, the gate dielectric layer conformally covers the first inner wall of the first annular groove, and the gate dielectric layer itself encloses a second annular groove; a semiconductor layer, the semiconductor layer conformally covers the second inner wall of the second annular groove, and the semiconductor layer itself encloses a third annular groove, the third annular groove has a first groove and a second groove arranged at relative intervals along a second direction, and the first direction and the second direction intersect; a first conductive structure, filling the first groove; a second conductive structure, filling the second groove; a capacitor structure comprising a lower electrode layer, an upper electrode layer and a capacitor dielectric layer located between the lower electrode layer and the upper electrode layer, the lower electrode layer is in contact with the second conductive structure.

[0006] In some embodiments, the second conductive structure has a contact surface away from the semiconductor layer, and the lower electrode layer is in contact with the contact surface.

[0007] In some embodiments, along the second direction, a groove depth of the third annular groove is less than or equal to a length of the second conductive structure.

[0008] In some embodiments, along the cross-section perpendicular to the first direction, the cross-sectional shapes of the first annular groove, the second annular groove and the third annular groove are all square rings, circular rings, elliptical rings or N-sided rings, where N is a positive integer greater than or equal to 5.

[0009] In some embodiments, the lower electrode layer includes a supporting portion, and a first inner extension portion and a second inner extension portion respectively contacting and connected to both ends of the supporting portion in the first direction, the supporting portion, the first inner extension portion and the second inner extension portion are all annular structures and the three form a hollow area, and the first inner extension portion and the second inner extension portion extend toward a direction close to the center of the hollow area in a plane perpendicular to the first direction.

[0010] In some embodiments, the memory cell structure further includes: a third conductive structure located on a side of the support portion away from the main body portion in the second direction.

[0011] In some embodiments, the second conductive structure is in contact with the third conductive structure, and the second conductive structure and the third conductive structure jointly surround a side wall of the support portion that is away from the hollow region and extends along the first direction.

[0012] In some embodiments, along the third direction, the maximum width of the gate is greater than the maximum width of the lower electrode layer, and the first direction, the second direction and the third direction intersect each other.

[0013] According to some embodiments of the present disclosure, on the other hand, the embodiments of the present disclosure further provide a memory cell array structure, comprising: a plurality of memory cell structures as described in any one of the above items, the plurality of memory cell structures are arranged along the first direction and / or the third direction, the first direction, the second direction and the third direction intersect each other; a plurality of the memory cell structures are arranged in contact along the first direction, the gate contacts in the adjacent memory cell structures along the first direction are connected; and / or a plurality of the memory cell structures are arranged at intervals along the third direction, the memory cell array structure further comprising a bit line structure extending along the third direction, one bit line structure being in contact with a plurality of the first conductive structures arranged at intervals along the third direction.

[0014] According to some embodiments of the present disclosure, another aspect of the embodiments of the present disclosure further provides a method for manufacturing a memory cell array structure, comprising: providing a substrate; forming a plurality of memory cell structures arranged along a first direction and / or a third direction on the substrate; the memory cell structure comprising: a semiconductor layer, a gate dielectric layer, a gate, a first conductive structure, a second conductive structure and a capacitor structure; wherein the gate comprises a main body and a first extension portion and a second extension portion respectively contacting and connected to both ends of the main body in the first direction, the first extension portion and the second extension portion extending in a plane perpendicular to the first direction in a direction away from the main body, and the gate itself encloses a first annular groove; The gate dielectric layer conformally covers the first inner wall of the first annular groove, and the gate dielectric layer itself forms a second annular groove; the semiconductor layer conformally covers the second inner wall of the second annular groove, and the semiconductor layer itself forms a third annular groove, the third annular groove has a first groove and a second groove arranged opposite to each other along a second direction, and the first direction and the second direction intersect; the first conductive structure fills the first groove, and the second conductive structure fills the second groove; the capacitor structure includes a lower electrode layer, an upper electrode layer and a capacitor dielectric layer located between the lower electrode layer and the upper electrode layer, and the lower electrode layer is in contact with the second conductive structure.

[0015] In some embodiments, the steps of forming the semiconductor layer, the gate dielectric layer and the gate include: forming a stacking structure on the substrate, the stacking structure including a first sacrificial layer and a second sacrificial layer alternately stacked along the first direction; etching the stacking structure to form a first through hole that penetrates the stacking structure in the first direction, the first through hole including a first sub-through hole formed in each of the first sacrificial layers and a second sub-through hole formed in each of the second sacrificial layers, the plane perpendicular to the first direction is a reference plane, the area of ​​the orthographic projection of the first sub-through hole on the reference plane is larger than the area of ​​the orthographic projection of the second sub-through hole on the reference plane; forming a semiconductor layer on the surface of each of the second sacrificial layers exposed by the first through hole, with a spacing between adjacent semiconductor layers along the first direction; conformally covering the surface of the remaining first through holes with a layer of the gate dielectric layer; forming the gate that fills the remaining first through holes.

[0016] In some embodiments, after forming the first through hole and before forming the semiconductor layer, it also includes: etching the stacked structure to form a second through hole that penetrates the stacked structure in the first direction, the second through hole includes a third sub-through hole formed in each of the first sacrificial layers and a fourth sub-through hole formed in each of the second sacrificial layers, the plane perpendicular to the first direction is a reference plane, the area of ​​the orthographic projection of the third sub-through hole on the reference plane is larger than the area of ​​the orthographic projection of the fourth sub-through hole on the reference plane, the first through hole and the second through hole are arranged at intervals along the second direction; forming a first dielectric layer that fills the first through hole and the second through hole respectively; removing the second sacrificial layer surrounding the first through hole and the second through hole to form a plurality of lateral gaps spaced along the first direction, the lateral gaps being located between adjacent first sacrificial layers along the first direction; forming the first conductive structure and the second conductive structure in the lateral gaps; removing the first dielectric layer located in the first through hole.

[0017] In some embodiments, the plurality of storage unit structures are arranged at intervals along the third direction; in the step of forming the first through holes and the second through holes, the plurality of first through holes are arranged at intervals along the third direction, and the plurality of second through holes are arranged at intervals along the third direction; after forming the first dielectric layer and before removing the first sacrificial layer, it also includes: etching the stacked structure between the first dielectric layers adjacent to each other along the third direction to form a plurality of grooves arranged at intervals along the third direction, the grooves exposing the first dielectric layers on both sides thereof.

[0018] In some embodiments, the step of forming the first through hole and the second through hole includes: patterning the stacking structure to form a first main through hole and a second main through hole that penetrate the stacking structure in the first direction, the first main through hole and the second main through hole are arranged at intervals along the second direction, the first main through hole located in the second sacrificial layer serves as the second sub-through hole, and the second main through hole located in the second sacrificial layer serves as the fourth sub-through hole; and laterally etching the first sacrificial layer exposed by the first main through hole and the second main through hole to form a first sub-through hole in each of the first sacrificial layers, and to form a third sub-through hole in each of the first sacrificial layers.

[0019] In some embodiments, the step of forming the capacitor structure includes: forming a stacked structure on the substrate, the stacked structure including a first sacrificial layer and a second sacrificial layer alternately stacked along the first direction; etching the stacked structure to form a third through hole penetrating the stacked structure in the first direction, the third through hole including a fifth sub-through hole formed in each of the first sacrificial layers and a sixth sub-through hole formed in each of the second sacrificial layers, the plane perpendicular to the first direction being a reference plane, the area of ​​the orthographic projection of the fifth sub-through hole on the reference plane being smaller than the area of ​​the orthographic projection of the sixth sub-through hole on the reference plane; forming a plurality of lower electrode layers arranged at intervals along the first direction, each of the lower electrode layers covering a surface of the second sacrificial layer exposed by the third through hole, and covering surfaces of two first sacrificial layers located on both sides of the second sacrificial layer extending along the direction perpendicular to the first direction; conformally covering the surfaces of the remaining third through holes with a layer of the capacitor dielectric layer; and forming the upper electrode layer filling the remaining third through holes.

[0020] The technical solution provided by the embodiments of the present disclosure has at least the following advantages:

[0021] On the one hand, the gate itself is designed to enclose a first annular groove to increase the surface area of ​​the gate. On this basis, the gate dielectric layer conformally covers the first inner wall of the gate, and the semiconductor layer conformally covers the second inner wall of the gate dielectric layer, which is conducive to increasing the facing area between the gate and the semiconductor layer. It can be understood that the gate, the gate dielectric layer, the semiconductor layer, the first conductive structure and the second conductive structure constitute a transistor structure. When the transistor structure is in a working state, at least part of the semiconductor layer serves as the channel region of the transistor structure. Therefore, increasing the facing area between the gate and the semiconductor layer is conducive to increasing the gate's control ability over the semiconductor layer, that is, the channel region, so as to reduce the leakage current in the transistor structure, such as the leakage current at the first conductive structure and the second conductive structure.

[0022] On the other hand, the semiconductor layer itself forms a third annular groove to increase the surface area of ​​the semiconductor layer. On this basis, the first conductive structure and the second conductive structure respectively fill part of the third annular groove and are arranged relatively spaced apart, which is beneficial to increase the contact area between the first conductive structure and the semiconductor layer to reduce the contact resistance between the first conductive structure and the semiconductor layer, and is beneficial to increase the contact area between the second conductive structure and the semiconductor layer to reduce the contact resistance between the second conductive structure and the semiconductor layer.

[0023] In this way, the two aspects cooperate with each other, and when the size of the transistor structure is reduced, the electrical performance of the storage unit structure can be improved by increasing the facing area between the gate and the semiconductor layer, and increasing the contact area between the first conductive structure and the second conductive structure and the semiconductor layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings, which do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements, and the figures in the drawings do not constitute a scale limitation unless otherwise stated. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0025] Figure 1 A schematic cross-sectional structure diagram of a storage unit structure provided by an embodiment of the present disclosure;

[0026] Figure 2 A schematic diagram of a three-dimensional structure of a gate in a memory cell structure provided in an embodiment of the present disclosure;

[0027] Figure 3 A schematic diagram of a three-dimensional structure of a gate dielectric layer in a memory cell structure provided in an embodiment of the present disclosure;

[0028] Figure 4 4a is a schematic diagram of a three-dimensional structure of a semiconductor layer in a memory cell structure provided in an embodiment of the present disclosure;

[0029] Figure 4 4b is a schematic diagram of a top view of the structure of the third annular groove in the storage unit structure provided in one embodiment of the present disclosure;

[0030] Figure 5 5a is a schematic diagram of a three-dimensional structure of a lower electrode layer in a memory cell structure provided in an embodiment of the present disclosure;

[0031] Figure 5 5b is a schematic diagram of a top view of a lower electrode layer in a memory cell structure provided in an embodiment of the present disclosure;

[0032] Figure 6 Another schematic cross-sectional view of a storage unit structure provided by an embodiment of the present disclosure;

[0033] Figure 7 and Figure 8 Two schematic diagrams of top views of a storage unit structure provided in one embodiment of the present disclosure;

[0034] Fig. 9 A schematic diagram of another cross-sectional structure of a storage unit structure provided by an embodiment of the present disclosure;

[0035] Fig.10 A schematic diagram of a three-dimensional structure of a storage cell array structure provided by another embodiment of the present disclosure;

[0036] Figures 11 to 13 Three partial cross-sectional structural schematic diagrams of a memory cell array structure provided by another embodiment of the present disclosure;

[0037] Figures 14 to 35 A schematic diagram of cross-sectional structures corresponding to each step in a method for manufacturing a memory cell array structure provided in yet another embodiment of the present disclosure. DETAILED DESCRIPTION

[0038] As known from the background art, the electrical performance of the memory cell structure needs to be improved.

[0039] The present disclosure provides a memory cell structure, a memory cell array structure and a manufacturing method thereof. In the memory cell structure, on the one hand, the gate itself is designed to form a first annular groove, the gate dielectric layer conformally covers the first inner wall of the gate, and the semiconductor layer conformally covers the second inner wall of the gate dielectric layer, which is conducive to increasing the facing area between the gate and the semiconductor layer, so as to increase the facing area between the gate and the semiconductor layer, thereby facilitating the control ability of the gate over the semiconductor layer, so as to reduce the leakage current in the memory bile duct structure. On the other hand, the semiconductor layer itself forms a third annular groove, and the first conductive structure and the second conductive structure respectively fill part of the third annular groove and are arranged at a relative interval, which is conducive to increasing the contact area between the first conductive structure and the semiconductor layer, so as to reduce the contact resistance between the first conductive structure and the semiconductor layer, and is conducive to increasing the contact area between the second conductive structure and the semiconductor layer, so as to reduce the contact resistance between the second conductive structure and the semiconductor layer. In this way, the two aspects cooperate to improve the electrical performance of the memory cell structure.

[0040] The following will describe the various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, it will be appreciated by those skilled in the art that in the various embodiments of the present disclosure, many technical details are provided in order to enable the reader to better understand the embodiments of the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the embodiments of the present disclosure can be implemented.

[0041] An embodiment of the present disclosure provides a memory cell structure, which will be described in detail below with reference to the accompanying drawings. Figure 1 A schematic cross-sectional structure diagram of a storage unit structure provided by an embodiment of the present disclosure; Figure 2 A schematic diagram of a three-dimensional structure of a gate in a memory cell structure provided in an embodiment of the present disclosure; Figure 3 A schematic diagram of a three-dimensional structure of a gate dielectric layer in a memory cell structure provided in an embodiment of the present disclosure; Figure 4 4a is a schematic diagram of a three-dimensional structure of a semiconductor layer in a memory cell structure provided in an embodiment of the present disclosure; Figure 4 4b is a schematic diagram of a top view of the structure of the third annular groove in the storage unit structure provided in one embodiment of the present disclosure; Figure 5 5a is a schematic diagram of a three-dimensional structure of a lower electrode layer in a memory cell structure provided in an embodiment of the present disclosure; Figure 5 5b is a schematic diagram of a top view of a lower electrode layer in a memory cell structure provided in an embodiment of the present disclosure; Figure 6 Another schematic cross-sectional view of a storage unit structure provided by an embodiment of the present disclosure; Figure 7 and Figure 8 Two schematic diagrams of top views of a storage unit structure provided in one embodiment of the present disclosure; Fig. 9 A schematic diagram of another cross-sectional structure of a storage unit structure provided in an embodiment of the present disclosure.

[0042] refer to Figures 1 to 4 The memory cell structure 100 includes: a gate 101, the gate 101 includes a main body 111, and a first extension portion 121 and a second extension portion 131 respectively contacting and connecting with two ends of the main body 111 in a first direction X, the first extension portion 121 and the second extension portion 131 extend in a plane perpendicular to the first direction X in a direction away from the main body 111, and the gate 101 itself surrounds a first annular groove 141; a gate dielectric layer 102, the gate dielectric layer 102 conformally covers a first inner wall 141a of the first annular groove 141, and the gate dielectric layer 102 itself surrounds a second annular groove 112; a semiconductor layer 103, the semiconductor layer 103 The second inner wall 112a of the second annular groove 112 is conformally covered, and the semiconductor layer 103 itself forms a third annular groove 113, the third annular groove 113 has a first groove 123 and a second groove 133 arranged relatively spaced apart along the second direction Y, and the first direction X and the second direction Y intersect; the first conductive structure 104 fills the first groove 123; the second conductive structure 105 fills the second groove 133; the capacitor structure 106 includes a lower electrode layer 116, an upper electrode layer 136 and a capacitor dielectric layer 126 located between the lower electrode layer 116 and the upper electrode layer 136, and the lower electrode layer 116 is in contact with the second conductive structure 105.

[0043] The plane perpendicular to the first direction X is a plane formed by the second direction Y and the third direction Z. The first direction X, the second direction Y and the third direction Z intersect each other. In one example, the first direction X, the second direction Y and the third direction Z are orthogonal to each other.

[0044] Understandably, reference Figure 1 and Figure 2The first annular groove 141 is surrounded by the main body 111, the first extension 121 and the second extension 131. The first annular groove 141 can be regarded as a groove whose cross-sectional shape along each cross-sectional direction parallel to the first direction X is C-shaped, and the head end and the tail end of the C-shaped groove are connected. In other words, the first annular groove 141 can be similar to a double-sided H-shaped groove, that is, the appearance structure of the gate 101 is similar to the appearance structure of an H-shaped heavy I-beam pulley or an H-shaped double-sided track wheel pulley.

[0045] It should be noted that, in order to clearly illustrate the main body 111, the first extension portion 121 and the second extension portion 131, Figure 1 The gate 101 is divided into the above three parts by dotted lines. Figure 2 The main body 111 and the first extension 121 are divided by a dotted line. It can be understood that Figure 2 The main body portion 111 and the second extension portion 131 can be clearly distinguished by themselves.

[0046] refer to Figures 2 to 4 Since the gate dielectric layer 102 conformally covers the first inner wall 141a of the first annular groove 141, the second annular groove 112 formed by the gate dielectric layer 102 itself is defined based on the first annular groove 141, and the shape of the second annular groove 112 is similar to that of the first annular groove 141, except that the groove depth of the second annular groove 112 is less than that of the first annular groove 141. Since the semiconductor layer 103 conformally covers the second inner wall 112a of the second annular groove 112, the third annular groove 113 formed by the semiconductor layer 103 itself is defined based on the second annular groove 112, and the shape of the third annular groove 113 is similar to that of the second annular groove 112, except that the groove depth of the third annular groove 113 is less than that of the second annular groove 112.

[0047] It can be understood that the groove depths of the first annular groove 141, the second annular groove 112 and the third annular groove 113 refer to: the distance between the opening of the groove and the bottom surface corresponding to the opening, and the depth direction of the groove depths of any area of ​​the above three is perpendicular to the first direction X.

[0048] It should be noted that, in order to clearly illustrate the structure of the gate dielectric layer 102, Figure 3 In the figure, the top layer of the gate dielectric layer 102 is drawn in perspective, and different filling methods are used for the gate dielectric layer 102 located on the sidewall of the main body 111 extending along the first direction X and the gate dielectric layer 102 in other areas. In order to clearly illustrate the structure of the gate 101, Figure 2 The top layer of the gate 101, i.e., the first extension 121, is drawn in perspective. In order to clearly illustrate the structure of the gate 101, Figure 4In FIG. 4 a , the top layer in the semiconductor layer 103 is drawn in a perspective manner.

[0049] refer to Figure 4 In FIG. 4 b , the first groove 123 and the second groove 133 are actually partial spaces of the third annular groove 113 . The first groove 123 and the second groove 133 are located at two ends of the third annular groove 113 along the second direction Y, respectively.

[0050] In some embodiments, reference Figure 4 In Figure 4b, the third annular groove 113 can be divided into a first groove 123 and a second groove 133 arranged relatively spaced apart along the second direction Y, and a third groove 143 and a fourth groove 153 arranged relatively spaced apart along the third direction Z, wherein Figure 4 In the clockwise direction of 4b, the first groove 123, the third groove 143, the second groove 133 and the fourth groove 153 are connected in sequence, that is, the first groove 123, the third groove 143, the second groove 133 and the fourth groove 153 together constitute the entire third annular groove 113.

[0051] It should be noted that Figure 4 The division of the first groove 123, the third groove 143, the second groove 133 and the fourth groove 153 in 4b is only an example. The division of the third groove 143 and the fourth groove 153 is to space the first groove 123 and the second groove 133 from each other to ensure that the first conductive structure 104 filling the first groove 123 and the second conductive structure 105 filling the second groove 133 are spaced from each other.

[0052] It can be understood that the gate 101, the gate dielectric layer 102, the semiconductor layer 103, the first conductive structure 104 and the second conductive structure 105 constitute a transistor structure, one of the first conductive structure 104 and the second conductive structure 105 can be used as the source of the transistor structure, and the other of the first conductive structure 104 and the second conductive structure 105 can be used as the drain of the transistor structure. In addition, when the transistor structure is in a working state, at least a portion of the semiconductor layer 103 can be used as a channel region of the transistor structure. It should be noted that the transistor structures described below are all transistor structures composed of the gate 101, the gate dielectric layer 102, the semiconductor layer 103, the first conductive structure 104 and the second conductive structure 105.

[0053] Thus, on the one hand, the gate 101 itself is designed to form a first annular groove 141 to increase the surface area of ​​the gate 101. On this basis, the gate dielectric layer 102 conformally covers the first inner wall 141a of the gate 101, and the semiconductor layer 103 conformally covers the second inner wall 112a of the gate dielectric layer 102, which is conducive to increasing the facing area between the gate 101 and the semiconductor layer 103, thereby facilitating increasing the facing area between the gate 101 and the semiconductor layer 103, so as to increase the control capability of the gate 101 over the semiconductor layer 103, that is, the channel region, thereby facilitating reducing the leakage current in the transistor structure, such as the leakage current at the first conductive structure 104 and the second conductive structure 105.

[0054] On the other hand, the semiconductor layer 103 itself forms a third annular groove 113 to increase the surface area of ​​the semiconductor layer 103. On this basis, the first conductive structure 104 and the second conductive structure 105 are relatively spaced and respectively fill a part of the third annular groove 113, which is beneficial to increase the contact area between the first conductive structure 104 and the semiconductor layer 103 to reduce the contact resistance between the first conductive structure 104 and the semiconductor layer 103, and is beneficial to increase the contact area between the second conductive structure 105 and the semiconductor layer 103 to reduce the contact resistance between the second conductive structure 105 and the semiconductor layer 103.

[0055] In this way, the two aspects cooperate with each other. When the size of the transistor structure is reduced, the electrical performance of the storage cell structure 100 can be improved by increasing the facing area between the gate 101 and the semiconductor layer 103, and increasing the contact area between the first conductive structure 104 and the second conductive structure 105 and the semiconductor layer 103.

[0056] The memory cell structure provided by an embodiment of the present disclosure will be described in more detail below with reference to the accompanying drawings.

[0057] refer to Figure 1 , a plane perpendicular to the first direction X is a reference plane a, and the orthographic projection of one of the first extension portion 121 and the second extension portion 131 on the reference plane a is located in the orthographic projection of the other on the reference plane a.

[0058] In some embodiments, the orthographic projection of the first extension portion 121 on the reference plane a may coincide with the orthographic projection of the second extension portion 131 on the reference plane a. This is beneficial to improving the structural regularity of the gate 101, ensuring that the groove depths of different regions in the first annular groove 141 are consistent, facilitating the accommodation of the gate dielectric layer 102, the semiconductor layer 103, the first conductive structure 104, and the second conductive structure 105, thereby reducing the complexity of preparing the memory cell structure 100.

[0059] In some embodiments, reference Figure 1 The second conductive structure 105 has a contact surface 105a away from the semiconductor layer 103, and the lower electrode layer 116 is in contact with the contact surface 105a. It can be understood that the second conductive structure 105 not only serves as a source or drain of the transistor structure, but also serves as an electrical connection layer between the transistor structure and the capacitor structure 106 to achieve electrical connection between the transistor structure and the capacitor structure 106, so as to form a 1T1C type memory cell structure 100.

[0060] It should be noted that the 1T1C type memory cell structure 100 is a memory cell structure formed by electrically connecting a source or a drain of a transistor structure and a capacitor structure.

[0061] In some embodiments, reference Figure 1 , along the second direction Y, the second conductive structure 105 has a contact surface 105a away from the semiconductor layer 103, the lower electrode layer 116 is in contact with the contact surface 105a, and the groove depth D of the third annular groove 113 is less than or equal to the length L of the second conductive structure 105. In this way, the distance between the semiconductor layer 103 and the lower electrode layer 116 in the second direction Y is the difference between the depth D and the length L, so as to ensure that there is a sufficient distance between the semiconductor layer 103 and the lower electrode layer 116.

[0062] Combined with reference Figure 1 and Figure 4 In Figure 4a, the third annular groove 113 has a third inner wall 113a and a third outer wall 113b that are relatively spaced apart. Different areas of the third inner wall 113a are in contact and connected with the first conductive structure 104 and the second conductive structure 105, respectively. The gate dielectric layer 102 and the gate electrode 101 conformally cover the third outer wall 113b of the third annular groove 113 in sequence.

[0063] In this way, when the depth D of the third annular groove 113 is less than or equal to the length L of the second conductive structure 105, not only is there a sufficient spacing between the semiconductor layer 103 and the lower electrode layer 116, but also the spacing between the gate dielectric layer 102 and the gate electrode 101 and the lower electrode layer 116 in the second direction Y is also the difference between the depth D and the length L, which is also conducive to ensuring that both the gate dielectric layer 102 and the gate electrode 101 have a sufficient spacing from the lower electrode layer 116. It can be understood that, in the transistor structure, except for the second conductive structure 105 electrically connected to the capacitor structure 106, all other structures have a sufficient spacing from the capacitor structure 106, which is conducive to reducing the parasitic effects between the transistor structure and the capacitor structure 106.

[0064] In some embodiments, reference Figures 2 to 4, along the cross section perpendicular to the first direction X, the cross-sectional shapes of the first annular groove 141, the second annular groove 112 and the third annular groove 113 are all square rings. In other embodiments, the cross-sectional shapes of the first annular groove, the second annular groove and the third annular groove may be circular rings, elliptical rings or N-sided rings, where N is a positive integer greater than or equal to 5.

[0065] It should be noted that Figures 2 to 4 In the example, the cross-sectional shapes of the first annular groove 141, the second annular groove 112 and the third annular groove 113 are all square rings on the cross-sectional plane perpendicular to the first direction X. In practical applications, it is only necessary that the cross-sectional shapes of the first annular groove 141, the second annular groove 112 and the third annular groove 113 on the cross-sectional plane perpendicular to the first direction X are the same ring. Moreover, due to different preparation processes, the corners of other rings except the circular ring and the elliptical ring are rounded, for example, the ring can be a rounded rectangle.

[0066] It can be understood that the first annular groove 141, the second annular groove 112 and the third annular groove 113 are related to each other and have similar shapes. Therefore, the cross-sectional shapes of the first annular groove 141, the second annular groove 112 and the third annular groove 113 on the cross-sectional plane perpendicular to the first direction X are similar, except that the ring widths of the annular cross-sections of the first annular groove 141, the second annular groove 112 and the third annular groove 113 are different. Figures 2 to 4 , the first ring width W1 of the annular section of the first annular groove 141, the second ring width W2 of the annular section of the second annular groove 112, and the third ring width W3 of the annular section of the third annular groove 113 decrease in sequence. Moreover, the outer contours of the first annular groove 141, the second annular groove 112, and the third annular groove 113 in the cross section perpendicular to the first direction X coincide.

[0067] In some embodiments, reference Figure 2 The orthographic projection of the main body portion 111 on the reference plane a is a square, but the orthographic projections of the first extension portion 121 and the second extension portion 131 on the reference plane a are both square rings.

[0068] In some embodiments, reference Figure 5 The lower electrode layer 116 may include a support portion 146, and a first inner extension portion 156 and a second inner extension portion 166 respectively contacting and connected with both ends of the support portion 146 in the first direction X. The support portion 146, the first inner extension portion 156 and the second inner extension portion 166 are all annular structures and the three of them form a hollow area 176. The first inner extension portion 156 and the second inner extension portion 166 extend in a plane perpendicular to the first direction X toward a direction close to the center of the hollow area 176.

[0069] Understandably, reference Figure 5 In Figure 5b, the support portion 146 can be regarded as a hollow columnar structure, and the hollow columnar structure has a first end face 146a and a second end face 146b relative to each other in the first direction X, the first inner extension portion 156 can be regarded as an annular cover plate, which covers the first end face 146a and covers a part of the hollow area of ​​the hollow columnar structure, and the second inner extension portion 166 can be regarded as another annular cover plate, which covers the second end face 146b and covers a part of the hollow area of ​​the hollow columnar structure.

[0070] In some embodiments, reference Figure 5 The hollow area 176 may include: a first hollow area 176a surrounded by the support portion 146, that is, a hollow area of ​​the hollow columnar structure, a second hollow area 176b surrounded by the first inner extension portion 156, and a third hollow area 176c surrounded by the second inner extension portion 166.

[0071] It should be noted that, in order to clearly illustrate the support portion 146, the first inner extension portion 156 and the second inner extension portion 166, Figure 5 In FIG. 5b, the lower electrode layer 116 is divided into the above three parts by dotted lines, and the hollow area 176 is divided into a first hollow area 176a, a second hollow area 176b and a third hollow area 176c by dotted lines, and Figure 5 5b is a schematic diagram of an enlarged cross-sectional structure of the lower electrode layer 116.

[0072] In some embodiments, in conjunction with reference Figure 1 and Figure 5 The first inner extension portion 156 has a first top surface 156a away from the first end surface 146a, the second inner extension portion 166 has a second top surface 166a away from the second end surface 146b, and the capacitor dielectric layer 126 conformally covers the inner wall of the hollow area 176, the first top surface 156a and the second top surface 166a; the upper electrode layer 136 covers the surface of the capacitor dielectric layer 126 away from the lower electrode layer 116 and fills the hollow area.

[0073] It can be understood that the first inner extension portion 156 and the second inner extension portion 166 are conducive to further increasing the surface area of ​​the capacitor lower electrode layer 116 without increasing the outer size of the lower electrode layer 116, thereby increasing the facing area between the upper electrode layer 136 and the lower electrode layer 116 to increase the capacitance of the capacitor structure 106. Moreover, it is conducive to ensuring a larger facing area between the upper electrode layer 136 and the lower electrode layer 116 in the capacitor structure 106 when the overall size of the capacitor structure 106 is reduced, so as to ensure that the overall size of the capacitor structure 106 is reduced without reducing the capacitance of the capacitor structure 106.

[0074] refer to Figure 1 or Figure 5 , the orthographic projection of one of the first inner extension portion 156 and the second inner extension portion 166 on the reference plane a is located in the orthographic projection of the other on the reference plane a.

[0075] In some embodiments, the orthographic projection of the first inner extension 156 on the reference plane a may overlap with the orthographic projection of the second inner extension 166 on the reference plane a. This is beneficial to improving the structural regularity of the lower electrode layer 116, ensuring that the orthographic projection areas of the second hollow region 176b and the third hollow region 176c on the reference plane are consistent, facilitating the accommodation of the capacitor dielectric layer 126 and the upper electrode layer 136, thereby reducing the complexity of preparing the memory cell structure 100.

[0076] In some embodiments, reference Figure 5 , along the cross section perpendicular to the first direction X, the cross-sectional shapes of the support portion 146, the first inner extension portion 156, and the second inner extension portion 166 can all be square rings. In other embodiments, the cross-sectional shapes of the support portion, the first inner extension portion, and the second inner extension portion can also be circular rings, elliptical rings, or N-sided rings, where N is a positive integer greater than or equal to 5.

[0077] It should be noted that Figure 5 In the example, the cross-sectional shapes of the support portion 146, the first inner extension portion 156 and the second inner extension portion 166 are all square rings in the cross-sectional plane perpendicular to the first direction X. In practical applications, it is only necessary for the cross-sectional shapes of the support portion 146, the first inner extension portion 156 and the second inner extension portion 166 to be the same ring in the cross-sectional plane perpendicular to the first direction X. Moreover, due to different manufacturing processes, the corners of other rings except the circular ring and the elliptical ring are rounded, for example, the ring can be a rounded rectangle.

[0078] It can be understood that the support portion 146, the first inner extension portion 156 and the second inner extension portion 166 are related to each other and have similar shapes. Therefore, the cross-sectional shapes of the support portion 146, the first inner extension portion 156 and the second inner extension portion 166 on the cross-sectional plane perpendicular to the first direction X are similar, except that the ring widths of the annular cross-sections of the support portion 146, the first inner extension portion 156 and the second inner extension portion 166 are different. Figure 5 , the fourth ring width W4 of the annular cross section of the support portion 146 is smaller than the fifth ring width W5 of the annular cross section of the first inner extension portion 156, and the fourth ring width W4 of the annular cross section of the support portion 146 is smaller than the sixth ring width W6 of the annular cross section of the second inner extension portion 166. Moreover, the inner contours of the support portion 146, the first inner extension portion 156, and the second inner extension portion 166 in the cross section perpendicular to the first direction X overlap.

[0079] It should be noted that the size relationship between the fifth ring width W5 and the sixth ring width W6 can be adjusted according to actual needs.

[0080] In some embodiments, in conjunction with reference Figure 5 and Figure 6 The memory cell structure 100 may further include: a third conductive structure 107 located on a side of the support portion 146 away from the main body portion 111 in the second direction Y.

[0081] In this way, while the second conductive structure 105 is in contact and connected with the support portion 146 , the third conductive structure 107 is also in contact and connected with the support portion 146 , which is beneficial for improving the structural stability of the lower electrode layer 116 through the supporting effect of the added third conductive structure 107 on the lower electrode layer 116 , thereby helping to improve the structural stability of the capacitor structure 106 .

[0082] In some embodiments, in conjunction with reference Figure 7 and Figure 5 , the second conductive structure 105 and the third conductive structure 107 can be in contact and connected, and the second conductive structure 105 and the third conductive structure 107 jointly surround the side wall of the support portion 146 away from the hollow area 176 and extending along the first direction X. It can be understood that, Figure 7 The outer contour of the capacitor structure 106 shown in FIG. 1 is the lower electrode layer 116 in the capacitor structure 106 (refer to Figure 5 )’s outer contour.

[0083] It should be noted that Figure 7 It is a top view of the second conductive structure 105 , the third conductive structure 107 and the capacitor structure 106 .

[0084] Understandably, reference Figure 5 5a or Figure 7 The support portion 146 has a first sub-outer wall 146c and a second sub-outer wall 146d arranged relatively spaced apart in the second direction Y, and a third sub-outer wall 146e and a fourth sub-outer wall 146f arranged relatively spaced apart in the third direction Z, wherein Figure 5 In the clockwise direction of 5a, or along Figure 7 In the clockwise direction, the first sub-outer wall 146c, the third sub-outer wall 146e, the second sub-outer wall 146d and the fourth sub-outer wall 146f are sequentially contacted and connected, that is, the first sub-outer wall 146c, the third sub-outer wall 146e, the second sub-outer wall 146d and the fourth sub-outer wall 146f together constitute the entire outer wall of the support portion 146. The second conductive structure 105 at least covers the first sub-outer wall 146c, and the third conductive structure 107 at least covers the second sub-outer wall 146d.

[0085] In this way, the contact connection between the second conductive structure 105 and the third conductive structure 107 means that: the second conductive structure 105, in addition to covering the first sub-outer wall 146c, also covers at least a portion of the area of ​​one of the third sub-outer wall 146e and the fourth sub-outer wall 146f; the third conductive structure 107, in addition to covering the second sub-outer wall 146d, also covers at least a portion of the area of ​​the other of the third sub-outer wall 146e and the fourth sub-outer wall 146f, that is, the second conductive structure 105 and the third conductive structure 107 jointly surround the entire outer wall of the support portion 146.

[0086] In this way, on the one hand, it is beneficial to achieve all-round support for the support part 146 through the second conductive structure 105 and the third conductive structure 107, so as to further improve the structural stability of the lower electrode layer 116 and the capacitor structure 106; on the other hand, the second conductive structure 105 and the third conductive structure 107 can both serve as an electrical connection layer between the semiconductor layer 103 in the transistor structure and the lower electrode layer 116 in the capacitor structure 106, and the electrical connection layer surrounds the entire outer wall of the support part 146, which is beneficial to increase the contact area between the electrical connection layer and the lower electrode layer 116, so as to reduce the contact resistance between the electrical connection layer and the lower electrode layer 116, thereby helping to improve the efficiency of electrical signal transmission between the transistor structure and the capacitor structure, so as to further improve the electrical performance of the storage unit structure 100.

[0087] It should be noted that Figure 7 The figure is only an example of the second conductive structure 105 and the third conductive structure 107. In practical applications, there is no restriction on the area size of the third sub-outer wall 146e and / or the fourth sub-outer wall 146f covered by the second conductive structure 105, and there is no restriction on the area size of the third sub-outer wall 146e and / or the fourth sub-outer wall 146f of the third conductive structure 107. It is only necessary to meet the contact connection between the second conductive structure 105 and the third conductive structure 107. Moreover, the second conductive structure 105 and the third conductive structure 107 are in contact connection, and the second conductive structure 105 and the third conductive structure 107 can be an integrally formed structure.

[0088] In other embodiments, reference Figure 8 , the second conductive structure 105 may only cover the first sub-outer wall 146c, and the third conductive structure 107 may only cover the second sub-outer wall 146d, that is, the second conductive structure 105 and the third conductive structure 107 are relatively spaced apart along the second direction Y. It can be understood that, Figure 8 The outer contour of the capacitor structure 106 shown in FIG. 1 is the lower electrode layer 116 in the capacitor structure 106 (refer to Figure 5 )’s outer contour.

[0089] It should be noted that Figure 7 and Figure 8The division of the first sub-outer wall 146c, the second sub-outer wall 146d, the third sub-outer wall 146e and the fourth sub-outer wall 146f is only an example. The division of the third sub-outer wall 146e and the fourth sub-outer wall 146f is to space the first sub-outer wall 146c and the second sub-outer wall 146d from each other, so as to facilitate the description of the layout of the second conductive structure 105 and the third conductive structure 107.

[0090] In some embodiments, reference Figure 7 , along the third direction Z, the maximum width W7 of the gate 101 may be greater than the maximum width W8 of the lower electrode layer 116. It can be understood that when the second conductive structure 105 and the third conductive structure 107 are in contact with each other, the second conductive structure 105 and the third conductive structure 107 jointly surround the lower electrode layer 116 in the capacitor structure 106 (refer to Figure 5 ), and the gate 101 is in contact with the contact surface 105a of the second conductive structure 105, so that the maximum width W7 of the gate 101 can be greater than the maximum width W8 of the lower electrode layer 116.

[0091] It should be noted that Figure 7 The main body 111 of the gate 101 is shown in the dashed box (refer to Figure 2 ).

[0092] In other embodiments, reference Figure 8 , along the third direction Z, the maximum width W7 of the gate 101 can be equal to the maximum width W8 of the lower electrode layer 116. It can be understood that the second conductive structure 105 and the third conductive structure 107 are relatively spaced apart along the second direction Y, and the gate 101 is in contact with the contact surface 105a of the second conductive structure 105, so that the maximum width W7 of the gate 101 can be equal to the maximum width W8 of the lower electrode layer 116.

[0093] In some embodiments, reference Fig. 9 The first conductive structure 104 may include a first diffusion barrier layer 114 and a first conductive layer 124, wherein the first diffusion barrier layer 114 is located between the semiconductor layer 103 and the first conductive layer 124. The first diffusion barrier layer 114 is used to block mutual diffusion of elements in the semiconductor layer 103 and the first conductive layer 124, thereby preventing the electrical properties of the semiconductor layer 103 and the first conductive layer 124 from being interfered with by each other.

[0094] In some embodiments, reference Fig. 9The second conductive structure 105 may include a second diffusion barrier layer 115 and a second conductive layer 125. The second diffusion barrier layer 115 is located between the semiconductor layer 103 and the second conductive layer 125. Moreover, the second diffusion barrier layer 115 is also located between the lower electrode layer 116 and the second conductive layer 125. The second diffusion barrier layer 115 is used to block the mutual diffusion of elements in the semiconductor layer 103 and the second conductive layer 125 to prevent the electrical properties of the semiconductor layer 103 and the second conductive layer 125 from being interfered with by each other, and to block the mutual diffusion of elements in the lower electrode layer 116 and the second conductive layer 125 to prevent the electrical properties of the lower electrode layer 116 and the second conductive layer 125 from being interfered with by each other.

[0095] In some embodiments, reference Fig. 9 The third conductive structure 107 may include a third diffusion barrier layer 117 and a third conductive layer 127, wherein the third diffusion barrier layer 117 is located between the lower electrode layer 116 and the third conductive layer 127. The third diffusion barrier layer 117 is used to block mutual diffusion of elements in the lower electrode layer 116 and the third conductive layer 127, so as to prevent the electrical properties of the lower electrode layer 116 and the third conductive layer 127 from being interfered with by each other.

[0096] It should be noted that Fig. 9 In the example, the first conductive structure 104, the second conductive structure 105 and the third conductive structure 107 all include a diffusion barrier layer and a conductive layer. In practical applications, any one or any two of the first conductive structure 104, the second conductive structure 105 and the third conductive structure 107 can be designed to include a diffusion barrier layer and a conductive layer according to actual needs. The diffusion barrier layer here generally refers to at least one of the first diffusion barrier layer 114, the second diffusion barrier layer 115 and the third diffusion barrier layer 117, and the conductive layer here generally refers to at least one of the first conductive layer 124, the second conductive layer 125 and the third conductive layer 127. In one example, the material of the diffusion barrier layer is titanium nitride, and the material of the conductive layer is tungsten.

[0097] In some embodiments, the upper electrode layer 136 may include a fifth diffusion barrier layer (not shown) and a fifth conductive layer (not shown), and the fifth diffusion barrier layer is located between the capacitor dielectric layer 126 and the fifth conductive layer. The fifth diffusion barrier layer is used to prevent mutual diffusion of elements in the fifth conductive layer and the capacitor dielectric layer 126, so as to prevent the electrical properties of the fifth conductive layer from being interfered by the capacitor dielectric layer 126. The material of the fifth diffusion barrier layer may be titanium nitride, and the material of the fifth conductive layer may be polysilicon.

[0098] In summary, on the one hand, the gate 101 is designed to enclose a first annular groove 141 to increase the surface area of ​​the gate 101, which is conducive to increasing the facing area between the gate 101 and the semiconductor layer 103, so as to increase the facing area between the gate 101 and the semiconductor layer 103, thereby facilitating the control capability of the gate 101 over the semiconductor layer 103, thereby facilitating the reduction of leakage current in the transistor structure, such as the leakage current at the first conductive structure 104 and the second conductive structure 105. On the other hand, the semiconductor layer 103 itself encloses a third annular groove 113 to increase the surface area of ​​the semiconductor layer 103, thereby facilitating the increase of the contact area and contact resistance between the first conductive structure 104 and the semiconductor layer 103, and the increase of the contact area and contact resistance between the second conductive structure 105 and the semiconductor layer 103. In this way, the two aspects cooperate with each other. When the size of the transistor structure is reduced, the electrical performance of the storage cell structure 100 can be improved by increasing the facing area between the gate 101 and the semiconductor layer 103, and increasing the contact area between the first conductive structure 104 and the second conductive structure 105 and the semiconductor layer 103.

[0099] Another embodiment of the present disclosure further provides a memory cell array structure, which is composed of a plurality of memory cell structures provided by the above-mentioned embodiments. The memory cell array structure provided by another embodiment of the present disclosure will be described in detail below in conjunction with the accompanying drawings. Fig.10 A schematic diagram of a three-dimensional structure of a storage cell array structure provided by another embodiment of the present disclosure; Figures 11 to 13 Three partial cross-sectional structural schematic diagrams of a memory cell array structure provided in another embodiment of the present disclosure. It should be noted that the parts identical or corresponding to the above embodiments are not described in detail here.

[0100] refer to Fig.10 The memory cell array structure may include: a plurality of memory cell structures 100 provided in the foregoing embodiments, the plurality of memory cell structures 100 are arranged along a first direction X and / or a third direction Z, and the first direction X, the second direction Y and the third direction Z intersect each other.

[0101] It should be noted that, for the sake of clarity of the diagram, Fig.10 Only the overall structure of the capacitor structure 106 is drawn, that is, only the outer contour of the capacitor structure 106 is illustrated, and the lower electrode layer, the capacitor dielectric layer and the upper electrode layer in the capacitor structure 106 are not drawn.

[0102] The memory cell structure 100 in the memory cell array structure is described in detail below.

[0103] In some embodiments, reference Figure 11 to Figure 12, a plurality of memory cell structures 100 are arranged in contact with each other along the first direction X, the gate electrodes 101 in the memory cell structures 100 adjacent to each other along the first direction X are in contact with each other, and the upper electrode layers 136 in the capacitor structures 106 adjacent to each other along the first direction X are in contact with each other. It can be understood that the plurality of upper electrode layers 136 in the plurality of capacitor structures 106 arranged in the first direction X can be an integrated structure, that is, the plurality of capacitor structures 106 arranged in the first direction X share the same overall upper electrode layer.

[0104] In some embodiments, continue to refer to Figure 11 to Figure 12 , the multiple gates 101 arranged along the first direction X can be an integrally formed structure. It can be understood that two adjacent main bodies 111 along the first direction X can share an extension, and one of the two adjacent main bodies 111 along the first direction X regards the shared extension as the first extension 121, and the other regards the shared extension as the second extension 131. In this way, the total gate composed of the multiple gates 101 arranged along the first direction X can be regarded as a columnar structure, and multiple extensions with a ring-shaped cross-section located on the outer wall of the columnar structure and arranged at intervals along the first direction X.

[0105] In some embodiments, reference Fig.11 , the plurality of gate dielectric layers 102 arranged along the first direction X may also be an integrated structure, that is, the total gate dielectric layer formed by the plurality of gate dielectric layers 102 arranged along the first direction X may cover the outer wall of the total gate. Fig.12 The multiple gate dielectric layers 102 arranged along the first direction X may also be spaced apart from each other like the multiple semiconductor layers 103 arranged along the first direction X, that is, each gate dielectric layer 102 is only located between the corresponding gate 101 and semiconductor layer 103 .

[0106] In other embodiments, reference Fig.10 In the memory cell array structure, a plurality of memory cell structures 100 are arranged at intervals along a third direction Z. The memory cell array structure further includes a bit line structure 108 extending along the third direction Z. One bit line structure 108 is in contact with and connected to a plurality of first conductive structures 104 arranged at intervals along the third direction Z. It can be understood that the bit line structure 108 and the first conductive structure 104 are located in the same layer.

[0107] In some embodiments, reference Fig.13 The bit line structure 108 may include a fourth diffusion barrier layer 118 and a fourth conductive layer 128 , wherein the fourth diffusion barrier layer 118 is at least located on two opposite sides of the fourth conductive layer 128 along the first direction X.

[0108] In some embodiments, continue to refer to Fig.13The first conductive structure 104 may include a first diffusion barrier layer 114 and a first conductive layer 124 , a fourth diffusion barrier layer 118 is in contact with and connected to the first diffusion barrier layer 114 , and a fourth conductive layer 128 is in contact with and connected to the first conductive layer 124 .

[0109] In some further embodiments, continue to refer to Fig.10 , in the memory cell array structure, a plurality of memory cell structures 100 are arranged along a first direction X and a third direction Z. It should be noted that the parts that are the same as or corresponding to the above embodiments are not described in detail here. The plurality of transistor structures arranged along the third direction Z are spaced apart from each other and electrically isolated from each other; the plurality of capacitor structures 106 arranged along the third direction Z are spaced apart from each other and electrically isolated from each other; the plurality of bit line structures 108 arranged along the first direction X are spaced apart from each other and electrically isolated from each other. It can be understood that the plurality of memory cell structures 100 arranged along the third direction Z are spaced apart from each other, but the first conductive structures 104 in the plurality of memory cell structures 100 arranged along the third direction Z are all in contact with and connected to the same bit line structure 108.

[0110] It can be understood that the gate 101 , the gate dielectric layer 102 , the semiconductor layer 103 , the first conductive structure 104 and the second conductive structure 105 constitute a transistor structure.

[0111] It should be noted that Fig.10 In the example, a plurality of storage cell structures 100 are arranged in contact along a first direction X, and a plurality of storage cell structures 100 are arranged at intervals along a third direction Z. In practical applications, with reference to Fig.10 The memory cell structures 100 in the memory cell array structure may be arranged in contact only along the first direction X, or the memory cell structures 100 in the memory cell array structure may be arranged in intervals only along the third direction Z.

[0112] also, Fig.10 In the example, the number of the memory cell structures 100 arranged in contact with each other along the first direction X is 2. Fig.11 and Fig.12 In the example, the number of storage cell structures 100 arranged in contact along the first direction X is 3. It can be understood that in another embodiment of the present disclosure, there is no limitation on the number of storage cell structures 100 arranged in contact along the first direction X in the storage cell array structure. For example, the number can be 5, 6, 8 or 10. Fig.10 In the example, the number of storage cell structures 100 arranged along the third direction Z is 2. It can be understood that in another embodiment of the present disclosure, the number of storage cell structures 100 arranged along the third direction Z in the storage cell array structure is not limited. For example, the number can be 5, 6, 8 or 10.

[0113] In some further embodiments, Fig.13 In the memory cell array structure, two memory cell structures 100 (reference Fig.12 ) are axially symmetric along the second direction Y, and the two memory cell structures 100 share a bit line structure 108.

[0114] In some further embodiments, in the memory cell array structure, the plurality of memory cell structures 100 are arranged not only along the first direction X and the third direction Z, but also along the second direction Y, and two adjacent memory cell structures 100 along the second direction Y are axially symmetrical. It is understandable that Fig.13 The storage combination of the two storage unit structures 100 axially symmetrical along the second direction Y shown can also be arranged along the first direction X and the third direction Z.

[0115] In some embodiments, reference Figures 10 to 12 The memory cell array structure may further include: a substrate 110, a plurality of memory cell structures 100 arranged along the first direction X and / or the second direction Y and / or the third direction Z are all located on the substrate 110, and the substrate 110 is used to support the plurality of memory cell structures 100.

[0116] In summary, in the memory cell structure 100, the shapes and relative positional relationship of the gate 101, the gate dielectric layer 102 and the semiconductor layer 103 are conducive to increasing the facing area between the gate 101 and the semiconductor layer 103, thereby increasing the facing area between the gate 101 and the semiconductor layer 103, so as to increase the control capability of the gate 101 over the semiconductor layer 103, thereby facilitating the reduction of the leakage current in the memory cell structure 100; and, the shapes and relative positional relationship of the semiconductor layer 103, the first conductive structure 104 and the second conductive structure 105 are conducive to increasing the contact area and contact resistance between the first conductive structure 104 and the semiconductor layer 103, and increasing the contact area and contact resistance between the second conductive structure 105 and the semiconductor layer 103. In this way, when the size of the memory cell structure 100 is reduced, the electrical performance of the memory cell structure 100 can also be improved through the above structure. Therefore, it is conducive to increasing the number of memory cell structures 100 in the memory cell array structure within a unit volume, that is, it is conducive to improving the integration density of the memory cell array structure. In addition, the improvement of the electrical performance of the memory cell structure 100 is also beneficial to improving the electrical performance of the memory cell array structure.

[0117] Another embodiment of the present disclosure further provides a method for manufacturing a memory cell array structure, which is used to form the memory cell array structure provided by the above embodiment. The method for manufacturing a memory cell array structure provided by another embodiment of the present disclosure will be described in detail below in conjunction with the accompanying drawings. Figures 14 to 35The cross-sectional structure diagram corresponding to each step in the manufacturing method of the memory cell array structure provided in another embodiment of the present disclosure is as follows. It should be noted that, in order to facilitate the description and clearly illustrate the steps of the semiconductor structure manufacturing method, the cross-sectional structure diagram corresponding to each step in the manufacturing method of the memory cell array structure provided in another embodiment of the present disclosure is as follows: Figures 14 to 35 All of them are partial structural schematic diagrams of semiconductor structures. Parts that are the same as or corresponding to the above embodiments will not be described in detail here.

[0118] refer to Figures 14 to 35 The manufacturing method of the memory cell array structure includes the following steps: providing a substrate 110; forming a plurality of memory cell structures 100 arranged along a first direction X and / or a third direction Z on the substrate 110.

[0119] The memory cell structure 100 includes: a semiconductor layer 103, a gate dielectric layer 102, a gate 101, a first conductive structure 104, a second conductive structure 105 and a capacitor structure 106; wherein the gate 101 includes a main body 111 and a first extension 121 and a second extension 131 respectively contacting and connecting the main body 111 at two ends in a first direction X, the first extension 121 and the second extension 131 extend in a plane perpendicular to the first direction X in a direction away from the main body 111, and the gate 101 itself forms a first annular groove 141; the gate dielectric layer 102 conformally covers the first inner wall 141a of the first annular groove 141, and the gate dielectric layer 102 itself forms a second annular groove 141a. shaped groove 112; the semiconductor layer 103 conformally covers the second inner wall 112a of the second annular groove 112, and the semiconductor layer 103 itself surrounds a third annular groove 113, the third annular groove 113 has a first groove 123 and a second groove 133 arranged relatively spaced along the second direction Y, and the first direction X and the second direction Y intersect; the first conductive structure 104 fills the first groove 123, and the second conductive structure 105 fills the second groove 133; the capacitor structure 106 includes a lower electrode layer 116, an upper electrode layer 136 and a capacitor dielectric layer 126 located between the lower electrode layer 116 and the upper electrode layer 136, and the lower electrode layer 116 is in contact with the second conductive structure 105.

[0120] It should be noted that the order of forming the semiconductor layer 103, the gate dielectric layer 102 and the gate 101, the step of forming the first conductive structure 104 and the second conductive structure 105, and the step of forming the capacitor structure 106 can be adjusted, which is described in detail below.

[0121] In some embodiments, reference Figures 14 to 18 Before forming the first conductive structure 104 and the second conductive structure 105, forming the semiconductor layer 103, the gate dielectric layer 102 and the gate 101 may include the following steps:

[0122] refer to Fig.14 A stacked structure 120 is formed on a substrate 110 , and the stacked structure 120 includes first sacrificial layers 130 and second sacrificial layers 140 that are alternately stacked along a first direction X.

[0123] It is understood that the material of the first sacrificial layer 130 may be different from the material of the second sacrificial layer 140. In some embodiments, the material of the first sacrificial layer 130 may be silicon oxide, and the material of the second sacrificial layer 140 may be silicon nitride.

[0124] It should be noted that Fig.14 In the example, four first sacrificial layers 130 and three second sacrificial layers 140 are stacked along the first direction X. In practical applications, the number of first sacrificial layers 130 and the number of second sacrificial layers 140 stacked along the first direction X can be flexibly adjusted according to needs.

[0125] Combined with reference Fig.14 and Fig.15 , etching the stacked structure 120 to form a first through hole 109 penetrating the stacked structure 120 in the first direction X, the first through hole 109 includes a first sub-through hole 119 formed in each first sacrificial layer 130 and a second sub-through hole 129 formed in each second sacrificial layer 140, the plane perpendicular to the first direction X is the reference plane a, and the area of ​​the orthographic projection of the first sub-through hole 119 on the reference plane a is greater than the area of ​​the orthographic projection of the second sub-through hole 129 on the reference plane a.

[0126] It should be noted that the reference Fig.15 , the first sub-through holes 119 correspond to the first sacrificial layers 130 one by one, and the second sub-through holes 129 correspond to the second sacrificial layers 140 one by one. That is, the number of the first sub-through holes 119 included in one first through hole 109 is consistent with the number of the first sacrificial layers 130 stacked in the stacking structure 120, and the number of the second sub-through holes 129 is consistent with the number of the second sacrificial layers 140 stacked in the stacking structure 120.

[0127] It can be understood that, along the first direction X, among the multiple first sub-through holes 119 and the multiple second sub-through holes 129 used to constitute the same first through hole 109, each first sub-through hole 119 and each second sub-through hole 129 are arranged alternately, so that the size of the orthographic projection area of ​​the first through hole 109 on the reference plane a will change with the change of the film layer constituting the first through hole 109, so that the fourth inner wall 109a of the first through hole 109 presents an uneven morphology. In this way, when the semiconductor layer 103, the gate dielectric layer 102 and the gate 101 are subsequently formed by the first through hole 109 based on the fourth inner wall 109a with an uneven morphology, the fourth inner wall 109a with an uneven morphology is conducive to making the semiconductor layer 103 subsequently formed based thereon also present an uneven morphology similar to the fourth inner wall 109a, and making the gate dielectric layer 102 subsequently formed also present an uneven morphology similar to the fourth inner wall 109a, so that after the gate 101 is subsequently formed, it is conducive to increasing the facing area between the gate 101 and the semiconductor layer 103, so as to increase the control ability of the gate 101 over the semiconductor layer 103, thereby helping to reduce the leakage current in the transistor structure formed subsequently.

[0128] In some embodiments, in conjunction with reference Fig.10 and Fig.15 In order to finally form a memory cell array structure in which a plurality of memory cell structures 100 are arranged along both the first direction X and the third direction Z, the step of forming the first through hole 109 may further include: etching the stacked structure 120 to form a plurality of first through holes 109 arranged at intervals along the third direction Z. In some embodiments, in order to form a plurality of first through holes 109 arranged at intervals along the third direction Z in the stacked structure 120, the mask layer for patterning the stacked structure 120 has a plurality of openings arranged at intervals along the third direction Z.

[0129] In some embodiments, in conjunction with reference Fig.13 and Fig.15 In order to finally form a memory cell array structure of a plurality of memory cell structures 100 that are axisymmetric along the second direction Y, the step of forming the first through hole 109 may further include: etching the stacked structure 120 to form two first through holes 109 that are spaced apart along the second direction Y. In some embodiments, in order to form two first through holes 109 spaced apart along the second direction Y in the stacked structure 120, the mask layer for patterning the stacked structure 120 has two openings spaced apart along the second direction Y.

[0130] It should be noted that the steps of the above two embodiments can be performed simultaneously to finally form a memory cell array structure in which a plurality of memory cell structures 100 are arranged along the first direction X and the third direction Z and to form a memory cell array structure in which a plurality of memory cell structures 100 are axially symmetrical along the second direction Y. In addition, the formation of the first through hole 109 will be described in detail later.

[0131] refer to Figures 15 to 18 A semiconductor layer 103 is formed on the surface of each second sacrificial layer 140 exposed by the first through hole 109, and there is a spacing between adjacent semiconductor layers 103 along the first direction X; a gate dielectric layer 102 is conformally covered on the surface of the remaining first through holes 109; and a gate 101 that fills the remaining first through holes 109 is formed.

[0132] In some embodiments, forming the semiconductor layer 103, the gate dielectric layer 102 and the gate 101 may include the following steps:

[0133] Combined with reference Fig.15 and Fig.16 , forming a semiconductor film 163 that conformally covers the fourth inner wall 109a of the first through hole 109, so that the semiconductor film 163 also surrounds a through hole similar to the first through hole 109, that is, the inner wall of the semiconductor film 163 also presents an uneven morphology similar to the fourth inner wall 109a; forming a gate dielectric film 122 that conformally covers the inner wall of the semiconductor film 163, so that the gate dielectric film 122 also surrounds a through hole similar to the first through hole 109, that is, the inner wall of the gate dielectric film 122 also presents an uneven morphology similar to the fourth inner wall 109a; forming an initial gate 151 that fills the through hole similar to the first through hole 109 surrounded by the gate dielectric film 122.

[0134] Combined with reference Figure 16 to Figure 17 , the first sacrificial layer 130 is removed to expose a portion of the surface of the semiconductor film 163. It can be understood that before the first sacrificial layer 130 is removed, the surface of the exposed semiconductor film 163 is located on the surface of the side wall of the first sub-through hole 119 extending along the first direction X. In other words, the surface of the exposed semiconductor film 163 is located on the side wall of the first sacrificial layer 130 that surrounds the first sub-through hole 119 and extends along the first direction X.

[0135] Combined with reference Figure 17 to Figure 18 , removing the exposed surface of the semiconductor film 163, so that the semiconductor film 163 is cut into a plurality of semiconductor layers 103 arranged at intervals along the first direction X, and referring to Fig.18 , the semiconductor layer 103 covers the first through hole 109 (refer to Fig.15), and the orthographic projection of the exposed second sacrificial layer 140 on the substrate 110 is a ring, so as to form a semiconductor layer 103 which surrounds a third annular groove 113.

[0136] It should be noted that the reference Fig.18 After removing the exposed surface of the semiconductor film 163, the further exposed surface of the gate dielectric film 122 may be removed. It is understood that before removing the second sacrificial layer 140, the exposed surface of the gate dielectric film 122 is located on the side of the exposed semiconductor film 163 away from the second sacrificial layer 140. In this way, the multiple gate dielectric layers 102 arranged along the first direction X may be spaced apart from each other like the multiple semiconductor layers 103 arranged along the first direction X. In practical applications, the gate dielectric film 122 (refer to Fig.17 ) can be taken as an example of a total gate dielectric layer composed of multiple gate dielectric layers 102 arranged along the first direction X.

[0137] In addition, the initial gate 151 may be a total gate composed of a plurality of gates 101 arranged along the first direction X.

[0138] In some embodiments, in conjunction with reference Fig.10 and Fig.18 In order to finally form a memory cell array structure in which a plurality of memory cell structures 100 are arranged along the first direction X and the third direction Z, after forming the initial gate 151 and before removing the first sacrificial layer 130, the step of forming the semiconductor layer 103 may further include: etching the stacked structure 120 to form a groove 179 between the adjacent initial gates 151 along the third direction Z, in other words, between the adjacent semiconductor films 163. It can be understood that, on the one hand, the groove 179 is used to expose the first sub-through hole 119 (refer to Fig.15 ) in the sidewall of the semiconductor film 163 extending along the first direction X, and the exposed sidewall is subsequently removed to form the semiconductor layer 103; on the other hand, the groove 179 is used to define the layout space occupied by the second sacrificial layer 140 that is required to make the bit line structure later, and the second sacrificial layer 140 therein is subsequently removed to form the bit line structure 108.

[0139] It is understandable that, combined with reference Fig.10 and Fig.15 , the first sub-through hole 119 is the space where the epitaxial portion of the gate 101 and the corresponding gate dielectric layer 102 and semiconductor layer 103 are located, and the first through hole 109 is the space where the entire gate 101 is located. Fig.11 The epitaxial portion in the gate 101 refers to the first epitaxial portion 121 or the second epitaxial portion 131 .

[0140] refer to Fig.15,as well as Figures 19 to 27 In some other embodiments, after forming the first through hole 109 and before forming the semiconductor layer 103, that is, after forming the first through hole 109 and before forming the semiconductor layer 103, the gate dielectric layer 102 and the gate 101 in the first through hole 109, the manufacturing method may further include the following steps:

[0141] Combined with reference Fig.15 and Fig.19 , etching the stacked structure 120 to form a second through hole 139 penetrating the stacked structure 120 in the first direction X, the second through hole 139 includes a third sub-through hole 149 formed in each first sacrificial layer 130 and a fourth sub-through hole 159 formed in each second sacrificial layer 140, the plane perpendicular to the first direction X is the reference plane a, the area of ​​the orthographic projection of the third sub-through hole 149 on the reference plane a is smaller than the area of ​​the orthographic projection of the fourth sub-through hole 159 on the reference plane a, and the first through hole 109 and the second through hole 139 are arranged at intervals along the second direction Y.

[0142] It should be noted that the reference Fig.19 , the third sub-through holes 149 correspond to the first sacrificial layers 130 one by one, and the fourth sub-through holes 159 correspond to the second sacrificial layers 140 one by one. That is, the number of the third sub-through holes 149 included in one second through hole 139 is consistent with the number of the first sacrificial layers 130 stacked in the stacked structure 120, and the number of the fourth sub-through holes 159 is consistent with the number of the second sacrificial layers 140 stacked in the stacked structure 120.

[0143] It can be understood that, along the first direction X, among the multiple third sub-through holes 149 and the multiple fourth sub-through holes 159 used to constitute the same second through hole 139, each third sub-through hole 149 and each fourth sub-through hole 159 are arranged alternately, so that the size of the orthographic projection area of ​​the second through hole 139 on the reference plane a will change with the change of the film layer constituting the second through hole 139, so that the fourth inner wall 109a of the second through hole 139 presents an uneven morphology. In this way, it can be regarded as the part of the first sacrificial layer 130 exposed in the second through hole 139, and the positive projection of the exposed first sacrificial layer 130 on the substrate 110 is a ring. The exposed first sacrificial layer 130 and the second sacrificial layer 140 adjacent to each other in the first direction X together form an annular groove opening inward. In other words, the annular groove opening inward can be regarded as the area where the fourth sub-through hole 159 extends beyond the third sub-through hole 149, which is conducive to the subsequent formation of a lower electrode layer 116 having a support portion 146 (refer to the figure), a first inner extension portion 156 and a second inner extension portion 166 based on the annular groove opening inward.

[0144] The steps of forming the first through hole 109 and / or the second through hole 139 are described in detail below.

[0145] In some embodiments, the step of forming the first through hole 109 may include: first forming a mask layer (not shown) having an opening on the stacked structure 120, wherein the orthographic projection of the mask layer on the substrate 110 coincides with the orthographic projection of the second sub-through hole 129 formed subsequently on the substrate 110; Fig.14 and Fig. 20 The stacked structure 120 is patterned with a mask layer having an opening to form a first main through hole 189 penetrating the stacked structure 120. It can be understood that in this step, the second sub-through hole 129 (refer to Fig.19 ) has been formed; combined with reference Fig. 20 and Fig.15 The first sacrificial layer 130 exposed by the first main through hole 189 is laterally etched, i.e., isotropically etched, such as wet etched, to widen the first main through hole 189 in each first sacrificial layer 130 into a first sub-through hole 119, thereby finally forming a first through hole 109.

[0146] In some other embodiments, the step of forming the second through hole 139 may include: first forming a mask layer (not shown) having an opening on the stacked structure 120, wherein the orthographic projection of the mask layer on the substrate 110 coincides with the orthographic projection of the second sub-through hole 129 formed subsequently on the substrate 110; Fig.14 and Fig. 20 The stacked structure 120 is patterned with a mask layer having an opening to form a second main through hole 199 penetrating the stacked structure 120. It can be understood that in this step, the third sub-through hole 149 (refer to Fig.19 ) has been formed; combined with reference Fig. 20 and Fig.19 The second sacrificial layer 140 exposed by the second main through hole 199 is laterally etched, i.e., isotropically etched, such as wet etched, to widen the second main through hole 199 in each second sacrificial layer 140 into a fourth sub-through hole 159, thereby finally forming a second through hole 139.

[0147] In some other embodiments, the first through hole 109 and the second through hole 139 can be formed simultaneously, and the steps of forming the first through hole 109 and the second through hole 139 can include: Fig.14 and Fig. 20 , the stacked structure 120 is patterned to form a first main through hole 189 and a second main through hole 199 that penetrate the stacked structure 120 in the first direction X, the first main through hole 189 and the second main through hole 199 are arranged at intervals along the second direction Y, the first main through hole 189 located in the second sacrificial layer 140 is used as the second sub-through hole 129, and the second main through hole 199 located in the first sacrificial layer 130 is used as the third sub-through hole 149; combined with reference Fig. 20and Fig.19 , the first sacrificial layer 130 exposed by the first main through hole 189 is laterally etched to form a first sub-through hole 119 in each first sacrificial layer 130, and the second sacrificial layer 140 exposed by the second main through hole 199 is laterally etched to form a fourth sub-through hole 159 in each second sacrificial layer 140. It should be noted that the same or corresponding parts as those in the above two embodiments are not repeated here.

[0148] In some embodiments, in conjunction with reference Fig.10 and Fig.19 To finally form a memory cell array structure in which a plurality of memory cell structures 100 are arranged along the first direction X and the third direction Z, the step of forming the first through hole 109 and the second through hole 139 may further include: etching the stack structure 120 (refer to Fig.14 ) to form a plurality of first through holes 109 and a plurality of second through holes 139 spaced apart along the third direction Z. In some embodiments, to form a plurality of first through holes 109 spaced apart along the third direction Z in the stacked structure 120, the mask layer for patterning the stacked structure 120 has a plurality of openings spaced apart along the third direction Z.

[0149] In some embodiments, in conjunction with reference Fig.13 and Fig.19 To finally form a memory cell array structure of a plurality of memory cell structures 100 that are axisymmetric along the second direction Y, the step of forming the first through hole 109 and the second through hole 139 may further include: etching the stacked structure 120 (refer to Fig.14 ), so as to form two first through holes 109 that are axially symmetrical along the second direction Y and two second through holes 139 that are axially symmetrical along the second direction Y. In some embodiments, to form two first through holes 109 and two second through holes 139 in the stacked structure 120, the mask layer for patterning the stacked structure 120 has four openings that are spaced apart along the second direction Y.

[0150] It should be noted that in order to ultimately form a memory cell array structure in which a plurality of memory cell structures 100 are arranged along the first direction X and the third direction Z and a memory cell array structure in which a plurality of memory cell structures 100 are axially symmetrical along the second direction Y, the steps of the above two embodiments can be performed simultaneously.

[0151] Combined with reference Fig.19 and Fig.21 , forming a first dielectric layer 132 that fills the first through hole 109 and the second through hole 139 respectively. It can be understood that the material of the first dielectric layer 132 is different not only from the material of the first sacrificial layer 130 , but also from the material of the second sacrificial layer 140 .

[0152] In some embodiments, in conjunction with reference Fig.10 and Fig.19 , the formed multiple storage unit structures 100 are arranged at intervals along the third direction Z; in the step of forming the first through holes 109 and the second through holes 139, the multiple first through holes 109 are arranged at intervals along the third direction Z, and the multiple second through holes 139 are arranged at intervals along the third direction Z.

[0153] Combined with reference Fig.21 and Fig.10 After forming the first dielectric layer 132 and before removing the first sacrificial layer 130, the manufacturing method may further include: etching the stacked structure 120 between the first dielectric layers 132 adjacent to each other along the third direction Z (refer to Fig.14 ) to form a plurality of grooves 179 spaced apart along the third direction Z, wherein the grooves 179 expose the first dielectric layer 132 on both sides thereof.

[0154] It is understandable that, combined with reference Fig.10 and Fig.19 The trench 179 exposes the first dielectric layer 132 on both sides thereof (refer to Fig.21 ) refers to: the groove 179 exposes the sidewall of the first dielectric layer 132 located in the first sacrificial layer 130 (i.e., filling the first sub-through hole 119) extending along the first direction X, and exposes the sidewall of the first dielectric layer 132 located in the second sacrificial layer 140 (i.e., filling the fourth sub-through hole 159) extending along the first direction X. In this way, the groove 179 exposes the sidewall of the first dielectric layer 132 filling the first sub-through hole 119, which is convenient for the subsequent formation of the semiconductor layer 103 spaced apart from each other along the first direction X, and is convenient for the subsequent formation of the first conductive structure 104 and the second conductive structure 105 relatively spaced apart along the second direction Y; the groove 179 exposes the sidewall of the first dielectric layer 132 filling the fourth sub-through hole 159, which is convenient for the subsequent formation of the capacitor structure 106; and the groove 179 is used to define the layout space occupied by the second sacrificial layer 140 that is needed to be used as the bit line structure in the future, and the second sacrificial layer 140 is removed in the future to form the bit line structure 108.

[0155] It is understandable that, combined with reference Fig.10 and Fig.19 , the second through hole 139 is the space where the capacitor structure 106 is located as a whole; combined with reference Fig.11 and Fig.19 , the partial space in the fourth sub-through hole 159 is the space where the entire lower electrode layer 116 is located.

[0156] Combined with reference Figure 21 to Figure 23, the second sacrificial layer 140 surrounding the first through hole 109 and the second through hole 139 is removed to form a plurality of transverse gaps 169 spaced along the first direction X, wherein the transverse gaps 169 are located between adjacent first sacrificial layers 130 along the first direction X.

[0157] In some embodiments, reference Fig. 22 and Fig.23 After forming the groove 179, in the step of removing the second sacrificial layer 140 surrounding the first through hole 109 and the second through hole 139, in addition to forming the lateral gap 169, a longitudinal gap 168 is also formed. It can be understood that, in conjunction with reference Fig.10 and Fig. 22 The transverse gap 169 extends along the second direction Y, and subsequently the first conductive structure 104 and the second conductive structure 105 are formed in the transverse gap 169 ; the longitudinal gap 168 extends along the third direction Z, and subsequently the bit line structure 108 is formed in the longitudinal gap 168 .

[0158] It can be understood that the subsequently formed bit line structure 108 will be in contact with and connected to the first conductive structure 104 , so the transverse gap 169 and the longitudinal gap 168 are connected.

[0159] Combined with reference Figure 22 to Figure 25 , a first conductive structure 104 and a second conductive structure 105 are formed in the transverse gap 169. It should be noted that the first conductive structure 104 and the second conductive structure 105 are arranged along the second direction Y with a relative spacing.

[0160] In some embodiments, reference Fig. 22 and Fig.23 , in order to finally form a plurality of memory cell structures 100 arranged along the first direction X and the third direction Z (refer to Fig.11 ) of the memory cell array structure, after forming the trench 179, the step of forming the transverse gap 169 also forms the longitudinal gap 168. It should be noted that, Fig.23 23a is Fig. 22 The schematic cross-sectional structure diagram of the semiconductor structure shown is along the first cross-sectional direction AA1, Fig.23 23b is Fig. 22 The cross-sectional structure diagram of the semiconductor structure is shown along the second cross-sectional direction BB1.

[0161] Forming the first conductive structure 104 and the second conductive structure 105 may include the following steps:

[0162] Combined with reference Fig.23 and Fig.24, forming an initial conductive structure 145 that fills the trench 179, the lateral gap 169, and the longitudinal gap 168. In some embodiments, the step of forming the initial conductive structure 145 may include: forming an initial diffusion barrier layer (not shown) that conformally covers the trench 179, the lateral gap 169, and the longitudinal gap 168; forming an initial conductive layer (not shown) that fills the remaining trench 179, the lateral gap 169, and the longitudinal gap 168. It should be noted that Fig.24 The dotted lines in FIG. 24 b are used to distinguish the initial conductive structure 145 located in the trench 179 , the lateral gap 169 and the longitudinal gap 168 .

[0163] Etching the initial conductive structure 145 to form the first conductive structure 104 and the second conductive structure 105 includes at least the following two embodiments:

[0164] In some embodiments, in conjunction with reference Fig.24 , Fig.25 25a, Fig.19 and Fig.21 , remove the initial conductive structure 145 located in the groove 179, and etch the initial conductive structure 145 exposed in the groove 179 and facing the first dielectric layer 132 that fills the second sub-through hole 129 to expose the surface of the first dielectric layer 132 that fills the second sub-through hole 129. In this way, the first conductive structure 104 and the second conductive structure 105 that are relatively spaced apart along the second direction Y are formed. Moreover, while forming the first conductive structure 104 and the second conductive structure 105, a bit line structure 108 that is in contact with the first conductive structure 104 is also formed, and a third conductive structure 107 that is in contact with the second conductive structure 105 is also formed. It can be understood that along the third direction Z, the widths of the first conductive structure 104, the second conductive structure 105, and the third conductive structure 107 are equal and are the same as the gate 101 (reference Figure 7 )'s maximum width W7 (reference Figure 7 ) are consistent.

[0165] In other embodiments, in combination with reference Fig.24 , Fig.25 25b, Fig.19 and Fig.21, remove the initial conductive structure 145 located in the groove 179, and etch the first dielectric layer 132 exposed in the groove 179 until the surface of the first dielectric layer 132 that fills the second sub-through hole 129 is exposed. In this way, the first conductive structure 104 and the second conductive structure 105 that are relatively spaced apart along the second direction Y are formed. Moreover, while forming the first conductive structure 104 and the second conductive structure 105, a bit line structure 108 that is in contact with the first conductive structure 104 is formed, and the second conductive structure 105 and the third conductive structure 107 that are relatively spaced apart along the second direction Y are formed. It can be understood that along the third direction Z, the widths of the first conductive structure 104, the second conductive structure 105, and the third conductive structure 107 are equal and smaller than the gate 101 (refer to Figure 7 )'s maximum width W7 (reference Figure 7 ).

[0166] It should be noted that Fig.25 The dotted lines in FIG. 140 indicate the etching of the initial conductive structure 145 (refer to Fig.24 ) and the exposed groove 179 and the partial lateral gap 169 that is directly opposite to the first dielectric layer 132 along the third direction Z. In addition, in practical applications, the third conductive structure 107 can be replaced by an isolation material layer, for example, a silicon nitride layer is used to replace the position where the third conductive structure 107 is located. In addition, Fig.24 for Fig.23 A schematic diagram of a cross-sectional structure along a first cross-sectional direction AA1 and a second cross-sectional direction BB1 formed after the semiconductor structure shown in the figure undergoes subsequent process steps, Fig.25 Among them, 25a and 25b are Fig.24 Schematic diagrams of two cross-sectional structures along the second cross-sectional direction BB1 formed after the semiconductor structure shown in the figure undergoes subsequent process steps.

[0167] Combined with reference Fig.26 and Fig. 27 , remove the first through hole 109 (reference Fig.19 ). In this way, the fourth inner wall 109a of the first through hole 109 is exposed, so that the semiconductor layer 103, the gate dielectric layer 102 and the gate 101 are formed based on the fourth inner wall 109a. It can be understood that the first through hole 109 and the second through hole 139 are filled with the first dielectric layer 132 in order to first form the first conductive structure 104, the second conductive structure 105 and the third conductive structure 107, and then form the semiconductor layer 103, the gate dielectric layer 102, the gate 101 and the capacitor structure 106 (refer to Fig.10 ).

[0168] It should be noted that Fig.26 Can be Fig.25In addition, the process steps of forming the semiconductor layer 103, the gate dielectric layer 102 and the gate 101 based on the fourth inner wall 109a are similar to those of the aforementioned embodiment, except that the space where the second sacrificial layer 140 in the aforementioned embodiment is located is occupied by the first conductive structure 104, the second conductive structure 105 and the third conductive structure 107 in this embodiment. It can be understood that Fig. 27 The fourth inner wall 109a shown in FIG. Fig.19 The fourth inner wall 109a shown in FIG. 1 has the same appearance, but the structure constituting the fourth inner wall 109a is different. Fig.19 The fourth inner wall 109a shown in FIG. 1 is composed of a first sacrificial layer 130 and a second sacrificial layer 140. Fig. 27 The fourth inner wall 109 a shown in FIG. 1 is composed of the first sacrificial layer 130 , the first conductive structure 104 and the second conductive structure 105 .

[0169] It can be understood that after the above-mentioned targeted etching is performed on the initial conductive structure 145, the remaining initial conductive structure 145 is divided into a bit line structure 108, a first conductive structure 104, a second conductive structure 105 and a third conductive structure 107, that is, the bit line structure 108, the first conductive structure 104, the second conductive structure 105 and the third conductive structure 107 can be an integrated structure. Based on this, in order to clearly illustrate the bit line structure 108, the first conductive structure 104, the second conductive structure 105 and the third conductive structure 107, Figure 25 to Figure 28 The bit line structure 108 , the first conductive structure 104 , the second conductive structure 105 , and the third conductive structure 107 are drawn using different filling methods.

[0170] In some other embodiments, reference Figures 27 to 31 After forming the first through hole 109 and the second through hole 139 and before forming the groove 179, the manufacturing method may include the following steps:

[0171] Combined with reference Fig. 27 and Fig.28 , forming a semiconductor film 163 conformally covering the fourth inner wall 109a of the first through hole 109; forming a gate dielectric film 122 conformally covering the inner wall of the semiconductor film 163; forming an initial gate 151 that fills the through hole surrounded by the gate dielectric film 122 and is similar to the first through hole 109. It should be noted that the same or corresponding parts as the steps of forming the semiconductor film 163, the gate dielectric film 122 and the initial gate 151 in the above-mentioned embodiment are not repeated here.

[0172] Combined with reference Figures 28 to 30, forming the trench 179 and removing the first sacrificial layer 130. It can be understood that at this time, the semiconductor film 163, the gate dielectric film 122 and the initial gate 151 together fill the first through hole 109 (refer to Fig.19 ), similar to the first dielectric layer 132 filling the first through hole 109 in the above embodiment, therefore, the groove 179 formed here needs to expose the semiconductor film 163 located in the first sacrificial layer 130 (ie, located in the first sub-through hole 119).

[0173] It can be understood that after removing the first sacrificial layer 130, a gap 178 is formed, and the gap 178 occupies the position of the removed first sacrificial layer 130. In this way, after forming the groove 179 and removing the first sacrificial layer 130, the surface of the exposed semiconductor film 163 is located on the side of the first sacrificial layer 130 that is not removed and surrounds the first sub-through hole 119 and extends along the first direction X. In addition, an isolation layer can be formed in the gap 178 later to achieve electrical insulation between the bit line structures 108 arranged at intervals along the first direction X, to achieve electrical insulation between the first conductive structures 104 arranged at intervals along the first direction X, to achieve electrical insulation between the second conductive structures 105 arranged at intervals along the first direction X, to achieve electrical insulation between the third conductive structures 107 arranged at intervals along the first direction X, and to achieve electrical insulation between the semiconductor layers 103 arranged at intervals along the first direction X that are subsequently formed based on the semiconductor film 163.

[0174] Combined with reference Figure 29 to Figure 31 , removing the exposed surface of the semiconductor film 163, so that the semiconductor film 163 is cut into a plurality of semiconductor layers 103 arranged at intervals along the first direction X, and referring to Fig.31 , the semiconductor layer 103 covers the first through hole 109 (refer to Fig. 27 ) in the same layer, the surfaces of the first conductive structure 104 and the second conductive structure 105 are exposed.

[0175] It should be noted that the relationship between the gate dielectric film 122 and the gate dielectric layer 102 and the relationship between the initial gate 151 and the gate 101 are the same as or corresponding to those in the above-mentioned embodiment, and are not described in detail here. Fig.30 30a is Fig.29 A schematic cross-sectional structure diagram of the semiconductor structure along a first cross-sectional direction AA1 is shown, Fig.30 30b is Fig.29 A schematic diagram of the cross-sectional structure of the semiconductor structure along the second cross-sectional direction BB1 is shown.

[0176] In some embodiments, reference Fig.14 and Figure 32 to Figure 35 Before forming the first conductive structure 104 and the second conductive structure 105, forming the capacitor structure 106 may include the following steps:

[0177] refer to Fig.14 , a stacked structure 120 is formed on the substrate 110 , and the stacked structure 120 includes first sacrificial layers 130 and second sacrificial layers 140 alternately stacked along a first direction X. It should be noted that the parts identical or corresponding to the above embodiments are not described in detail herein.

[0178] Combined with reference Fig.14 and Fig.32 , etching the stacked structure 120 to form a third through hole 138 penetrating the stacked structure 120 in the first direction X, the third through hole 138 includes a fifth sub-through hole 148 formed in each first sacrificial layer 130 and a sixth sub-through hole 158 formed in each second sacrificial layer 140, the plane perpendicular to the first direction X is the reference plane a, and the area of ​​the orthographic projection of the fifth sub-through hole 148 on the reference plane a is smaller than the area of ​​the orthographic projection of the sixth sub-through hole 158 on the reference plane a.

[0179] It should be noted that the reference Fig.32 , the fifth sub-through holes 148 correspond to the first sacrificial layers 130 one by one, and the sixth sub-through holes 158 correspond to the second sacrificial layers 140 one by one. That is, the number of the fifth sub-through holes 148 included in one third through hole 138 is consistent with the number of the first sacrificial layers 130 stacked in the stacked structure 120, and the number of the sixth sub-through holes 158 is consistent with the number of the second sacrificial layers 140 stacked in the stacked structure 120.

[0180] It can be understood that, along the first direction X, among the multiple fifth sub-through holes 148 and the multiple sixth sub-through holes 158 used to constitute the same third through hole 138, each fifth sub-through hole 148 and each sixth sub-through hole 158 are arranged alternately, so that the size of the orthographic projection area of ​​the third through hole 138 on the reference plane a will change with the change of the film layer constituting the third through hole 138, so that the fifth inner wall 138a of the third through hole 138 presents an uneven morphology. In this way, it can be considered that part of the first sacrificial layer 130 is exposed in the third through hole 138, and the orthographic projection of the exposed first sacrificial layer 130 on the substrate 110 is annular, and the exposed first sacrificial layer 130 and the second sacrificial layer 140 adjacent to each other in the first direction X jointly form an annular groove opening inwards. In other words, the annular groove opening inwards can be regarded as the area where the sixth sub-through hole 158 is more than the fifth sub-through hole 148, which is conducive to the subsequent formation of the lower electrode layer 116 having the support portion 146 (refer to the figure), the first inner extension portion 156 and the second inner extension portion 166 based on the annular groove opening inwards. It should be noted that the formation of the third through hole 138 will be described in detail later.

[0181] It should be noted that both the third through hole 138 and the second through hole 139 are used to form the capacitor structure 106 , and thus the aforementioned step of forming the second through hole 139 can also be applied to forming the third through hole 138 .

[0182] Combined with reference Fig.32 and Fig.33 , forming a plurality of lower electrode layers 116 arranged at intervals along the first direction X, each lower electrode layer 116 covers a surface of a second sacrificial layer 140 exposed by the third through hole 138, and covers surfaces of two first sacrificial layers 130 located on both sides of the second sacrificial layer 140 extending in a direction perpendicular to the first direction X.

[0183] It is understandable that, in combination with reference to Tu 32, Fig.33 and Figure 5 The exposed first sacrificial layer 130 and the second sacrificial layer 140 adjacent to each other in the first direction X together form an annular groove opening inward, that is, the sixth sub-through hole 158 is located beyond the area of ​​the fifth sub-through hole 148, and the surface of the second sacrificial layer 140 exposed by the third through hole 138 is the support portion 146 of the lower electrode layer 116, and the surfaces of the two first sacrificial layers 130 located on both sides of the second sacrificial layer 140 extending along the direction perpendicular to the first direction X are the first inner extension portion 156 or the second inner extension portion 166 of the lower electrode layer 116.

[0184] In some embodiments, the step of forming a plurality of lower electrode layers 116 arranged at intervals along the first direction X includes: forming a lower electrode film (not shown) that conformally covers the fifth inner wall 138a of the third through hole 138; removing the lower electrode film on the side wall of the first sacrificial layer 130 exposed in the third through hole 138 extending along the first direction X, so that the lower electrode film is broken to form a plurality of lower electrode layers 116 arranged at intervals along the first direction X, and combining with reference Fig.32 and Fig.33 The lower electrode layer 116 covers the surface of the area where the sixth sub-through hole 158 protrudes from the fifth sub-through hole 148, and the area where the sixth sub-through hole 158 protrudes from the fifth sub-through hole 148 has a positive projection on the substrate 110 that is annular, so as to form the lower electrode layer 116 that itself surrounds an annular groove.

[0185] Combined with reference Fig.33 and Fig.34 After forming the lower electrode layer 116 and before forming the capacitor dielectric layer 126 and the upper electrode layer 136, the step of forming the capacitor structure 106 further includes: removing the first sacrificial layer 130 that is directly opposite to the lower electrode layer 116 along the first direction X, that is, removing the first inner extension portion 156 (reference Figure 5 ) and the second inner extension 166 (reference Figure 5 ) contacts the first sacrificial layer 130 to expose the first extension portion 156 and the second extension portion 166.

[0186] In some embodiments, after a portion of the first sacrificial layer 130 is removed, a portion of the width of the second sacrificial layer 140 in the second direction Y may be exposed, and the portion of the width of the second sacrificial layer 140 is in contact with and connected to the lower electrode layer 116 .

[0187] Combined with reference Fig.34 and Fig.35 , in the remaining third through hole 138 (reference Fig.32 ) is conformally covered with a capacitor dielectric layer 126; forming an upper electrode layer 136 that fills the remaining third through holes 138. It should be noted that in this step, the exposed first inner extension portion 156 (reference Figure 5 ) and the second inner extension 166 (reference Figure 5 ) is conformally covered with a capacitor dielectric layer 126 and an upper electrode layer 136 to increase the facing area between the upper electrode layer 136 and the lower electrode layer 116, thereby facilitating increasing the capacitance of the capacitor structure 106.

[0188] It can be understood that the multiple lower electrode layers 116 arranged along the first direction X can share one capacitor dielectric layer 126 , and the multiple lower electrode layers 116 arranged along the first direction X can share one upper electrode layer 136 .

[0189] It should be noted that the above steps of forming the semiconductor layer 103, the gate dielectric layer 102 and the gate 101 and the step of forming the capacitor structure 106 can be located before the step of forming the first conductive structure 104 and the second conductive structure 105. Therefore, the order of forming the semiconductor layer 103, the gate dielectric layer 102 and the gate 101 and forming the capacitor structure 106 can be adjusted according to actual needs. For example, the semiconductor layer 103, the gate dielectric layer 102 and the gate 101 can be formed first, and then the capacitor structure 106 is formed; or the capacitor structure 106 can be formed first, and then the semiconductor layer 103, the gate dielectric layer 102 and the gate 101 are formed.

[0190] In addition, in practical applications, the semiconductor layer 103, the gate dielectric layer 102 and the gate 101 may be formed first, and then the first conductive structure 104 and the second conductive structure 105 may be formed, and finally the capacitor structure 106 may be formed. It is understandable that in the manufacturing method provided in another embodiment of the present disclosure, there is no restriction on the order of forming the semiconductor layer 103, the gate dielectric layer 102 and the gate 101, forming the first conductive structure 104 and the second conductive structure 105, and forming the capacitor structure 106, and the order may be adjusted according to actual needs.

[0191] In addition, the manufacturing method of the memory cell structure 100 is similar to the manufacturing method of the memory cell array structure, except that when forming a single memory cell structure 100, the manufacturing method has shorter process steps.

[0192] In summary, the manufacturing method provided in another embodiment of the present disclosure is conducive to increasing the number of memory cell structures 100 in the memory cell array structure within a unit volume, that is, it is conducive to improving the integration density of the memory cell array structure, and it is also conducive to improving the electrical performance of the memory cell array structure.

[0193] Those skilled in the art can understand that the above-mentioned embodiments are specific examples for implementing the present disclosure, and in practical applications, various changes can be made to them in form and detail without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the embodiments of the present disclosure, so the protection scope of the embodiments of the present disclosure shall be based on the scope defined in the claims.

Claims

1. A storage unit structure, characterized in that: include: A gate, the gate comprising a main body, and a first extension portion and a second extension portion respectively contacting and connected with two ends of the main body in a first direction, the first extension portion and the second extension portion extending in a plane perpendicular to the first direction in a direction away from the main body, and the gate itself encloses a first annular groove; a gate dielectric layer, wherein the gate dielectric layer conformally covers the first inner wall of the first annular groove, and the gate dielectric layer itself surrounds a second annular groove; a semiconductor layer, wherein the semiconductor layer conformally covers the second inner wall of the second annular groove, and the semiconductor layer itself forms a third annular groove, wherein the third annular groove has a first groove and a second groove that are arranged relatively spaced apart along a second direction, and the first direction and the second direction intersect; A first conductive structure, filling the first groove; A second conductive structure, filling the second groove; A capacitor structure comprising a lower electrode layer, an upper electrode layer and a capacitor dielectric layer located between the lower electrode layer and the upper electrode layer, wherein the lower electrode layer is in contact with and connected to the second conductive structure.

2. The storage unit structure according to claim 1, characterized in that: The second conductive structure has a contact surface away from the semiconductor layer, and the lower electrode layer is in contact with the contact surface.

3. The storage unit structure according to claim 1 or 2, characterized in that: Along the second direction, a groove depth of the third annular groove is less than or equal to a length of the second conductive structure.

4. The storage unit structure according to claim 1, characterized in that: Along the section perpendicular to the first direction, the cross-sectional shapes of the first annular groove, the second annular groove and the third annular groove are all square rings, circular rings, elliptical rings or N-sided rings, where N is a positive integer greater than or equal to 5.

5. The storage unit structure according to claim 1, characterized in that: The lower electrode layer includes a supporting portion, and a first inner extension portion and a second inner extension portion respectively contacting and connected with both ends of the supporting portion in the first direction, the supporting portion, the first inner extension portion and the second inner extension portion are all annular structures and the three of them form a hollow area, and the first inner extension portion and the second inner extension portion extend toward a direction close to the center of the hollow area in a plane perpendicular to the first direction.

6. The storage unit structure according to claim 5, characterized in that: Also includes: The third conductive structure is located at a side of the support portion away from the main body portion in the second direction.

7. The storage unit structure according to claim 6, characterized in that: The second conductive structure is in contact with the third conductive structure, and the second conductive structure and the third conductive structure jointly surround a side wall of the support portion that is away from the hollow area and extends along the first direction.

8. The storage unit structure according to claim 1 or 7, characterized in that: Along the third direction, the maximum width of the gate is greater than the maximum width of the lower electrode layer, and the first direction, the second direction and the third direction intersect each other.

9. A memory cell array structure, characterized in that: include: A plurality of storage unit structures according to any one of claims 1 to 8, wherein the plurality of storage unit structures are arranged along the first direction and / or the third direction, and the first direction, the second direction and the third direction intersect each other; The plurality of memory cell structures are arranged in contact with each other along the first direction, and the gate contacts in the adjacent memory cell structures along the first direction are connected; And / or, a plurality of the memory cell structures are arranged at intervals along the third direction, the memory cell array structure further comprises a bit line structure extending along the third direction, and one of the bit line structures is in contact and connected with a plurality of the first conductive structures arranged at intervals along the third direction.

10. A method for manufacturing a memory cell array structure, characterized in that: include: providing a substrate; forming a plurality of storage unit structures arranged along a first direction and / or a third direction on the substrate; The memory cell structure comprises: a semiconductor layer, a gate dielectric layer, a gate, a first conductive structure, a second conductive structure and a capacitor structure; Among them, the gate includes a main body and a first epitaxial part and a second epitaxial part respectively contacting and connected with the two ends of the main body in the first direction, the first epitaxial part and the second epitaxial part extend in a plane perpendicular to the first direction in a direction away from the main body, and the gate itself forms a first annular groove; the gate dielectric layer conformally covers the first inner wall of the first annular groove, and the gate dielectric layer itself forms a second annular groove; the semiconductor layer conformally covers the second inner wall of the second annular groove, and the semiconductor layer itself forms a third annular groove, the third annular groove has a first groove and a second groove arranged relatively spaced apart along the second direction, and the first direction and the second direction intersect; the first conductive structure fills the first groove, and the second conductive structure fills the second groove; the capacitor structure includes a capacitor structure of a lower electrode layer, an upper electrode layer and a capacitor dielectric layer located between the lower electrode layer and the upper electrode layer, and the lower electrode layer is in contact with the second conductive structure.

11. The manufacturing method according to claim 10, characterized in that: The steps of forming the semiconductor layer, the gate dielectric layer and the gate include: forming a stacking structure on the substrate, the stacking structure comprising first sacrificial layers and second sacrificial layers alternately stacked along the first direction; Etching the stack structure to form a first through hole penetrating the stack structure in the first direction, wherein the first through hole includes a first sub-through hole formed in each of the first sacrificial layers and a second sub-through hole formed in each of the second sacrificial layers, a plane perpendicular to the first direction is a reference plane, and an area of ​​an orthographic projection of the first sub-through hole on the reference plane is greater than an area of ​​an orthographic projection of the second sub-through hole on the reference plane; forming a semiconductor layer on the surface of each of the second sacrificial layers exposed by the first through hole, with a spacing between adjacent semiconductor layers along the first direction; Conformally covering the surface of the remaining first through hole with a layer of the gate dielectric layer; The gate electrode is formed to fill the remaining first through hole.

12. The manufacturing method according to claim 11, characterized in that: After forming the first through hole and before forming the semiconductor layer, the method further includes: Etching the stacked structure to form a second through hole penetrating the stacked structure in the first direction, wherein the second through hole includes a third sub-through hole formed in each of the first sacrificial layers and a fourth sub-through hole formed in each of the second sacrificial layers, a plane perpendicular to the first direction is a reference plane, an area of ​​an orthographic projection of the third sub-through hole on the reference plane is smaller than an area of ​​an orthographic projection of the fourth sub-through hole on the reference plane, and the first through hole and the second through hole are arranged at intervals along the second direction; forming a first dielectric layer filling the first through hole and the second through hole respectively; removing the second sacrificial layer surrounding the first through hole and the second through hole to form a plurality of lateral gaps spaced along the first direction, wherein the lateral gaps are located between adjacent first sacrificial layers along the first direction; forming the first conductive structure and the second conductive structure in the lateral gap; The first dielectric layer in the first through hole is removed.

13. The manufacturing method according to claim 12, characterized in that: The plurality of storage unit structures are arranged at intervals along the third direction; In the step of forming the first through holes and the second through holes, a plurality of the first through holes are arranged at intervals along the third direction, and a plurality of the second through holes are arranged at intervals along the third direction; After forming the first dielectric layer and before removing the first sacrificial layer, the method further includes: etching the stacked structure between the first dielectric layers adjacent to each other along the third direction to form a plurality of grooves spaced apart along the third direction, wherein the grooves expose the first dielectric layers on both sides thereof.

14. The manufacturing method according to claim 12, characterized in that: The steps of forming the first through hole and the second through hole include: Patterning the stacked structure to form a first main through hole and a second main through hole penetrating the stacked structure in the first direction, the first main through hole and the second main through hole being arranged at intervals along the second direction, the first main through hole located in the second sacrificial layer serving as the second sub-through hole, and the second main through hole located in the second sacrificial layer serving as the fourth sub-through hole; The first sacrificial layer exposed by the first main through hole and the second main through hole is laterally etched to form a first sub-through hole in each of the first sacrificial layers and a third sub-through hole in each of the first sacrificial layers.

15. The manufacturing method according to claim 10, characterized in that: The steps of forming the capacitor structure include: forming a stacking structure on the substrate, the stacking structure comprising first sacrificial layers and second sacrificial layers alternately stacked along the first direction; Etching the stack structure to form a third through hole penetrating the stack structure in the first direction, the third through hole comprising a fifth sub-through hole formed in each of the first sacrificial layers and a sixth sub-through hole formed in each of the second sacrificial layers, a plane perpendicular to the first direction being a reference plane, an area of ​​an orthographic projection of the fifth sub-through hole on the reference plane being smaller than an area of ​​an orthographic projection of the sixth sub-through hole on the reference plane; forming a plurality of lower electrode layers spaced apart along the first direction, each of the lower electrode layers covering a surface of the second sacrificial layer exposed by the third through hole, and covering two surfaces of the first sacrificial layers extending perpendicular to the first direction on both sides of the second sacrificial layer; Conformally covering the surface of the remaining third through hole with a layer of the capacitor dielectric layer; The upper electrode layer is formed to fill the remaining third through holes.

Images