Memory and method of making the same

Abstract

The present disclosure relates to a memory and a preparation method thereof. The memory comprises a memory material structure, a plurality of active pillars arranged in a plurality of rows and columns along a first direction, a bit line and a word line located in a substrate, and the second direction and the third direction are perpendicular to the first direction. The memory material structure is arranged corresponding to the plurality of active pillars and located on the top surface of the active pillar. The bit line is located directly below the active pillar and extends along the third direction. The bit line is arranged in intervals along the second direction. The word line is located between the bit line and the memory material structure, extends along the second direction and the third direction, and circumferentially surrounds the plurality of active pillars. At least the integration, performance and reliability of the memory can be improved without reducing the performance of the semiconductor device, and the complexity of the preparation process and the complexity of the read-write control can be reduced.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuit design and manufacturing, and in particular to a memory and a method for manufacturing the same. Background Art

[0002] With the rapid development of semiconductor technology, the market has increasingly higher requirements for the integration, performance, and reliability of integrated circuits. The use of vertical channel transistors can reduce the cross-sectional area of ​​transistors while ensuring that semiconductor device performance does not decrease, thereby improving the integration of integrated circuits.

[0003] However, in related memory structures, isolation structures need to be prepared between word lines connected to vertical channel transistors, which increases the complexity of the memory preparation process; and multiple word lines need to be controlled separately, which increases the complexity of memory read and write control; if leakage channels appear between adjacent word lines, it will seriously affect the performance and reliability of the memory. Summary of the Invention

[0004] Based on this, it is necessary to provide a memory and a method for preparing the same to address the problems in the above-mentioned background technology, which can at least improve the integration, performance and reliability of the memory while ensuring that the performance of the semiconductor device is not reduced, and reduce the complexity of the preparation process and the complexity of the read-write control.

[0005] According to various embodiments of the present disclosure, the first aspect of the present disclosure provides a memory, including a memory material structure, and bit lines, word lines and a plurality of active pillars located in a substrate, extending along a first direction and arranged in multiple rows and columns along a second direction and a third direction; the second direction intersects with the third direction and is perpendicular to the first direction; the memory material structure is arranged corresponding to the plurality of active pillars and is located on the top surface of the active pillar; the bit lines are located directly below the active pillars and extend along the third direction, and the bit lines are arranged at intervals along the second direction; the word lines are located between the bit lines and the memory material structure, extend along the second direction and the third direction and circumferentially surround the plurality of active pillars.

[0006] The memory in the above-described embodiment is configured such that a bit line is positioned within the substrate directly below the active pillar and extends along a third direction, so that memory cells on adjacent active pillars along the third direction share a common bit line extending along the third direction. A memory material structure for non-volatile storage is disposed on the top surface of the active pillar, and a word line is disposed between the bit line and the memory material structure, extending along the second and third directions and circumferentially surrounding multiple active pillars. This facilitates disposing a conductive line extending along the second direction on the top surface of the adjacent memory material structure along the second direction, so that a memory material structure can be selected via the conductive line extending along the second direction and the bit line extending along the third direction, thereby achieving individual control of memory cells in a memory array layer in the memory. Because the word line extends along the second and third directions and multiple active pillars penetrate the word line along the first direction, the process step of forming a word line isolation structure between word lines in the same layer is avoided, thereby effectively reducing the complexity of the memory manufacturing process. Furthermore, in the memory data read and write control method, the control step of scanning word lines one by one is relatively reduced, thereby effectively reducing the complexity of the memory read and write control.

[0007] In some embodiments, the memory further includes a gate dielectric layer, which is located between the active pillar and the word line and circumferentially surrounds the active pillar.

[0008] In some embodiments, the memory further includes a first doping region, a channel region, and a second doping region sequentially distributed on the active pillar along the first direction; and the gate dielectric layer circumferentially surrounds the channel region.

[0009] In some embodiments, the memory material structure includes a memory material layer and a conductive layer located between the memory material layer and the active pillar.

[0010] In some embodiments, the memory material layer includes a magnetic tunnel junction, a phase change material, a ferroelectric material, a resistive material, or a combination thereof.

[0011] In some embodiments, the memory further includes a word line capping layer, which is located on a top surface of the word line, extends along the second direction and the third direction, and circumferentially surrounds the plurality of active pillars.

[0012] In some embodiments, the memory further includes an isolation layer, which is located between adjacent memory material structures along the second direction and the third direction and is located on a top surface of the word line capping layer.

[0013] In some embodiments, the memory further includes a conductive wire and a conductive plug arranged corresponding to the memory material structure, the conductive plug being located on the top surface of the corresponding memory material structure; the conductive wire extends along the second direction and is electrically connected to the conductive plug directly below it; wherein, adjacent conductive wires along the third direction are insulated from each other via an insulating structure located on the top surface of the isolation layer.

[0014] In some embodiments, a bottom surface dimension of the conductive plug is smaller than a top surface dimension of the conductive plug.

[0015] A second aspect of the present disclosure provides a method for preparing a memory, comprising: providing a substrate, the substrate comprising a plurality of active pillars extending along a first direction and arranged in multiple rows and columns along a second direction and a third direction, the second direction intersecting the third direction and both being perpendicular to the first direction; forming bit lines extending along the third direction and arranged at intervals along the second direction in the substrate directly below the active pillars; forming word lines extending along the second direction and the third direction and circumferentially surrounding the plurality of active pillars; and forming a one-to-one memory material structure on the top surfaces of the plurality of active pillars.

[0016] In the above-described embodiment, the memory fabrication method comprises forming a plurality of active pillars extending in a first direction and arranged in multiple rows and columns along a second and third direction within a substrate, wherein the second and third directions intersect and are both perpendicular to the first direction. Bit lines extending in the third direction and spaced apart along the second direction are formed within the substrate directly below the active pillars. Then, word lines extending in the second and third directions and circumferentially surrounding the plurality of active pillars are formed. Furthermore, a one-to-one memory material structure is formed on the top surfaces of the plurality of active pillars, facilitating selection of a memory material structure via the conductive lines extending in the second direction and the bit lines extending in the third direction, thereby enabling individual control of memory cells in a memory array layer within the memory. Because the word lines extend in the second and third directions and circumferentially surrounding the plurality of active pillars, the process step of forming word line isolation structures between word lines in the same layer is avoided, thereby effectively reducing the complexity of the memory fabrication process. Furthermore, in the memory data read and write control method, the control step of scanning word lines one by one is relatively reduced, thereby effectively reducing the complexity of the memory read and write control.

[0017] In some embodiments, providing a substrate includes: providing an initial substrate, wherein a plurality of active walls are formed in the initial substrate and are arranged along the second direction and spaced apart by first initial isolation structures, and the active walls extend along the third direction;

[0018] A plurality of intermediate trenches extending along the second direction and spaced apart along the third direction are formed in the initial substrate to isolate the active wall into a plurality of active pillars. The remaining initial substrate is used to form the substrate. The bottom surface of the intermediate trench is higher than the bottom surface of the first initial isolation structure.

[0019] In some embodiments, providing a substrate includes: providing an initial substrate, in which a plurality of active walls are formed along a second direction and spaced apart by a first initial isolation structure, and the active walls extend along a third direction; forming a plurality of intermediate trenches extending along the second direction and spaced apart along the third direction in the initial substrate, isolating the active walls into a plurality of active pillars, and the remaining initial substrate is used to constitute a substrate; the bottom surface of the intermediate trench is higher than the bottom surface of the first initial isolation structure.

[0020] In some embodiments, forming the bit line includes: implanting ions into the substrate directly below the active pillar through the middle trench to form the bit line extending along the third direction.

[0021] In some embodiments, forming a word line includes: forming an isolation material in the middle trench; etching back the isolation material and the first initial isolation structure to form a word line trench extending along the second direction and the third direction and circumferentially surrounding multiple active pillars; and forming a word line in the word line trench.

[0022] In some embodiments, the active pillar includes a first doped region, a channel region, and a second doped region sequentially distributed along a first direction; a gate dielectric layer circumferentially surrounding the channel region is included between the channel region and the word line; a word line is formed in the word line groove, including: forming a gate dielectric layer during or after etching back the isolation material and the first initial isolation structure.

[0023] In some embodiments, after forming the word line and before forming the memory material structure, the method includes: forming a word line capping layer on the top surface of the word line, wherein the top surface of the word line capping layer is not lower than the top surface of the substrate; the word line capping layer extends along the second direction and the third direction and circumferentially surrounds a plurality of active pillars; an isolation layer is formed between adjacent memory material structures along the second direction and the third direction; after forming the memory material structure, the method further includes: forming a conductive plug on the top surface of the memory material structure; forming a conductive line extending along the second direction, and an insulating structure located between adjacent conductive lines along the third direction; and the conductive line electrically connecting the conductive plug directly thereunder. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0025] Figure 1 Shown is a schematic top view of an array area of ​​a memory provided in one embodiment of the present disclosure;

[0026] Figure 2 It is shown that a memory provided in one embodiment of the present disclosure Figure 1 Schematic diagram of the cross-sectional structure obtained in the aa' direction, bb' direction, cc' direction and dd' direction shown in ;

[0027] Figure 3 Shown is a schematic flow chart of a method for preparing a memory provided in one embodiment of the present disclosure;

[0028] Figure 4-10The three-dimensional structure obtained in different steps of the preparation method of a memory provided in one embodiment of the present disclosure is shown. Figure 1 Schematic diagram of the cross-sectional structure obtained in the aa' direction, bb' direction, cc' direction and dd' direction shown in ;

[0029] Figure 11 Shown is a schematic diagram of a three-dimensional structure of a memory provided in one embodiment of the present disclosure;

[0030] Figure 12 Display as Figure 11 Schematic diagram of the longitudinal section of an active column.

[0031] Description of reference numerals:

[0032] 100', initial substrate; 100, substrate; 101, first trench; 10', first initial isolation structure; 10, first isolation structure; 11', second initial isolation structure; 11, second isolation structure; 20, active wall; 31, middle trench; 32, isolation material; 33, word line trench; 341, gate dielectric layer; 51, interlayer conductive layer; 52, main conductive layer; 50, word line; 21, active pillar; 211, channel region; 40, bit line; 501, word line isolation structure; 60, word line cap layer; 71, conductive layer; 72, memory material layer; 70, memory material structure; 701, isolation layer; 702, interlayer dielectric layer; 80, conductive plug; 90, conductive line; 91, insulation structure. DETAILED DESCRIPTION

[0033] To facilitate understanding of the present disclosure, a more comprehensive description of the present disclosure will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the present disclosure. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0035] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0036] Spatially relative terms such as "under," "beneath," "beneath," "under," "above," "above," etc., may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, the element or feature described as "under" or "beneath" or "beneath" the other elements will be oriented as "above" the other elements or features. Thus, the exemplary terms "under" and "under" can include both upper and lower orientations. In addition, the device can also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0037] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "comprising" and / or "including" are used in this specification, they may specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0038] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic illustrations of idealized embodiments (and intermediate structures) of the present disclosure, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Accordingly, embodiments of the present disclosure should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation occurs. Accordingly, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the present disclosure.

[0039] It should be noted that the illustrations provided in this embodiment are only used to schematically illustrate the basic concept of the present disclosure. Although the illustrations only show components related to the present disclosure and are not drawn according to the number, shape and size of components in actual implementation, the type, quantity and proportion of each component in actual implementation can be changed arbitrarily, and the component layout type may also be more complex.

[0040] Please note that the mutual insulation between the two in the embodiments of the present disclosure includes but is not limited to at least one of the presence of insulating material, insulating air or a gap between the two.

[0041] See also Figure 1-Figure 2 , Figure 1 The diagram shows a top view of a dynamic random access memory (DRAM) array area. The array area includes multiple memory cells. Specifically, each memory cell in the array area includes a capacitor and a transistor. The gate of the transistor is connected to a word line 50, the drain of the transistor is connected to a bit line 40, and the source of the transistor is connected to a capacitor (not shown). The transistor is turned on and off by a voltage signal on the word line 50, and the data stored in the capacitor is read through the bit line 40, or the data is written to the capacitor for storage through the bit line 40.

[0042] See also Figure 2 , Figure 2 For Figure 1As shown in the cross-sectional structural diagram obtained along the aa', bb', cc', and dd' directions perpendicular to the substrate, word lines 50 extend along the cc' / dd' directions, and adjacent word lines 50 along the aa' / bb' directions are insulated from each other via word line isolation structures 501. However, with the miniaturization of semiconductor device structures, the continuous reduction in pattern pitch, and the increase in density, the size of the active area has been reduced to below 40nm. The use of vertical gate all around transistors (VGAA) can further effectively reduce the cross-sectional area of ​​the memory cell. However, this undoubtedly increases the complexity of preparing different word lines 50 in the same layer. Due to the reduced spacing between different word lines 50 in the same layer, the process complexity of preparing word line isolation structures 501 between different word lines 50 in the same layer increases, which can easily lead to the generation of leakage channels between adjacent word lines 50 in the same layer, thereby reducing the performance and reliability of the prepared memory.

[0043] Based on the above reasons, the embodiments of the present disclosure aim to provide a memory and a method for preparing the same, which can at least improve the integration, performance and reliability of the memory while ensuring that the performance of the semiconductor device is not reduced, and reduce the complexity of the preparation process and the complexity of the read-write control.

[0044] See also Figure 3 In one embodiment of the present disclosure, a method for preparing a semiconductor device is provided, comprising the following steps:

[0045] Step S20: providing a substrate, wherein the substrate includes a plurality of active pillars extending along a first direction and arranged in multiple rows and columns along a second direction and a third direction, wherein the second direction intersects the third direction and is perpendicular to the first direction;

[0046] Step S40: forming bit lines extending along the third direction and spaced apart along the second direction in the substrate directly below the active pillars;

[0047] Step S60: forming a word line extending along the second direction and the third direction and circumferentially surrounding the plurality of active pillars;

[0048] Step S80 : forming a one-to-one memory material structure on top surfaces of the plurality of active pillars.

[0049] As an example, see Figure 3After forming a plurality of active pillars in a substrate extending along a first direction and arranged in multiple rows and columns along a second direction and a third direction, the second direction intersects the third direction and is perpendicular to the first direction; bit lines extending along the third direction and spaced apart along the second direction are formed in the substrate directly below the active pillars; then word lines extending along the second and third directions and circumferentially surrounding the plurality of active pillars are formed; and a one-to-one memory material structure is formed on the top surfaces of the plurality of active pillars, so that one of the memory material structures can be selected via the conductive lines extending along the second direction and the bit lines extending along the third direction, thereby achieving one-to-one control of memory cells in a memory array layer in the memory. Because the word lines extend along the second and third directions and circumferentially surround the plurality of active pillars, the process step of forming word line isolation structures between word lines in the same layer is avoided, thereby effectively reducing the complexity of the memory manufacturing process; because the control step of scanning word lines one by one is relatively reduced in the memory data read and write control method, the complexity of the memory read and write control is effectively reduced.

[0050] Please note that the cross-sectional structural diagrams in the aa' direction, bb' direction, cc' direction and dd' direction shown in the following embodiments are all obtained along the three-dimensional structure obtained in the corresponding process steps. Figure 1 The aa' direction, bb' direction, cc' direction and dd' direction are shown, and a schematic diagram of the cross-sectional structure obtained along the direction perpendicular to the substrate; wherein, the first direction is parallel to the vertical substrate direction, the second direction is parallel to the cc' direction / dd' direction, and the third direction is parallel to the aa' direction / bb' direction; the vertical substrate direction refers to the direction perpendicular to the top surface of the substrate.

[0051] As an example, see Figure 4-Figure 5 , providing the substrate 100 in step S20 includes:

[0052] Step S22: providing an initial substrate 100 ′, in which a plurality of active walls 20 are formed and arranged along the second direction by first initial isolation structures 10 ′, and the active walls 20 extend along the third direction;

[0053] Step S24: forming a plurality of intermediate trenches 31 extending along the second direction and spaced apart along the third direction in the initial substrate 100', isolating the active wall 20 into a plurality of active pillars 21, and the remaining initial substrate 100' is used to constitute a substrate; the bottom surface of the intermediate trench 31 is higher than the bottom surface of the first initial isolation structure 10'.

[0054] As an example, see Figure 4The initial substrate 100' provided in step S22 can be made of a semiconductor material, an insulating material, a conductive material, or any combination of these materials. The initial substrate 100' can be a single-layer structure or a multi-layer structure. For example, the initial substrate 100' can be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the initial substrate 100' can be a layered substrate including a stack of Si and SiGe, a stack of Si and SiC, a silicon-on-insulator (SOI), or a silicon-germanium-on-insulator (SiGe-on-insulator) substrate. P-type ions can be implanted into the initial substrate 100' using an ion implantation process to form a first-type doped well region (not shown). The P-type ions can include, but are not limited to, at least one of boron (B) ions, gallium (Ga) ions, boron fluoride ions, and indium (In) ions.

[0055] As an example, see Figure 4 In the embodiment where the initial substrate 100' comprises a P-type substrate in step S20, the active wall 20 can be formed by implanting N-type ions; correspondingly, in the embodiment where the silicon substrate comprises an N-type substrate, the active wall 20 can be formed by implanting P-type ions. Accordingly, the active wall 20 can be a P-type active wall 20 or an N-type active wall 20. The P-type active wall 20 can form an N-type metal oxide semiconductor (Negative channel Metal Oxide Semiconductor, referred to as NMOS) device, and the N-type active wall 20 can form a P-type metal oxide semiconductor (Positive channel Metal Oxide Semiconductor, referred to as PMOS) device. The N-type impurity ions can include but are not limited to at least one of phosphorus (P) ions, arsenic (As) ions and antimony (Sb) ions. The concentration of N-type or P-type impurities can be less than or equal to 10 18 cm -3 , such as at about 10 17 cm -3 With about 10 18 cm -3 within the range between.

[0056] As an example, see Figure 4In step S22, a dry etching process can be used to form first trenches 101 spaced apart along the second direction and extending along the third direction in the initial substrate 100'. Subsequently, a deposition process can be used to fill at least the first trenches 101 with an isolation material 32, which also covers the exposed top surface of the initial substrate 100'. A planarization process can then be used to treat the top surface of the isolation material 32. The isolation material 32 located in the first trenches 101 is used to form a first initial isolation structure 10'. The isolation material retained on the top surface of the initial substrate 100' can prevent subsequent processes from causing contamination or damage to the initial substrate 100'. The deposition process can include, but is not limited to, at least one of a chemical vapor deposition process (CVD), a physical vapor deposition process (CVD), an atomic layer deposition process (ALD), a high density plasma deposition process (HDP), a plasma enhanced deposition process, and a spin-on dielectric layer (SOD). The planarization process may include but is not limited to at least one of a chemical mechanical polishing process, a dry etching process, and a push-flat process, etc. The isolation material 32 may be selected from silicon nitride, silicon oxide, silicon oxynitride, silicon carbide nitride, aluminum oxide, etc., and combinations thereof.

[0057] As an example, see Figure 5 In step S24, a dry etching process can be used to form a plurality of intermediate trenches 31 extending along the second direction and spaced apart along the third direction in the initial substrate 100', thereby isolating the active walls 20 into a plurality of active pillars 21. The remaining initial substrate 100' is used to form the substrate 100; the bottom surface of the intermediate trenches 31 is higher than the bottom surface of the first initial isolation structure 10', so that the first initial isolation structure 10' can be used to isolate the subsequently prepared bit lines, so that adjacent bit lines along the second direction are isolated from each other via the first initial isolation structure 10'.

[0058] As an example, see Figure 6 , forming the bit line 40 in step S40 includes:

[0059] Step S42 : ions are implanted into the substrate 100 directly below the active pillar 21 through the middle trench 31 to form a bit line 40 extending along the third direction.

[0060] As an example, see Figure 6In step S42, a liner material layer (not shown) may be formed on the bottom surface of the middle trench 31 and the sidewalls opposite to the middle trench 31 in the third direction to protect the active pillar 21 and prevent the active pillar 21 from being damaged or contaminated by doped ions in the subsequent ion implantation process; and then, an ion implantation layer of about 10 18 cm -3 and 10 19 cm -3 doping ions with a high dopant concentration between the two; the doping ions can use P-type ions. Of course, in other embodiments, the doping ions can use N-type ions, and N-type ions have a higher current. Specifically, for example, As and P ions can be used. After performing at least one, for example, one low-energy, high-dose ion implantation, an annealing process can be performed to diffuse the doping ions in the substrate 100 to form a bit line 40 extending along the third direction. Due to the segregation of impurities during the annealing process, the Schottky contact resistance is reduced. By forming a continuous metal silicide as a buried bit line 40 in the substrate 100, the resistance of the bit line 40 is reduced, and the performance of the memory is improved; by forming a VGAA transistor, the size of the memory is effectively reduced and the integration of the memory is improved.

[0061] As an example, see Figure 6-Figure 8 The step S60 of forming the word line 50 includes:

[0062] Step S62: forming an isolation material 32 in the middle trench 31;

[0063] Step S64 : etching back the isolation material 32 and the first initial isolation structure 10 ′ to form a word line trench 33 extending along the second direction and the third direction and circumferentially surrounding the plurality of active pillars 21 ;

[0064] Step S66 : forming a word line 50 in the word line trench 33 .

[0065] As an example, see Figure 6 After forming bit lines 40, in step S62, a deposition process may be used to fill at least the interior of middle trench 31 with isolation material 32. A planarization process may then be performed on the top surface of isolation material 32. Isolation material 32 within middle trench 31 forms a second preliminary isolation structure 11'. The bottom surface of second preliminary isolation structure 11' is higher than the bottom surface of first preliminary isolation structure 10'. Isolation material 32 may be selected from silicon nitride, silicon oxide, silicon oxynitride, silicon carbide nitride, aluminum oxide, and combinations thereof.

[0066] As an example, see Figure 7In step S64, the first initial isolation structure 10' and the second initial isolation structure 11' can be etched back to form a word line trench 33 whose bottom surface is flush with and higher than the top surface of the bit line 40. The word line trench 33 extends along the second and third directions and circumferentially surrounds the active pillar 21. The remaining first initial isolation structure 10' is used to form the first isolation structure 10; the remaining second initial isolation structure 11' is used to form the second isolation structure 11. The bottom surface of the second isolation structure 11 is higher than the bottom surface of the first isolation structure 10, and the top surface of the second isolation structure 11 is flush with the top surface of the first isolation structure 10 and lower than the bottom surface of the subsequently formed word line, thereby forming a word line extending along the second and third directions.

[0067] As an example, see Figure 8 The active pillar 21 includes a first doping region, a channel region 211 and a second doping region sequentially distributed along the first direction; forming the word line 50 in the word line trench 33 in step S66 includes:

[0068] Step S662 : during or after etching back the first initial isolation structure 10 ′ and the second initial isolation structure 11 ′, forming a gate dielectric layer 341 circumferentially surrounding the channel region.

[0069] As an example, see Figure 8 During the process of etching back the first initial isolation structure 10' and the second initial isolation structure 11' to form the word line trench 33, a layer of isolation material can be retained on the outer surface of the active pillar 21 to serve as the gate dielectric layer 341, thereby reducing the process flow of additionally preparing the gate dielectric layer 341. The material of the gate dielectric layer 341 can be silicon oxide.

[0070] As an example, see Figure 8 The first doped region may be used to form a source electrode, and the second doped region may be used to form a drain electrode. In other embodiments, the first doped region may be used to form a drain electrode, and the second doped region may be used to form a source electrode.

[0071] As an example, see Figure 8 During the process of etching back the first initial isolation structure 10' and the second initial isolation structure 11' to form the word line trench 33, the word line trench 33 can be formed to expose the side surface of the active pillar 21. Then, a thermal oxidation process can be used to treat the side surface of the active pillar 21 to form a gate dielectric layer 341 on the side surface of the active pillar 21. Since the active pillar 21 can be partially consumed during the thermal oxidation process to form the gate dielectric layer 341, the spacing between adjacent gate dielectric layers 341 along the second direction or the third direction is relatively increased, thereby increasing the size of the word line 50 between adjacent gate dielectric layers 341 along the second direction or the third direction, and reducing the impedance of the word line 50. The gate dielectric layer 341 can be made of silicon oxide.

[0072] As an example, see Figure 8 After forming the gate dielectric layer 341 in step S60, an interlayer conductive layer 51 is also formed on the bottom surface and sidewall of the word line trench 33, and the interlayer conductive layer 51 also circumferentially surrounds the active pillar 21; then, a main conductive layer 52 is filled in the word line trench 33, and the interlayer conductive layer 51 and the main conductive layer 52 are etched back until the top surfaces of the two are lower than the top surface of the active pillar 21 and not lower than the top surface of the channel region 211. For example, the top surfaces of the interlayer conductive layer 51 and the main conductive layer 52 after etching back can be set to be flush with the top surface of the channel region 211, and the remaining interlayer conductive layer 51 and the remaining main conductive layer 52 are used to form the word line 50, and the top surface of the word line 50 is not lower than the top surface of the channel region 211. The interlayer conductive layer 51 can serve as a barrier layer. The material of the barrier layer can include TiN, TaN, WN or a combination thereof to prevent the conductive material from diffusing to form a leakage channel during the process of depositing the main conductive layer 52 to prepare the word line 50, thereby improving the performance and reliability of the prepared semiconductor device.

[0073] As an example, see Figure 8 The interlayer conductive layer 51 can serve as a work function layer. The work function layer includes one or more layers of a conductive material, such as a single layer of TiN, TaN, TaAlC, TiC, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi, or TiAlC, or a multilayer of two or more of these materials. The main conductive layer 52 can include W, Cu, Ti, Al, Co, or a combination thereof.

[0074] As an example, see Figure 9 , after forming the word line 50 and before forming the memory material structure 70, comprising:

[0075] Step S72 : forming a word line capping layer 60 on the top surface of the word line 50 , wherein the top surface of the word line capping layer 60 is not lower than the top surface of the active pillar 21 ; the word line capping layer 60 extends along the second direction and the third direction and circumferentially surrounds the plurality of active pillars 21 .

[0076] As an example, see Figure 8 In step S72, a deposition process may be used to form a word line capping layer 60 on the top surface of the word line 50, the top surface of which is not lower than the top surface of the active pillar 21. The material of the word line capping layer 60 includes silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride or a combination thereof.

[0077] As an example, see Figure 9 In step S80, a one-to-one memory material structure 70 is formed on the top surfaces of the plurality of active pillars 21, including:

[0078] Step S81: After forming the word line capping layer 60 , forming an isolation material layer (not shown) covering the word line capping layer 60 , wherein the isolation material layer extends along the second direction and the third direction;

[0079] Step S82: patterning the isolation material layer to obtain a first through hole (not shown) located directly above the active pillar 21 , with the first through hole and the active pillar 21 arranged one-to-one; the remaining isolation material layer is used to form the isolation layer 701 ;

[0080] Step S83: removing the isolation material 32 on the top surface of the active pillar 21 through the first through hole;

[0081] Step S84: forming a conductive layer 71 on the top surface of the active pillar 21 in the first through hole, wherein the conductive layer 71 covers the exposed top surface of the active pillar 21;

[0082] Step S85 : forming a memory material layer 72 on the exposed top surface of the conductive layer 71 in the first through hole. The conductive layer 71 and the memory material layer 72 are used to together constitute the memory material structure 70 .

[0083] As an example, see Figure 9 In step S82, a wet etching process may be used to remove the isolation material 32 on the top surface of the active pillar 21 to expose the top surface of the active pillar 21. In step S84, a deposition process may be used to form a conductive layer 71 on the exposed top surface of the active pillar 21. The conductive layer 71 covers the exposed top surface of the active pillar 21. In step S86, a deposition process may be used to form a memory material layer 72 on the exposed top surface of the conductive layer 71. The conductive layer 71 and the memory material layer 72 are used to together constitute the memory material structure 70. The material of the conductive layer 71 may include, but is not limited to, titanium, tungsten, cobalt, nickel, tantalum, tantalum titanium, tungsten silicide, tungsten nitride, etc., or a combination thereof. The material of the memory material layer 72 may include, but is not limited to, a magnetic tunnel junction, a phase change material, a ferroelectric material, a resistive material, or a combination thereof.

[0084] As an example, see Figure 9 In step S80 , a self-aligned double patterning (SADP) process or a self-aligned quadruple patterning (SAQP) process may also be used to form a one-to-one memory material structure 70 on the top surfaces of the plurality of active pillars 21 .

[0085] As an example, see Figure 10 , an isolation layer 701 is formed between adjacent memory material structures 70 along the second direction and the third direction; after forming the memory material structure 70, the method further includes:

[0086] Step S92: forming a conductive plug 80 on the top surface of the memory material structure 70;

[0087] Step S94 : forming conductive lines 90 extending along the second direction and insulating structures 91 located between adjacent conductive lines 90 along the third direction; the conductive lines 90 are electrically connected to the conductive plugs 80 directly thereunder.

[0088] As an example, see Figure 10 In step S94, a self-aligned double patterning (SADP) process or a self-aligned quadruple patterning (SAQP) process can be used to form a conductive line 90 extending along the second direction, and the conductive lines 90 adjacent to each other along the third direction are insulated from each other via an insulating structure 91.

[0089] As an example, see Figure 10 In step S92, a conductive plug 80 is formed on the top surface of the memory material structure 70, including:

[0090] Step S921: forming an interlayer dielectric material layer (not shown), the interlayer dielectric material layer covering the isolation layer 701 and extending along the second direction and the third direction;

[0091] Step S922: Patterning the interlayer dielectric material layer to obtain a second through hole (not shown) located directly above the active pillar 21. The second through hole is arranged one-to-one with the active pillar 21. The remaining interlayer dielectric material layer is used to form the interlayer dielectric layer 702. The top opening size of the second through hole is larger than the bottom opening size of the second through hole.

[0092] Step S923: forming a conductive plug 80 in the second through hole.

[0093] As an example, see Figure 9In step S921, a deposition process can be used to form an interlayer dielectric material layer (not shown). The interlayer dielectric material layer includes silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In step S922, a first patterned mask layer (not shown) is formed on the top surface of the interlayer dielectric material layer. The first patterned mask layer has a pattern for defining the second through hole. The interlayer dielectric material layer is dry-etched using the first patterned mask layer as a mask. Based on the physical property of dry etching where the ion etching rate of the top layer is greater than the etching rate of the bottom layer, a second through hole that is wider at the top and narrower at the bottom is obtained. In step S923, a deposition process can be used to fill the second through hole with a conductive plug material. Then, a planarization process is used to treat the top surface of the conductive plug material to obtain a conductive plug 80 located in the second through hole. The bottom surface size of the conductive plug 80 is smaller than the top surface size of the conductive plug 80 to relatively increase the contact area between the conductive plug 80 and the subsequently prepared conductive line 90, thereby reducing impedance. The material of the conductive plug 80 may include titanium, tungsten, cobalt, nickel, tantalum, tantalum titanium, tungsten silicide, tungsten nitride, etc. or a combination thereof to meet the actual needs of various application scenarios and reduce the cost and complexity of preparation.

[0094] As an example, see Figure 10 The conductive plug 80, the memory material layer 72, and the conductive layer 71 can form a stacked structure with memory function. The conductive layer 71 can be made of a non-magnetic metal material, which contains non-magnetic metal elements. For example, the non-magnetic metal material used to make the conductive layer 71 can include but is not limited to TiN, TaN, WN, W, Cu, Al, Ta, Ru, Mo, Pt, or a combination thereof. The conductive plug 80 can be made of a non-magnetic metal material, and the conductive plug 80 and the conductive layer 71 can be made of the same or different materials. The memory material layer 72 may include a magnetic tunnel junction material layer, for example, a reference magnetic layer, a tunnel barrier layer, and a free magnetic layer stacked in sequence along a first direction, with the reference magnetic layer adjacent to the conductive layer 71. The reference magnetic layer may be made of a first ferromagnetic material, and the free magnetic layer may be made of a second ferromagnetic material. The first ferromagnetic material may include a hard ferromagnetic material, such as Co, CoFe, CoFeB, CoFeBTa, NiFe, CoPt, CoFeNi, or a combination thereof. The second ferromagnetic material may include a hard ferromagnetic material, which may be the same as or different from the first ferromagnetic material. The tunnel barrier layer may be an electrically insulating material that allows electron tunneling, for example, magnesium oxide (MgO), aluminum oxide (Al2O3), aluminum nitride (AlN), aluminum oxynitride (AlON), hafnium oxide (HfO2), zirconium oxide (ZrO2), or a combination thereof.

[0095] As an example, see Figure 10 After forming the conductive plug 80 in the second through hole, the method further includes:

[0096] Step S101: forming an insulating material layer (not shown), the insulating material layer covering the top surface of the interlayer dielectric layer 702 and extending along the second direction and the third direction;

[0097] Step S102: patterning the insulating material layer to obtain conductive traces (not shown) located directly above the active pillars 21 , the conductive traces extending along the second direction and spaced apart along the third direction; the remaining insulating material layer is used to form the insulating structure 91 ;

[0098] Step S103: forming a conductive wire 90 in the conductive groove.

[0099] As an example, see Figure 10 In step S101, a deposition process may be used to form an insulating material layer covering the top surface of the interlayer dielectric layer 702 and extending in the second and third directions. The insulating material layer may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In step S102, a second patterned mask layer may be formed on the top surface of the insulating material layer. The second patterned mask layer includes an opening pattern for defining the shape, position, and size of the conductive traces. Using this second patterned mask layer as a mask, the insulating material layer is etched to form conductive traces located directly above the active pillars 21. The conductive traces extend in the second direction and are spaced apart in the third direction. The remaining insulating material layer is used to form the insulating structure 91. In step S103, at least one of an electroplating process, a chemical plating process, a placement process, a printing process, a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, and a photolithography process may be used to form the conductive line 90 in the conductive groove. The material of the conductive line 90 may include titanium, tungsten, cobalt, nickel, tantalum, tantalum titanium, tungsten silicide, tungsten nitride, or a combination thereof.

[0100] As an example, see Figure 10 By selecting a bit line 40 and a conductive line 90, a memory cell on the active column 21 electrically connecting the two can be selected to perform read and write control on the memory cell, which relatively reduces the control steps of scanning the word lines 50 one by one, thereby effectively reducing the complexity of memory read and write control.

[0101] It should be understood that although Figure 3 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, although Figure 3At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The order of execution of these steps or stages is not necessarily one by one, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0102] In some embodiments, see Figure 1 、 Figure 10-12 , provides a memory, including a memory material structure 70, and a bit line 40, a word line 50 and a plurality of active pillars 21 extending along a first direction and arranged in multiple rows and columns along a second direction and a third direction in a substrate 100; the second direction intersects with the third direction and is perpendicular to the first direction; the memory material structure 70 is arranged corresponding to the plurality of active pillars 21 and is located on the top surface of the active pillar 21; the bit line 40 is located directly below the active pillar 21 and extends along the third direction, and the bit line 40 is arranged at intervals along the second direction; the word line 50 is located between the bit line 40 and the memory material structure 70, extends along the second direction and the third direction and circumferentially surrounds the plurality of active pillars 21.

[0103] As an example, see Figure 1 、 Figure 10-12 , by setting a bit line 40 located in the substrate directly below the active pillar 21 and extending along the third direction, so that the memory cells on the active pillars 21 adjacent along the third direction share a bit line 40 extending along the third direction; by setting a memory material structure 70 for non-volatile storage on the top surface of the active pillar 21, a word line 50 extending along the second direction and the third direction and circumferentially surrounding multiple active pillars 21 is set between the bit line 40 and the memory material structure 70, that is, multiple active pillars 21 pass through the word line 50 along the first direction, so that it is convenient to set a conductive line 90 extending along the second direction on the top surface of the memory material structure 70 adjacent along the second direction, so as to select a memory material structure 70 via the conductive line 90 extending along the second direction and the bit line 40 extending along the third direction, thereby realizing one-by-one control of the memory cells in a memory array of a layer in the memory. Since the word line 50 extends along the second direction and the third direction and circumferentially surrounds multiple active pillars 21, the process steps of preparing the word line 50 isolation structure between the word lines 50 of the same layer are avoided, thereby effectively reducing the complexity of the memory preparation process; since in the data reading and writing control method of the memory, the control steps of scanning the word lines 50 one by one are relatively reduced, thereby effectively reducing the complexity of the memory reading and writing control.

[0104] As an example, see Figure 1 、 Figure 10-12The memory device further includes a gate dielectric layer 341, which is located between the active pillar 21 and the word line 50 and circumferentially surrounds the active pillar 21. By providing the gate dielectric layer 341 circumferentially surrounding the active pillar 21 between the active pillar 21 and the word line 50, a ring gate is formed during the formation of the word line 50, reducing the complexity of the ring gate fabrication process while improving the performance of the fabricated transistor.

[0105] As an example, see Figure 1 、 Figure 10-12 The memory also includes a first doped region, a channel region 211, and a second doped region sequentially distributed along a first direction on the active pillar 21. A gate dielectric layer 341 circumferentially surrounds the channel region 211. A junctionless transistor can be formed on the active pillar 21. A source, a vertical channel, and a drain can be sequentially formed on the active pillar 21, ensuring the controllability of the transistor gate and improving the integration density and electrical performance of the memory.

[0106] As an example, see Figure 11-12 The memory material structure 70 includes a magnetic tunnel junction, a phase change material, a ferroelectric material, a resistive material, or a combination thereof.

[0107] As an example, see Figure 1 、 Figure 10-12 The memory also includes a first isolation structure 10 extending along the third direction, and the first isolation structure 10 is located between the bit lines 40 adjacent to each other along the second direction and the active pillars 21 adjacent to each other along the second direction; the bottom surface of the first isolation structure 10 is lower than the bottom surface of the bit line 40 and the top surface is lower than the bottom surface of the word line 50, so that the first isolation structure 10 is used to electrically isolate the bit lines 40 adjacent to each other along the second direction.

[0108] As an example, see Figure 1 、 Figure 10-12 The memory further includes a word line capping layer 60 located on the top surface of the word line 50. The word line capping layer 60 is located on the top surface of the word line 50, and the top surface of the word line capping layer 60 is not lower than the top surface of the active pillar 21. The word line capping layer 60 extends along the second direction and the third direction and circumferentially surrounds the multiple active pillars 21.

[0109] As an example, see Figure 1 、 Figure 10-12 The memory further includes an isolation layer 701 located on the top surface of the word line capping layer 60. The isolation layer 701 is located between adjacent memory material structures 70 along the second and third directions and is located on the top surface of the word line capping layer 60. For example, the isolation layer 701 can be arranged to extend along the second and third directions, and the memory material structure 70 can penetrate the isolation layer 701 along the first direction.

[0110] As an example, see Figure 1 、 Figure 10-12The memory also includes a conductive line 90 and a conductive plug 80 corresponding to the memory material structure 70. The conductive plug 80 is located on the top surface of the corresponding memory material structure 70. The conductive line 90 extends along the second direction and electrically connects the conductive plug 80 directly below it. The conductive lines 90 adjacent to each other along the third direction are insulated from each other by an insulating structure 91 located on the top surface of the isolation layer. The material of the conductive plug 80 may include titanium, tungsten, cobalt, nickel, tantalum, tantalum titanium, tungsten silicide, tungsten nitride, etc., or a combination thereof. The material of the conductive line 90 may include titanium, tungsten, cobalt, nickel, tantalum, tantalum titanium, tungsten silicide, tungsten nitride, etc., or a combination thereof. The material of the conductive plug 80 and the conductive line 90 may be the same or different.

[0111] As an example, see Figure 1 、 Figure 10-12 The bottom surface size of the conductive plug 80 is smaller than the top surface size of the conductive plug 80 , so as to relatively increase the contact area between the conductive plug 80 and the subsequently prepared conductive wire 90 , thereby reducing the impedance.

[0112] As an example, see Figure 1 、 Figure 10-12 The memory material structure 70 includes a memory material layer 72 and a conductive layer 71 located between the memory material layer 72 and the active pillar 21. The conductive plug 80, the memory material layer 72, and the conductive layer 71 can form a stacked structure with a memory function. The conductive layer 71 can include a non-magnetic metal material, and the non-magnetic metal material contains a non-magnetic metal element. For example, the non-magnetic metal material used to make the conductive layer 71 can include but is not limited to titanium, tungsten, cobalt, nickel, tantalum, tantalum titanium, tungsten silicide, tungsten nitride, etc. or a combination thereof; the conductive plug 80 can include a non-magnetic metal material, and the materials of the conductive plug 80 and the conductive layer 71 can be the same or different. The memory material layer 72 may include a magnetic tunnel junction material layer, for example, a reference magnetic layer, a tunnel barrier layer, and a free magnetic layer stacked in sequence along a first direction, with the reference magnetic layer adjacent to the conductive layer 71. The reference magnetic layer may be made of a first ferromagnetic material, and the free magnetic layer may be made of a second ferromagnetic material. The first ferromagnetic material may include a hard ferromagnetic material, such as Co, CoFe, CoFeB, CoFeBTa, NiFe, CoPt, CoFeNi, or a combination thereof. The second ferromagnetic material may include a hard ferromagnetic material, which may be the same as or different from the first ferromagnetic material. The tunnel barrier layer may be an electrically insulating material that allows electron tunneling, for example, magnesium oxide (MgO), aluminum oxide (Al2O3), aluminum nitride (AlN), aluminum oxynitride (AlON), hafnium oxide (HfO2), zirconium oxide (ZrO2), or a combination thereof.

[0113] As an example, see Figure 1 、 Figure 10-12By selecting a bit line 40 and a conductive line 90, a memory cell on the active column 21 electrically connecting the two can be selected to perform read and write control on the memory cell, which relatively reduces the control steps of scanning the word lines 50 one by one, thereby effectively reducing the complexity of memory read and write control.

[0114] Please note that for the sake of simplicity of the specification, in the structural diagrams given in the embodiments below, unless the corresponding cross-sectional structural diagrams are given separately, other structural diagrams from different perspectives of structures related to the inventive points of the embodiments of the present disclosure can be referenced to each other.

[0115] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0116] The above-described embodiments merely represent several implementation methods of the present disclosure. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present disclosure, all of which fall within the scope of protection of the present disclosure. Therefore, the scope of protection of the patent disclosed herein shall be determined by the appended claims.

Claims

1. A method for preparing a memory, characterized in that: include: Providing a substrate, wherein the substrate includes a plurality of active pillars extending along a first direction and arranged in multiple rows and columns along a second direction and a third direction, wherein the second direction intersects the third direction and is perpendicular to the first direction; forming bit lines extending along the third direction and arranged at intervals along the second direction in the substrate directly below the active pillar; Forming a word line extending along the second direction and the third direction and circumferentially surrounding the plurality of active pillars, comprising: forming an isolation material in a middle trench of the substrate; Etching back the isolation material and the first initial isolation structure to form a word line trench extending along the second direction and the third direction and circumferentially surrounding the plurality of active pillars, wherein a gate dielectric layer is formed during or after etching back the isolation material and the first initial isolation structure; forming an interlayer conductive layer on the bottom surface and sidewalls of the word line trench, wherein the interlayer conductive layer circumferentially surrounds the active pillars; then filling the word line trench with a main conductive layer, etching back the interlayer conductive layer and the main conductive layer until their top surfaces are lower than the top surface of the active pillars and not lower than the top surface of the channel region; and forming the word line in the word line trench; A one-to-one memory material structure is formed on top surfaces of the plurality of active pillars.

2. The preparation method according to claim 1, characterized in that Providing a substrate comprises: Providing an initial substrate, in which a plurality of active walls are formed and arranged along the second direction and spaced apart by first initial isolation structures, and the active walls extend along the third direction; A plurality of intermediate trenches extending along the second direction and spaced apart along the third direction are formed in the initial substrate to isolate the active walls into the plurality of active pillars, and the remaining initial substrate is used to constitute the substrate; the bottom surface of the intermediate trench is higher than the bottom surface of the first initial isolation structure.

3. The preparation method according to claim 2, characterized in that forming the bit line, comprising: Ions are implanted into the substrate directly below the active pillar through the middle trench to form a bit line extending along the third direction.

4. The preparation method according to claim 1, characterized in that The active pillar includes a first doping region, a channel region and a second doping region sequentially distributed along the first direction; and a gate dielectric layer circumferentially surrounding the channel region is provided between the channel region and the word line.

5. The preparation method according to any one of claims 1 to 4, characterized in that After forming the word line and before forming the memory material structure, the method includes: forming a word line capping layer on a top surface of the word line, wherein the top surface of the word line capping layer is not lower than a top surface of the substrate; the word line capping layer extends along the second direction and the third direction and circumferentially surrounds the plurality of active pillars; An isolation layer is formed between adjacent memory material structures along the second direction and the third direction; after forming the memory material structure, the method further includes: forming a conductive plug on the top surface of the memory material structure; Conductive lines extending along the second direction and insulating structures located between the conductive lines adjacent to each other along the third direction are formed; the conductive lines are electrically connected to the conductive plugs directly below them.

6. A memory obtained by the preparation method according to any one of claims 1 to 5, characterized in that: The invention comprises a memory material structure, a bit line, a word line and a plurality of active pillars extending in a first direction and arranged in multiple rows and columns along a second direction and a third direction in a substrate; the second direction intersects the third direction and is perpendicular to the first direction; The memory material structure is arranged corresponding to the plurality of active pillars and is located on the top surface of the active pillars; The bit lines are located directly below the active pillars and extend along the third direction, and the bit lines are arranged at intervals along the second direction; The word line is located between the bit line and the memory material structure, extends along the second direction and the third direction, and circumferentially surrounds the plurality of active pillars.

7. The memory according to claim 6, wherein: Also includes: The gate dielectric layer is located between the active pillar and the word line and circumferentially surrounds the active pillar.

8. The memory according to claim 7, wherein: It also includes a first doping region, a channel region and a second doping region sequentially distributed on the active pillar along the first direction; The gate dielectric layer circumferentially surrounds the channel region.

9. The memory according to any one of claims 6 to 8, characterized in that: The memory material structure includes a memory material layer and a conductive layer located between the memory material layer and the active pillar.

10. The memory according to claim 9, wherein: The memory material layer includes a magnetic tunnel junction, a phase change material, a ferroelectric material, a resistive material or a combination thereof.

11. The memory according to any one of claims 6 to 8, characterized in that: Also includes: The word line capping layer is located on a top surface of the word line, extends along the second direction and the third direction, and circumferentially surrounds the plurality of active pillars.

12. The memory according to claim 11, wherein: Also includes: The isolation layer is located between the memory material structures adjacent to each other along the second direction and the third direction, and is located on a top surface of the word line cap layer.

13. The memory according to claim 12, wherein: Also includes: a conductive plug, arranged corresponding to the memory material structure and located on the top surface of the corresponding memory material structure; as well as a conductive line extending along the second direction and electrically connected to a conductive plug directly below the conductive line; The conductive lines adjacent to each other along the third direction are insulated from each other via an insulating structure located on a top surface of the isolation layer.

14. The memory according to claim 13, wherein: The bottom surface size of the conductive plug is smaller than the top surface size of the conductive plug.

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