Semiconductor structure and method of manufacturing the same, storage system

Abstract

This application provides a semiconductor structure, a method for manufacturing the same, and a memory system. The method for manufacturing the semiconductor structure includes: forming a conductive structure within a memory region and extending along a second direction; forming an isolation structure extending along the second direction through a memory region and a non-memory region; wherein the conductive structure is located at a first sidewall of a semiconductor pillar, and a portion of the isolation structure is located at a second sidewall of the semiconductor pillar opposite to the first sidewall; and forming an outgoing structure connected to the isolation structure in a non-memory region.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to semiconductor structures, methods for manufacturing semiconductor structures, and memory systems. Background Technology

[0002] With the rise and development of artificial intelligence, big data, the Internet of Things, mobile communications, mobile devices, and cloud storage, the requirements for storage density in semiconductor structures, such as three-dimensional semiconductor memory devices, are becoming increasingly stringent. However, as the storage density of semiconductor structures increases, the number of memory cells and wiring leads also increases, their size decreases, and their spatial density increases, leading to more severe coupling between adjacent components. Furthermore, the space available for wiring leads in isolation structures used to isolate adjacent components, such as adjacent memory cells, is also limited. Summary of the Invention

[0003] The embodiments proposed in this application can solve or partially solve the deficiencies mentioned in the background section above or other deficiencies in the prior art.

[0004] This application provides a method for manufacturing a semiconductor structure. The semiconductor structure includes a semiconductor layer, which includes a plurality of memory regions and at least one non-memory region. Both the memory regions and the non-memory regions extend along a first direction and are arranged along a second direction. The memory regions include a plurality of semiconductor pillars extending along a third direction, with the first, second, and third directions perpendicular to each other. The method includes: forming a conductive structure within the memory regions and extending along the second direction; and forming an isolation structure extending along the second direction through the memory regions and the non-memory regions, wherein the conductive structure is located at a first sidewall of the semiconductor pillars, and a portion of the isolation structure is located at a second sidewall of the semiconductor pillars opposite to the first sidewall; and forming an outgoing structure connected to the isolation structure in the non-memory region.

[0005] In one embodiment, a conductive structure is formed within a storage region and extending along a second direction, and an isolation structure is formed extending along the second direction through the storage region and a non-storage region, comprising: forming a plurality of initial semiconductor pillars extending along a first direction in the storage region; forming a third trench within the storage region, through the initial semiconductor pillars and extending along the second direction, and forming a fourth trench extending along the second direction through the initial semiconductor pillars and a non-storage region, wherein the third trench and the fourth trench divide the initial semiconductor pillars into a plurality of semiconductor pillars, and the width of the third trench is greater than the width of the fourth trench; and forming a conductive structure in the third trench and forming an isolation structure in the fourth trench.

[0006] In one embodiment, forming a conductive structure extending in a second direction within a storage region and forming an isolation structure extending in the second direction through the storage region and a non-storage region includes: forming a plurality of initial semiconductor pillars extending in a first direction in the storage region; forming a third trench and a fourth trench alternately arranged in the first direction and extending in the second direction through the initial semiconductor pillars and the non-storage region, wherein the third trench and the fourth trench divide the initial semiconductor pillars into a plurality of semiconductor pillars, and the width of the third trench is greater than the width of the fourth trench; forming an initial conductive structure in the third trench and forming an isolation structure in the fourth trench; and removing at least a portion of the initial conductive structure located in the non-storage region to form the conductive structure.

[0007] In one embodiment, forming a plurality of initial semiconductor pillars extending along a first direction in a storage region includes: forming a plurality of first trenches extending along the first direction in the storage region, and forming a second trench extending along the first direction in a non-storage region, wherein the width of the second trench is greater than the width of the first trench; and forming a filling dielectric layer in the first trench and the second trench, wherein the semiconductor layer that has not been removed in the storage region forms the initial semiconductor pillars.

[0008] In one embodiment, forming a third trench within a storage region, passing through an initial semiconductor pillar and extending along a second direction, and forming a fourth trench extending along the second direction through the initial semiconductor pillar and a non-storage region, includes: forming an initial third trench within a storage region, passing through an initial semiconductor pillar and extending along a second direction, and forming a fourth trench extending along the second direction through the initial semiconductor pillar and a non-storage region; forming a first sacrificial layer and a second sacrificial layer in the initial third trench and the fourth trench, respectively; removing a portion of the second sacrificial layer along a third direction and forming a protective layer in the removed space; and removing the first sacrificial layer and increasing the width and depth of the initial third trench to form the third trench.

[0009] In one embodiment, forming a conductive structure in a third trench and an isolation structure in a fourth trench includes: forming a first dielectric layer in the third trench; removing a portion of the first dielectric layer in a third direction to form a first gap; forming a gate dielectric layer on the sidewall of the first gap; forming a conductive layer inside the gate dielectric layer; removing a portion of the conductive layer in a third direction to form a second gap; forming a third gap in a third direction through the conductive layer to expose the first dielectric layer, wherein the remaining conductive layer forms a conductive structure; forming a second dielectric layer within the second and third gaps; removing a protective layer and the remaining second sacrificial layer to form a fourth gap; and forming an isolation structure within the fourth gap.

[0010] In one embodiment, the method further includes forming a contact structure connected to the conductive structure.

[0011] In one embodiment, the isolation structure includes a first isolation structure located at the second sidewall of the semiconductor pillar and a second isolation structure located in the non-memory region, forming a contact structure connected to the conductive structure, including: a first isolation structure etched back along a third direction and forming a third dielectric layer within the etched-back space; and forming a contact structure on the side of the conductive structure corresponding to the third dielectric layer.

[0012] In one embodiment, forming an exit structure connected to an isolation structure in a non-memory area includes: forming an exit hole in the non-memory area extending in a third direction to the isolation structure; and forming an exit structure within the exit hole.

[0013] In one embodiment, forming an exit structure connected to an isolation structure in a non-memory area includes: forming an exit groove in the non-memory area extending to the isolation structure in a third direction and extending in a first direction; and forming an exit structure within the exit groove.

[0014] This application also provides a semiconductor structure. The semiconductor structure includes: a semiconductor layer comprising a plurality of memory regions and at least one non-memory region, both extending along a first direction and arranged along a second direction; the memory regions comprising a plurality of semiconductor pillars extending along a third direction, the first direction, the second direction, and the third direction being perpendicular to each other; a conductive structure located at a first sidewall of the semiconductor pillars and extending along the second direction within the memory regions; an isolation structure extending along the second direction through the memory regions and non-memory regions, a portion of which is located at a second sidewall of the semiconductor pillars opposite to the first sidewall; and a lead-out structure disposed in the non-memory region and connected to the isolation structure.

[0015] In one embodiment, the semiconductor structure further includes: a gate dielectric layer located between the conductive structure and the semiconductor pillar, wherein the conductive structure includes a first conductive layer located inside the gate dielectric layer and a second conductive layer located inside the first conductive layer; and a second dielectric layer located inside the second conductive layer.

[0016] In one embodiment, the isolation structure is made of metal, and the semiconductor structure further includes a third dielectric layer located on one side of the isolation structure and connected to the isolation structure.

[0017] In one embodiment, the semiconductor structure further includes a contact structure located on the side of the conductive structure corresponding to the third dielectric layer and connected to the conductive structure.

[0018] In one embodiment, the lead-out structure includes: a plurality of sub-lead-out structures connected to the isolation structure and arranged along a first direction.

[0019] In one implementation, the lead-out structure extends along a first direction.

[0020] In one embodiment, the semiconductor structure further includes a source and a drain respectively disposed at both ends of the semiconductor pillar.

[0021] Another aspect of this application provides a storage system including at least one three-dimensional memory, each three-dimensional memory including a semiconductor structure as described above; and a controller coupled to the semiconductor structure for controlling the storage of data in the three-dimensional memory.

[0022] In one or more embodiments of this application, by setting the isolation structure to extend through the storage area and non-storage area along the second direction, and forming an outgoing structure connected to the isolation structure in the non-storage area, the isolation structures of multiple storage areas can be connected to the outgoing structure through the non-storage area, which is beneficial to reduce the outgoing space of the isolation structure and reduce the difficulty of outgoing the isolation structure. Attached Figure Description

[0023] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments, taken in conjunction with the accompanying drawings. In the drawings:

[0024] Figure 1 This is a flowchart of a method for manufacturing a semiconductor structure according to an exemplary embodiment of this application;

[0025] Figures 2 to 17 This is a process step diagram illustrating the formation of a conductive structure and an isolation structure according to an exemplary embodiment of this application;

[0026] Figures 18 to 35 This is a process step diagram of forming a conductive structure and an isolation structure according to another exemplary embodiment of this application;

[0027] Figure 36 This is a process step diagram of forming a contact structure according to an exemplary embodiment of this application;

[0028] Figure 37 This is a process step diagram of forming a contact structure according to another exemplary embodiment of this application;

[0029] Figure 38 This is a process step diagram of forming an lead-out structure according to an exemplary embodiment of this application;

[0030] Figure 39 This is a process step diagram of forming an lead-out structure according to another exemplary embodiment of this application;

[0031] Figure 40 This is an exemplary block diagram of a system having a storage system according to an exemplary embodiment of this application; and

[0032] Figure 41Aand Figure 41B This is a schematic diagram of a storage system according to an exemplary embodiment of this application. Detailed Implementation

[0033] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely descriptions of exemplary embodiments of this application and are not intended to limit the scope of this application in any way.

[0034] It should be noted that in this specification, the terms "first," "second," "third," etc., are used only to distinguish one feature from another and do not imply any limitation on the features, especially not any order of precedence. Therefore, without departing from the teachings of this application, the first trench discussed herein may also be referred to as the second trench or the third trench, and the first direction may also be referred to as the second direction or the third direction, and vice versa.

[0035] In the accompanying drawings, the thickness, dimensions, and shapes of the parts have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale. As used herein, the terms “approximately,” “about,” and similar terms are used as expressions of approximation, not as expressions of degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art.

[0036] Furthermore, in this text, when describing a part as being "on" another part, such as "on," "above," and "above," the meaning should be interpreted in the broadest possible sense, such that "on" not only means "directly on" something, but also includes the meaning of "on" something with intermediate features or layers in between. Moreover, "above" or "above" does not absolutely mean being above something with respect to the direction of gravity, nor does it only mean "on" something or "above" something, but can also include the meaning of "on" something or "above" something without intermediate features or layers in between (i.e., directly on) something.

[0037] It should also be understood that expressions such as "comprising," "including," "having," "containing," and / or "comprising" are open-ended rather than closed-ended expressions in this specification, indicating the presence of the stated features, elements, and / or components, but not excluding the presence of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not just individual elements in the list. Additionally, when describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to examples or illustrations.

[0038] This document describes the embodiments with reference to schematic diagrams of exemplary implementations. The exemplary implementations disclosed herein should not be construed as limited to the specific shapes and sizes shown, but rather include various equivalent structures capable of achieving the same function, as well as shape and size variations arising, for example, during manufacturing. The positions shown in the accompanying drawings are schematic in nature and not intended to limit the positions of the components.

[0039] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Terms such as those defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant field and shall not be interpreted in an idealized or overly formalized sense unless expressly defined herein.

[0040] As used herein, the term "layer" refers to a portion of material comprising a region having height. A layer can be a region of a homogeneous or non-homogeneous continuous structure, the height of which is less than the height of the continuous structure. For example, a layer can be located at or between any set of horizontal planes on or between the top and bottom surfaces of a continuous structure. A layer can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer, and may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer can include multiple layers.

[0041] Furthermore, in this application, the use of "connection" or "linkage" may indicate direct or indirect contact between the corresponding components, unless otherwise expressly defined or deduced from the context.

[0042] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. Furthermore, unless explicitly limited or contradicted by the context, the specific steps included in the methods described in this application are not limited to the order in which they are described, but can be performed in any order or in parallel. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0043] Figure 1 This is a flowchart of a method 1000 for manufacturing a semiconductor structure according to an exemplary embodiment of this application.

[0044] like Figure 1As shown, a method 1000 for manufacturing a semiconductor structure may include: S1100, forming a conductive structure within a storage region and extending along a second direction, and forming an isolation structure extending along the second direction through the storage region and a non-storage region, wherein the conductive structure is located at a first sidewall of a semiconductor pillar, and a portion of the isolation structure is located at a second sidewall of the semiconductor pillar opposite to the first sidewall; and S1200, forming an outgoing lead structure connected to the isolation structure in the non-storage region. Steps S1100 and S1200 will be described in detail below.

[0045] In the exemplary embodiments of this application, such as Figure 2 As shown, semiconductor layer 1100 may include a plurality of memory regions A and at least one non-memory region B. Both memory regions A and non-memory regions B may extend along a first direction Y and be arranged along a second direction X. Memory regions A may include a plurality of semiconductor pillars (not shown) extending along a third direction Z, wherein the first direction Y, the second direction X, and the third direction Z may be perpendicular to each other. Memory regions A may be used to form a memory array including a plurality of memory cells (including the conductive structure 1400 formed below), and non-memory regions B may be used to form wiring lead-out structures (including the lead-out structure 1800 formed below). Exemplarily, non-memory regions B may be located between two adjacent memory regions A or on one side of a plurality of memory regions A.

[0046] Although this application only exemplifies the location of non-memory area B between two adjacent memory areas A, it should be understood that this application does not specifically limit the location of non-memory area B. In actual processes, the location of non-memory area B can be reasonably set according to actual needs. For example, non-memory area B can also be set on one side of multiple memory areas A, and this application does not impose specific restrictions on this.

[0047] In the exemplary embodiments of this application, such as Figure 16 and Figure 17 (or Figure 34 and Figure 35 As shown, a conductive structure 1400 may be formed in the storage region A and extending along the second direction X, and an isolation structure 1500 may be formed extending along the second direction X through the storage region A and the non-storage region B. The conductive structure 1400 may be located at the first sidewall of the semiconductor pillar 1210, and a portion of the isolation structure 1500 may be located at the second sidewall of the semiconductor pillar 1210 opposite to the first sidewall.

[0048] In one exemplary embodiment of this application, such as Figures 2 to 17 The diagram shows a process step diagram for forming a conductive structure 1400 and an isolation structure 1500.

[0049] For example, such as Figure 2 As shown, a first dielectric layer 1110 and a second dielectric layer 1120 may be formed on the surface of the semiconductor layer 1100 in sequence.

[0050] The material of semiconductor layer 1100 may include at least one of monocrystalline silicon, polycrystalline silicon, monocrystalline germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, or other semiconductor materials known in the art. The material of first dielectric layer 1110 may include oxides such as silicon oxide. The material of second dielectric layer 1120 may include nitrides such as silicon nitride.

[0051] In one exemplary embodiment, the first dielectric layer 1110 and the second dielectric layer 1120 may be deposited using a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. In another exemplary embodiment, the first dielectric layer 1110 may be formed by oxidizing the surface of the semiconductor layer 1100 using an oxidation process, for example.

[0052] Figure 3 and Figure 4 This is a schematic diagram of the structure for forming the initial semiconductor pillar 1200 according to an exemplary embodiment of this application, wherein, Figure 4 for Figure 3 Cross-sectional view along the CC direction.

[0053] For example, such as Figure 3 and Figure 4 As shown, a plurality of initial semiconductor pillars 1200 extending along the first direction Y can be formed in the storage region A. For example, a plurality of first trenches 100 extending along the first direction Y can be formed in the storage region A, and a second trench 200 extending along the first direction Y can be formed in the non-storage region B, wherein the width of the second trench 200 may be greater than the width of the first trench 100; and a filling dielectric layer 1130 can be formed in the first trench 100 and the second trench 200, wherein the semiconductor layer 1100 that has not been removed in the storage region A forms the initial semiconductor pillars 1200.

[0054] For example, an etching process can be used to etch the second dielectric layer 1120, the first dielectric layer 1110, and the semiconductor layer 1100 to form the first trench 100, the second trench 200, and the initial semiconductor pillar 1200. For instance, a photolithography process can be used to etch the second dielectric layer 1120 and the first dielectric layer 1110 to form a patterned mask, wherein the second dielectric layer 1120 can serve as the bottom anti-reflection layer for photolithography, and the first dielectric layer 1110 can serve as a hard mask; then, using the patterned mask as a mask, the semiconductor layer 1100 is etched using one or more dry etching and / or wet etching processes to etch and form the first trench 100 and the second trench 200 in the semiconductor layer 1100, wherein the semiconductor layer 1100 that is not removed in the memory region A can form the initial semiconductor pillar 1200.

[0055] In this application, the initial semiconductor pillar 1200 can be formed by etching the semiconductor layer 1100. Therefore, the initial semiconductor pillar 1200 can have the same material as the semiconductor layer 1100, such as monocrystalline silicon. Furthermore, since the non-memory region B is mainly used to form the lead-out structure described below, the width of the second trench 200 can be greater than the width of the first trench 100 to provide more space for the subsequent formation of the lead-out structure.

[0056] For example, a filling dielectric layer 1130 can be deposited in the first trench 100 and the second trench 200 by a thin film deposition process, such as a thin film deposition process, so that adjacent initial semiconductor pillars 1200 are isolated by the filling dielectric layer 1130. In addition, a planarization process such as a mechanical polishing process can be performed to remove the filling dielectric layer 1130 from the surface of the second dielectric layer 1120.

[0057] In the exemplary embodiments of this application, such as Figures 5 to 12 As shown, a third trench 310 can be formed within the memory region A, passing through the initial semiconductor pillar 1200 and extending along the second direction X. Figure 11 or Figure 12 ), and form a fourth trench 400 extending along the second direction X through the initial semiconductor pillar 1200 and the non-memory region B. Figure 6 or Figure 7 The third trench 310 and the fourth trench 400 can divide the initial semiconductor pillar 1200 into multiple semiconductor pillars 1210, and the width of the third trench 310 can be greater than the width of the fourth trench 400.

[0058] Figure 6 and Figure 7 This is a schematic diagram of the structure forming the initial third trench 300, the fourth trench 400, and the semiconductor pillar 1210 according to an exemplary embodiment of this application, wherein, Figure 7 for Figure 6 Cross-sectional view along the DD direction.

[0059] For example, such as Figure 6 and Figure 7 As shown, an initial third trench 300 can be formed within memory region A, passing through the initial semiconductor pillar 1200 and extending along the second direction X, and a fourth trench 400 extending along the second direction X through the initial semiconductor pillar 1200 and outside memory region B can be formed. In other words, the initial third trench 300 can be formed within memory region A, passing through the initial semiconductor pillar 1200 and extending along the second direction X, meaning the initial third trench 300 can be located within memory region A. The fourth trench 400 extending along the second direction X through the initial semiconductor pillar 1200 and outside memory region B can be formed within memory region A and outside memory region B, meaning the fourth trench 400 can be located within both memory region A and outside memory region B.

[0060] For example, such as Figure 5 As shown, a patterned mask H can be formed on the surface of the filling dielectric layer 1130 and the second dielectric layer 1120. Using the patterned mask H as a mask, the filling dielectric layer 1130, the second dielectric layer 1120, the first dielectric layer 1110, and the semiconductor layer 1100 are etched to form an initial third trench 300 located in the memory region A and a fourth trench 400 extending through the memory region A and the non-memory region B. For example, one or more dry etching and / or wet etching processes can be used to etch and form the initial third trench 300 and the fourth trench 400. The initial third trench 300 and the fourth trench 400 can divide the initial semiconductor pillar 1200 into a plurality of semiconductor pillars 1210. In this application, the semiconductor pillars 1210 are formed by etching the semiconductor layer 1100; therefore, the semiconductor pillars 1210 can have the same material as the semiconductor layer 1100 and can extend in the semiconductor layer 1100 in a third direction Z.

[0061] In this application, by setting the initial third trench 300 and the fourth trench 400 to pass through the initial semiconductor pillar 1200, it is beneficial to divide the initial semiconductor pillar 1200 into multiple semiconductor pillars 1210. By setting the fourth trench 400 to extend through the memory region A and the non-memory region B, the isolation structure subsequently formed on the fourth trench 400 can extend through the memory region A and the non-memory region B. This allows the isolation structures of multiple memory regions A to be connected to the lead-out structure via the non-memory region B, which simplifies the circuit layout of memory region A and reduces the process difficulty of memory region A.

[0062] Figure 8 and Figure 9 This is a schematic diagram of the structure forming the first sacrificial layer 1310 and the second sacrificial layer 1320 according to an exemplary embodiment of this application, wherein, Figure 9 for Figure 8 Cross-sectional view along the DD direction.

[0063] For example, such as Figure 8 and Figure 9 As shown, a first sacrificial layer 1310 and a second sacrificial layer 1320 can be formed in the initial third trench 300 and the fourth trench 400, respectively. For example, the first sacrificial layer 1310 and the second sacrificial layer 1320 can be formed by depositing dielectric materials such as silicon oxide and carbon materials through one or more thin film deposition processes.

[0064] For example, such as Figure 10 As shown, a portion of the second sacrificial layer 1320 can be removed along a third direction Z, and a protective layer 1330 can be formed within the removed space. For example, a photolithography process, one or more dry etching and / or wet etching processes can be used to remove a portion of the second sacrificial layer 1320; then one or more thin film deposition processes can be used to form the protective layer 1330 within the removed space to cover and protect the remaining second sacrificial layer 1320. The material of the protective layer 1330 may include, but is not limited to, dielectric materials such as silicon nitride.

[0065] Figure 11 and Figure 12 This is a schematic diagram of the structure forming the third trench 310 according to an exemplary embodiment of this application, wherein, Figure 12 for Figure 11 Cross-sectional view along the DD direction.

[0066] For example, such as Figure 11 and Figure 12 As shown, the first sacrificial layer 1310 can be removed, and the width and depth of the initial third trench 300 can be increased to form the third trench 310. For example, the first sacrificial layer 1310 can be removed using photolithography, one or more dry etching and / or wet etching processes, etc. Exemplarily, during the removal of the first sacrificial layer 1310, the initial third trench 300 can be enlarged and deepened to form a third trench 310 with a width and depth greater than that of the initial third trench 300.

[0067] In the exemplary embodiments of this application, such as Figures 13 to 17 As shown, a conductive structure 1400 can be formed in the third trench 310, and an isolation structure 1500 can be formed in the fourth trench 400.

[0068] For example, such as Figure 13As shown, a first dielectric layer 1610 can be formed in the third trench 310; a portion of the first dielectric layer 1610 is removed along the third direction Z to form a first gap 500. For example, one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof, can be used to deposit and form the first dielectric layer 1610. The material of the first dielectric layer 1610 includes, but is not limited to, silicon oxide. Exemplarily, before forming the first dielectric layer 1610, a dielectric layer 1620 can be deposited on the sidewalls of the third trench 310 to partially fill the third trench 310. Exemplarily, a portion of the first dielectric layer 1610 can be removed along the third direction Z, such that the remaining first dielectric layer 1610 covers the bottom surface of the third trench 310.

[0069] For example, such as Figure 14 As shown, a gate dielectric layer 1630 can be formed on the sidewall of the first gap 500; a conductive layer 1410 is formed on the inner side of the gate dielectric layer 1630.

[0070] Exemplarily, the gate dielectric layer 1630 may be part of a continuous dielectric layer 1620 formed on the sidewall of a semiconductor pillar 1210 extending along the second direction X. The material of the gate dielectric layer 1630 may include, but is not limited to, oxides such as silicon oxide. Exemplarily, wet oxidation and / or dry oxidation processes, such as in-situ vapor oxidation processes, may be performed to form the gate dielectric layer 1630 on the sidewall of the third trench 310.

[0071] Then, a conductive layer 1410 may be formed inside the gate dielectric layer 1630 in the third trench 310. Exemplarily, the conductive layer 1410 may be formed by depositing one or more conductive materials, such as metals and / or metal compounds, such as tungsten W and titanium nitride TiN, inside the gate dielectric layer 1630 using one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. For example, TiN and W may be deposited sequentially to form the conductive layer 1410. Exemplarily, a planarization process, such as a chemical mechanical polishing process, may be performed to remove excess conductive material from the surface of the second dielectric layer 1120.

[0072] For example, such as Figure 15 As shown, a portion of the conductive layer 1410 can be removed along the third direction Z to form a second gap (not shown); a third gap (not shown) is formed along the third direction Z through the conductive layer 1410 to expose the first dielectric layer 1610, wherein the conductive layer 1410 that was not removed forms a conductive structure 1400; and a second dielectric layer 1640 is formed within the second gap and the third gap.

[0073] For example, a reverse etching process can be used to remove a portion of the conductive layer 1410 along the third direction Z, such that the upper end of the conductive layer 1410 is below the top surface of the semiconductor pillar 1210. Furthermore, since the gate dielectric layer 1630 is not etched back, the upper end of the conductive layer 1410 is below the upper end of the gate dielectric layer 1630. Thus, the etched-back conductive layer 1410 can extend along the second direction X, and the portion corresponding to the semiconductor pillar 1210 can serve as a gate electrode, forming a gate structure together with the corresponding gate dielectric layer 1630; the remaining portion can serve as a connection between the gate structure and the contact structure 1700 (…). Figure 36 or Figure 37 () Connecting word lines.

[0074] For example, etching processes such as bottom-down etching, dry etching, and / or wet etching can be used to form the third gap to form two disconnected conductive structures 1400 in the third trench 310. For example, a bottom-down etching process can be used to disconnect the conductive structure 1400 at the bottom of the third trench 310 until the first dielectric layer 1610 is exposed.

[0075] Exemplarily, one or more thin-film deposition processes may be used to deposit and form the second dielectric layer 1640 within the second and third gaps. In other words, the second dielectric layer 1640 may be deposited and formed in the remaining space of the third trench 310. The material of the second dielectric layer 1640 includes, but is not limited to, silicon oxide.

[0076] For example, such as Figure 16 As shown, vias 700 can be formed along a third direction Z through the gate dielectric layer 1630 and the conductive structure 1400 to separate the annular gate dielectric layer 1630 and the conductive structure 1400 in the third trench 310 into at least two parts. For example, two vias 700 with a certain interval can be formed in each annular gate dielectric layer 1630 and conductive structure 1400 to separate the annular gate dielectric layer 1630 and the conductive structure 1400 into two parts. In other words, the two vias 700 separate the annular gate dielectric layer 1630 into two parts and the conductive structure 1400 into two parts.

[0077] It should be understood that this application does not specifically limit the size and / or location of the via 700. The size and / or location of the via 700 can be arbitrarily set according to the actual process to separate the gate dielectric layer 1630 and the conductive structure 1400 in the third trench 310 into two parts.

[0078] Figure 16 and Figure 17 This is a schematic diagram of the structure forming the isolation structure 1500 according to an exemplary embodiment of this application, wherein, Figure 17 for Figure 16Cross-sectional view along the DD direction.

[0079] For example, such as Figure 16 and Figure 17 As shown, the protective layer 1330 and the remaining second sacrificial layer 1320 can be removed to form a fourth gap 600; and an isolation structure 1500 is formed within the fourth gap 600. For example, the fourth gap 600 can be formed using photolithography, one or more dry etching and / or wet etching processes, and the isolation structure 1500 can be formed using one or more thin-film deposition processes. Exemplarily, the material of the isolation structure 1500 may include, but is not limited to, metallic materials such as tungsten and copper. Exemplarily, such as... Figure 17 As shown, a reverse etching process can be used to remove part of the isolation structure 1500 along the third direction Z, and fill the removed space with dielectric material.

[0080] In another exemplary embodiment of this application, such as Figures 18 to 35 The diagram shows a process step diagram for forming a conductive structure 1400 and an isolation structure 1500.

[0081] For example, such as Figure 18 As shown, a first dielectric layer 1110 and a second dielectric layer 1120 may be formed on the surface of the semiconductor layer 1100 in sequence.

[0082] The material of semiconductor layer 1100 may include at least one of monocrystalline silicon, polycrystalline silicon, monocrystalline germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, or other semiconductor materials known in the art. The material of first dielectric layer 1110 may include oxides such as silicon oxide. The material of second dielectric layer 1120 may include nitrides such as silicon nitride.

[0083] Figure 19 and Figure 20 This is a schematic diagram of the structure for forming the initial semiconductor pillar 1200 according to an exemplary embodiment of this application, wherein, Figure 20 for Figure 19 Cross-sectional view along the CC direction.

[0084] For example, such as Figure 19 and Figure 20 As shown, a plurality of initial semiconductor pillars 1200 extending along the first direction Y can be formed in the storage region A. For example, a plurality of first trenches 100 extending along the first direction Y can be formed in the storage region A, and a second trench 200 extending along the first direction Y can be formed in the non-storage region B, wherein the width of the second trench 200 may be greater than the width of the first trench 100; and a filling dielectric layer 1130 can be formed in the first trench 100 and the second trench 200, wherein the semiconductor layer 1100 that has not been removed in the storage region A forms the initial semiconductor pillars 1200.

[0085] In the exemplary embodiments of this application, such as Figures 21 to 28 As shown, a third trench 310 can be formed, which is alternately arranged along the first direction Y and extends along the second direction X through the initial semiconductor pillar 1200 and the non-memory region B. Figure 27 or Figure 28 ) and the fourth trench 400 ( Figure 22 or Figure 23 The third trench 310 and the fourth trench 400 can divide the initial semiconductor pillar 1200 into multiple semiconductor pillars 1210, and the width of the third trench 310 can be greater than the width of the fourth trench 400.

[0086] Figure 22 and Figure 23 This is a schematic diagram of the structure forming the initial third trench 300, the fourth trench 400, and the semiconductor pillar 1210 according to an exemplary embodiment of this application, wherein, Figure 23 for Figure 22 Cross-sectional view along the DD direction.

[0087] For example, such as Figure 22 and Figure 23 As shown, initial third trenches 300 and fourth trenches 400, alternating along the first direction Y and extending along the second direction X through the initial semiconductor pillar 1200 and the non-memory region B, can be formed. In other words, initial third trenches 300 and fourth trenches 400 extending along the second direction X through the initial semiconductor pillar 1200 and the non-memory region B can be formed within the memory region A and the non-memory region B, meaning that both initial third trenches 300 and fourth trenches 400 can pass through the memory region A and the non-memory region B.

[0088] For example, such as Figure 21 As shown, a patterned mask H can be formed on the surface of the filling dielectric layer 1130 and the second dielectric layer 1120. Using the patterned mask H as a mask, the filling dielectric layer 1130, the second dielectric layer 1120, the first dielectric layer 1110, and the semiconductor layer 1100 are etched to form initial third trenches 300 and fourth trenches 400, which are alternately arranged along the first direction Y and extend along the second direction X through the initial semiconductor pillar 1200 and the non-memory region B. For example, the initial third trenches 300 and fourth trenches 400 can be formed by etching using one or more dry etching and / or wet etching processes. The initial third trenches 300 and fourth trenches 400 can divide the initial semiconductor pillar 1200 into a plurality of semiconductor pillars 1210. In this application, the semiconductor pillars 1210 are formed by etching the semiconductor layer 1100; therefore, the semiconductor pillars 1210 can have the same material as the semiconductor layer 1100 and can extend along the third direction Z in the semiconductor layer 1100.

[0089] Figure 24 and Figure 25This is a schematic diagram of the structure forming the first sacrificial layer 1310 and the second sacrificial layer 1320 according to an exemplary embodiment of this application, wherein, Figure 25 for Figure 24 Cross-sectional view along the DD direction.

[0090] For example, such as Figure 24 and Figure 25 As shown, a first sacrificial layer 1310 and a second sacrificial layer 1320 can be formed in the initial third trench 300 and the fourth trench 400, respectively. For example, the first sacrificial layer 1310 and the second sacrificial layer 1320 can be formed by depositing dielectric materials such as silicon oxide and carbon materials through one or more thin film deposition processes.

[0091] For example, such as Figure 26 As shown, a portion of the second sacrificial layer 1320 can be removed along a third direction Z, and a protective layer 1330 can be formed within the removed space. For example, a photolithography process, one or more dry etching and / or wet etching processes can be used to remove a portion of the second sacrificial layer 1320; then one or more thin film deposition processes can be used to form the protective layer 1330 within the removed space to cover and protect the remaining second sacrificial layer 1320. The material of the protective layer 1330 may include, but is not limited to, dielectric materials such as silicon nitride.

[0092] Figure 27 and Figure 28 This is a schematic diagram of the structure forming the third trench 310 according to an exemplary embodiment of this application, wherein, Figure 28 for Figure 27 Cross-sectional view along the DD direction.

[0093] For example, such as Figure 27 and Figure 28 As shown, the first sacrificial layer 1310 can be removed, and the width and depth of the initial third trench 300 can be increased to form the third trench 310. For example, the first sacrificial layer 1310 can be removed using photolithography, one or more dry etching and / or wet etching processes, etc. Exemplarily, during the removal of the first sacrificial layer 1310, the initial third trench 300 can be enlarged and deepened to form a third trench 310 with a width and depth greater than that of the initial third trench 300.

[0094] In the exemplary embodiments of this application, such as Figures 29 to 33 As shown, an initial conductive structure 1420 can be formed in the third trench 310, and an isolation structure 1500 can be formed in the fourth trench 400.

[0095] For example, such as Figure 29As shown, a first dielectric layer 1610 can be formed in the third trench 310; a portion of the first dielectric layer 1610 is removed along the third direction Z to form a first gap 500. For example, one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof, can be used to deposit and form the first dielectric layer 1610. The material of the first dielectric layer 1610 includes, but is not limited to, silicon oxide. Exemplarily, before forming the first dielectric layer 1610, a dielectric layer 1620 can be deposited on the sidewalls of the third trench 310 to partially fill the third trench 310. Exemplarily, a portion of the first dielectric layer 1610 can be removed along the third direction Z, such that the remaining first dielectric layer 1610 covers the bottom surface of the third trench 310.

[0096] For example, such as Figure 30 As shown, a gate dielectric layer 1630 can be formed on the sidewall of the first gap 500; a conductive layer 1410 is formed on the inner side of the gate dielectric layer 1630.

[0097] Exemplarily, the gate dielectric layer 1630 may be part of a continuous dielectric layer 1620 formed on the sidewall of a semiconductor pillar 1210 extending along the second direction X. The material of the gate dielectric layer 1630 may include, but is not limited to, oxides such as silicon oxide. Exemplarily, wet oxidation and / or dry oxidation processes, such as in-situ vapor oxidation processes, may be performed to form the gate dielectric layer 1630 on the sidewall of the third trench 310.

[0098] Then, a conductive layer 1410 may be formed inside the gate dielectric layer 1630 in the third trench 310. Exemplarily, the conductive layer 1410 may be formed by depositing one or more conductive materials, such as metals and / or metal compounds, such as tungsten W and titanium nitride TiN, inside the gate dielectric layer 1630 using one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. For example, TiN and W may be deposited sequentially to form the conductive layer 1410. Exemplarily, a planarization process, such as a chemical mechanical polishing process, may be performed to remove excess conductive material from the surface of the second dielectric layer 1120.

[0099] For example, such as Figure 31 As shown, a portion of the conductive layer 1410 can be removed along the third direction Z to form a second gap (not shown); a third gap (not shown) is formed along the third direction Z through the conductive layer 1410 to expose the first dielectric layer 1610, wherein the conductive layer 1410 that was not removed forms an initial conductive structure 1420; and a second dielectric layer 1640 is formed within the second gap and the third gap.

[0100] For example, a reverse etching process can be used to remove a portion of the conductive layer 1410 along the third direction Z, such that the upper end of the conductive layer 1410 is below the top surface of the semiconductor pillar 1210. Furthermore, since the gate dielectric layer 1630 is not etched back, the upper end of the conductive layer 1410 is below the upper end of the gate dielectric layer 1630. Thus, the etched-back conductive layer 1410 can extend along the second direction X, and the portion corresponding to the semiconductor pillar 1210 can serve as a gate electrode, forming a gate structure together with the corresponding gate dielectric layer 1630; the remaining portion can serve as a connection between the gate structure and the contact structure 1700 (…). Figure 36 or Figure 37 () Connecting word lines.

[0101] Exemplarily, etching processes such as bottom-drilling etching, dry etching, and / or wet etching can be used to form the third gap to create two disconnected initial conductive structures 1420 in the third trench 310. Exemplarily, a bottom-drilling etching process can be used to disconnect the initial conductive structures 1420 at the bottom of the third trench 310 until the first dielectric layer 1610 is exposed. Exemplarily, one or more thin-film deposition processes can be used to deposit and form the second dielectric layer 1640 within the second and third gaps. In other words, the second dielectric layer 1640 can be deposited and formed in the remaining space of the third trench 310. The material of the second dielectric layer 1640 includes, but is not limited to, silicon oxide.

[0102] Figure 32 and Figure 33 This is a schematic diagram of the structure forming the isolation structure 1500 according to an exemplary embodiment of this application, wherein, Figure 33 for Figure 32 Cross-sectional view along the DD direction.

[0103] For example, such as Figure 32 and Figure 33 As shown, the protective layer 1330 and the remaining second sacrificial layer 1320 can be removed to form a fourth gap 600; and an isolation structure 1500 is formed within the fourth gap 600. For example, the fourth gap 600 can be formed using photolithography, one or more dry etching and / or wet etching processes, and the isolation structure 1500 can be formed using one or more thin-film deposition processes. Exemplarily, the material of the isolation structure 1500 may include, but is not limited to, metallic materials such as tungsten and copper. Exemplarily, such as... Figure 33 As shown, a reverse etching process can be used to remove part of the isolation structure 1500 along the third direction Z, and fill the removed space with dielectric material.

[0104] For example, such as Figure 32As shown, vias 700 can be formed along a third direction Z through the gate dielectric layer 1630 and the initial conductive structure 1420 to separate the annular gate dielectric layer 1630 and the initial conductive structure 1420 in the third trench 310 into at least two parts. For example, two vias 700 with a certain interval can be formed in each annular gate dielectric layer 1630 and the initial conductive structure 1420 to separate the annular gate dielectric layer 1630 and the initial conductive structure 1420 into two parts. In other words, the two vias 700 separate the annular gate dielectric layer 1630 into two parts and the initial conductive structure 1420 into two parts.

[0105] It should be understood that this application does not specifically limit the size and / or location of the via 700. The size and / or location of the via 700 can be arbitrarily set according to the actual process to separate the gate dielectric layer 1630 and the initial conductive structure 1420 in the third trench 310 into two parts.

[0106] Figure 34 and Figure 35 This is a schematic diagram of the structure forming the conductive structure 1400 according to an exemplary embodiment of this application, wherein, Figure 35 for Figure 34 Cross-sectional view along the DD direction.

[0107] For example, such as Figure 34 and Figure 35 As shown, at least a portion of the initial conductive structure 1420 located in the non-storage region B can be removed to form a conductive structure 1400. In other words, the non-storage region B may not have a conductive structure 1400, or the conductive structure 1400 of the non-storage region B may be discontinuous.

[0108] Figure 36 and Figure 37 These are schematic diagrams of two structures forming the contact structure 1700 according to exemplary embodiments of this application. It should be understood that in this application, Figure 36 or Figure 37 The contact structure 1700 shown can be in Figure 17 or Figure 35 It is formed based on the semiconductor structure shown.

[0109] In the exemplary embodiments of this application, such as Figure 36 or Figure 37 As shown, the isolation structure 1500 may include a first isolation structure 1510 located at the second sidewall of the semiconductor pillar 1210 and a second isolation structure (not shown) located in the non-memory region B.

[0110] The contact structure 1700 formed to connect with the conductive structure 1400 may include: a first isolation structure 1510 etched back along a third direction Z, and a third dielectric layer 1650 formed within the etched space; and the contact structure 1700 formed on the side of the conductive structure 1400 corresponding to the third dielectric layer 1650. In an exemplary embodiment of this application, as... Figure 36 As shown, a contact structure 1700 can be formed that connects to one end of the conductive structure 1400 away from the first dielectric layer 1610. In another exemplary embodiment of this application, as Figure 37 As shown, a contact structure 1700 can be formed that is connected to one end of the conductive structure 1400 near the first dielectric layer 1610.

[0111] This application connects the contact structure 1700 to the conductive structure 1400, enabling the connection between the word line (the portion of the conductive structure 1400 extending along the second direction X) and the contact structure 1700. This facilitates the transmission of electrical signals between the gate structure and the peripheral circuitry via the contact structure 1700 and the word line. Furthermore, this application reduces the electrical connection between the contact structure 1700 and the first isolation structure 1510 by etching back the first isolation structure 1510.

[0112] For example, the contact structure 1700 may be formed by a combination of one or more dry etching and / or wet etching processes, and one or more thin film deposition processes. The material of the contact structure 1700 may include, but is not limited to, metallic materials such as tungsten and copper.

[0113] Figure 38 and Figure 39 These are schematic diagrams illustrating two structures forming the lead-out structure 1800 according to exemplary embodiments of this application. It should be understood that in this application, Figure 38 or Figure 39 The lead-out structure 1800 shown can be in Figure 36 or Figure 37 It is formed based on the semiconductor structure shown.

[0114] In the exemplary embodiments of this application, such as Figure 38 or Figure 39 As shown, an outgoing structure 1800 connected to the isolation structure 1500 can be formed in the non-memory area B.

[0115] For example, the isolation structure 1500 may include a first isolation structure 1510 located at the second sidewall of the semiconductor pillar 1210 and a second isolation structure 1520 located in the non-memory region B. A lead-out structure 1800 connected to the isolation structure 1500 may be formed in the non-memory region B, and may include: a lead-out structure 1800 connected to the second isolation structure 1520 formed in the non-memory region B.

[0116] In one exemplary embodiment of this application, such as Figure 38 As shown, forming an exit structure 1800 connected to the isolation structure 1500 in the non-memory area B may include: forming an exit hole 1810 in the non-memory area B extending along the third direction Z to the second isolation structure 1520; and forming the exit structure 1800 within the exit hole 1810.

[0117] Exemplarily, a dielectric layer may be formed on the surface of the non-storage area B, and a plurality of lead-out holes 1810 extending along a third direction Z to the second isolation structure 1520 may be formed in the dielectric layer, wherein the plurality of lead-out holes 1810 may be arranged along a first direction Y. Then, conductive material may be filled into the lead-out holes 1810 to form lead-out structures 1800. Exemplarily, the lead-out structures 1800 and the contact structures 1700 may be located on the same side of the conductive structure 1400; of course, the lead-out structures 1800 and the contact structures 1700 may also be located on opposite sides of the conductive structure 1400.

[0118] For example, a dielectric layer can be formed on the surface of the non-storage region B by one or more thin-film deposition processes. The via 1810 can be formed by one or more dry etching and / or wet etching processes.

[0119] In another exemplary embodiment of this application, such as Figure 39 As shown, forming an exit structure 1800 connected to the isolation structure 1500 in the non-memory area B may include: forming an exit groove 1820 in the non-memory area B that extends along a third direction Z to the second isolation structure 1520 and along a first direction Y; and forming the exit structure 1800 within the exit groove 1820.

[0120] For example, a dielectric layer may be formed on the surface of the non-storage area B, and an exit groove 1820 extending in the dielectric layer along a third direction Z to the second isolation structure 1520 and extending in a first direction Y may be formed. Then, a conductive material may be filled into the exit groove 1820 to form an exit structure 1800. For example, the exit structure 1800 and the contact structure 1700 may be located on the same side of the conductive structure 1400; of course, the exit structure 1800 and the contact structure 1700 may also be located on opposite sides of the conductive structure 1400.

[0121] For example, a dielectric layer can be formed on the surface of the non-storage region B by one or more thin-film deposition processes. The lead-out groove 1820 can be formed by one or more dry etching and / or wet etching processes.

[0122] In this application, the lead-out structure 1800 can be grounded or a fixed potential can be applied to the lead-out structure 1800. Multiple isolation structures 1500 of the memory regions can be connected together and connected to the lead-out structure 1800 of the non-memory region B. This allows the isolation structure 1500 to electrically insulate adjacent semiconductor pillars 1210, reducing coupling between adjacent semiconductor pillars 1210. Furthermore, this arrangement can reduce the number of lead-out structures 1800, reduce the lead-out space of the isolation structure 1500, and lower the difficulty of leading out the isolation structure 1500.

[0123] As described above, this application provides two processes for forming the conductive structure 1400 and the isolation structure 1500, two processes for forming the contact structure 1700, and two processes for forming the lead-out structure 1800. Specifically, Figures 2 to 17 A process for forming the conductive structure 1400 and the insulating structure 1500 is shown. Figures 18 to 35 Another process for forming the conductive structure 1400 and the isolation structure 1500 is shown; Figure 36 and Figure 37 Two processes for forming the contact structure 1700 are shown respectively; and Figure 38 and Figure 39 Two processes for forming the lead-out structure 1800 are shown respectively.

[0124] It should be understood that in the method 1000 for manufacturing a semiconductor structure provided in this application, the processes for forming the conductive structure 1400 and the isolation structure 1500, the process for forming the contact structure 1700, and the process for forming the lead-out structure 1800 can be combined with each other. That is, this application provides at least eight exemplary embodiments above to introduce the method 1000 for manufacturing a semiconductor structure.

[0125] Figure 38 and Figure 39 These are schematic diagrams of semiconductor structures according to exemplary embodiments of this application.

[0126] The semiconductor structure may include a semiconductor layer 1100 ( Figure 37 ), conductive structure 1400, isolation structure 1500 and lead-out structure 1800.

[0127] Semiconductor layer 1100 may include a plurality of memory regions A and at least one non-memory region B. Both memory regions A and non-memory regions B may extend along a first direction Y and be arranged along a second direction X. Memory regions A may include a plurality of semiconductor pillars 1210 extending along a third direction Z, wherein the first direction Y, the second direction X, and the third direction Z may be perpendicular to each other. Memory regions A may be used to form a memory array (including conductive structure 1400) comprising a plurality of memory cells, and non-memory regions B may be used to form wiring lead-out structures (including lead-out structures 1800). Exemplarily, non-memory regions B may be located between two adjacent memory regions A or on one side of a plurality of memory regions A.

[0128] Although this application only exemplifies the location of non-memory area B between two adjacent memory areas A, it should be understood that this application does not specifically limit the location of non-memory area B. In actual processes, the location of non-memory area B can be reasonably set according to actual needs. For example, non-memory area B can also be set on one side of multiple memory areas A, and this application does not impose specific restrictions on this.

[0129] Semiconductor pillar 1210 may have the same material as semiconductor layer 1100 and may extend in semiconductor layer 1100 in a third direction Z. Conductive structure 1400 may be located at a first sidewall of semiconductor pillar 1210 and extend in storage region A in a second direction X.

[0130] Exemplarily, the semiconductor structure further includes a gate dielectric layer 1630 located between the conductive structure 1400 and the semiconductor pillar 1210. The conductive structure 1400 may include a first conductive layer located inside the gate dielectric layer 1630 and a second conductive layer located inside the first conductive layer. The material of the first conductive layer may include, but is not limited to, titanium nitride (TiN). The material of the second conductive layer may include, but is not limited to, tungsten (W). The material of the gate dielectric layer 1630 may include, but is not limited to, oxides such as silicon oxide. The portion of the conductive structure 1400 corresponding to the semiconductor pillar 1210 may serve as a gate electrode. The conductive structure 1400 and the corresponding gate dielectric layer 1630 may together constitute a gate structure.

[0131] The isolation structure 1500 may extend along a second direction X through the memory region A and the non-memory region B, and a portion of the isolation structure 1500 is located at the second sidewall of the semiconductor pillar 1210 opposite to the first sidewall. The material of the isolation structure 1500 may include, but is not limited to, metallic materials such as tungsten and copper. Exemplarily, the isolation structure 1500 may include a first isolation structure 1510 located at the second sidewall of the semiconductor pillar 1210 and a second isolation structure 1520 located in the non-memory region B.

[0132] Exemplarily, the semiconductor structure may further include a third dielectric layer 1650 and a contact structure 1700. The third dielectric layer 1650 may be located on one side of the isolation structure 1500 and connected to the isolation structure 1500. The contact structure 1700 may be located on the side of the conductive structure 1400 corresponding to the third dielectric layer 1650 and connected to the conductive structure 1400. Exemplarily, the third dielectric layer 1650 may be located on one side of the first isolation structure 1510 and connected to the first isolation structure 1510.

[0133] This application connects the contact structure 1700 to the conductive structure 1400, enabling the connection between the word line (the portion of the conductive structure 1400 extending along the second direction X) and the contact structure 1700. This facilitates the transmission of electrical signals between the gate structure and the peripheral circuitry via the contact structure 1700 and the word line. Furthermore, by providing a third dielectric layer 1650, this application reduces the electrical connection between the contact structure 1700 and the first isolation structure 1510.

[0134] The lead-out structure 1800 can be disposed in the non-memory area B and connected to the isolation structure 1500. In an exemplary embodiment of this application, as... Figure 38 As shown, the lead-out structure 1800 can have multiple sub-lead-out structures. Each sub-lead-out structure can be connected to the isolation structure 1500 and is arranged along the first direction Y. In another exemplary embodiment of this application, as Figure 39 As shown, the lead-out structure 1800 may extend along a first direction Y. Exemplarily, the lead-out structure 1800 may be connected to the second isolation structure 1520. Exemplarily, the lead-out structure 1800 and the contact structure 1700 may be located on the same side of the conductive structure 1400; of course, the lead-out structure 1800 and the contact structure 1700 may also be located on opposite sides of the conductive structure 1400.

[0135] In this application, the lead-out structure 1800 can be grounded or a fixed potential can be applied to the lead-out structure 1800. Multiple isolation structures 1500 of the memory regions can be connected together and connected to the lead-out structure 1800 of the non-memory region B. This allows the isolation structure 1500 to electrically insulate adjacent semiconductor pillars 1210, reducing coupling between adjacent semiconductor pillars 1210. Furthermore, this arrangement can reduce the number of lead-out structures 1800, reduce the lead-out space of the isolation structure 1500, and lower the difficulty of leading out the isolation structure 1500.

[0136] For example, the semiconductor structure may further include a second dielectric layer 1640 located inside the second conductive layer. Figure 35 The material of the second dielectric layer 1640 may include, but is not limited to, silicon oxide. The second dielectric layer 1640 may be used to isolate adjacent conductive structures 1400.

[0137] Exemplarily, the semiconductor structure may further include a source and a drain respectively disposed at both ends of the semiconductor pillar 1210. Exemplarily, the source and drain at both ends of the semiconductor pillar 1210 may be connected to a capacitor and a bit line respectively. Exemplarily, the capacitor may be coupled to the drain of the semiconductor pillar 1210 to be charged or discharged through the drain. The bit line may be coupled to the source region of the semiconductor pillar 1210 and serves as a path for charging or discharging the capacitor. The word line (the portion of the conductive structure 1400 extending along the second direction X) may be coupled to the gate electrode (the portion of the conductive structure 1400 corresponding to the semiconductor pillar 1210) to turn on or off the transistor (including the semiconductor pillar 1210, the conductive structure 1400, and the portion of the gate dielectric layer 1630 corresponding to the semiconductor pillar).

[0138] Since the content and structure described above in the method 1000 for manufacturing a semiconductor structure can be applied in whole or in part to the semiconductor structure described herein, related or similar content will not be repeated here.

[0139] Although exemplary structures and fabrication methods of semiconductor structures have been described herein, it is understood that one or more features may be omitted, substituted, or added from the fabrication methods of the semiconductor structure. Furthermore, the layers and materials described are merely exemplary.

[0140] Figure 40 This is a block diagram of a system 10 having a storage system 12 according to an exemplary embodiment of this application.

[0141] System 10 can be a mobile phone, desktop computer, laptop, tablet computer, in-vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device (which has a storage system 12 located therein). Figure 40 As shown, system 10 may include a host 18 and a storage system 12, the storage system 12 having one or more three-dimensional memories 14 and a controller 16. The host 18 may be a processor of an electronic device, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). The host 18 may be configured to send or receive data to and from the three-dimensional memories 14.

[0142] The three-dimensional memory 14 may include the semiconductor structure described in any embodiment of this application. According to some embodiments, a controller 16 is coupled to the three-dimensional memory 14 and the host 18 and is configured to control the three-dimensional memory 14. The controller 16 may manage data stored in the three-dimensional memory 14 and communicate with the host 18. In some embodiments, the controller 16 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, the controller 16 is designed to operate in a high duty cycle environment, such as an SSD or embedded multi-media card (eMMC) used as a data storage device in a mobile device, such as a smartphone, tablet, laptop, etc. The controller 16 may be configured to control the operation of the three-dimensional memory 14, such as read, erase, and program operations. The controller 16 may also be configured to manage various functions related to data stored in or to be stored in the 3D memory 14, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the controller 16 is further configured to process error correction codes (ECCs) related to data read from or written to the 3D memory 14. The controller 16 may also perform any other appropriate functions, such as formatting the 3D memory 14. The controller 16 may communicate with external devices (e.g., the host 18) according to a specific communication protocol. For example, the controller 16 may communicate with external devices via at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronic Devices (IDE), Firewire, etc.

[0143] The controller 16 and one or more three-dimensional memories 14 can be integrated into various types of memory systems, for example, included in the same package (such as a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system 12 can be implemented and packaged into different types of end electronic products. Figure 41AIn one example shown, the controller 16 and a single three-dimensional memory 14 may be integrated into a memory card 22. The memory card 22 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 22 may further include a connection between the memory card 22 and a host computer (e.g., Figure 40 The host 18) is coupled to the memory card connector 24. In such a way... Figure 41B In another example shown, the controller 16 and multiple 3D memories 14 may be integrated into the SSD 26. The SSD 26 may further include a connection between the SSD 26 and a host (e.g., Figure 40 The SSD connector 28 is coupled to the host 18. In some embodiments, the storage capacity and / or operating speed of the SSD 26 is higher than that of the memory card 22.

[0144] The above description is merely a preferred embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of disclosure in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the inventive concept. For example, technical solutions formed by substituting the above-described features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A method of fabricating a semiconductor structure, characterized by, The semiconductor layer includes multiple memory regions and at least one non-memory region, both extending along a first direction and arranged along a second direction. Each memory region includes multiple semiconductor pillars extending along a third direction, wherein the first direction, the second direction, and the third direction are mutually perpendicular. The method includes: A conductive structure is formed within the storage region and extending along the second direction, and an isolation structure is formed extending along the second direction through the storage region and the non-storage region, wherein the conductive structure is located at a first sidewall of the semiconductor pillar, and a portion of the isolation structure is located at a second sidewall of the semiconductor pillar opposite to the first sidewall; and An outgoing structure connected to the isolation structure is formed in the non-storage area.

2. The method of claim 1, wherein, A conductive structure formed within the storage area and extending along the second direction, and an isolation structure extending along the second direction through the storage area and the non-storage area, comprising: A plurality of initial semiconductor pillars extending along the first direction are formed in the storage region; A third trench is formed within the memory region, passing through the initial semiconductor pillar and extending along the second direction, and a fourth trench is formed extending along the second direction through the initial semiconductor pillar and the non-memory region, wherein the third trench and the fourth trench divide the initial semiconductor pillar into a plurality of semiconductor pillars, and the width of the third trench is greater than the width of the fourth trench; and The conductive structure is formed in the third trench, and the isolation structure is formed in the fourth trench.

3. The method according to claim 1, characterized in that, A conductive structure extending in the second direction within the storage area is formed, and an isolation structure extending in the second direction through the storage area and the non-storage area is formed, comprising: A plurality of initial semiconductor pillars extending along the first direction are formed in the storage region; A third trench and a fourth trench are formed, which are alternately arranged along the first direction and extend through the initial semiconductor pillar and the non-memory area along the second direction, wherein the third trench and the fourth trench divide the initial semiconductor pillar into a plurality of semiconductor pillars, and the width of the third trench is greater than the width of the fourth trench. An initial conductive structure is formed in the third trench, and the isolation structure is formed in the fourth trench; and At least a portion of the initial conductive structure located in the non-storage area is removed to form the conductive structure.

4. The method according to claim 2 or 3, characterized in that, Forming a plurality of initial semiconductor pillars extending along the first direction in the storage region includes: A plurality of first trenches extending along the first direction are formed in the storage area, and a second trench extending along the first direction is formed in the non-storage area, wherein the width of the second trench is greater than the width of the first trench; and A filling dielectric layer is formed in the first trench and the second trench, wherein the semiconductor layer that has not been removed in the storage region forms an initial semiconductor pillar.

5. The method according to claim 2, characterized in that, A third trench is formed within the memory region, passing through the initial semiconductor pillar and extending along the second direction, and a fourth trench is formed extending along the second direction through the initial semiconductor pillar and the non-memory region, comprising: An initial third trench is formed within the storage region, passing through the initial semiconductor pillar and extending along the second direction, and a fourth trench is formed extending along the second direction through the initial semiconductor pillar and the non-storage region; A first sacrificial layer and a second sacrificial layer are formed in the initial third trench and the fourth trench, respectively; Removing a portion of the second sacrificial layer along a third direction, and forming a protective layer within the removed space; and The first sacrificial layer is removed, and the width and depth of the initial third trench are increased to form the third trench.

6. The method according to claim 5, characterized in that, The conductive structure is formed in the third trench, and the isolation structure is formed in the fourth trench, including: A first dielectric layer is formed in the third trench; A portion of the first dielectric layer is removed along the third direction to form a first gap; A gate dielectric layer is formed on the sidewall of the first gap; A conductive layer is formed inside the gate dielectric layer; A portion of the conductive layer is removed along the third direction to form a second gap; A third gap is formed along the third direction through the conductive layer to expose the first dielectric layer, wherein the conductive layer that is not removed forms the conductive structure; A second dielectric layer is formed within the second gap and the third gap; Remove the protective layer and the remaining second sacrificial layer to form a fourth gap; and The isolation structure is formed within the fourth gap.

7. The method according to claim 1, characterized in that, The method further includes: A contact structure is formed that is connected to the conductive structure.

8. The method according to claim 7, characterized in that, The isolation structure includes a first isolation structure located at the second sidewall of the semiconductor pillar and a second isolation structure located in the non-memory region, forming a contact structure connected to the conductive structure, including: The first isolation structure is etched back along the third direction, and a third dielectric layer is formed within the etched space; and The contact structure is formed on the side of the conductive structure corresponding to the third dielectric layer.

9. The method according to claim 1, characterized in that, An outgoing structure connected to the isolation structure is formed in the non-memory area, including: An outlet hole extending along the third direction to the isolation structure is formed in the non-storage area; and An outlet structure is formed within the outlet hole.

10. The method according to claim 1, characterized in that, An outgoing structure connected to the isolation structure is formed in the non-memory area, including: An exit groove is formed in the non-storage area, extending along the third direction to the isolation structure and extending along the first direction; and An outgoing structure is formed within the outgoing groove.

11. A semiconductor structure, characterized in that, include: A semiconductor layer includes multiple memory regions and at least one non-memory region, wherein the memory regions and the non-memory regions both extend along a first direction and are arranged along a second direction, and the memory regions include multiple semiconductor pillars extending along a third direction, wherein the first direction, the second direction and the third direction are perpendicular to each other; A conductive structure is located at the first sidewall of the semiconductor pillar and extends along the second direction within the storage region; An isolation structure extends along the second direction through the memory region and the non-memory region, and a portion of the isolation structure is located at the second sidewall of the semiconductor pillar, opposite to the first sidewall; as well as An outgoing structure is provided in the non-storage area and connected to the isolation structure.

12. The semiconductor structure according to claim 11, characterized in that, The semiconductor structure also includes: A gate dielectric layer is located between the conductive structure and the semiconductor pillar, wherein the conductive structure includes a first conductive layer located inside the gate dielectric layer and a second conductive layer located inside the first conductive layer; and The second dielectric layer is located inside the second conductive layer.

13. The semiconductor structure according to claim 11, characterized in that, The isolation structure is made of metal, and the semiconductor structure further includes: A third dielectric layer is located on one side of the isolation structure and is connected to the isolation structure.

14. The semiconductor structure according to claim 13, characterized in that, The semiconductor structure also includes: A contact structure is located on the side of the conductive structure corresponding to the third dielectric layer and is connected to the conductive structure.

15. The semiconductor structure according to claim 11, characterized in that, The lead-out structure includes: Multiple sub-lead-out structures are connected to the isolation structure and arranged along the first direction.

16. The semiconductor structure according to claim 11, characterized in that, The lead-out structure extends along the first direction.

17. The semiconductor structure according to claim 11, characterized in that, The semiconductor structure also includes a source and a drain respectively disposed at both ends of the semiconductor pillar.

18. A storage system, characterized in that, include: At least one three-dimensional memory, each of the three-dimensional memory comprising a semiconductor structure as described in any one of claims 11 to 17; as well as A controller, coupled to the semiconductor structure, is used to control the storage of data in the three-dimensional memory.

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