Semiconductor device and manufacturing method thereof, electronic device

Abstract

A semiconductor device, a manufacturing method thereof, and an electronic device, the semiconductor device comprising: a plurality of memory cells stacked along a vertical substrate direction; the memory cell comprising a transistor and a capacitor, a plurality of transistors of the plurality of memory cells being distributed in different layers stacked along the vertical substrate direction; a word line extending along the vertical substrate direction through the different layers; the transistor comprising a first electrode, a second electrode, and a semiconductor layer surrounding a sidewall of the word line; the capacitor comprising a first pole and a second pole, the first pole being connected to the first electrode; a plurality of first poles of a plurality of capacitors of the plurality of memory cells being distributed in different layers stacked along the vertical substrate direction; the semiconductor device further comprising: at least one first via hole through the first pole of the different layers, the second pole comprising a vertical portion extending along a direction perpendicular to the substrate direction and arranged in the first via hole. The scheme provided by the embodiment is that the second pole of the capacitor is arranged in the hole of the first pole, which is conducive to reducing the device area, increasing the device density, simplifying the process, and reducing the cost.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, device design and manufacturing in the field of semiconductor technology, and particularly to a semiconductor device and its manufacturing method, and electronic equipment. Background Technology

[0002] Semiconductor memory can be divided into volatile memory (RAM, including DRAM and SRAM) and non-volatile memory (ROM and non-ROM) based on its application.

[0003] Taking DRAM as an example, traditional DRAM has multiple repeating "memory cells," each containing a capacitor and a transistor. A capacitor can store one bit of data; after charging and discharging, the amount of charge stored in the capacitor corresponds to binary data "1" and "0," respectively. The transistor acts as a switch to control the charging and discharging of the capacitor.

[0004] To minimize product costs, the goal is to fabricate as many memory cells as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet current product demands. Summary of the Invention

[0005] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0006] This disclosure provides a semiconductor device and its manufacturing method, as well as an electronic device, which simplifies the process and reduces costs.

[0007] This disclosure provides a semiconductor device, the semiconductor device comprising:

[0008] Multiple memory cells stacked along a vertical substrate direction; each memory cell includes a transistor and a capacitor connected to the transistor, and the multiple transistors of the multiple memory cells are distributed in different layers and stacked along a vertical substrate direction;

[0009] Word lines extending along the direction perpendicular to the substrate through the different layers;

[0010] The transistor includes a first electrode, a second electrode, and a semiconductor layer surrounding the word line sidewall; the capacitor includes a first electrode and a second electrode, the first electrode being connected to the first electrode; the first electrodes of the multiple capacitors of the multiple memory cells are distributed in different layers and stacked along the direction perpendicular to the substrate.

[0011] The semiconductor device further includes: at least one first through-hole through the first electrode in different layers, and the second electrode includes a vertical portion disposed in the first through-hole extending in a direction perpendicular to the substrate.

[0012] In some embodiments, the semiconductor device includes a plurality of first vias, and the plurality of first vias are arranged along the extension direction of the first electrode.

[0013] In some embodiments, the second pole further includes a surrounding portion that encloses the end face of the first pole away from the word line and a sidewall adjacent to the end face in a direction perpendicular to the substrate.

[0014] In some embodiments, the first pole and the first electrode are connected to form an integral structure.

[0015] In some embodiments, the plurality of semiconductor layers of the plurality of transistors are spaced apart and distributed in different regions of the word line sidewalls.

[0016] In some embodiments, the transistor further includes a gate insulating layer disposed between the word line and the semiconductor layer surrounding the sidewall of the word line;

[0017] The semiconductor device further includes:

[0018] An insulating layer and a conductive layer are alternately distributed from bottom to top along the direction perpendicular to the substrate;

[0019] A second via penetrating each of the insulating layers and each of the conductive layers, wherein the word line, the gate insulating layer surrounding the sidewall of the word line, and the plurality of semiconductor layers surrounding different regions of the sidewall of the gate insulating layer are distributed sequentially from the inside to the outside in the second via;

[0020] The plurality of semiconductor layers extend along a direction perpendicular to the substrate and are broken at the sidewalls of the insulating layer; the conductive layer includes the first electrode and the second electrode.

[0021] In some embodiments, the diameter of the second via corresponding to the first region of the conductive layer is larger than the diameter of the second region corresponding to the insulating layer;

[0022] The conductive layer is exposed on the sidewall inside the second through hole, and the insulating layer is exposed on the sidewall and a portion of the upper and lower surfaces of the second through hole.

[0023] The semiconductor layer is distributed on the sidewall of the conductive layer, and in portions of the upper and lower surfaces of the insulating layer exposed in the second via, but not on the sidewall of the insulating layer.

[0024] In some embodiments, the gate insulating layer is distributed on the surface of each semiconductor layer but not on the sidewalls of the insulating layer, and the gate insulating layers on the surfaces of different semiconductor layers are spaced apart from each other.

[0025] In some embodiments, the word line includes a second portion extending along the second via and a first portion located on the sidewall of each of the gate insulating layers.

[0026] In some embodiments, the contact area between the conductive layer and the insulating layer is laterally etched to form a recessed area along the lateral direction. An isolation layer is disposed in the recessed area, and the isolation layer is distributed on the surface of the semiconductor layer and the surface of the gate insulating layer.

[0027] This disclosure discloses a method for manufacturing a semiconductor device, the semiconductor device comprising: a plurality of memory cells stacked along a direction perpendicular to a substrate and word lines extending along a direction perpendicular to the substrate through different layers; each memory cell includes a transistor and a capacitor connected to the transistor, the plurality of transistors of the plurality of memory cells being distributed in the different layers stacked along a direction perpendicular to the substrate; each transistor including a first electrode and a second electrode, the method for manufacturing the semiconductor device comprising:

[0028] A substrate is provided, the substrate including an active region and a capacitor region disposed on at least one side of the active region, and a plurality of stacked structures are formed by sequentially and alternately depositing a first insulating film and a first conductive film on the active region and the capacitor region of the substrate, each of the stacked structures including a stack of alternately disposed first insulating layers and conductive layers.

[0029] The plurality of stacked structures are etched to form trenches, a plurality of first vias, and a plurality of second vias penetrating the plurality of stacked structures. The trenches cause the first insulating layer and the conductive layer to form a preset pattern. The preset pattern of the conductive layer includes a first electrode and a second electrode of the transistor to be formed, and a first electrode of the capacitor, with the first electrode connected to the first electrode. Each first electrode is provided with at least one first via penetrating the first electrode, and each first electrode is provided with a second via. The first via is located in the capacitor region, and the second via is located in the active region.

[0030] A second insulating film is deposited to fill the trenches, the plurality of first through holes, and the plurality of second through holes to form a second insulating layer; the second insulating film is different from the first insulating film;

[0031] The second insulating layer in the trench located in the capacitor region is etched away to expose the sidewall of the first electrode, and the second insulating layer in the plurality of first vias is etched away.

[0032] A dielectric film and a second conductive film are sequentially deposited on the substrate. The dielectric film and the second conductive film located in the active region are etched away to form a dielectric layer and a second electrode of the capacitor located in the capacitor region. The second electrode fills the second via and the trench located in the capacitor region. The dielectric layer is disposed between the second electrode and the first electrode.

[0033] The second insulating layer located in the second via is etched away, and the word line extending along the direction perpendicular to the substrate is formed in the second via, as well as the plurality of semiconductor layers surrounding the sidewalls of the word line of the plurality of transistors.

[0034] In some embodiments, a word line extending along a direction perpendicular to the substrate is formed within the second via, and the plurality of semiconductor layers surrounding the sidewalls of the word line of the plurality of transistors comprises:

[0035] The conductive layer is etched laterally by wet etching, such that the orthographic projection of the second via located in the first insulating layer falls into the orthographic projection of the second via located in the conductive layer on a plane parallel to the substrate, and the second via disconnects the first electrode and the second electrode in the preset pattern.

[0036] A semiconductor thin film and a gate insulating film are sequentially deposited in the second via to form a multilayer semiconductor layer and a gate insulating layer of the transistor, wherein the semiconductor layer is connected to the first electrode and the second electrode;

[0037] A third conductive film is deposited in the second via to form a sacrificial layer, the sacrificial layer covering the gate insulating layer;

[0038] Etch a portion of the sacrificial layer within the second via, such that the sidewall of the second via located in the first insulating layer exposes the gate insulating layer, and the sidewall of the second via located in the conductive layer exposes the sacrificial layer;

[0039] Etching removes the semiconductor layer and the gate insulating layer located within the second via of the first insulating layer;

[0040] A gate electrode film is deposited in the second via, and the gate electrode film fills the second via to form the word line.

[0041] In some embodiments, etching a portion of the sacrificial layer within the second via such that the sidewalls of the second via located in the insulating layer expose the gate insulating layer, and the sidewalls of the second via located in the conductive layer expose the sacrificial layer, includes:

[0042] By wet etching the sacrificial layer within the second via, the sidewall of the second via located in the insulating layer is exposed to the gate insulating layer;

[0043] The semiconductor layer and the gate insulating layer located within the second via of the insulating layer are removed by wet etching.

[0044] In some embodiments, after etching away the semiconductor layer and the gate insulating layer located within the second via of the insulating layer, and before depositing a gate electrode film within the second via, the method further includes:

[0045] A third insulating film is deposited in the second through-hole to form an isolation layer;

[0046] The isolation layer covering the sacrificial layer is etched away.

[0047] In some embodiments, after forming the word line extending along a direction perpendicular to the substrate within the second via, and after the plurality of semiconductor layers surrounding the sidewalls of the word line of the plurality of transistors, the method further includes:

[0048] The second insulating layer located in the trench of the active region is etched, and a third insulating film is deposited to fill the trench of the active region to form the third insulating layer.

[0049] This disclosure provides an electronic device, including the semiconductor device described in any of the above embodiments, or including a semiconductor device formed by the manufacturing method of the semiconductor device described in any of the above embodiments.

[0050] This disclosure includes a semiconductor device comprising: a plurality of memory cells stacked along a direction perpendicular to a substrate; each memory cell including a transistor and a capacitor connected to the transistor, the transistors of the plurality of memory cells being distributed in different layers and stacked along the direction perpendicular to the substrate; a word line extending through the different layers along the direction perpendicular to the substrate; each transistor including a first electrode, a second electrode, and a semiconductor layer surrounding the sidewalls of the word line; each capacitor including a first electrode and a second electrode, the first electrode being connected to the first electrode; the first electrodes of the plurality of capacitors of the plurality of memory cells being distributed in different layers and stacked along the direction perpendicular to the substrate; the semiconductor device further comprising: at least one first via penetrating the first electrode through the different layers, the second electrode including a vertical portion extending perpendicular to the substrate direction disposed within the first via. The semiconductor device provided in this disclosure, where the second electrode of the capacitor is disposed within the via of the first electrode, facilitates a reduction in device area and an increase in device density.

[0051] Other features and advantages of this disclosure will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the disclosure. The objects and advantages of this disclosure may be realized and obtained by means of the structures particularly pointed out in the description and the accompanying drawings.

[0052] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0053] The accompanying drawings are used to provide a further understanding of the technical solutions disclosed herein and form part of the specification. They are used together with the embodiments of the present disclosure to explain the technical solutions and do not constitute a limitation on the technical solutions.

[0054] Figure 1A A schematic plan view of a semiconductor device provided for an exemplary embodiment;

[0055] Figure 1B For along Figure 1A A schematic diagram of the direction aa' in the middle;

[0056] Figure 1C For along Figure 1A A schematic diagram of the direction of bb' in the middle;

[0057] Figure 1D For along Figure 1A A schematic diagram in the cc' direction;

[0058] Figure 2A A cross-sectional schematic diagram of the stacked structure provided as an exemplary embodiment;

[0059] Figure 2B A schematic plan view of a substrate provided for an exemplary embodiment;

[0060] Figure 3A A planar schematic diagram of a pre-defined pattern provided as an exemplary embodiment;

[0061] Figure 3B A schematic diagram along the aa' direction after forming a preset pattern, provided as an exemplary embodiment;

[0062] Figure 4A A schematic plan view of the formation of the second insulating layer provided as an exemplary embodiment;

[0063] Figure 4B A schematic diagram along the aa' direction after the formation of the second insulating layer, provided as an exemplary embodiment;

[0064] Figure 5A A planar schematic diagram showing the capacitor region after being opened, as provided in an exemplary embodiment;

[0065] Figure 5BA schematic diagram along the aa' direction after the capacitor region is opened, provided as an exemplary embodiment;

[0066] Figure 6A A schematic cross-sectional view along the direction parallel to the substrate after forming the dielectric layer, the second electrode, and the fourth insulating layer, as provided in an exemplary embodiment;

[0067] Figure 6B A schematic diagram along the aa' direction after forming the dielectric layer, the second electrode, and the fourth insulating layer, as provided in an exemplary embodiment;

[0068] Figure 6C A schematic diagram along the bb' direction after the formation of the dielectric layer, the second electrode, and the fourth insulating layer, as provided in an exemplary embodiment;

[0069] Figure 7A A schematic cross-sectional view along the direction parallel to the substrate after removing the second insulating layer located in the second via, as provided in an exemplary embodiment;

[0070] Figure 7B A schematic diagram along the aa' direction after removing the second insulating layer located in the second through-hole, provided as an exemplary embodiment;

[0071] Figure 8A A schematic cross-sectional view of the conductive layer after lateral etching, provided as an exemplary embodiment;

[0072] Figure 8B A schematic diagram along the aa' direction after lateral etching of the conductive layer, provided as an exemplary embodiment;

[0073] Figure 9A A schematic cross-sectional view along the direction parallel to the substrate after forming a semiconductor layer, a gate insulating layer and a sacrificial layer, as provided in an exemplary embodiment;

[0074] Figure 9B A schematic diagram along the aa' direction after forming a semiconductor layer, a gate insulating layer and a sacrificial layer, provided for an exemplary embodiment;

[0075] Figure 9C A schematic diagram along the cc' direction after forming a semiconductor layer, a gate insulating layer and a sacrificial layer, provided for an exemplary embodiment;

[0076] Figure 10A A schematic cross-sectional view along the direction parallel to the substrate after removing a portion of the sacrificial layer, semiconductor layer, and gate insulating layer, as provided in an exemplary embodiment;

[0077] Figure 10B A schematic diagram along the aa' direction after removing a portion of the sacrificial layer, semiconductor layer, and gate insulating layer, as provided in an exemplary embodiment;

[0078] Figure 10CA schematic diagram along the cc' direction after removing a portion of the sacrificial layer, semiconductor layer, and gate insulating layer, as provided in an exemplary embodiment;

[0079] Figure 11A A schematic cross-sectional view of the second portion forming the isolation layer and word line, provided for an exemplary embodiment, along the direction parallel to the substrate.

[0080] Figure 11B A schematic diagram along the aa' direction after forming the second portion of the isolation layer and word line, as provided in an exemplary embodiment;

[0081] Figure 11C A schematic diagram along the cc' direction after forming the second portion of the isolation layer and word line, as provided in an exemplary embodiment;

[0082] Figure 12A A schematic cross-sectional view along the direction parallel to the substrate after the formation of the third insulating layer, provided as an exemplary embodiment;

[0083] Figure 12B A schematic diagram along the aa' direction after the formation of the third insulating layer, provided as an exemplary embodiment;

[0084] Figure 12C A schematic diagram along the cc' direction after the formation of a third insulating layer, provided as an exemplary embodiment. Detailed Implementation

[0085] The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Unless otherwise specified, the embodiments of this disclosure and the features thereof can be combined arbitrarily with each other.

[0086] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains.

[0087] The embodiments disclosed herein are not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect actual proportions. Furthermore, the drawings schematically illustrate ideal examples, and the embodiments of this disclosure are not limited to the shapes or values ​​shown in the drawings.

[0088] The ordinal numbers “first,” “second,” “third,” etc., used in this disclosure are provided to avoid confusion among the constituent elements and do not indicate any order, quantity, or importance.

[0089] In this disclosure, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification of the specification, and does not imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the direction in which each constituent element is described. Therefore, the disclosure is not limited to the terms used herein and may be appropriately replaced as appropriate.

[0090] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to physical or signal connections, contact or integral connections; direct connections, indirect connections via intermediate components, or internal communication between two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure according to the specific circumstances.

[0091] In this disclosure, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0092] In this disclosure, the first electrode may be the drain electrode and the second electrode may be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this disclosure, the "source electrode" and the "drain electrode" can be interchanged.

[0093] In this disclosure, "connection" includes the situation where constituent elements are connected together by a component having some electrical function. There are no particular limitations on the "component having some electrical function," as long as it enables the transmission and reception of electrical signals between the connected constituent elements. Examples of "component having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0094] In this disclosure, "parallel" means approximately parallel or nearly parallel, for example, two straight lines forming an angle of -10° or more and less than 10°, and therefore also includes angles of -5° or more and less than 5°. Similarly, "perpendicular" means approximately perpendicular, for example, two straight lines forming an angle of 80° or more and less than 100°, and therefore also includes angles of 85° or more and less than 95°.

[0095] In this embodiment of the disclosure, "A and B are an integral structure" can refer to a structure without obvious boundaries such as discontinuities or gaps in its microstructure. Generally, an integral structure is formed by patterning interconnected membrane layers on a single membrane layer. For example, A and B may be formed using the same material as a single membrane layer and simultaneously created through the same patterning process, resulting in a structure with interconnected relationships.

[0096] In this embodiment of the disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A.

[0097] Figure 1A A schematic diagram of a semiconductor device provided as an exemplary embodiment; Figure 1B For along Figure 1A Cross-sectional view along the aa' direction. Figure 1C For along Figure 1A Cross-sectional view in the bb' direction. Figure 1D For along Figure 1A A cross-sectional view along the cc' direction. The semiconductor device may be a transistor, or a memory cell containing transistors, or a memory cell array containing memory cells, or a 3D stacked structure containing a memory cell array, or a memory containing transistors or a memory cell array, etc.

[0098] like Figure 1A , Figure 1B , Figure 1C , Figure 1D As shown, this disclosure provides a semiconductor device, which may include:

[0099] Multiple memory cells are stacked along a direction perpendicular to substrate 1; each memory cell includes a transistor and a capacitor connected to the transistor, and the multiple transistors of the multiple memory cells are distributed in different layers and stacked along a direction perpendicular to substrate 1.

[0100] Word lines 40 extending along the direction perpendicular to the substrate through the different layers;

[0101] The transistor includes a first electrode 51, a second electrode 52, and a semiconductor layer 23 surrounding the sidewall of the word line 40; the capacitor includes a first electrode 41 and a second electrode 42, the first electrode 41 being connected to the first electrode 51; the first electrodes 41 of the multiple capacitors of the multiple memory cells are distributed in different layers and stacked along the direction perpendicular to the substrate 1.

[0102] The semiconductor device may further include: at least one first through hole K1 penetrating the first electrode 41 through different layers, and the second electrode 42 includes a vertical portion disposed in the first through hole K1 extending in a direction perpendicular to the substrate 1.

[0103] The solution provided in this embodiment places the second electrode of the capacitor inside the hole of the first electrode, which helps to reduce the device area and increase the device density. Furthermore, this structure facilitates the one-time formation of capacitor patterns, transistor patterns, and word line patterns, simplifying the process and reducing costs.

[0104] In some embodiments, the semiconductor device may include a plurality of first vias K1, and the plurality of first vias K1 may be arranged along the extension direction of the first electrode 41. Figure 1A The illustration shows two first through holes K1, but the embodiments of this disclosure are not limited to this. They may include more or fewer first through holes K1, and the layout of the first through holes K1 may be changed, for example, they may be arranged vertically.

[0105] In some embodiments, the first through hole K1 along a cross section parallel to the substrate 1 can be circular, square, elliptical, etc.

[0106] In some embodiments, when there are multiple identical through holes K1, the size and shape of different first through holes K1 may be the same or different.

[0107] In some embodiments, the second electrode 42 may further include a surrounding portion that encloses the end face of the first electrode 41 away from the word line 40 and a sidewall adjacent to the end face and perpendicular to the substrate 1. That is, the second electrode 42 comprises two parts, one part being disposed within the first through hole K1, and the other part being disposed on the surface of the first electrode 41, enclosing the three sidewalls of the first electrode 41 (one of which is called the end face), thereby further increasing the electrode area of ​​the capacitor and increasing the capacitance.

[0108] In some embodiments, the first electrode 41 and the first electrode 51 can be connected to form an integral structure. Alternatively, they can share a single electrode, which can be a wire extending laterally in the direction parallel to the substrate 1.

[0109] In some embodiments, the semiconductor device may further include a gate electrode 26, wherein the gate electrode 26 of transistors in different layers may be a part of the word line 40. It is understood that the gate electrode 26 does not need to be fabricated separately before or after the word line 40 is formed; after the word line 40 is fabricated, a part of the word line 40 serves as the gate electrode 26.

[0110] In some embodiments, the first electrode 51 and the second electrode 52 may be located in the same conductive film layer along a direction perpendicular to the substrate 1. This can be understood as the first electrode 51 and the second electrode 52 being patterned from the same conductive film layer. In some embodiments, the conductive film layer is approximately parallel to the upper surface of the substrate 1. However, the embodiments of this disclosure are not limited thereto, and the first electrode 51 and the second electrode 52 may be located in different conductive film layers.

[0111] In some embodiments, the transistor may further include a gate insulating layer 24 disposed between the word line 40 and the semiconductor layer 23, the gate insulating layer 24 being able to surround the sidewall of the word line 40.

[0112] In some embodiments, the plurality of semiconductor layers 23 of the plurality of transistors are spaced apart and distributed in different regions of the word line sidewalls. That is, the plurality of semiconductor layers 23 of the plurality of transistors are physically disconnected, thereby eliminating parasitic MOS transistors between layers.

[0113] In some embodiments, the semiconductor device further includes:

[0114] An insulating layer and a conductive layer are alternately distributed from bottom to top along the direction perpendicular to the substrate;

[0115] A second via K2 penetrates each of the insulating layers and each of the conductive layers. From the inside to the outside, the word line 40, the gate insulating layer 24 surrounding the sidewall of the word line 40, and the plurality of semiconductor layers 23 surrounding different regions of the sidewall of the gate insulating layer 24 are distributed in the second via K2.

[0116] The plurality of semiconductor layers 23 extend along a direction perpendicular to the substrate and are broken at the sidewalls of the insulating layer; the conductive layer includes the first electrode and the second electrode.

[0117] In some embodiments, the diameter of the second through hole K2 corresponding to the first region of the conductive layer is larger than the diameter of the second region corresponding to the insulating layer;

[0118] The conductive layer is exposed on the sidewall inside the second through hole K2, and the insulating layer is exposed on the sidewall and a portion of the upper and lower surfaces of the second through hole K2.

[0119] The semiconductor layer is distributed 23 times on the sidewall of the conductive layer, and distributed in a portion of the upper and lower surfaces of the insulating layer exposed in the second via, but not distributed on the sidewall of the insulating layer.

[0120] In some embodiments, the gate insulating layer 24 is distributed on the surface of each semiconductor layer 23 and is not distributed on the sidewall of the insulating layer, and the gate insulating layers 24 on the surfaces of different semiconductor layers 23 may be spaced apart from each other.

[0121] In some embodiments, the word line 40 may include a second portion 402 extending along the second via K2, and a first portion 401 located on the sidewall of each of the gate insulating layers 24.

[0122] In some embodiments, the contact area between the conductive layer and the insulating layer is laterally etched to form a laterally recessed region A1, and an isolation layer 19 is disposed in the recessed region A1. The isolation layer 19 is distributed on the surface of the semiconductor layer 23 and the surface of the gate insulating layer 24.

[0123] In some embodiments, the semiconductor device may form a memory cell array, the memory cell array comprising a plurality of memory cells. For example... Figure 1A As shown, the memory cell array is distributed along the first direction X and the second direction Y. Each layer may also include a bit line 30, which is connected to the second electrode 52 of the transistor in the same column of the layer. Figure 1A The illustration shows a storage unit consisting of three rows and two columns per layer, but the embodiments of this disclosure are not limited thereto. Each layer may include storage units with other numbers of rows and columns, for example, it may include only one storage unit.

[0124] In some embodiments, the second electrode 52 of the transistors in two adjacent columns of memory cells is connected to the same bit line 30.

[0125] In some embodiments, the second electrode 52 of the transistor may be a portion of the bit line 30 to which the second electrode 52 is connected. For example, the bit line 30 may be a straight line with its sidewalls connected to the semiconductor layer 23, or the bit line 30 may have an integrally designed branch connected to the semiconductor layer 23, wherein the extension direction of the branch intersects the extension direction of the bit line 30, such as approximately perpendicular.

[0126] The branch can be multiple branches on one sidewall of the bit line, or multiple branches on two sidewalls at the same time, and each branch will form a transistor or a memory cell.

[0127] In some embodiments, the bit line 30 may extend along the second direction Y.

[0128] In some embodiments, the first electrode 51 may extend along a first direction X.

[0129] The technical solution of this embodiment is further illustrated below through the manufacturing process of the semiconductor device in this embodiment. The "patterning process" mentioned in this embodiment includes deposition of a film layer, coating with photoresist, mask exposure, development, etching, and photoresist stripping, which are mature manufacturing processes in related technologies. The "photolithography process" mentioned in this embodiment includes coating of a film layer, mask exposure, and development, which are mature manufacturing processes in related technologies. Deposition can employ known processes such as sputtering, evaporation, and chemical vapor deposition; coating can employ known coating processes; and etching can employ known methods, without specific limitations. In the description of this embodiment, it should be understood that a "thin film" refers to a thin film made of a certain material on a substrate using a deposition or coating process. If the "thin film" does not require a patterning process or photolithography process during the entire manufacturing process, it can also be called a "layer." If the "thin film" requires a patterning process or photolithography process during the entire manufacturing process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process or photolithography process contains at least one "pattern."

[0130] In one exemplary embodiment, the manufacturing process of the semiconductor device may include:

[0131] 1) Provide a substrate 1, on which a first insulating film and a first conductive film are sequentially and alternately deposited to form a plurality of stacked structures. Figure 2A This is a planar schematic diagram of the substrate. Figure 2B This is a cross-sectional view of the stacked structure along a direction perpendicular to the substrate. For example... Figure 2A As shown, the substrate 1 may include an active region 100 and two capacitor regions 200 disposed on both sides of the active region 100, and the stacked structure is disposed on the active region 100 and the capacitor regions 200. Figure 2B As shown, the stacked structure may include an alternating stack of a first insulating layer 10 and a conductive layer 12.

[0132] In some embodiments, substrate 1 may be a semiconductor substrate, a base semiconductor layer on a support structure, a metal electrode, or a semiconductor substrate having one or more layers, structures, or regions formed thereon. The substrate may be a conventional silicon substrate or other bulk substrate including a layer of semiconductor material.

[0133] In some embodiments, the first insulating film and the first conductive film may be deposited using a chemical vapor deposition method.

[0134] In some embodiments, the first insulating film may be a low-K dielectric layer, that is, a dielectric layer with a dielectric constant K < 3.9, including but not limited to silicon oxide, such as silicon dioxide (SiO2).

[0135] In some embodiments, the first conductive film may be a conductive material as follows:

[0136] For example, it contains metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, and cobalt; it can also be a metal alloy containing these metals.

[0137] Alternatively, it can be metal oxides, metal nitrides, metal silicides, metal carbides, etc., such as highly conductive metal oxide materials like indium tin oxide (ITO), indium zinc oxide (IZO), and indium oxide (InO); or metal nitride materials like titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), and titanium aluminum nitride (TiAlN).

[0138] Alternatively, it could be polycrystalline silicon, conductive doped semiconductor materials, such as conductive doped silicon, conductive doped germanium, conductive doped silicon-germanium, etc.; or other materials that exhibit conductivity.

[0139] Figure 2B The stacked structure shown includes four first insulating layers 10 and three conductive layers 12. This is merely an example; in other embodiments, the stacked structure may include more or fewer alternating layers of first insulating layers 10 and conductive layers 12.

[0140] 2) Etch the multiple stacked structures to form a preset pattern;

[0141] The etching of the plurality of stacked structures to form a preset pattern may include: etching the plurality of stacked structures to form a plurality of trenches T1, a plurality of first vias K1, and a plurality of second vias K2 penetrating the plurality of stacked structures. The plurality of trenches T1 cause the first insulating layer 10 and the conductive layer 12 to form a preset pattern. The preset pattern of the conductive layer 12 includes a first electrode 51 and a second electrode 52 of the transistor to be formed, and a first electrode 41 of the capacitor, and the first electrode 41 is connected to the first electrode 51. Each first electrode 41 is provided with at least one first via K1 penetrating the first electrode 41, and each first electrode 51 is provided with one second via K2. The first via K1 is located in the capacitor region 200, and the second via K2 is located in the active region 100. The first via K1 extends in a direction perpendicular to the substrate 1, and the second via K2 extends in a direction perpendicular to the substrate 1.

[0142] The preset pattern of the conductive layer 12 may include a plurality of first conductive portions 121 and second conductive portions 122 connecting the first conductive portions 121, wherein the first conductive portions 121 may extend along a first direction X, and the second conductive portions 122 may extend along a second direction Y, such as... Figure 3A , Figure 3B As shown, where, Figure 3A A planar schematic diagram of a predetermined shape provided as an exemplary embodiment. Figure 3B This is a schematic diagram along the aa' direction after forming a preset pattern, provided as an exemplary embodiment. The preset pattern and the patterns of the plurality of trenches T1 are complementary, that is, the combination of the pattern of the preset pattern and the pattern of the plurality of trenches T1 constitutes the shape of the conductive layer 12 in step 1).

[0143] In some embodiments, the first conductive portion 121 may include two first through holes K1 and one second through hole K2. However, the embodiments disclosed herein are not limited thereto, and the first conductive portion 121 may include more or fewer first through holes K1, for example, it may include one first through hole K1, or three first through holes K1, etc.

[0144] In some embodiments, the two first through holes K1 may be arranged along the extending direction of the first conductive portion 121. However, the embodiments disclosed herein are not limited thereto, and the arrangement of the plurality of first through holes K1 is not limited.

[0145] In some embodiments, the cross-section of the first through hole K1 parallel to the substrate direction can be square, circular, or elliptical, etc.

[0146] In some embodiments, when there are multiple first through holes K1, the size and shape of the multiple first through holes K1 may be the same or different.

[0147] The first conductive portion 121 can subsequently form the first electrode 51 of the transistor and the first terminal 41 of the capacitor, the second conductive portion 122 can form the second electrode 52 of the transistor, and form the bit line 30.

[0148] Alternatively, the first conductive portion 121 may subsequently form the first electrode 51 and the second electrode 52 of a transistor, the first electrode 41 of a capacitor, and the second conductive portion 122 may form the bit line 30.

[0149] In some embodiments, the plurality of stacked structures can be etched using a dry etching method.

[0150] The solution provided in this embodiment can form capacitor patterns, active area patterns, and letter line patterns in one step, avoiding multiple etchings of the stacked structure, simplifying the process, and reducing costs.

[0151] 3) Forming a second insulating layer 13;

[0152] The formation of the second insulating layer 13 may include: depositing a second insulating film on the substrate 1 forming the aforementioned structure and then polishing it to form a second insulating layer 13 that fills the plurality of trenches T1, the plurality of first vias K1, and the plurality of second vias K2, as shown below. Figure 4A and Figure 4B As shown, Figure 4A A schematic plan view of the formation of the second insulating layer 13 is provided as an exemplary embodiment. Figure 4B This is a schematic diagram along the aa' direction after the formation of the second insulating layer 13, provided as an exemplary embodiment. The second insulating layer 13, filling the second through-hole K2, serves as a dummy wordline (dummy WL). The second insulating layer 13 is flush with the topmost first insulating layer 10.

[0153] The second insulating film may be an insulating layer different from the first insulating film, including but not limited to silicon nitride (SiN). The second insulating film and the first insulating film have a certain etching selectivity ratio, so that the first insulating layer 10 is not affected when the second insulating layer 13 is etched subsequently.

[0154] 4) Open capacitor area 200;

[0155] Opening the capacitor region 200 may include: removing the second insulating layer 13 located in the capacitor region 200, including the second insulating layer 13 located in the plurality of trenches T1 of the capacitor region 200 and the second insulating layer 13 located in the plurality of first through holes K1, thereby exposing the sidewalls of the first conductive portion 121 located in the capacitor region 200, including the end face of the first conductive portion 121 away from the second conductive portion 122 and two sidewalls extending in a direction perpendicular to the substrate 1 at a distance less than or equal to a preset distance from the end face, such as... Figure 5A and Figure 5B As shown, Figure 5A A planar schematic diagram of the capacitor region 200 after it is opened, as provided in an exemplary embodiment. Figure 5B This is a schematic diagram along the aa' direction after the capacitor region 200 is opened, provided as an exemplary embodiment. The preset distance is the dimension of the portion of the first conductive part 121 located in the capacitor region 200 along the extension direction of the first conductive part 121.

[0156] In some embodiments, the second insulating layer 13 located in the capacitor region 200 can be removed by dry etching, with the dry etching stopping on the substrate 1.

[0157] 5) Forming the dielectric layer 43, the second electrode 42, and the fourth insulating layer 15;

[0158] The formation of the dielectric layer 43, the second electrode 42, and the fourth insulating layer 15 may include:

[0159] In a substrate 1 forming the above structure, a dielectric thin film and a conductor material are sequentially deposited to form a dielectric layer 43 and a second electrode 42, respectively. The dielectric layer 43 covers the exposed area of ​​the conductive layer 12, namely the sidewall and bottom wall of the first via K1. The first conductive portion 121 has an end face away from the second conductive portion 122 and two sidewalls extending perpendicular to the substrate 1 at a distance less than or equal to a preset distance from the end face. The second electrode 42 fills the first via K1 and the plurality of trenches T1 located in the capacitor region 200. The second electrode 42 is insulated from the first conductive portion 121 through the dielectric layer 43. The second electrode 42 wraps around the end face of the first conductive portion 121 away from the substrate and the two sidewalls extending perpendicular to the substrate 1 at a distance less than or equal to a preset distance from the end face.

[0160] The dielectric layer 43 and the second electrode 42 located in the active region 100 are removed by etching. The etching stops on the topmost first insulating layer 10, exposing the upper surface (the surface away from the substrate 1) of the second insulating layer 13 deposited in the second via K2.

[0161] A fourth insulating film is deposited and smoothed to form a fourth insulating layer 15 covering the active region 100, such as... Figure 6A , Figure 6B and Figure 6C As shown, Figure 6A A schematic cross-sectional view (film layer containing conductive layer 12) provided for an exemplary embodiment after the formation of dielectric layer 43, second electrode 42 and fourth insulating layer 15, along a direction parallel to the substrate. Figure 6B A schematic diagram along the aa' direction after the formation of the dielectric layer 43, the second electrode 42, and the fourth insulating layer 15, as provided in an exemplary embodiment. Figure 6C This is a schematic diagram along the bb' direction after forming the dielectric layer 43, the second electrode 42, and the fourth insulating layer 15, as provided in an exemplary embodiment. During polishing, the fourth insulating layer 15 is flush with the second electrode 42. The bb' direction is perpendicular to the substrate and perpendicular to the aa' direction.

[0162] In some embodiments, the second electrode 42 may include a first sublayer 421 and a second sublayer 422. After forming the dielectric layer 43, a second conductive film may be deposited on the substrate 1 to form the first sublayer 421; then a third conductive film may be deposited to form the second sublayer 422, and the second sublayer 422 may fill the first via K1 and the plurality of trenches T1 located in the capacitor region 200. The first sublayer 412 covers the dielectric layer 43, and the second sublayer 422 covers the first sublayer 411. The second sublayer 422 is connected to the first sublayer 421.

[0163] In some embodiments, the dielectric film and conductor material can be deposited by atomic layer deposition (ALD).

[0164] In some embodiments, the dielectric film may be a High-K dielectric material, i.e., a dielectric material with a dielectric constant K ≥ 3.9. In some embodiments, it may include one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. Exemplary examples include, but are not limited to, at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2), and other high-K materials.

[0165] In some embodiments, the second conductive film includes, but is not limited to, at least one of the following or a combination thereof:

[0166] Metals or alloys, such as those containing tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, cobalt, etc., or metal alloys containing the aforementioned metals;

[0167] Alternatively, it can be metal oxides, metal nitrides, metal silicides, metal carbides, etc., such as tin-doped indium oxide (ITO), indium-doped zinc oxide (IZO), indium oxide (InO), aluminum-doped zinc oxide (Al-doped ZnO, AZO), iridium oxide (IrOx), ruthenium oxide (RuOx) and other conductive metal oxide materials; such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN) and other metal nitride materials.

[0168] In some embodiments, the third conductive film includes, but is not limited to, metal, metal alloy, polycrystalline silicon, silicon-doped conductive layer, metal oxide conductive layer, etc.

[0169] In some embodiments, the fourth insulating film may be a low-K dielectric layer, including but not limited to silicon oxide, such as silicon dioxide (SiO2).

[0170] 6) Etch away the second insulating layer 13 located in the second through hole K2;

[0171] The etching removal of the second insulating layer 13 located in the second via K2 may include: removing the second insulating layer 13 located in the second via K2 by dry etching, that is, removing the dummy word line located in the second via K2, so as to facilitate the subsequent formation of the semiconductor layer 23, the gate insulating layer 24 and the word line 40 in the second via K2, such as... Figure 7A , Figure 7B As shown, where, Figure 7AA schematic cross-sectional view (film layer containing conductive layer 12) provided for an exemplary embodiment after removing the second insulating layer 13 located in the second via K2 along a direction parallel to the substrate 1. Figure 7B This is a schematic diagram along the aa' direction after removing the second insulating layer 13 located in the second through-hole K2, as provided in an exemplary embodiment. In this step, the second through-hole K2 penetrates the fourth insulating layer 15.

[0172] 7) Laterally etch the conductive layer 12;

[0173] The lateral etching of the conductive layer 12 may include: etching the conductive layer 12 in a direction away from the second via K2, which can be understood as lateral etching (etching along a direction parallel to the substrate 1), so as to expand the second sub-hole K22 of the second via K2 located in the conductive layer 12 in a direction away from the second via K2, with the first insulating layer 10 being almost unaffected by the etching, such that on a plane parallel to the substrate 1, the orthographic projection of the first sub-hole K21 located in the first insulating layer 10 falls within the orthographic projection of the second sub-hole K22 located in the conductive layer 12, and such that the conductive layer 12 forms a first electrode 51 and a second electrode 52 that are separate from each other; Figure 8A , Figure 8B As shown, where, Figure 8A A schematic cross-sectional view (film layer where conductive layer 12 is located) of the conductive layer 12 after lateral etching of the conductive layer 12 as an exemplary embodiment; Figure 8B This is a schematic diagram along the aa' direction after lateral etching of the conductive layer 12, as provided in an exemplary embodiment.

[0174] The plurality of first sub-holes K21 and the plurality of second sub-holes K22 cause the second through-hole K2 to form multiple dumbbell-shaped structures, such as forming multiple holes of two different sizes. The diameter of the second sub-hole K22 located in the conductive layer 12 is larger than the diameter of the first sub-hole K21 located in the first insulating layer 10.

[0175] In some embodiments, wet etching can be used, employing an acid solution with a high etching selectivity ratio for the conductive layer 12 and the first insulating layer 10, to laterally etch the conductive layer 12 to a first predetermined thickness L1. Due to the high etching selectivity, almost no etching occurs on the first insulating layer 10.

[0176] 8) Forming a semiconductor layer 23, a gate insulating layer 24, and a sacrificial layer 25;

[0177] The formation of the semiconductor layer 23, the gate insulating layer 24, and the sacrificial layer 25 may include:

[0178] A semiconductor thin film and a gate insulating thin film are sequentially deposited in the second via K2 to form a semiconductor layer 23 and a gate insulating layer 24.

[0179] A sacrificial layer film is deposited within the second via K2 to form a sacrificial layer 25, such as... Figure 9A , Figure 9B , Figure 9C As shown, where, Figure 9A A schematic cross-sectional view (film layer containing conductive layer 12) provided for an exemplary embodiment after the formation of semiconductor layer 23, gate insulating layer 24 and sacrificial layer 25, along a direction parallel to the substrate. Figure 9B A schematic diagram along the aa' direction after the formation of the semiconductor layer 23, the gate insulating layer 24, and the sacrificial layer 25, as provided in an exemplary embodiment. Figure 9C This is a schematic diagram along the cc' direction after the formation of the semiconductor layer 23, gate insulating layer 24, and sacrificial layer 25, provided for an exemplary embodiment. The sacrificial layer 25 serves as a sacrificial layer for the semiconductor layer 23 located on the sidewall of the second via K2 in the conductive layer 12 during subsequent etching of the semiconductor layer 23 and the gate insulating layer 24 located on the sidewall of the second via K2 in the first insulating layer 10. The cc' direction is parallel to the bb' direction.

[0180] In one exemplary embodiment, the material of the sacrificial layer film can be a conductive material, such as the same material as the subsequent gate electrode film. Therefore, after etching away the semiconductor layer 23 and gate insulating layer 24 located on the sidewalls of the first insulating layer 10, the sacrificial layer 25 does not need to be removed before depositing the gate electrode film, and the gate electrode film can be deposited directly. The sacrificial layer 25 and the deposited gate electrode film together serve as the word line of the final device. However, this embodiment is not limited to this; the material of the sacrificial layer film may be different from that of the gate electrode film. The sacrificial layer 25 does not completely fill the second via K2. However, this embodiment is not limited to this; the sacrificial layer 25 may fill the second via K2.

[0181] In an exemplary embodiment, the semiconductor thin film, the gate insulating film, and the sacrificial layer film can be deposited by ALD.

[0182] In an exemplary embodiment of this disclosure, the material of the semiconductor layer 23 may be silicon or polycrystalline silicon with a band gap of less than 2 eV, or it may be a wide band gap material, such as a metal oxide material with a band gap of greater than 2 eV.

[0183] For example, the material of the metal oxide semiconductor layer or channel may include metal oxides of at least one of the following metals: indium, gallium, zinc, tin, tungsten, magnesium, zirconium, aluminum, hafnium, etc. Of course, the metal oxide may also contain compounds of other elements, such as nitrogen (N) and silicon (Si); it may also contain trace amounts of other doping elements.

[0184] In some embodiments, the material of the metal oxide semiconductor layer or channel may include one or more of the following: indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), and indium tungsten oxide (InWO4). Materials such as IWO, titanium oxide (TiO), zinc oxynitride (ZnON), zinc magnesium oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), and zirconium zinc tin oxide (ZrZnSnO) can be used. As long as the leakage current of the transistor meets the requirements, it is acceptable. The specific requirements can be adjusted according to the actual situation.

[0185] These materials have wide band gaps and low leakage current. For example, when the metal oxide material is IGZO, the transistor leakage current is less than or equal to 10. -15 A. This can improve the performance of dynamic memory.

[0186] The above-mentioned materials for metal oxide semiconductor layers or channels only emphasize the element type of the material, without emphasizing the atomic ratio or the film quality of the material.

[0187] In exemplary embodiments of this disclosure, the material of the gate insulating layer 24 may comprise one or more high-K dielectric materials. In some embodiments, it may include one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. Exemplarily, for example, it may include, but is not limited to, at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2), and other high-K materials.

[0188] In one exemplary embodiment, the sacrificial layer film may be one or more of the following different types of materials:

[0189] For example, it contains metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, and cobalt; it can also be a metal alloy containing these metals.

[0190] Alternatively, it can be metal oxides, metal nitrides, metal silicides, metal carbides, etc., such as highly conductive metal oxide materials like indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (InO), and aluminum-doped zinc oxide (AZO); or metal nitride materials like titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), and titanium aluminum nitride (TiAlN).

[0191] Alternatively, it could be polycrystalline silicon, conductive doped semiconductor materials, such as conductive doped silicon, conductive doped germanium, conductive doped silicon-germanium, etc.; or other materials that exhibit conductivity.

[0192] 9) Remove the sacrificial layer 25, semiconductor layer 23 and gate insulating layer 24 distributed on the sidewall of the second via K2 located in the first insulating layer 10 and the fourth insulating layer 15.

[0193] The removal of the sacrificial layer 25, semiconductor layer 23, and gate insulating layer 24 distributed on the sidewalls of the second via K2 located in the first insulating layer 10 and the fourth insulating layer 15 may include: removing the sacrificial layer 25 distributed on the sidewalls of the second via K2 located in the first insulating layer 10 and the fourth insulating layer 15 by wet etching. At this time, the sacrificial layer 25 is only distributed on the sidewalls of the second via K2 located in the conductive layer 12.

[0194] The semiconductor layer 23 and gate insulating layer 24 distributed on the sidewalls of the second via K2 located in the first insulating layer 10 and the fourth insulating layer 15 are removed by wet etching. At this time, the sidewalls of the second via K2 located in the first insulating layer 10 and the fourth insulating layer 15 are free of semiconductor layer 23 and gate insulating layer 24, and the semiconductor layer 23 and gate insulating layer 24 located on the sidewalls of the second via K2 located in the conductive layer 12 are partially etched away, forming a lateral recessed region A1, such as... Figure 10A , Figure 10B , Figure 10C As shown, where, Figure 10A A schematic cross-sectional view (film layer containing conductive layer 12) provided for an exemplary embodiment after removing a portion of the sacrificial layer 25, semiconductor layer 23, and gate insulating layer 24 along a direction parallel to the substrate. Figure 10B A schematic diagram along the aa' direction after removing a portion of the sacrificial layer 25, semiconductor layer 23, and gate insulating layer 24, as provided in an exemplary embodiment. Figure 10CThis is a schematic diagram along the cc' direction after removing a portion of the sacrificial layer 25, semiconductor layer 23, and gate insulating layer 24, as provided in an exemplary embodiment. A portion of the sacrificial layer 25 is etched away during this process, leaving a portion of the sacrificial layer 25 covering the gate insulating layer 24. The retained sacrificial layer 25 serves as the first portion 401 of the word line 40. In this embodiment, the interlayer semiconductor layer 23 is removed, thereby eliminating interlayer parasitic MOS transistors and improving device stability.

[0195] 10) Forming the isolation layer 19 and the second part 402 of the word line;

[0196] The formation of the isolation layer 19 may include: depositing an isolation layer film in the second via K2 to form the isolation layer 19, the isolation layer 19 filling the recessed region A1, avoiding exposure of the semiconductor layer 23, and preventing short circuits caused by conduction between the semiconductor layer 23 and the second portion 402 of the subsequently formed word line 40.

[0197] The isolation layer 19 covering the sacrificial layer 25 on the side facing the second via K2 is etched away. The sacrificial layer 25, together with the subsequently deposited gate electrode film, serves as a word line. Therefore, the isolation layer 19 covering the surface of the sacrificial layer 25 is removed to avoid affecting the resistance of the word line 40.

[0198] A gate electrode thin film is deposited within the second via K2 to form the second portion 402 of the word line 40, as shown below. Figure 11A , Figure 11B , Figure 11C As shown, where, Figure 11A A schematic cross-sectional view (film layer containing conductive layer 12) provided for an exemplary embodiment after the formation of the isolation layer 19 and the second portion 402 of the word line along a direction parallel to the substrate. Figure 11B A schematic diagram along the aa' direction after the formation of the isolation layer 19 and the second portion 402 of the word line, as provided in an exemplary embodiment. Figure 11C This is a schematic diagram along the cc' direction after the formation of the isolation layer 19 and the second portion 402 of the word line 40, as provided for an exemplary embodiment. The second portion 402 of the word line 40 fills the second via K2. The second portion 402 of the word line 40 and the first portion 401 of the word line 40 (i.e., the previously retained holding layer 25) together form the word line 40. In this embodiment, the isolation layer 19 can isolate the semiconductor layer 23 and the subsequently deposited second portion 402 of the word line 40.

[0199] In some embodiments, the isolation layer film can be deposited via ALD.

[0200] In some embodiments, the insulating layer film may include, but is not limited to, silicon oxides, such as SiO2.

[0201] In some embodiments, the gate electrode film can be deposited by ALD.

[0202] In some embodiments, the gate electrode thin film can be one or more of the following different types of materials:

[0203] For example, it contains metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, and cobalt; it can also be a metal alloy containing these metals.

[0204] Alternatively, it can be metal oxides, metal nitrides, metal silicides, metal carbides, etc., such as highly conductive metal oxide materials like indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (InO), and aluminum-doped zinc oxide (AZO); or metal nitride materials like titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), and titanium aluminum nitride (TiAlN).

[0205] Alternatively, it could be polycrystalline silicon, conductive doped semiconductor materials, such as conductive doped silicon, conductive doped germanium, conductive doped silicon-germanium, etc.; or other materials that exhibit conductivity.

[0206] 11) Forming a third insulating layer 14;

[0207] The formation of the third insulating layer 14 may include: etching the second insulating layer 13 located in the plurality of trenches T1 of the active region 100, depositing a third insulating film filling the plurality of trenches T1 of the active region 100, and forming the third insulating layer 14, as shown below. Figure 12A , Figure 12B and Figure 12C As shown, where, Figure 12A A schematic cross-sectional view (film layer containing conductive layer 12) provided for an exemplary embodiment after the formation of the third insulating layer 14 along a direction parallel to the substrate. Figure 12B A schematic diagram along the aa' direction after the formation of the third insulating layer 14, provided for an exemplary embodiment. Figure 12C A schematic diagram along the cc' direction after the formation of the third insulating layer 14, provided for an exemplary embodiment.

[0208] In some embodiments, the third insulating film may be a low-K dielectric layer, including but not limited to silicon oxide, such as silicon dioxide (SiO2). The first insulating layer 10 typically uses a low-K dielectric layer, and the second insulating layer 13 uses a material with a higher etching selectivity than the first insulating layer 10, which may result in a larger parasitic capacitance. Therefore, replacing the second insulating layer 13 with a third insulating layer 14 made of a low-K material can reduce the parasitic capacitance.

[0209] The manufacturing method provided in this embodiment uses fewer photomasks, and the structure reduces the lateral etching process and support process. In another embodiment, the active area pattern and the letter line pattern are formed in one process, avoiding multiple etchings of the stacked structure, simplifying the process and reducing costs.

[0210] In some embodiments, the third insulating film may be made of the same material as the first insulating film, but is not limited thereto; the third insulating film may be made of a different material than the first insulating film.

[0211] This disclosure provides a method for manufacturing a semiconductor device, the semiconductor device comprising: a plurality of memory cells stacked along a direction perpendicular to a substrate and word lines extending along a direction perpendicular to the substrate through different layers; each memory cell includes a transistor and a capacitor connected to the transistor, the plurality of transistors of the plurality of memory cells being distributed in the different layers stacked along a direction perpendicular to the substrate; each transistor includes a first electrode and a second electrode, and the method for manufacturing the semiconductor device may include:

[0212] A substrate is provided, the substrate including an active region and a capacitor region disposed on at least one side of the active region, and a plurality of stacked structures are formed by sequentially and alternately depositing a first insulating film and a first conductive film on the active region and the capacitor region of the substrate, each of the stacked structures including a stack of alternately disposed first insulating layers and conductive layers.

[0213] The plurality of stacked structures are etched to form trenches, a plurality of first vias, and a plurality of second vias penetrating the plurality of stacked structures. The trenches cause the first insulating layer and the conductive layer to form a preset pattern. The preset pattern of the conductive layer includes a first electrode and a second electrode of the transistor to be formed, and a first electrode of the capacitor, with the first electrode connected to the first electrode. Each first electrode is provided with at least one first via penetrating the first electrode, and each first electrode is provided with a second via. The first via is located in the capacitor region, and the second via is located in the active region.

[0214] A second insulating film is deposited to fill the trenches, the plurality of first through holes, and the plurality of second through holes to form a second insulating layer; the second insulating film is different from the first insulating film;

[0215] The second insulating layer in the trench located in the capacitor region is etched away to expose the sidewall of the first electrode, and the second insulating layer in the plurality of first vias is etched away.

[0216] A dielectric film and a second conductive film are sequentially deposited on the substrate. The dielectric film and the second conductive film located in the active region are etched away to form a dielectric layer and a second electrode of the capacitor located in the capacitor region. The second electrode fills the second via and the trench located in the capacitor region. The dielectric layer is disposed between the second electrode and the first electrode.

[0217] The second insulating layer located in the second via is etched away, and the word line extending along the direction perpendicular to the substrate is formed in the second via, as well as the plurality of semiconductor layers surrounding the sidewalls of the word line of the plurality of transistors.

[0218] The semiconductor device manufacturing method provided in this embodiment can form cylindrical capacitors, increase the capacitor area, and form capacitor patterns, active area patterns, and word line patterns in one step, avoiding multiple etching of stacked structures, simplifying the process, and reducing costs.

[0219] In some embodiments, a word line extending along a direction perpendicular to the substrate is formed within the second via, and a plurality of semiconductor layers surrounding the sidewalls of the word line of the plurality of transistors comprises:

[0220] The conductive layer is etched laterally by wet etching, such that the orthographic projection of the second via located in the first insulating layer falls into the orthographic projection of the second via located in the conductive layer on a plane parallel to the substrate, and the second via disconnects the first electrode and the second electrode in the preset pattern.

[0221] A semiconductor thin film and a gate insulating film are sequentially deposited in the second via to form a multilayer semiconductor layer and a gate insulating layer of the transistor, wherein the semiconductor layer is connected to the first electrode and the second electrode;

[0222] A third conductive film is deposited in the second via to form a sacrificial layer, the sacrificial layer covering the gate insulating layer;

[0223] Etch a portion of the sacrificial layer within the second via, such that the sidewall of the second via located in the first insulating layer exposes the gate insulating layer, and the sidewall of the second via located in the conductive layer exposes the sacrificial layer;

[0224] Etching removes the semiconductor layer and the gate insulating layer located within the second via of the first insulating layer;

[0225] A gate electrode film is deposited in the second via, and the gate electrode film fills the second via to form the word line.

[0226] In some embodiments, etching a portion of the sacrificial layer within the second via, such that the sidewall of the second via located in the insulating layer exposes the gate insulating layer, and the sidewall of the second via located in the conductive layer exposes the sacrificial layer, may include:

[0227] By wet etching the sacrificial layer within the second via, the sidewall of the second via located in the insulating layer is exposed to the gate insulating layer;

[0228] The semiconductor layer and the gate insulating layer located within the second via of the insulating layer are removed by wet etching.

[0229] In some embodiments, after etching away the semiconductor layer and the gate insulating layer located within the second via of the insulating layer, and before depositing a gate electrode film within the second via, the process may further include:

[0230] A third insulating film is deposited in the second through-hole to form an isolation layer;

[0231] The isolation layer covering the sacrificial layer is etched away.

[0232] In some embodiments, after forming the word line extending along a direction perpendicular to the substrate within the second via, and after the plurality of semiconductor layers surrounding the sidewalls of the word line of the plurality of transistors, the following may be included:

[0233] The second insulating layer located in the trench of the active region is etched, and a third insulating film is deposited to fill the trench of the active region to form the third insulating layer.

[0234] This disclosure also provides an electronic device, including the semiconductor device described in any of the foregoing embodiments or a semiconductor device formed by the manufacturing method of the semiconductor device described in any of the foregoing embodiments. The electronic device may be a storage device, smartphone, computer, tablet computer, artificial intelligence device, wearable device, or power bank, etc. The storage device may include memory in a computer, etc., and is not limited thereto.

[0235] While the embodiments disclosed in this invention are as described above, the content is merely for the purpose of facilitating understanding of the invention and is not intended to limit the invention. Any person skilled in the art to which this invention pertains may make any modifications and changes to the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this invention shall still be determined by the scope defined in the appended claims.

Claims

1. A semiconductor device, characterized in that, The semiconductor device includes: Multiple memory cells stacked along a vertical substrate direction; each memory cell includes a transistor and a capacitor connected to the transistor, and the multiple transistors of the multiple memory cells are distributed in different layers and stacked along a vertical substrate direction; Word lines extending along the direction perpendicular to the substrate through the different layers; The transistor includes a first electrode, a second electrode, and a semiconductor layer surrounding the word line sidewall; the capacitor includes a first electrode and a second electrode, the first electrode being connected to the first electrode; the first electrodes of the multiple capacitors of the multiple memory cells are distributed in different layers and stacked along the direction perpendicular to the substrate. The semiconductor device further includes: at least one first through-hole through the first electrode in different layers, the second electrode including a vertical portion extending perpendicular to the substrate direction disposed in the first through-hole, and a surrounding portion enclosing the end face of the first electrode away from the word line and a sidewall perpendicular to the substrate direction adjacent to the end face, wherein the first electrode completely surrounds the vertical portion, and an insulating layer is filled between adjacent first electrodes perpendicular to the substrate direction.

2. The semiconductor device according to claim 1, characterized in that, The semiconductor device includes a plurality of first vias penetrating the same first electrode, and the plurality of first vias penetrating the same first electrode are arranged along the extension direction of the first electrode.

3. The semiconductor device according to claim 1, characterized in that, The first pole and the first electrode are connected to form an integral structure.

4. The semiconductor device according to claim 1, characterized in that, The plurality of semiconductor layers of the plurality of transistors are spaced apart, and the plurality of semiconductor layers distributed along a direction perpendicular to the substrate are distributed in different regions of the word line sidewall.

5. The semiconductor device according to claim 1, characterized in that, The transistor further includes: a gate insulating layer disposed between the word line and the semiconductor layer surrounding the sidewall of the word line; The semiconductor device further includes: An insulating layer and a conductive layer are alternately distributed from bottom to top along the direction perpendicular to the substrate; A second via penetrating each of the insulating layers and each of the conductive layers, wherein the word line, the gate insulating layer surrounding the sidewall of the word line, and the plurality of semiconductor layers surrounding different regions of the sidewall of the gate insulating layer are distributed sequentially from the inside to the outside in the second via; The plurality of semiconductor layers extend along a direction perpendicular to the substrate and are broken at the sidewalls of the insulating layer; the conductive layer includes the first electrode and the second electrode.

6. The semiconductor device according to claim 5, characterized in that, The diameter of the second through-hole corresponding to the first region of the conductive layer is larger than the diameter of the second region corresponding to the insulating layer; The conductive layer is exposed on the sidewall inside the second through hole, and the insulating layer is exposed on the sidewall and a portion of the upper and lower surfaces of the second through hole. The semiconductor layer is distributed on the sidewall of the conductive layer, and in portions of the upper and lower surfaces of the insulating layer exposed in the second via, but not on the sidewall of the insulating layer.

7. The semiconductor device according to claim 6, characterized in that, The gate insulating layer is distributed on the surface of each semiconductor layer but not on the sidewall of the insulating layer, and the gate insulating layers on the surfaces of different semiconductor layers are spaced apart from each other.

8. The semiconductor device according to claim 7, characterized in that, The word line includes a second portion extending along the second via and a first portion located on the sidewall of each of the gate insulating layers.

9. The semiconductor device according to claim 6, characterized in that, The contact area between the conductive layer and the insulating layer is laterally etched to form a recessed area along the lateral direction. An isolation layer is disposed in the recessed area, and the isolation layer is distributed on the surface of the semiconductor layer and the surface of the gate insulating layer.

10. A method for manufacturing a semiconductor device, characterized in that, The semiconductor device includes: a plurality of memory cells stacked along a direction perpendicular to a substrate and word lines extending through different layers along a direction perpendicular to the substrate; each memory cell includes a transistor and a capacitor connected to the transistor, and the plurality of transistors of the plurality of memory cells are distributed in the different layers stacked along a direction perpendicular to the substrate; each transistor includes a first electrode and a second electrode, and the method for manufacturing the semiconductor device includes: A substrate is provided, the substrate including an active region and a capacitor region disposed on at least one side of the active region, and a plurality of stacked structures are formed by sequentially and alternately depositing a first insulating film and a first conductive film on the active region and the capacitor region of the substrate, each of the stacked structures including a stack of alternately disposed first insulating layers and conductive layers. The plurality of stacked structures are etched to form trenches, a plurality of first vias, and a plurality of second vias penetrating the plurality of stacked structures. The trenches cause the first insulating layer and the conductive layer to form a preset pattern. The preset pattern of the conductive layer includes a first electrode and a second electrode of the transistor to be formed, and a first electrode of the capacitor, with the first electrode connected to the first electrode. Each first electrode is provided with at least one first via penetrating the first electrode, and the first electrode surrounds the first via. Each first electrode is provided with a second via. The first via is located in the capacitor region, and the second via is located in the active region. A second insulating film is deposited to fill the trenches, the plurality of first through holes, and the plurality of second through holes to form a second insulating layer; the second insulating film is different from the first insulating film; The second insulating layer in the trench located in the capacitor region is etched away to expose the sidewall of the first electrode, and the second insulating layer in the plurality of first vias is etched away. A dielectric film and a second conductive film are sequentially deposited on the substrate. The dielectric film and the second conductive film located in the active region are etched away to form a dielectric layer and a second electrode of the capacitor located in the capacitor region. The second electrode fills the first via and the trench located in the capacitor region. The dielectric layer is disposed between the second electrode and the first electrode. The second insulating layer located in the second via is etched away, and the word line extending along the direction perpendicular to the substrate is formed in the second via, as well as the plurality of semiconductor layers surrounding the sidewalls of the word line of the plurality of transistors.

11. The method for manufacturing a semiconductor device according to claim 10, characterized in that, The word line is formed within the second via, extending along a direction perpendicular to the substrate, and the plurality of semiconductor layers surrounding the sidewalls of the word line of the plurality of transistors include: The conductive layer is etched laterally by wet etching, such that the orthographic projection of the second via located in the first insulating layer falls into the orthographic projection of the second via located in the conductive layer on a plane parallel to the substrate, and the second via disconnects the first electrode and the second electrode in the preset pattern. A semiconductor thin film and a gate insulating film are sequentially deposited in the second via to form a multilayer semiconductor layer and a gate insulating layer of the transistor, wherein the semiconductor layer is connected to the first electrode and the second electrode; A third conductive film is deposited in the second via to form a sacrificial layer, the sacrificial layer covering the gate insulating layer; Etch a portion of the sacrificial layer within the second via, such that the sidewall of the second via located in the first insulating layer exposes the gate insulating layer, and the sidewall of the second via located in the conductive layer exposes the sacrificial layer; Etching removes the semiconductor layer and the gate insulating layer located within the second via of the first insulating layer; A gate electrode film is deposited in the second via, and the gate electrode film fills the second via to form the word line.

12. The method for manufacturing a semiconductor device according to claim 11, characterized in that, The etching of a portion of the sacrificial layer within the second via, such that the sidewalls of the second via located in the insulating layer expose the gate insulating layer, and the sidewalls of the second via located in the conductive layer expose the sacrificial layer, comprises: By wet etching the sacrificial layer within the second via, the sidewall of the second via located in the insulating layer is exposed to the gate insulating layer; The semiconductor layer and the gate insulating layer located within the second via of the insulating layer are removed by wet etching.

13. The method for manufacturing a semiconductor device according to claim 12, characterized in that, After etching away the semiconductor layer and the gate insulating layer located within the second via of the insulating layer, and before depositing a gate electrode thin film within the second via, the method further includes: A third insulating film is deposited in the second through-hole to form an isolation layer; The isolation layer covering the sacrificial layer is etched away.

14. The method for manufacturing a semiconductor device according to claim 11, characterized in that, After forming the word line extending along the perpendicular direction to the substrate within the second via, and after the plurality of semiconductor layers surrounding the sidewalls of the word line of the plurality of transistors, the method further includes: The second insulating layer located in the trench of the active region is etched, and a third insulating film is deposited to fill the trench of the active region to form the third insulating layer.

15. An electronic device, characterized in that, It includes the semiconductor device as described in any one of claims 1 to 9, or the semiconductor device formed by the manufacturing method of the semiconductor device as described in any one of claims 10 to 14.

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