Semiconductor device and preparation method thereof, and memory system

Abstract

The invention provides a semiconductor device and a preparation method thereof and a memory system, and the semiconductor device comprises a first semiconductor structure, and the first semiconductor structure comprises a first transistor which comprises a first grid electrode, a first channel and a first drain electrode; the first grid electrode extends along a first direction; the capacitor structure comprises a first electrode layer extending along a first direction; the capacitor structure and the first transistor are stacked in the first direction, one end of the first electrode layer is connected with the first grid electrode, the first channel surrounds the first grid electrode, and the first drain electrode is located on the side, away from the capacitor structure, of the first channel in the first direction and connected with the surface, away from the first grid electrode, of the first channel. According to the semiconductor device, the preparation method thereof and the memory system provided by the invention, the stability and performance of the semiconductor device can be improved.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor devices, and in particular to a semiconductor device and a method for manufacturing the same, as well as a memory system. Background Art

[0002] Planar memory devices have reached their practical expansion limit. In order to further increase storage capacity and reduce storage cost per bit, three-dimensional memory has been proposed.

[0003] The preparation process and structure of three-dimensional memory need to be further optimized to improve the stability and performance of three-dimensional memory. Summary of the invention

[0004] In view of this, the present application provides a semiconductor device and a manufacturing method thereof, as well as a memory system that can solve the above-mentioned technical problems.

[0005] To solve the above problems, the technical solutions provided by this application are as follows:

[0006] The present application provides a semiconductor device, which includes a first semiconductor structure, wherein the first semiconductor structure includes: a first transistor, including a first gate, a first channel and a first drain; the first gate extends along a first direction; and a capacitor structure, including a first electrode layer, the first electrode layer extends along the first direction; wherein the capacitor structure and the first transistor are stacked in the first direction, one end of the first electrode layer is connected to the first gate of the first transistor, the first channel surrounds the first gate, and the first drain is located on a side of the first channel away from the capacitor structure in the first direction and is connected to a surface of the first channel away from the first gate.

[0007] In some embodiments, the first channel includes a first channel portion and a second channel portion, and the second channel portion is connected to an end of the first channel portion away from the capacitor structure;

[0008] The first drain is located on a side of the second channel portion away from the first gate.

[0009] In some embodiments, the first transistor further includes a first gate insulating layer, wherein the first gate insulating layer is located between the first channel and the first gate;

[0010] The first gate includes a first gate portion and a second gate portion connected to the first gate portion in the first direction;

[0011] The first gate portion is connected to the capacitor structure, and a width of the first gate portion in a second direction perpendicular to the first direction is greater than a width of the second gate portion in the second direction;

[0012] The first gate insulating layer covers the second gate portion and the surface of the first gate portion away from the capacitor structure, the end of the first channel portion away from the second channel portion is located on the first gate insulating layer connected to the first gate portion, and the second channel portion is located on the first gate insulating layer connected to the end of the second gate portion away from the first gate portion.

[0013] In some embodiments, the first semiconductor structure further comprises:

[0014] A first stacked structure includes a source line; the source line extends along a second direction perpendicular to the first direction; and

[0015] A first channel structure, located in the first stacked structure and passing through the source line;

[0016] Among them, the first drain is located on a side of the first channel structure away from the capacitor structure, the first channel structure includes the first gate and the first channel, the source line is connected to the first channel in the second direction, and the first transistor includes the source line and the first channel structure.

[0017] In some embodiments, the first stacking structure further includes:

[0018] a first insulating layer; and

[0019] a second insulating layer;

[0020] The source line is located between the first insulating layer and the second insulating layer, and the first channel structure penetrates the first insulating layer, the source line and the second insulating layer;

[0021] A surface of the first channel extending in the first direction contacts the first insulating layer, the source line, and a portion of the second insulating layer, and a portion of the first gate contacts the second insulating layer.

[0022] In some embodiments, the first semiconductor structure further comprises:

[0023] a first bit line extending along a third direction perpendicular to the first direction and intersecting the second direction and located at a side of the first drain away from the capacitor structure;

[0024] The extending direction of the first bit line is perpendicular to the extending direction of the source line, and one of the first drains is connected to one of the first bit lines.

[0025] In some embodiments, the first semiconductor structure further comprises:

[0026] A second stacking structure comprises a second electrode layer and a third insulating layer; one second electrode layer is located between two adjacent third insulating layers, and one third insulating layer is located on a side of the first stacking structure away from the first drain electrode; and

[0027] An energy storage structure, which penetrates the second electrode layer; the energy storage structure includes the first electrode layer and the energy storage layer;

[0028] The second electrode layer is arranged around the energy storage layer, the energy storage layer is arranged around the first electrode layer, and the capacitor structure includes the first electrode layer, the energy storage layer and the second electrode layer.

[0029] In some embodiments, the first semiconductor structure further comprises:

[0030] A second transistor comprising a channel layer; the channel layer extends along the first direction;

[0031] The second transistor is located at a side of the capacitor structure away from the first transistor, and one end of the first electrode layer away from the first transistor is connected to the channel layer of the second transistor.

[0032] In some embodiments, the first semiconductor structure further comprises:

[0033] A third stacking structure is located on a side of the second stacking structure away from the first stacking structure; the third stacking structure comprises a word line and a fourth insulating layer extending along the second direction, the word line is located between two adjacent fourth insulating layers, and one of the fourth insulating layers is connected to one of the third insulating layers; and

[0034] A second channel structure is located in the third stacked structure and runs through the word line;

[0035] The second channel structure includes the channel layer and a second gate insulating layer, one end of the channel layer is connected to an end of the first electrode layer of the capacitor structure away from the first gate, and the second gate insulating layer surrounds the channel layer and contacts the word line;

[0036] The second transistor includes the word line and the second channel structure.

[0037] In some embodiments, the first semiconductor structure further comprises:

[0038] A second bit line extending along a third direction perpendicular to the first direction and intersecting the second direction and located at a side of the channel layer away from the capacitor structure;

[0039] The extension direction of the second bit line is perpendicular to the extension direction of the source line, and one of the second bit lines is connected to one end of the channel layer away from the capacitor structure.

[0040] In some embodiments, the semiconductor device further comprises:

[0041] A second semiconductor structure having a circuit element for controlling the first semiconductor structure and located at a side of the first semiconductor structure away from the first stacked structure;

[0042] The second semiconductor structure is bonded to the first semiconductor structure in the first direction.

[0043] In some embodiments, the semiconductor device further comprises:

[0044] The connecting portion connects one of the first transistor and the second transistor and connects the second semiconductor structure.

[0045] In some embodiments, the first transistor is configured to be turned on or off according to the storage content of the capacitor structure and allow the storage content of the capacitor structure to be read, and the second transistor is configured to be turned on or off according to the written content and allow the write voltage to flow into the capacitor structure through the second transistor.

[0046] The present application also provides a method for preparing a semiconductor device, comprising:

[0047] forming a first stack structure having an intermediate state transistor, and making the intermediate state transistor include a first gate and a first channel surrounding the first gate;

[0048] forming a second stacking structure having a capacitor structure on one side of the first stacking structure, and making the capacitor structure include a first electrode layer, and the first gate is connected to one end of the first electrode layer; and

[0049] A first drain is formed on a side of the first stacking structure away from the second stacking structure to obtain a first transistor, and the first drain is connected to the first channel; the first transistor includes the intermediate state transistor and the first drain.

[0050] In some embodiments, before the step of forming a first drain on a side of the first stack structure away from the second stack structure, the method further includes:

[0051] A third stack structure having a second transistor is formed on a side of the second stack structure away from the first stack structure, and the second transistor includes a channel layer connected to an end of the first electrode layer away from the first gate.

[0052] In some embodiments, before the step of forming the first stacked structure, the method further includes: providing a substrate; forming the first stacked structure on the substrate;

[0053] Wherein, the second stacking structure is located on a side of the first stacking structure away from the substrate; before forming the first drain, the method further includes:

[0054] The substrate is removed.

[0055] In some embodiments, the step of forming a first stack structure having an intermediate state transistor includes:

[0056] forming a first insulating layer, a source line and a second insulating layer on the substrate along a stacking direction of the first stacking structure and the second stacking structure to obtain the first stacking structure;

[0057] forming a first channel hole penetrating the first stack structure on the first stack structure; and

[0058] Filling the first channel hole with a channel material to obtain a first channel structure, wherein the first channel structure includes the first gate, the first channel, and a first gate insulating layer located between the first gate and the first channel;

[0059] The first transistor includes the first channel structure and the source line.

[0060] In some embodiments, the step of filling the channel hole with a channel material to obtain the first channel structure includes:

[0061] forming an intermediate channel layer on the inner wall of the first channel hole and on the surface of the first stacked structure away from the substrate;

[0062] forming an intermediate gate insulating layer covering the intermediate channel layer;

[0063] forming an intermediate gate layer covering the intermediate gate insulating layer;

[0064] Patterning the intermediate state channel layer, the intermediate state gate insulating layer and the intermediate state gate layer to obtain a first channel, a first gate insulating layer and a first gate, and to obtain a first channel structure including the first channel, the first gate insulating layer and the first gate; and

[0065] A fifth insulating layer covering the second insulating layer is formed on the second insulating layer, and a portion of the first channel structure protruding from the second stacked structure is located in the fifth insulating layer.

[0066] In some embodiments, after the step of forming a first drain on a side of the first stack structure away from the second stack structure and connecting the first drain to the first channel, the method further includes:

[0067] A first bit line is formed on a side of the first drain away from the second stack structure, and each of the first bit lines is connected to one of the first drains.

[0068] In some embodiments, after the step of forming a third stack structure having a second transistor on a side of the second stack structure away from the first stack structure, the method further includes:

[0069] A second bit line is formed on a side of the third stacking structure away from the second stacking structure, and the second bit line is connected to the second transistor to obtain a first semiconductor structure.

[0070] In some embodiments, after the step of forming a second bit line on a side of the third stacked structure away from the second stacked structure and connecting the second bit line to the second transistor to obtain the first semiconductor structure, the step further includes:

[0071] forming a second semiconductor structure bonded to the first semiconductor structure on a side of the second bit line away from the third stacked structure; and

[0072] A connection portion is formed that connects the second semiconductor structure and connects one of the first transistor and the second transistor.

[0073] The present application also provides a memory system, comprising: at least one semiconductor device as described above; and a controller configured to control the semiconductor device.

[0074] The semiconductor device and its preparation method and memory system provided by the present application are formed by first forming a first stacking structure on a substrate, then forming an intermediate state transistor (vertical transistor) including a source line, a first gate and a first channel in the first stacking structure, and then forming a capacitor structure on the first stacking structure. After removing the substrate, a first drain is formed on the side of the first stacking structure away from the capacitor structure. The first drain, the source line, the first gate and the first channel constitute a first transistor. The present application forms an intermediate state transistor (vertical transistor) including a source line, a first gate and a first channel on a substrate, and then removes the substrate to form a first drain on one side of the capacitor structure. The temperature selection when manufacturing the intermediate state transistor is not affected by other process flows, and the preparation process and structure of the semiconductor device are further optimized, which can improve the stability and performance of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0075] In order to more clearly illustrate the technical solutions in some embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without paying any creative work.

[0076] Figure 1 A flow chart of a method for preparing a semiconductor structure provided in some embodiments of the present application.

[0077] Figure 2 A cross-sectional view of a first stacked structure including an intermediate state transistor provided in the present application.

[0078] Figure 3 Preparation provided for some embodiments of the present application Figure 2 Flowchart of the intermediate state transistor shown.

[0079] Figure 4 A cross-sectional view of a first stacking structure provided in some embodiments of the present application.

[0080] Figure 5 For Figure 4 A cross-sectional view of the first stacked structure after a first channel hole is formed is shown.

[0081] Figure 6 For Figure 5 A cross-sectional view is shown after an intermediate channel layer is formed in the first channel hole.

[0082] Figure 7 For Figure 6 A cross-sectional view showing a structure after an intermediate gate insulating layer is formed on the intermediate channel layer.

[0083] Figure 8 For Figure 7 A cross-sectional view is shown after an intermediate gate is formed on the intermediate gate insulating layer.

[0084] Fig. 9 For patterning Figure 8 The intermediate state channel layer, the intermediate state gate insulating layer and the intermediate state gate are shown, and a cross-sectional view after obtaining the intermediate state transistor.

[0085] Fig.10 For Figure 2 The schematic diagram shows a first stacking structure formed on a side away from the substrate and including a capacitor structure.

[0086] Fig.11 For Fig.10 A cross-sectional view of a third stack structure including a second transistor formed on the second stack structure.

[0087] Fig.12 for Fig.11 A cross-sectional view of the intermediate state transistor, the capacitor structure and the second transistor is shown.

[0088] Fig.13 For Fig.11 The third stacked structure is shown as a cross-sectional view after a second semiconductor structure is formed on a side away from the capacitor structure.

[0089] Fig.14 To remove Fig.13 The substrate shown forms a first drain on a side of the first stacked structure away from the capacitor structure, thereby obtaining a first transistor, a first semiconductor structure, and a cross-sectional view of the semiconductor structure.

[0090] Fig.15 for Fig.14 A cross-sectional view of the first transistor is shown.

[0091] Fig.16 A module diagram of a memory system provided for some embodiments of the present application. DETAILED DESCRIPTION

[0092] The following will be combined with the drawings in some embodiments of the present application to clearly and completely describe the technical solutions in some embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of this application.

[0093] In the description of the present application, it should be understood that the orientation or positional relationship indicated by the terms "upper", "lower", etc. is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0094] In the description of the present application, it is to be understood that the term "layer" refers to a portion of a material including an area having a thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range that is less than the range of a lower or upper structure. In addition, a layer may be a region of a homogeneous or inhomogeneous continuous structure having a thickness less than the thickness of a continuous structure. A layer may extend horizontally, vertically and / or along an inclined surface. A layer may include multiple sublayers. For example, an interconnect layer may include one or more conductor and contact sublayers (where interconnects and / or via contacts are formed), and one or more dielectric sublayers.

[0095] The present application may repeat reference numerals and / or reference letters in different implementations. Such repetition is for the purpose of simplicity and clarity and does not in itself indicate the relationship between the various implementations and / or settings discussed.

[0096] The present application aims at the technical problems that need to be optimized in the preparation process and structure of a three-dimensional memory, and provides a semiconductor device, a preparation method thereof, and a memory system, by first forming a first stacking structure on a substrate, then forming an intermediate state transistor (vertical transistor) including a source line, a first gate, and a first channel in the first stacking structure, and then forming a capacitor structure on the first stacking structure, after removing the substrate, and then forming a first drain on the side of the first stacking structure away from the capacitor structure, and the first drain, the source line, the first gate, and the first channel constitute a first transistor. The present application first forms an intermediate state transistor (vertical transistor) including a source line, a first gate, and a first channel on a substrate, and then removes the substrate to form a first drain on one side of the capacitor structure. The selection of the temperature when manufacturing the intermediate state transistor is not affected by other process flows, and the preparation process and structure of the semiconductor device are further optimized, which can improve the stability and performance of the semiconductor device.

[0097] The following will be combined Figures 1 to 15 , the structure of the semiconductor device 100 and the method for manufacturing the semiconductor device 100 are specifically described.

[0098] See also Figures 1 to 15 Some embodiments of the present application provide a method for preparing a semiconductor device 100, including:

[0099] Step S1, see Figure 1 to Figure 2 , forming a first stacked structure 20 having an intermediate state transistor 111, and making the intermediate state transistor 111 include a first gate 31 and a first channel 32 surrounding the first gate 31.

[0100] Before step S1, the method for preparing the semiconductor device 100 further includes providing a substrate 10. The first stacked structure 20 is formed on the substrate 10. The substrate 10 and the first stacked structure 20 are stacked in a first direction Z.

[0101] The first stacked structure 20 includes a first insulating layer 21, a second insulating layer 22 and a source line 23. The first insulating layer 21 is located on the substrate 10. The source line 23 is located between the first insulating layer 21 and the second insulating layer 22 and extends along a second direction X perpendicular to the first direction Z.

[0102] In some embodiments, the constituent material of the substrate 10 includes a single semiconductor material (such as silicon, germanium), a III-V compound semiconductor material, a II-VI compound semiconductor material, an organic semiconductor material, a silicon-on-insulator (SOI) or other semiconductor materials known in the art or inorganic materials such as glass and ceramics. In this embodiment, the substrate 10 is a silicon substrate.

[0103] In some embodiments, the constituent materials of the first insulating layer 21 and the second insulating layer 22 include insulating materials such as silicon oxide, silicon nitride or silicon oxynitride. In this embodiment, the constituent material of the first insulating layer 21 and the second insulating layer 22 is silicon oxide.

[0104] In some embodiments, the source line 23 is made of a conductive material, such as single crystal silicon, polycrystalline silicon, doped single crystal silicon, doped polycrystalline silicon, tungsten, copper, aluminum, platinum, titanium or ruthenium.

[0105] Specifically, step S1 includes:

[0106] Step S11, see Figure 3 to Figure 4 , a first insulating layer 21 , a source line 23 and a second insulating layer 22 are formed on the substrate 10 along the first direction Z to obtain the first stacked structure 20 .

[0107] Step S12, see Figure 3 and Figure 5 , a first channel hole 25 penetrating the first stack structure 20 is formed on the first stack structure 20 .

[0108] The first channel hole 25 penetrates the second insulating layer 22 , the source line 23 , and the first insulating layer 21 to the substrate 10 along the first direction Z.

[0109] Step S13, see Figure 3 and Figures 6 to 9 , a channel material is filled in the first channel hole 25 to obtain a first channel structure 30 , and the first channel structure 30 includes the first gate 31 , the first channel 32 , and a first gate insulating layer 33 located between the first gate 31 and the first channel 32 .

[0110] Specifically, step S13 includes: first, refer to Figure 6 , an intermediate channel layer 26 is formed on the inner wall of the first channel hole 25 and the surface of the first stacked structure 20 away from the substrate 10; secondly, refer to Figure 7 , forming an intermediate gate insulating layer 27 covering the intermediate channel layer 26; again, refer to Figure 8 , forming an intermediate gate layer 28 covering the intermediate gate insulating layer 27; thereafter, referring to Fig. 9 , patterning the intermediate state channel layer 26, the intermediate state gate insulating layer 27 and the intermediate state gate layer 28 to obtain a first channel 32, a first gate insulating layer 33 and a first gate 31, and obtaining a first channel structure 30 including the first channel 32, the first gate insulating layer 33 and the first gate 31; finally, please refer to Fig. 9 , a fifth insulating layer 24 covering the second insulating layer 22 is formed on the second insulating layer 22 , and a portion of the first channel structure 30 protruding from the second stacked structure 40 is located in the fifth insulating layer 24 .

[0111] The step of “patterning the intermediate channel layer 26 , the intermediate gate insulating layer 27 and the intermediate gate layer 28 ” includes: removing part of the intermediate channel layer 26 , part of the intermediate gate insulating layer 27 and part of the intermediate gate layer 28 outside the first channel hole 25 .

[0112] The intermediate state transistor 111 includes the first channel structure 30 and the source line 23 .

[0113] Please refer again Fig. 9 The first gate 31 includes a first gate portion 311 and a second gate portion 312 connected to the first gate portion 311 in the first direction Z. One end of the second gate portion 312 away from the first gate portion 311 is close to the substrate 10. The width of the first gate portion 311 in a second direction X perpendicular to the first direction Z is greater than the width of the second gate portion 312 in the second direction X. That is, the cross section of the first gate 31 in the second direction X is T-shaped. The first gate insulating layer 33 covers the second gate portion 312 and the surface of the first gate portion 311 facing the substrate 10 and not in direct contact with the second gate portion 312.

[0114] The first channel 32 includes a first channel portion 321 and a second channel portion 322, and the second channel portion 322 is connected to an end of the first channel portion 321 away from the first gate portion 311. That is, the first channel 32 is U-shaped. An end of the first channel portion 321 away from the second channel portion 322 is located on the first gate insulating layer 33 connected to the first gate portion 311, and the second channel portion 322 is located on the first gate insulating layer 33 connected to an end of the second gate portion 312 away from the first gate portion 311.

[0115] In some embodiments, the first gate 31 is made of a conductive material, such as single crystal silicon, polycrystalline silicon, doped single crystal silicon, doped polycrystalline silicon, tungsten, copper, aluminum, platinum, titanium or ruthenium.

[0116] In some embodiments, the constituent material of the first channel 32 includes at least one of single crystal silicon, polycrystalline silicon, single crystal germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials and other semiconductor materials.

[0117] In some embodiments, the constituent material of the first gate insulating layer 33 includes insulating materials such as silicon oxide, silicon nitride or silicon oxynitride. In this embodiment, the constituent material of the first gate insulating layer 33 is silicon oxide.

[0118] Step S2, see Figure 1 , Fig.10 and Fig.12 A second stacking structure 40 having a capacitor structure 120 is formed on one side of the first stacking structure 20 , and the capacitor structure 120 includes a first electrode layer 52 , and the first gate 31 is connected to one end of the first electrode layer 52 .

[0119] The second stacking structure 40 includes a third insulating layer 41 and a second electrode layer 42. The third insulating layer 41 and the second electrode layer 42 are alternately stacked in the first direction Z. One second electrode layer 42 is located between two adjacent third insulating layers 41, and one third insulating layer 41 is located on the side of the first stacking structure 20 away from the substrate 10.

[0120] The steps of forming the capacitor structure 120 include: first, forming a second stack structure 40 on one side of the first stack structure 20 ; second, forming an energy storage structure 50 in the second stack structure 40 , and connecting one end of the energy storage structure 50 to the first gate 31 .

[0121] The energy storage structure 50 penetrates the second electrode layer 42 and the third insulating layer 41. The energy storage structure 50 includes the first electrode layer 52 and the energy storage layer 51, the first electrode layer 52 and the energy storage layer 51 both extend along the first direction Z, the second electrode layer 42 is arranged around the energy storage layer 51, the energy storage layer 51 is arranged around the first electrode layer 52, and the capacitor structure 120 includes the first electrode layer 52, the energy storage layer 51 and the second electrode layer 42.

[0122] Step S3, see Figure 1 , Fig.11 and Fig.12 A third stacked structure 60 having a second transistor 130 is formed on the side of the second stacked structure 40 away from the first stacked structure 20 , and the second transistor 130 includes a channel layer 71 connected to an end of the first electrode layer 52 away from the first gate 31 .

[0123] In some embodiments, step S3 may be omitted.

[0124] In some embodiments, the second transistor 130 is configured to be turned on or off according to the written content and allow the written voltage to flow into the capacitor structure 120 through the second transistor 130 .

[0125] The third stacked structure 60 includes a word line 62 and a fourth insulating layer 61 extending along the second direction X. The word line 62 is located between two adjacent fourth insulating layers 61 . One of the fourth insulating layers 61 is connected to one of the third insulating layers 41 .

[0126] Forming the second transistor 130 includes the following steps: first, forming a third stacking structure 60 on the side of the second stacking structure 40 away from the first stacking structure 20; second, forming a second channel structure 70 in the third stacking structure 60 and connecting one end of the second channel structure 70 to one end of the first electrode layer 52 away from the first gate 31.

[0127] The second channel structure 70 penetrates the word line 62 and the fourth insulating layer 61. The second channel structure 70 includes the channel layer 71 and a second gate insulating layer 72, one end of the channel layer 71 is connected to one end of the first electrode layer 52 of the capacitor structure 120 away from the first gate 31, the second gate insulating layer 72 surrounds the channel layer 71 and contacts the word line 62, and the second transistor 130 includes the word line 62 and the second channel structure 70.

[0128] Step S4, see Figure 1 , Fig.11 and Fig.12A second bit line 82 is formed on a side of the third stack structure 60 away from the second stack structure 40 , and the second bit line 82 is connected to the second transistor 130 , thereby obtaining an intermediate semiconductor structure 102 .

[0129] In some embodiments, step S4 may be omitted.

[0130] In some embodiments, the intermediate semiconductor structure 102 further includes a sixth insulating layer 81 . The sixth insulating layer 81 is located on a side of the third stacked structure 60 away from the capacitor structure 120 . The second bit line 82 is located in the sixth insulating layer 81 .

[0131] In some embodiments, the intermediate semiconductor structure 102 further includes a first bonding layer 83 , where the first bonding layer 83 is located on the sixth insulating layer 81 .

[0132] Step S5, see Figure 1 and Fig.13 A second semiconductor structure 103 bonded to the intermediate semiconductor structure 102 in the first direction Z is formed on a side of the second bit line 82 away from the third stacked structure 60 .

[0133] The second semiconductor structure 103 is a peripheral circuit structure for controlling the intermediate semiconductor structure 102 .

[0134] Step S6, see Figure 1 , Fig.14 and Fig.15 A first drain 34 is formed on a side of the first stacking structure 20 away from the second stacking structure 40 to obtain a first transistor 110, and the first drain 34 is connected to the first channel 32. The first transistor 110 includes the intermediate state transistor 111 and the first drain 34.

[0135] In some embodiments, the first transistor 10 is configured to be turned on or off according to the storage content of the capacitor structure 120 and allow the storage content of the capacitor structure 120 to be read.

[0136] Before step S6 , the method for preparing a semiconductor device further includes the step of removing the substrate 10 .

[0137] After step S6 , the method for preparing the semiconductor device further includes the steps of: forming a seventh insulating layer 35 on a side of the first stacking structure 20 away from the second stacking structure 40 , and positioning the first drain electrode 34 in the seventh insulating layer 35 .

[0138] After step S6 , the method for preparing the semiconductor device further includes the steps of forming a first bit line 37 on a side of the first drain 34 away from the second stacked structure 40 to obtain a first semiconductor structure 101 , and connecting each first bit line 37 to one of the first drains 34 .

[0139] In some embodiments, the first semiconductor structure 101 further includes an eighth insulating layer 36 , and the first bit line 37 is located in the eighth insulating layer 36 .

[0140] In some embodiments, the first semiconductor structure 101 further includes a ninth insulating layer 38 . The ninth insulating layer 38 is located on a side of the eighth insulating layer 36 away from the first drain 34 and is used to protect the first bit line 37 .

[0141] See also Fig. 9 , Fig.12 , Fig.14 and Fig.15 The present application also provides a semiconductor device 100, the semiconductor device 100 includes a first semiconductor structure 101, the first semiconductor structure 101 includes: a first transistor 110 and a capacitor structure 120. The first transistor 110 includes a first gate 31, a first channel 32 and a first drain 34, the first gate 31 extends along a first direction Z. The capacitor structure 120 includes a first electrode layer 52, the first electrode layer 52 extends along the first direction Z. The capacitor structure 120 and the first transistor 110 are stacked in the first direction Z, one end of the first electrode layer 52 is connected to the first gate 31 of the first transistor 110, the first channel 32 surrounds the first gate 31, and the first drain 34 is located on a side of the first channel 32 away from the capacitor structure 120 in the first direction Z and is connected to a surface of the first channel 32 away from the first gate 31.

[0142] In some embodiments, the first channel 32 includes a first channel portion 321 and a second channel portion 322 , the second channel portion 322 is connected to an end of the first channel portion 321 away from the capacitor structure 120 , and the first drain 34 is located on a side of the second channel portion 322 away from the first gate 31 .

[0143] In some embodiments, the first transistor 110 further includes a first gate insulating layer 33, and the first gate insulating layer 33 is located between the first channel 32 and the first gate 31. The first gate 31 includes a first gate portion 311 and a second gate portion 312 connected to the first gate portion 311 in the first direction Z. The first gate portion 311 is connected to the capacitor structure 120, and the width of the first gate portion 311 in a second direction X perpendicular to the first direction Z is greater than the width of the second gate portion 312 in the second direction X. The first gate insulating layer 33 covers the second gate portion 312 and the surface of the first gate portion 311 away from the capacitor structure 120, and one end of the first channel portion 321 away from the second channel portion 322 is located on the first gate insulating layer 33 connected to the first gate portion 311, and the second channel portion 322 is located on the first gate insulating layer 33 connected to one end of the second gate portion 312 away from the first gate portion 311.

[0144] In some embodiments, the first semiconductor structure 101 further includes a first stacked structure 20 and a first channel structure 30. The first stacked structure 20 includes a source line 23, the source line 23 extends along the second direction X, and the first channel structure 30 is located in the first stacked structure 20 and penetrates the source line 23. The first drain 34 is located on a side of the first channel structure 30 away from the capacitor structure 120, the first channel structure 30 includes the first gate 31 and the first channel 32, the source line 23 is connected to the first channel 32 in the second direction X, and the first transistor 110 includes the source line 23 and the first channel structure 30.

[0145] In some embodiments, the first stacked structure 20 further includes a first insulating layer 21 and a second insulating layer 22, the source line 23 is located between the first insulating layer 21 and the second insulating layer 22, and the first channel structure 30 penetrates the first insulating layer 21, the source line 23, and the second insulating layer 22. The surface of the first channel 32 extending in the first direction Z is in contact with the first insulating layer 21, the source line 23, and a portion of the second insulating layer 22, and a portion of the first gate 31 is in contact with the second insulating layer 22. Specifically, a portion of the first gate portion 311 is in contact with the second insulating layer 22 on its side in the first direction Z.

[0146] In some embodiments, the first semiconductor structure 101 further includes a first bit line 37, which extends along a third direction Y perpendicular to the first direction Z and intersecting the second direction X and is located on a side of the first drain 34 away from the capacitor structure 120. The extension direction of the first bit line 37 is perpendicular to the extension direction of the source line 23, and one first drain 34 is connected to one first bit line 37.

[0147] In some embodiments, the first semiconductor structure 101 further includes a second stacked structure 40 and an energy storage structure 50. The second stacked structure 40 includes a second electrode layer 42 and a third insulating layer 41, one second electrode layer 42 is located between two adjacent third insulating layers 41, and one third insulating layer 41 is located on the side of the first stacked structure 20 away from the first drain 34. The energy storage structure 50 penetrates the second electrode layer 42, the energy storage structure 50 includes the first electrode layer 52 and the energy storage layer 51, the second electrode layer 42 is arranged around the energy storage layer 51, the energy storage layer 51 is arranged around the first electrode layer 52, and the capacitor structure 120 includes the first electrode layer 52, the energy storage layer 51 and the second electrode layer 42.

[0148] In some embodiments, the first semiconductor structure 101 further includes a second transistor 130 , and the second transistor 130 includes a channel layer 71 , and the channel layer 71 extends along the first direction Z. The second transistor 130 is located on a side of the capacitor structure 120 away from the first transistor 110 , and one end of the first electrode layer 52 away from the first transistor 110 is connected to the channel layer 71 of the second transistor 130 .

[0149] In some embodiments, the first semiconductor structure 101 further includes a third stacked structure 60 and a second channel structure 70. The third stacked structure 60 is located on the side of the second stacked structure 40 away from the first stacked structure 20. The third stacked structure 60 includes a word line 62 and a fourth insulating layer 61 extending along the second direction X. The word line 62 is located between two adjacent fourth insulating layers 61, and one of the fourth insulating layers 61 is connected to one of the third insulating layers 41. The second channel structure 70 is located in the third stacked structure 60 and passes through the word line 62. The second channel structure 70 includes the channel layer 71 and a second gate insulating layer 72. One end of the channel layer 71 is connected to one end of the first electrode layer 52 of the capacitor structure 120 away from the first gate 31. The second gate insulating layer 72 surrounds the channel layer 71 and contacts the word line 62. The second transistor 130 includes the word line 62 and the second channel structure 70.

[0150] In some embodiments, the first semiconductor structure 101 further includes a second bit line 82, which extends along a third direction Y perpendicular to the first direction Z and intersecting the second direction X and is located on a side of the channel layer 71 away from the capacitor structure 120. The extension direction of the second bit line 82 is perpendicular to the extension direction of the source line 23, and one second bit line 82 is connected to one end of the channel layer 71 away from the capacitor structure 120.

[0151] In some embodiments, the semiconductor device 101 further includes a second semiconductor structure 103, wherein the second semiconductor structure 103 has a circuit element 1031 for controlling the first semiconductor structure 101 and is located on a side of the first semiconductor structure 101 away from the first stacked structure 20. The second semiconductor structure 103 is bonded to the first semiconductor structure 101 in the first direction Z.

[0152] In some embodiments, the semiconductor device 101 further includes a connection portion 85 , wherein the connection portion 85 connects the first transistor 110 and one of the second transistor 130 and connects the second semiconductor structure 103 .

[0153] In some embodiments, the first transistor 110 is configured to be turned on or off according to the storage content of the capacitor structure 120 and allow the storage content of the capacitor structure 120 to be read, and the second transistor 130 is configured to be turned on or off according to the written content and allow the write voltage to flow into the capacitor structure 120 through the second transistor 130.

[0154] See also Fig.16 The present application also provides a memory system 1000 , which includes one or more semiconductor devices 100 as described above and a controller 200 , wherein the controller 200 is connected to the semiconductor device 100 , and the controller 200 is configured to control the semiconductor device 100 .

[0155] The memory system 1000 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory therein. The controller may be configured to control operations of the semiconductor device, such as read, erase, and program operations.

[0156] In some embodiments, the controller is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, etc.

[0157] In some embodiments, the controller is designed to operate in a high duty cycle environment Solid State Disk (SSD) or Embedded Multi Media Card (eMMC), which is used as data storage for mobile devices such as smart phones, tablet computers, laptop computers, etc., as well as enterprise storage arrays.

[0158] The semiconductor device and its preparation method and memory system provided by the present application are formed by first forming a first stacking structure on a substrate, then forming an intermediate state transistor (vertical transistor) including a source line, a first gate and a first channel in the first stacking structure, and then forming a capacitor structure on the first stacking structure. After removing the substrate, a first drain is formed on the side of the first stacking structure away from the capacitor structure. The first drain, the source line, the first gate and the first channel constitute a first transistor. The present application forms an intermediate state transistor (vertical transistor) including a source line, a first gate and a first channel on a substrate, and then removes the substrate to form a first drain on one side of the capacitor structure. The selection of the temperature when manufacturing the intermediate state transistor is not affected by other process flows, and the preparation process and structure of the semiconductor device are further optimized, which can improve the stability and performance of the semiconductor device.

[0159] In addition, compared to using a back-side process (first forming a capacitor structure on a substrate, then bonding it to a second semiconductor structure including a peripheral circuit, then removing the substrate, and finally forming a transistor on the side of the capacitor structure away from the second semiconductor structure) to manufacture the first transistor, the selection of the manufacturing temperature of the intermediate state transistor of the semiconductor device obtained by the semiconductor device preparation method provided in the present application will not be affected by the temperature of the capacitor structure manufacturing process and the bonding process, and a temperature higher than the bonding process temperature can be selected, and the first transistor can withstand higher temperatures.

[0160] In addition, when the first transistor is made by the backside process, after removing the substrate, a punching process is required to remove part of the insulating layer (for example, the oxide layer, etc.) to expose the inner electrode of the capacitor structure, and the process is relatively complicated. However, the first transistor prepared by the method for preparing a semiconductor device provided by the present application does not require a punching process, and the preparation process is relatively simple. The preparation process and structure of the semiconductor device are further optimized, which can improve the stability and performance of the semiconductor device.

[0161] In addition, since the preparation method of the semiconductor device provided in the present application is to first produce an intermediate state transistor (the first transistor excluding the drain) and then produce a capacitor structure, the first gate of the intermediate state transistor can also serve as a stop layer when etching the capacitor structure. The preparation process is relatively simple, and the preparation process and structure of the semiconductor device are further optimized, which can improve the stability and performance of the semiconductor device.

[0162] In summary, although the present application has been disclosed as above with preferred embodiments, the above preferred embodiments are not intended to limit the present application. Ordinary technicians in this field can make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be based on the scope defined in the claims.

Claims

1. A semiconductor device comprising a first semiconductor structure, characterized in that: The first semiconductor structure comprises: A first transistor includes a first gate, a first channel and a first drain; the first gate extends along a first direction; and A capacitor structure, comprising a first electrode layer, wherein the first electrode layer extends along the first direction; Among them, the capacitor structure and the first transistor are stacked in the first direction, one end of the first electrode layer is connected to the first gate of the first transistor, the first channel surrounds the first gate, and the first drain is located on the side of the first channel away from the capacitor structure in the first direction and is connected to the surface of the first channel away from the first gate.

2. The semiconductor device according to claim 1, wherein The first channel includes a first channel portion and a second channel portion, and the second channel portion is connected to an end of the first channel portion away from the capacitor structure; The first drain is located on a side of the second channel portion away from the first gate.

3. The semiconductor device according to claim 2, wherein: The first transistor further includes a first gate insulating layer, wherein the first gate insulating layer is located between the first channel and the first gate; The first gate includes a first gate portion and a second gate portion connected to the first gate portion in the first direction; The first gate portion is connected to the capacitor structure, and a width of the first gate portion in a second direction perpendicular to the first direction is greater than a width of the second gate portion in the second direction; The first gate insulating layer covers the second gate portion and the surface of the first gate portion away from the capacitor structure, the end of the first channel portion away from the second channel portion is located on the first gate insulating layer connected to the first gate portion, and the second channel portion is located on the first gate insulating layer connected to the end of the second gate portion away from the first gate portion.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that: The first semiconductor structure further comprises: A first stacked structure includes a source line; the source line extends along a second direction perpendicular to the first direction; and A first channel structure, located in the first stacked structure and passing through the source line; Among them, the first drain is located on a side of the first channel structure away from the capacitor structure, the first channel structure includes the first gate and the first channel, the source line is connected to the first channel in the second direction, and the first transistor includes the source line and the first channel structure.

5. The semiconductor device according to claim 4, wherein: The first stacking structure further includes: a first insulating layer; and a second insulating layer; The source line is located between the first insulating layer and the second insulating layer, and the first channel structure penetrates the first insulating layer, the source line and the second insulating layer; A surface of the first channel extending in the first direction contacts the first insulating layer, the source line, and a portion of the second insulating layer, and a portion of the first gate contacts the second insulating layer.

6. The semiconductor device according to claim 4, wherein: The first semiconductor structure further comprises: a first bit line extending along a third direction perpendicular to the first direction and intersecting the second direction and located at a side of the first drain away from the capacitor structure; The extending direction of the first bit line is perpendicular to the extending direction of the source line, and one of the first drains is connected to one of the first bit lines.

7. The semiconductor device according to claim 4, wherein: The first semiconductor structure further comprises: A second stacking structure comprises a second electrode layer and a third insulating layer; one second electrode layer is located between two adjacent third insulating layers, and one third insulating layer is located on a side of the first stacking structure away from the first drain electrode; and An energy storage structure, which penetrates the second electrode layer; the energy storage structure includes the first electrode layer and the energy storage layer; The second electrode layer is arranged around the energy storage layer, the energy storage layer is arranged around the first electrode layer, and the capacitor structure includes the first electrode layer, the energy storage layer and the second electrode layer.

8. The semiconductor device according to claim 7, wherein: The first semiconductor structure further comprises: A second transistor comprising a channel layer; the channel layer extends along the first direction; The second transistor is located at a side of the capacitor structure away from the first transistor, and one end of the first electrode layer away from the first transistor is connected to the channel layer of the second transistor.

9. The semiconductor device according to claim 8, characterized in that The first semiconductor structure further comprises: A third stacking structure is located on a side of the second stacking structure away from the first stacking structure; the third stacking structure comprises a word line and a fourth insulating layer extending along the second direction, the word line is located between two adjacent fourth insulating layers, and one of the fourth insulating layers is connected to one of the third insulating layers; and A second channel structure is located in the third stacked structure and runs through the word line; The second channel structure includes the channel layer and a second gate insulating layer, one end of the channel layer is connected to an end of the first electrode layer of the capacitor structure away from the first gate, and the second gate insulating layer surrounds the channel layer and contacts the word line; The second transistor includes the word line and the second channel structure.

10. The semiconductor device according to claim 9, wherein: The first semiconductor structure further comprises: A second bit line extending along a third direction perpendicular to the first direction and intersecting the second direction and located at a side of the channel layer away from the capacitor structure; The extension direction of the second bit line is perpendicular to the extension direction of the source line, and one of the second bit lines is connected to one end of the channel layer away from the capacitor structure.

11. The semiconductor device according to claim 8, wherein The semiconductor device further comprises: A second semiconductor structure having a circuit element for controlling the first semiconductor structure and located at a side of the first semiconductor structure away from the first stacked structure; The second semiconductor structure is bonded to the first semiconductor structure in the first direction.

12. The semiconductor device according to claim 11, wherein The semiconductor device further comprises: The connecting portion connects one of the first transistor and the second transistor and connects the second semiconductor structure.

13. The semiconductor device according to claim 8, wherein: The first transistor is configured to be turned on or off according to the storage content of the capacitor structure and allow the storage content of the capacitor structure to be read, and the second transistor is configured to be turned on or off according to the written content and allow the write voltage to flow into the capacitor structure through the second transistor.

14. A method for preparing a semiconductor device, characterized in that: include: forming a first stack structure having an intermediate state transistor, and making the intermediate state transistor include a first gate and a first channel surrounding the first gate; forming a second stacking structure having a capacitor structure on one side of the first stacking structure, and making the capacitor structure include a first electrode layer, and the first gate is connected to one end of the first electrode layer; and A first drain is formed on a side of the first stacking structure away from the second stacking structure to obtain a first transistor, and the first drain is connected to the first channel; the first transistor includes the intermediate state transistor and the first drain.

15. The method for preparing a semiconductor device according to claim 14, characterized in that: Before the step of forming a first drain on a side of the first stacked structure away from the second stacked structure, the method further includes: A third stack structure having a second transistor is formed on a side of the second stack structure away from the first stack structure, and the second transistor includes a channel layer connected to an end of the first electrode layer away from the first gate.

16. The method for preparing a semiconductor device according to claim 14, wherein: Before the step of forming the first stacking structure, the method further includes: providing a substrate; forming the first stacking structure on the substrate; Wherein, the second stacking structure is located on a side of the first stacking structure away from the substrate; before forming the first drain, the method further includes: The substrate is removed.

17. The method for preparing a semiconductor device according to claim 16, wherein: The step of forming a first stacked structure having an intermediate state transistor comprises: forming a first insulating layer, a source line and a second insulating layer on the substrate along a stacking direction of the first stacking structure and the second stacking structure to obtain the first stacking structure; forming a first channel hole penetrating the first stack structure on the first stack structure; and Filling the first channel hole with a channel material to obtain a first channel structure, wherein the first channel structure includes the first gate, the first channel, and a first gate insulating layer located between the first gate and the first channel; The first transistor includes the first channel structure and the source line.

18. The method for preparing a semiconductor device according to claim 17, characterized in that: The step of filling the channel material in the channel hole to obtain the first channel structure includes: forming an intermediate channel layer on the inner wall of the first channel hole and on the surface of the first stacked structure away from the substrate; forming an intermediate gate insulating layer covering the intermediate channel layer; forming an intermediate gate layer covering the intermediate gate insulating layer; Patterning the intermediate state channel layer, the intermediate state gate insulating layer and the intermediate state gate layer to obtain a first channel, a first gate insulating layer and a first gate, and to obtain a first channel structure including the first channel, the first gate insulating layer and the first gate; and A fifth insulating layer covering the second insulating layer is formed on the second insulating layer, and a portion of the first channel structure protruding from the second stacked structure is located in the fifth insulating layer.

19. The method for preparing a semiconductor device according to claim 14, wherein: After the step of forming a first drain on a side of the first stacking structure away from the second stacking structure and connecting the first drain to the first channel, the method further includes: A first bit line is formed on a side of the first drain away from the second stack structure, and each of the first bit lines is connected to one of the first drains.

20. The method for preparing a semiconductor device according to claim 15, wherein: After the step of forming a third stack structure having a second transistor on a side of the second stack structure away from the first stack structure, the method further includes: A second bit line is formed on a side of the third stacking structure away from the second stacking structure, and the second bit line is connected to the second transistor to obtain a first semiconductor structure.

21. The method for preparing a semiconductor device according to claim 20, wherein: After the step of forming a second bit line on a side of the third stacking structure away from the second stacking structure and connecting the second bit line to the second transistor to obtain the first semiconductor structure, the method further includes: forming a second semiconductor structure bonded to the first semiconductor structure on a side of the second bit line away from the third stacked structure; and A connection portion is formed that connects the second semiconductor structure and connects one of the first transistor and the second transistor.

22. A memory system, characterized in that: include: At least one semiconductor device according to any one of claims 1 to 13; and A controller is configured to control the semiconductor device.

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