Electrical structure and preparation method thereof

Abstract

The invention provides an electrical structure and a preparation method thereof. The electrical structure includes a substrate, a first insulating layer, a second insulating layer and an electrical contact. The first insulating layer is disposed on a first surface of the substrate and defines a first through hole to extend through the first insulating layer. The first through hole has a first width. The second insulating layer is disposed on the first insulating layer and defines a second through hole to extend through the second insulating layer. The second through hole has a second width. A difference between the first width and the second width is less than one tenth of the first width. The electrical contact is disposed in the first through hole and the second through hole, and is electrically connected to the first surface of the substrate.

Description

[0001] This application is a divisional application of Chinese invention patent application No. 2023115330997, filed on November 16, 2023, with the invention name of “Electrical structure and preparation method thereof”. Application No. 2023115330997 claims priority and benefits of U.S. formal application No. 18 / 232,831 filed on August 11, 2023. The contents of the U.S. formal application are incorporated herein by reference in their entirety. Technical Field

[0002] The present disclosure relates to an electrical structure and a method for preparing the same, and more particularly to an electrical structure including an electrical contact point and a method for preparing the same. Background Art

[0003] Semiconductor structures are used in various electronic applications, and the size of semiconductor structures is constantly reduced to meet the current application requirements. However, various problems may occur during the reduction in size and affect the final electronic properties, quality, cost and yield. Typical memory components (such as dynamic random access memory (DRAM) components) include electrical contacts for electrically interconnecting different components. The profile of the electrical contacts is a key issue because it affects the contact resistance and the speed of electron current transmission.

[0004] The above “prior art” description only provides background technology, does not admit that the above “prior art” description reveals the subject matter of the present disclosure, does not constitute the prior art of the present disclosure, and any description of the above “prior art” should not be regarded as any part of this case. Summary of the invention

[0005] An embodiment of the present disclosure provides an electrical structure, including a substrate, a first insulating layer, a second insulating layer, and an electrical contact point. The first insulating layer is disposed on a first surface of the substrate and defines a first through-hole extending through the first insulating layer. The first through-hole has a first width. The second insulating layer is disposed on the first insulating layer and defines a second through-hole extending through the second insulating layer. The second through-hole has a second width. A difference between the first width and the second width is less than one tenth of the first width. The electrical contact point is disposed in the first through-hole and the second through-hole and is electrically connected to the first surface of the substrate.

[0006] Another embodiment of the present disclosure provides a method for preparing an electrical structure. The preparation method includes providing a stacked structure, which includes a substrate, a first insulating layer, and a second insulating layer stacked on each other. The preparation method also includes forming a first hole structure to extend through the first insulating layer and the second insulating layer and expose a portion of the substrate. The preparation method also includes cleaning the exposed portion of the substrate with a cleaning agent so as to expand the first hole structure to become a second hole structure, wherein the cleaning agent includes water and hydrofluoric acid (HF), and a weight ratio of water to HF is 500:1 to 2500:1. The preparation method also includes forming an electrical contact point in the second hole structure.

[0007] The present disclosure forms an electrical contact with an improved profile by using ultra-dilute hydrofluoric acid (HF).

[0008] The above has outlined the technical features and advantages of the present disclosure in a fairly broad manner, so that the detailed description of the present disclosure below can be better understood. Other technical features and advantages that constitute the subject matter of the claims of the present disclosure will be described below. It should be understood by those with ordinary knowledge in the technical field to which the present disclosure belongs that the concepts and specific embodiments disclosed below can be used to modify or design other structures or processes to achieve the same purpose as the present disclosure. It should also be understood by those with ordinary knowledge in the technical field to which the present disclosure belongs that such equivalent constructions cannot depart from the spirit and scope of the present disclosure as defined by the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] A more complete understanding of the present disclosure may be obtained by referring to the detailed description and claims when considered in conjunction with the drawings, wherein like reference numerals refer to similar elements throughout the drawings.

[0010] Figure 1 It is a cross-sectional schematic diagram illustrating the electrical structure of some embodiments of the present disclosure.

[0011] Figure 2 is a cross-sectional schematic diagram illustrating one stage of a method for preparing an electrical structure of some embodiments of the present disclosure.

[0012] Figure 3 is a cross-sectional schematic diagram illustrating one stage of a method for preparing an electrical structure of some embodiments of the present disclosure.

[0013] Figure 4 is a cross-sectional schematic diagram illustrating one stage of a method for preparing an electrical structure of some embodiments of the present disclosure.

[0014] Figure 5 is a cross-sectional schematic diagram illustrating one stage of a method for preparing an electrical structure of some embodiments of the present disclosure.

[0015] Figure 6 is a cross-sectional schematic diagram illustrating one stage of a method for preparing an electrical structure of some embodiments of the present disclosure.

[0016] Figure 7 is a cross-sectional schematic diagram illustrating one stage of a method for preparing an electrical structure of some embodiments of the present disclosure.

[0017] Figure 8 is a cross-sectional schematic diagram illustrating one stage of a method for preparing an electrical structure of some embodiments of the present disclosure.

[0018] Fig. 9 is a cross-sectional schematic diagram illustrating one stage of a method for preparing an electrical structure of some embodiments of the present disclosure.

[0019] Fig.10 Schematic diagram of a process flow diagram illustrating a method for preparing an electrical structure according to some embodiments of the present disclosure.

[0020] The reference numerals are described as follows:

[0021] 1: Electrical structure

[0022] 2: Base

[0023] 3: First Metal Oxide Semiconductor Transistor

[0024] 3a: Second metal oxide semiconductor transistor

[0025] 4: First insulation layer

[0026] 5: Second insulation layer

[0027] 6: Electrical contact points

[0028] 7: Base

[0029] 13: Hole structure

[0030] 13': Hole structure

[0031] 21: First Surface

[0032] 22: Drain electrode

[0033] 23: Source electrode

[0034] 24: Source electrode

[0035] 25: Depression

[0036] 26: Low resistance layer

[0037] 28: Part

[0038] 31: Gate oxide layer

[0039] 31a: Gate oxide layer

[0040] 32: First gate conductor layer

[0041] 32a: first gate conductor layer

[0042] 33: Second gate conductor layer

[0043] 33a: Second gate conductor layer

[0044] 34: Upper

[0045] 34a: Upper level

[0046] 35: Interstitial

[0047] 35a: Interstitial

[0048] 36: First floor

[0049] 36a: First floor

[0050] 37: Second floor

[0051] 37a: Second floor

[0052] 38: Third floor

[0053] 38a: Third floor

[0054] 41: First Surface

[0055] 43: First piercing

[0056] 43': Fourth Punch

[0057] 51: First surface

[0058] 53: Second piercing

[0059] 53': Fifth punch

[0060] 60: Center Material

[0061] 61: Part 1

[0062] 62: Part 2

[0063] 63: Part 3

[0064] 65: Peripheral layer

[0065] 72: Stacked structure

[0066] 80: Cleaning agent

[0067] 82: Splashing Cobalt

[0068] 380: Connection layer

[0069] 653: Center hole

[0070] 900: Preparation method

[0071] S901: Steps

[0072] S902: Steps

[0073] S903: Steps

[0074] S904: Steps

[0075] W1: First width

[0076] W2: Second width

[0077] W3: Third width

[0078] W4: fourth width

[0079] W5: Fifth width DETAILED DESCRIPTION

[0080] Specific examples of components and configurations are described below to simplify the embodiments of the present disclosure. Of course, these embodiments are for illustration only and are not intended to limit the scope of the present disclosure. For example, in the description, the first component is formed on the second component, which may include an embodiment in which the first and second components are in direct contact, and may also include an embodiment in which additional components are formed between the first and second components so that the first and second components are not in direct contact. In addition, the embodiments of the present disclosure may repeat reference numbers and / or letters in many examples. The purpose of these repetitions is to simplify and clarify, and unless otherwise specified in the text, they do not themselves represent a specific relationship between the various embodiments and / or the configurations discussed.

[0081] It should be understood that although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers, or sections, these elements, components, regions, layers, or sections are not limited by these terms. Instead, these terms are only used to distinguish one element, component, region, layer, or section from another region, layer, or section. Therefore, without departing from the teachings of the progressive conception of the present invention, the first element, component, region, layer, or section discussed below may be referred to as a second element, component, region, layer, or section.

[0082] The terms used herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that when the terms "comprises" and / or "comprising" are used in this specification, these terms specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups of the above.

[0083] Figure 1 1 is a cross-sectional schematic diagram illustrating an electrical structure 1 of some embodiments of the present disclosure. In some embodiments, the electrical structure 1 may be a semiconductor structure or a semiconductor element including a circuit, such as a memory cell. In some embodiments, the memory cell may include a dynamic random access memory cell (DRAM cell). In some embodiments, the electrical structure 1 may be an interconnect structure.

[0084] In addition, the electrical structure 1 can be or include a part of an integrated circuit (IC) chip, and the integrated circuit chip includes various passive and active microelectronic components, such as resistors, capacitors, inductors, diodes, p-type field effect transistors (pFETs), n-type field effect transistors (nFETs), metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused MOS (LDMOS) transistors, high voltage transistors, high frequency transistors, fin field effect transistors (FinFETs), other suitable IC components or combinations thereof.

[0085] The electrical structure 1 may include a substrate 2 (eg, a semiconductor substrate), a first metal oxide semiconductor (MOS) transistor 3 , a second metal oxide semiconductor transistor 3 a , a first insulating layer 4 , a second insulating layer 5 , and an electrical contact 6 .

[0086] In some embodiments, the substrate 2 may have a first surface 21 (e.g., an upper surface). For example, the substrate 2 may include silicon (Si), doped silicon, germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), gallium (Ga), gallium arsenide (GaAs), indium (In), indium arsenide (InAs), indium phosphide (InP), or other IV-IV, III-V, or II-VI semiconductor materials. In some other embodiments, the substrate 2 may include a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate.

[0087] Depending on the IC manufacturing stage, substrate 2 may include various material layers (e.g., dielectric layers, semiconductor layers, and / or conductive layers) configured to form IC features (e.g., doped regions, isolation features, gate features, source / drain features, interconnect features, other features, or combinations thereof).

[0088] like Figure 1 As shown, the substrate 2 may include a drain electrode 22, a source electrode 23, and a source electrode 24. The substrate 2 may define a recessed portion 25, which is recessed from the first surface 21 (e.g., the upper surface) of the substrate 2. The recessed portion 25 may be disposed in the drain electrode 22. The recessed portion 25 has a third width W3. The third width W3 may be the maximum width of the recessed portion 25. In addition, the substrate 2 may include a low resistance layer 26, which is disposed on a bottom wall of the recessed portion 25. The low resistance layer 26 may include cobalt (Co), such as cobalt disilicide (CoSi2).

[0089] The first metal oxide semiconductor transistor 3 and the second metal oxide semiconductor transistor 3a may be part of a word line. The first metal oxide semiconductor transistor 3 and the second metal oxide semiconductor transistor 3a may be disposed on the first surface 21 of the substrate 2. The first metal oxide semiconductor transistor 3 may correspond to the drain electrode 22 and the source electrode 23. The first metal oxide semiconductor transistor 3 may include a gate oxide layer 31, a first gate conductor layer 32, a second gate conductor layer 33, an upper layer 34 and a spacer 35. The gate oxide layer 31 may be disposed on the first surface 21 of the substrate 2, and may include an oxide material for electrical insulation. The first gate conductor layer 32 may be disposed on the gate oxide layer 31, and may include a polysilicon material. The second gate conductor layer 33 may be disposed on the first gate conductor layer 32, and may include a tungsten silicide (WSi x) material. The first gate conductor layer 32 and the second gate conductor layer 33 may together form a gate electrode. The upper layer 34 may be disposed on the second gate conductor layer 33 and may include a nitride material. In some embodiments, the gate electrode may include the upper layer 34.

[0090] The spacer 35 may surround the gate electrode (including, for example, the first gate conductor layer 32 and the second gate conductor layer 33) or may be disposed around the gate electrode. In some embodiments, the spacer 35 may include a first layer 36, a second layer 37, and a third layer 38. The first layer 36 may cover the gate oxide layer 31, the first gate conductor layer 32, the second gate conductor layer 33, and the upper layer 34, and may include a nitride material. The second layer 37 may be disposed on a side surface of the first layer 36 and on a portion of the first surface 21 of the substrate 2. The second layer 37 may taper upward and may include an oxide material. The third layer 38 may cover the first layer 36 and the second layer 37. For example, the third layer 38 may cover the outer surface of the first layer 36 and the upper surface of the second layer 37. Therefore, the second layer 37 may be sandwiched between the first layer 36 and the third layer 38. A bottom end of the third layer 38 may be disposed on the first surface 21 of the substrate 2.

[0091] Similarly, the second metal oxide semiconductor transistor 3a may correspond to the drain electrode 22 and the source electrode 24. The second metal oxide semiconductor transistor 3a may include a gate oxide layer 31a, a first gate conductor layer 32a, a second gate conductor layer 33a, an upper layer 34a and a spacer 35a. The gate oxide layer 31a, the first gate conductor layer 32a, the second gate conductor layer 33a, the upper layer 34a and the spacer 35a of the second metal oxide semiconductor transistor 3a may be respectively the same as the gate oxide layer 31, the first gate conductor layer 32, the second gate conductor layer 33, the upper layer 34 and the spacer 35 of the first metal oxide semiconductor transistor 3.

[0092] The gate oxide layer 31a may be disposed on the first surface 21 of the substrate 2 and may include an oxide material for electrical insulation. The first gate conductor layer 32a may be disposed on the gate oxide layer 31a and may include a polysilicon material. The second gate conductor layer 33a may be disposed on the first gate conductor layer 32a and may include a tungsten silicide (WSi x ) material. The first gate conductor layer 32a and the second gate conductor layer 33a may form a gate electrode together. The upper layer 34a may be disposed on the second gate conductor layer 33a and may include a nitride material. In some embodiments, the gate electrode may include the upper layer 34a.

[0093] The spacer 35a may surround the gate electrode (including, for example, the first gate conductor layer 32a and the second gate conductor layer 33a) or may be arranged around the gate electrode. In some embodiments, the spacer 35a may include a first layer 36a, a second layer 37a, and a third layer 38a. The first layer 36a may cover the gate oxide layer 31a, the first gate conductor layer 32a, the second gate conductor layer 33a, and the upper layer 34a, and may include a nitride material. The second layer 37a may be arranged on a side surface of the first layer 36a and on a portion of the first surface 21 of the substrate 2. The second layer 37a may taper upward and may include an oxide material. The third layer 38a may cover the first layer 36a and the second layer 37a. For example, the third layer 38a may cover the outer surface of the first layer 36a and the upper surface of the second layer 37a. Therefore, the second layer 37a may be sandwiched between the first layer 36a and the third layer 38a. A bottom end of the third layer 38a may be arranged on the first surface 21 of the substrate 2.

[0094] The first insulating layer 4 may be disposed above the first surface 21 of the substrate 2. In some embodiments, the first insulating layer 4 may be disposed on the first surface 21 of the substrate 2 and may cover the first metal oxide semiconductor transistor 3 and the second metal oxide semiconductor transistor 3a. The first insulating layer 4 may include an oxide material such as silicon dioxide (SiO2). The first surface 41 (e.g., the upper surface) of the first insulating layer 4 may be aligned with an upper surface of the third layer 38 of the first metal oxide semiconductor transistor 3 and an upper surface of the third layer 38a of the second metal oxide semiconductor transistor 3a. Therefore, the upper surface of the third layer 38 of the first metal oxide semiconductor transistor 3 and the upper surface of the third layer 38a of the second metal oxide semiconductor transistor 3a may be exposed from the first surface 41 of the first insulating layer 4.

[0095] The first insulating layer 4 may define a first through-hole 43 to extend through the first insulating layer 4. The first through-hole 43 has a first width W1. The first width W1 may be the maximum width of the first through-hole 43. The recessed portion 25 of the substrate 2 may be in communication with the first through-hole 43 of the first insulating layer 4. That is, the first through-hole 43 may also extend through the connection layer 380 (connecting the third layer 38 and the third layer 38a) covering the first surface 21 of the substrate 2. The connection layer 380, the third layer 38, and the third layer 38a may be the same layer. The third width W3 of the recessed portion 25 may be smaller than the first width W1 of the first through-hole 43. A width of the through-hole of the connection layer 380 may gradually decrease from the first width W1 to the third width W3.

[0096] The second insulating layer 5 may be disposed on the first insulating layer 4. The second insulating layer 5 may cover and contact the first surface 41 of the first insulating layer 4. A material of the second insulating layer 5 may be different from a material of the first insulating layer 4. The second insulating layer 5 may include a nitride material such as silicon nitride (Si3N4 or SiN). The second insulating layer 5 may define a second through-hole 53 to extend through the second insulating layer 5. The second through-hole 53 of the second insulating layer 5 may be connected to the first through-hole 43 of the first insulating layer 4 to form a hole structure 13 (or a contact hole). A central axis of the first through-hole 43 may be substantially aligned with a central axis of the second through-hole 53. Therefore, the hole structure 13 may extend through the first insulating layer 4 and the second insulating layer 5, and may include the first through-hole 43 and the second through-hole 53. In some embodiments, the hole structure 13 may also extend into the substrate 2, and may include a recessed portion 25.

[0097] The second through hole 53 has a second width W2. The second width W2 may be the maximum width of the second through hole 53. The second width W2 of the second through hole 53 may be smaller than the first width W1 of the first through hole 43. The third width W3 of the recessed portion 25 may be smaller than the second width W2 of the second through hole 53.

[0098] In some embodiments, a difference between the first width W1 and the second width W2 is less than one tenth of the first width W1. That is, the ratio of (W1-W2) / W1 may be less than 0.1, 0.09, 0.08, 0.07, or 0.06. Therefore, a gap (or a tolerance) between a side wall of the first through hole 43 and a side wall of the second through hole 53 may be very small. The side wall of the first through hole 43 and the side wall of the second through hole 53 may be substantially aligned with each other.

[0099] The electrical contact point 6 can be disposed in the hole structure 13 and can extend through the first insulating layer 4 and the second insulating layer 5 to electrically connect the first surface 21 of the substrate 2. In addition, the electrical contact point 6 can also extend into the substrate 2. The electrical contact point 6 can include a peripheral layer 65 and a core material 60. The peripheral layer 65 can be disposed on a side wall of the hole structure 13 and can define a core hole. The core material 60 can fill the core hole defined by the peripheral layer 65. The peripheral layer 65 can include titanium nitride (TiN), and the core material 60 can include tungsten (W).

[0100] The electrical contact point 6 may include a first portion 61, a second portion 62, and a third portion 63. The first portion 61 may be disposed in the first through-hole 43 of the first insulating layer 4, and may have a first width W1. It should be understood that the first width W1 of the first portion 61 may be the maximum width of the first portion 61, and may be substantially equal to the first width W1 of the first through-hole 43 of the first insulating layer 4. The first portion 61 may include a portion of the peripheral layer 65 and a portion of the core material 60.

[0101] The second portion 62 may be disposed in the second perforation 53 of the second insulating layer 5 and may have a second width W2. It should be understood that the second width W2 of the second portion 62 may be the maximum width of the second portion 62 and may be substantially equal to the second width W2 of the second perforation 53 of the second insulating layer 5. The second portion 62 may include a portion of the peripheral layer 65 and a portion of the central material 60. A ratio of a difference between the first width W1 and the second width W2 to the first width W1 may be less than 10%. That is, a ratio of (W1-W2) / W1 may be less than 10%, 9%, 8%, 7% or 6%. Therefore, a gap (or a tolerance) between a side wall of the first portion 61 and a side wall of the second portion 62 may be very small. The side wall of the first portion 61 and the side wall of the second portion 62 may be substantially aligned with each other.

[0102] The third portion 63 may be disposed in the recessed portion 25 of the substrate 2 and may have a third width W3. It should be understood that the third width W3 of the third portion 63 may be the maximum width of the third portion 63 and may be substantially equal to the third width W3 of the recessed portion 25 of the substrate 2. The third portion 63 may include a portion of the peripheral layer 65 and a portion of the core material 60. The third width W3 may be less than the first width W1 and the second width W2. The low-resistance layer 26 may be substantially conformal to the third portion 63 of the electrical contact 6.

[0103] The first portion 61, the second portion 62 and the third portion 63 of the electrical contact point 6 can be integrally formed and formed simultaneously, so that the electrical contact point 6 can be an integral structure. The electrical contact point 6 can be disposed between the first metal oxide semiconductor transistor 3 and the second metal oxide semiconductor transistor 3a. The electrical contact point 6 can be electrically connected to an electrode of the first metal oxide semiconductor transistor 3 and / or the second metal oxide semiconductor transistor 3a. Figure 1As shown, the electrical contact point 6 can be electrically connected to a common electrode (e.g., drain electrode 22) of the first metal oxide semiconductor transistor 3 and the second metal oxide semiconductor transistor 3a. However, in other embodiments, the electrical contact point 6 can be electrically connected to a first electrode of the first metal oxide semiconductor transistor 3 and / or a second electrode of the second metal oxide semiconductor transistor 3a. The first electrode of the first metal oxide semiconductor transistor 3 can be different from the second electrode of the second metal oxide semiconductor transistor 3a.

[0104] In some embodiments, a low resistance layer 26 may be disposed between the electrical contact point 6 and the drain electrode 22 of the substrate 2 to reduce the resistance of the ohmic contact between the electrical contact point 6 and the substrate 2. During a manufacturing process, before forming the low resistance layer 26, a portion of the substrate 2 exposed to a hole structure needs to be cleaned with a cleaning agent. In a comparative embodiment, the cleaning agent may cause a large difference between a first width of a first perforation in the first insulating layer and a second width of a second perforation in the second insulating layer. Therefore, the hole structure may have a "curved profile", which will result in a weak profile of an electrical contact point formed in such a hole structure. For example, such an electrical contact point may be prone to a seam or crack. As Figure 1 As shown, the manufacturing technology of the hole structure 13 can include the embodiments shown below, and the difference between the first width W1 of the first through-hole 43 and the second width W2 of the second through-hole 53 can be reduced. Therefore, the sidewalls of the hole structure 13 can be substantially straight to facilitate the deposition process of the surrounding layer 65 and the filling process of the core material 60. The electrical contact point 6 can have an improved profile. The quality of the electrical contact point 6 can be improved. That is, seams or cracks can be reduced. The electrical contact point 6 can have no seams or cracks.

[0105] Figures 2 to 9 It shows the method for preparing the electrical structure 1 according to some embodiments of the present disclosure. Please refer to Figures 2 to 5 , providing a stacked structure 72. The stacked structure 72 can be manufactured as follows.

[0106] Please refer to Figure 2 , providing a base 7. The base 7 may include a substrate 2, a first metal oxide semiconductor transistor 3 and a second metal oxide semiconductor transistor 3a. Figure 2 The substrate 2, the first metal oxide semiconductor transistor 3 and the second metal oxide semiconductor transistor 3a can be the same or similar to Figure 1 A substrate 2, a first metal oxide semiconductor transistor 3 and a second metal oxide semiconductor transistor 3a.

[0107] In some embodiments, the substrate 2 may have a first surface 21 (e.g., an upper surface). The substrate 2 may include a drain electrode 22, a source electrode 23, and a source electrode 24. For example, the substrate 2 may include silicon, doped silicon, germanium, silicon germanium, silicon carbide, silicon germanium carbide, gallium, gallium arsenide, indium, indium arsenide, indium phosphide, or other IV-IV, III-V, or II-VI semiconductor materials.

[0108] The first metal oxide semiconductor transistor 3 and the second metal oxide semiconductor transistor 3a can be formed or disposed on the first surface 21 of the substrate 2. The first metal oxide semiconductor transistor 3 can correspond to the drain electrode 22 and the source electrode 23. The first metal oxide semiconductor transistor 3 may include a gate oxide layer 31, a first gate conductor layer 32, a second gate conductor layer 33, an upper layer 34 and a spacer 35. The gate oxide layer 31 can be formed or disposed on the first surface 21 of the substrate 2, and can include an oxide material for electrical insulation. The first gate conductor layer 32 can be formed or disposed on the gate oxide layer 31, and can include a polysilicon material. The second gate conductor layer 33 can be formed or disposed on the first gate conductor layer 32, and can include a tungsten silicide (WSi x The upper layer 34 may be disposed on the second gate conductor layer 33 and may include a nitride material.

[0109] The spacer 35 may surround the gate electrode (including, for example, the first gate conductor layer 32 and the second gate conductor layer 33) or may be disposed around the gate electrode. In some embodiments, the spacer 35 may include a first layer 36, a second layer 37, and a third layer 38. The first layer 36 may cover the gate oxide layer 31, the first gate conductor layer 32, the second gate conductor layer 33, and the upper layer 34, and may include a nitride material. The second layer 37 may be disposed on a side surface of the first layer 36 and on a portion of the first surface 21 of the substrate 2. The second layer 37 may taper upward and may include an oxide material. The third layer 38 may cover the first layer 36 and the second layer 37. For example, the third layer 38 may cover the outer surface of the second layer 37 and the upper surface of the first layer 36. Therefore, the second layer 37 may be sandwiched between the first layer 36 and the third layer 38. A bottom end of the third layer 38 may be disposed on the first surface 21 of the substrate 2.

[0110] Similarly, the second metal oxide semiconductor transistor 3a may correspond to the drain electrode 22 and the source electrode 24. The structure of the second metal oxide semiconductor transistor 3a may be the same as or similar to the first metal oxide semiconductor transistor 3, and may include a gate oxide layer 31a, a first gate conductor layer 32a, a second gate conductor layer 33a, an upper layer 34a, and a spacer 35a. The gate oxide layer 31a, the first gate conductor layer 32a, the second gate conductor layer 33a, the upper layer 34a, and the spacer 35a of the second metal oxide semiconductor transistor 3a may be the same as or similar to the gate oxide layer 31, the first gate conductor layer 32, the second gate conductor layer 33, the upper layer 34, and the spacer 35 of the first metal oxide semiconductor transistor 3.

[0111] A connection layer 380 may connect the third layer 38 and the third layer 38a, and may cover the first surface 21 of the substrate 2. The connection layer 380, the third layer 38, and the third layer 38a may be the same layer and may be formed simultaneously.

[0112] Please refer to Figure 3 , the first insulating layer 4 may be formed or disposed above the first surface 21 of the substrate 2. In some embodiments, the first insulating layer 4 may be disposed on the first surface 21 of the substrate 2 and may cover the first metal oxide semiconductor transistor 3 and the second metal oxide semiconductor transistor 3a. A first surface 41 (e.g., an upper surface) of the first insulating layer 4 may be higher than an upper surface of the third layer 38 of the first metal oxide semiconductor transistor 3 and an upper surface of the third layer 38a of the second metal oxide semiconductor transistor 3a. Therefore, the upper surface of the third layer 38 of the first metal oxide semiconductor transistor 3 and the upper surface of the third layer 38a of the second metal oxide semiconductor transistor 3a may be covered by the first insulating layer 4.

[0113] Please refer to Figure 4 , for example, the first insulating layer 4 may be thinned from the first surface 41 by grinding. Therefore, an upper portion of the first insulating layer 4 may be removed, and the first surface 41 of the first insulating layer 4 may be aligned with the upper surface of the third layer 38 of the first metal oxide semiconductor transistor 3 and the upper surface of the third layer 38a of the second metal oxide semiconductor transistor 3a. Therefore, the upper surface of the third layer 38 of the first metal oxide semiconductor transistor 3 and the upper surface of the third layer 38a of the second metal oxide semiconductor transistor 3a may be exposed from the first surface 41 of the first insulating layer 4.

[0114] Please refer to Figure 5, the second insulating layer 5 may be formed or disposed on the first insulating layer 4. The second insulating layer 5 may cover and contact the first surface 41 of the first insulating layer 4. At the same time, a stacked structure 72 may be formed. The stacked structure 72 may include a substrate 2, a first insulating layer 4, and a second insulating layer 5 stacked on each other. In addition, the stacked structure 72 may also include a first metal oxide semiconductor transistor 3 and a second metal oxide semiconductor transistor 3a disposed on the substrate 2 and covered by the first insulating layer 4 and the second insulating layer 5.

[0115] Please refer to Figure 6 For example, a first hole structure 13' may be formed from the first surface 51 of the second insulating layer 5 by dry etching to expose a portion 28 of the substrate 2. The first hole structure 13' may extend through the first insulating layer 4 to form a fourth through-hole 43' having a fourth width W4. The first hole structure 13' may extend through the second insulating layer 5 to form a fifth through-hole 53' having a fifth width W5. The fourth width W4 may be substantially equal to the fifth width W5. The first hole structure 13' may be disposed between the first metal oxide semiconductor transistor 3 and the second metal oxide semiconductor transistor 3a. In some embodiments, the first hole structure 13' may also extend through the connecting layer 380 and extend into the substrate 2 to form a recessed portion 25 recessed from the first surface 21 of the substrate 2. The recessed portion 25 has a third width W3. The third width W3 may be the maximum width of the recessed portion 25 and may be less than the fourth width W4.

[0116] Please refer to Figure 7 , the exposed portion 28 of the substrate 2 can be cleaned via a cleaning agent 80 applied to the first hole structure 13'. At the same time, the cleaning agent 80 can etch the first insulating layer 4 and the second insulating layer 5 so as to expand the first hole structure 13' to become the second hole structure 13. For example, therefore, the manufacturing technology of the second hole structure 13 may include wet etching. The cleaning agent 80 may include water and hydrofluoric acid (HF), and the weight ratio of water to HF may be between 500:1 and 2500:1. The weight ratio of water to HF may be 1800:1 to 2200:1, 1000:1 to 2000:1, or 1500:1 to 2100:1. Such a cleaning agent 80 may also be referred to as "ultra-dilute hydrofluoric acid (HF)".

[0117] Figure 7 The second hole structure 13 may be the same as Figure 1The second hole structure 13 may extend through the first insulating layer 4 to form a first through-hole 43 (or a first enlarged through-hole) having a first width W1. The second hole structure 13 may extend through the second insulating layer 5 to form a second through-hole 53 (or a second enlarged through-hole) having a second width W2. Since the etching rate of the cleaning agent 80 on the first insulating layer 4 is greater than the etching rate of the cleaning agent 80 on the second insulating layer 5, the first width W1 may be greater than the second width W2.

[0118] In some embodiments, a difference between the first width W1 and the second width W2 is less than one tenth of the first width W1. That is, a ratio of (W1-W2) / W1 may be less than 0.1, 0.09, 0.08, 0.07, or 0.06. Therefore, the gap (or tolerance) between a side wall of the first through hole 43 and a side wall of the second through hole 53 may be very small. The side wall of the first through hole 43 and the side wall of the second through hole 53 may be substantially aligned with each other.

[0119] Reference Figure 8 , a low resistance layer 26 can be formed on the cleaned exposed portion 28 of the substrate 2 by, for example, sputtering and annealing. In some embodiments, the low resistance layer 26 is formed by sputtering cobalt 82 and then annealing, so that the low resistance layer 26 can include cobalt disilicide (CoSi2). In the present invention, the ultra-dilute hydrofluoric acid (HF) as described above does not affect the formation of the low resistance layer 26.

[0120] Then, the residual cobalt (Co) can be removed by, for example, wet cleaning. Then, as described below, an electrical contact 6 ( Figure 1 ).

[0121] Please refer to Fig. 9 The peripheral layer 65 may be formed by, for example, deposition or disposed on a side wall of the second hole structure 13. The peripheral layer 65 may define a central hole 653. The peripheral layer 65 may include titanium nitride (TiN). Figure 7 As shown, the difference between the first width W1 of the first through-hole 43 and the second width W2 of the second through-hole 53 can be reduced. Therefore, the sidewall of the second hole structure 13 can be substantially straight to facilitate the deposition process of the surrounding layer 65.

[0122] Then, please refer to Figure 1 , a central material 60 may fill the central hole 653 defined by the surrounding layer 65 to form an electrical contact point 6. The central material 60 may include tungsten (W). At the same time, an electrical structure 1 (or semiconductor structure) may be obtained. Figure 7As shown, the difference between the first width W1 of the first through-hole 43 and the second width W2 of the second through-hole 53 can be reduced. Therefore, the sidewalls of the second hole structure 13 can be substantially straight to facilitate the filling process of the core material 60. The quality of the electrical contact 6 can be improved. That is, the seams or cracks of the electrical contact 6 can be reduced. The electrical contact 6 can be free of seams or cracks. In addition, as shown in the contact resistance results in the wafer test, the resistance between the electrical contact 6 and the substrate 2 is still low. That is, the use of ultra-dilute hydrofluoric acid (HF) as described above does not affect the resistance between the electrical contact 6 and the substrate 2.

[0123] Fig.10 is a flow chart illustrating a method 900 for preparing an electrical structure 1 according to some embodiments of the present disclosure.

[0124] In some embodiments, the preparation method 900 may include step S901, providing a stack structure including a substrate, a first insulating layer, and a second insulating layer stacked on each other. Figure 5 As shown, a stack structure 72 may be provided, and the stack structure 72 may include a substrate 2, a first insulating layer 4, and a second insulating layer 5 stacked on each other.

[0125] In some embodiments, the preparation method 900 may include step S902, forming a first hole structure to extend through the first insulating layer and the second insulating layer and expose a portion of the substrate. Figure 6 As shown, a first hole structure 13 ′ may be formed to extend through the first insulating layer 4 and the second insulating layer 5 and expose a portion 28 of the substrate 2 .

[0126] In some embodiments, the preparation method 900 may include step S903, cleaning the exposed portion of the substrate with a cleaning agent to expand the first hole structure to form a second hole structure, wherein the cleaning agent includes water and hydrofluoric acid (HF), and the weight ratio of water to hydrofluoric acid is 500:1 to 2500:1. For example, Figure 7 As shown, the exposed portion 28 of the substrate 2 can be cleaned by a cleaning agent 80 to expand the first hole structure 13' to form a second hole structure 13. The cleaning agent 80 includes water and hydrofluoric acid (HF), and the weight ratio of water to hydrofluoric acid is between 500:1 and 2500:1.

[0127] In some embodiments, the preparation method 900 may include step S904, forming an electrical contact point in the second hole structure. Figure 1 As shown, the electrical contact point 6 is formed in the second hole structure 13 .

[0128] An embodiment of the present disclosure provides an electrical structure, including a substrate, a first insulating layer, a second insulating layer, and an electrical contact point. The first insulating layer is disposed on a first surface of the substrate and defines a first through-hole extending through the first insulating layer. The first through-hole has a first width. The second insulating layer is disposed on the first insulating layer and defines a second through-hole extending through the second insulating layer. The second through-hole has a second width. A difference between the first width and the second width is less than one tenth of the first width. The electrical contact point is disposed in the first through-hole and the second through-hole and is electrically connected to the first surface of the substrate.

[0129] Another embodiment of the present disclosure provides a method for preparing an electrical structure. The preparation method includes providing a stacked structure, which includes a substrate, a first insulating layer, and a second insulating layer stacked on each other. The preparation method also includes forming a first hole structure to extend through the first insulating layer and the second insulating layer and expose a portion of the substrate. The preparation method also includes cleaning the exposed portion of the substrate with a cleaning agent so as to expand the first hole structure to become a second hole structure, wherein the cleaning agent includes water and hydrofluoric acid (HF), and a weight ratio of water to HF is 500:1 to 2500:1. The preparation method also includes forming an electrical contact point in the second hole structure.

[0130] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and replacements may be made without departing from the spirit and scope of the present disclosure as defined in the claims. For example, many of the above processes may be implemented in different ways, and other processes or combinations thereof may be used to replace many of the above processes.

[0131] Furthermore, the scope of the present application is not limited to the specific embodiments of the processes, machines, manufactures, compositions of matter, means, methods, and steps described in the specification. A person skilled in the art can understand from the disclosure of the present disclosure that existing or future developed processes, machines, manufactures, compositions of matter, means, methods, or steps that have the same functions or achieve substantially the same results as the corresponding embodiments described herein can be used according to the present disclosure. Accordingly, such processes, machines, manufactures, compositions of matter, means, methods, or steps are included in the claims of the present application.

Claims

1. An electrical structure comprising: a base; A first insulating layer disposed on a first surface of the substrate and defining a first through hole extending through the first insulating layer, wherein the first through hole has a first width; a second insulating layer disposed on the first insulating layer and defining a second through-hole extending through the second insulating layer, wherein the second through-hole has a second width, wherein a difference between the first width and the second width is less than one tenth of the first width; as well as an electrical contact point, disposed in the first through hole and the second through hole and electrically connected to the first surface of the substrate, The base defines a recessed portion, wherein the recessed portion has a third width, and the third width is smaller than the second width. 2 . The electrical structure as claimed in claim 1 , wherein the first through hole is connected to the second through hole. The electrical structure as claimed in claim 1 , wherein the electrical contact point is an integral structure.

4. The electrical structure as claimed in claim 1, further comprising a first metal oxide semiconductor transistor and a second metal oxide semiconductor transistor disposed on the substrate, wherein the electrical contact point is disposed between the first metal oxide semiconductor transistor and the second metal oxide semiconductor transistor. 5 . The electrical structure of claim 4 , wherein the electrical contact is electrically connected to an electrode of the first metal oxide semiconductor transistor and / or the second metal oxide semiconductor transistor. The electrical structure as claimed in claim 1 , wherein a material of the second insulating layer is different from a material of the first insulating layer. 7 . The electrical structure as claimed in claim 1 , wherein the recessed portion is communicated with the first through-hole, and the electrical contact point is also disposed in the recessed portion. 8 . The electrical structure as claimed in claim 7 , wherein the substrate comprises a low resistance layer, and the low resistance layer is disposed on a bottom wall of the recessed portion.

9. The electrical structure of claim 8, wherein the substrate comprises silicon, and the low resistance layer comprises cobalt disilicide (CoSi2).

10. A method for preparing an electrical structure, comprising: A stacking structure is provided, the stacking structure comprising a substrate, a first insulating layer and a second insulating layer stacked on each other; forming a first hole structure to extend through the first insulating layer and the second insulating layer and expose a portion of the substrate; Cleaning the exposed portion of the substrate with a cleaning agent to expand the first hole structure to become a second hole structure, wherein the cleaning agent includes water and hydrofluoric acid (HF), and a weight ratio of water to hydrofluoric acid is 500:1 to 2500:1; and An electrical contact point is formed in the second hole structure.

11. The preparation method as claimed in claim 10, wherein the stacked structure further comprises a first metal oxide semiconductor transistor and a second metal oxide semiconductor transistor disposed on the substrate, wherein the first hole structure is disposed between the first metal oxide semiconductor transistor and the second metal oxide semiconductor transistor. 12 . The preparation method as claimed in claim 10 , wherein the first hole structure extends into the substrate.

13. The preparation method as claimed in claim 10, wherein the weight ratio is 1800:1 to 2200:

1.

14. The preparation method as described in claim 10, wherein the second hole structure includes a first through-hole extending through the first insulating layer and a second through-hole extending through the second insulating layer, wherein the first through-hole has a first width, the second through-hole has a second width, and a difference between the first width and the second width is less than one tenth of the first width.

15. The method of claim 10, wherein after cleaning the exposed portion of the substrate, the method further comprises: A low resistance layer is formed on the exposed cleaned portion of the substrate.

16. The method as claimed in claim 15, wherein the low resistance layer is formed by sputtering cobalt.

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