Memory cell, memory device and manufacturing method of memory device

Abstract

The invention provides a memory cell comprising: a write transistor comprising a first semiconductor channel, a first source-drain electrode, and a second source-drain electrode; the reading transistor comprises a second semiconductor channel, a third source drain electrode and a fourth source drain electrode; the part, located between the first source and drain electrode and the second source and drain electrode, of the first semiconductor channel is a first effective semiconductor channel; the part, located between the third source drain electrode and the fourth source drain electrode, of the second semiconductor channel is a second effective semiconductor channel; the channel outer ring size of the part, close to the first source and drain electrode, of the first effective semiconductor channel is different from the channel outer ring size of the part, close to the second source and drain electrode, of the first effective semiconductor channel; the channel outer ring size of the part, close to the third source and drain electrode, of the second effective semiconductor channel is different from the channel outer ring size of the part, close to the fourth source and drain electrode, of the second effective semiconductor channel. The invention also provides a memory device and a manufacturing method thereof. According to the invention, the channel length and the storage density can be improved.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and in particular relates to a storage unit, a storage device and a method for manufacturing the storage device. Background Art

[0002] As mobile consumer electronic products have further increased their requirements for miniaturization, functional integration, and large-capacity storage space, the demand for miniaturization and high density of components is increasing. How to achieve higher storage density of devices is the key research direction of many researchers and chip R&D engineers. 2T0CDRAM has no capacitor tube structure, so it is easier to achieve higher storage density than 1T1CDRAM, and has attracted much attention from manufacturers.

[0003] In the traditional process, the 2T0C transistor has a vertical structure. To solve the short channel effect, the channel height is required to be designed to be higher. However, increasing the height will bring problems such as wafer bending, which may cause device failure and pose greater challenges to the lithography alignment process.

[0004] Moreover, with the development of the semiconductor industry, the storage density requirements for DRAM are getting higher and higher. In addition to directly increasing the number of device stacking layers to improve storage density, it is also necessary to continuously reduce the height of each layer. However, if the height of each layer is directly reduced without corresponding structural changes, it will inevitably bring about a short channel effect, resulting in increased leakage. Summary of the invention

[0005] An embodiment of the present invention provides a memory cell, aiming to solve the technical problem of how to solve the short channel effect while controlling the channel height in a 2T0C DRAM structure.

[0006] The embodiment of the present invention is implemented as follows: a storage unit includes:

[0007] A write transistor, the write transistor comprising a first gate, a first gate dielectric surrounding the first gate, a first semiconductor channel surrounding the first gate dielectric, a first source and a drain, and a second source and a drain; the first source and a drain are arranged at a first end of the first gate and are located outside the first semiconductor channel; the second source and a drain are arranged at a second end of the first gate and are located outside the first semiconductor channel;

[0008] A read transistor, the read transistor comprising a second gate, a second gate dielectric surrounding the second gate, a second semiconductor channel surrounding the second gate dielectric, a third source and drain, and a fourth source and drain; the second source and drain are conductively connected to the second gate; the third source and drain are arranged at a first end of the second gate and are located outside the second semiconductor channel; the fourth source and drain are arranged at a second end of the second gate and are located outside the second semiconductor channel;

[0009] Wherein, the portion of the first semiconductor channel located between the first source-drain electrode and the second source-drain electrode is a first effective semiconductor channel; the portion of the second semiconductor channel located between the third source-drain electrode and the fourth source-drain electrode is a second effective semiconductor channel;

[0010] The channel outer ring size of the portion of the first effective semiconductor channel close to the first source and drain is different from the channel outer ring size of the portion of the first effective semiconductor channel close to the second source and drain; the channel outer ring size of the portion of the second effective semiconductor channel close to the third source and drain is different from the channel outer ring size of the portion of the second effective semiconductor channel close to the fourth source and drain.

[0011] An embodiment of the present invention further provides a storage device, including:

[0012] a semiconductor substrate; and

[0013] At least one memory cell according to any one of the above items is formed on the semiconductor substrate.

[0014] The present invention also provides a method for preparing a memory device, for manufacturing the memory device according to any one of the above items, the method comprising the following steps:

[0015] Providing a semiconductor substrate, depositing a first insulating layer and a first conductive material layer in sequence on the semiconductor substrate, and etching the first conductive material layer to form a first signal line;

[0016] Depositing a first dielectric layer and a second conductive material layer in sequence on the layer where the first signal line is located, and etching the second conductive material layer to form a second signal line;

[0017] Depositing a second insulating layer and a first hard mask layer in sequence on the layer where the second signal line is located, etching the first hard mask layer, the second insulating layer, the second signal line and the first dielectric layer to form a second through hole extending in a vertical direction to the upper surface of the first signal line, wherein the aperture of the second through hole located on the upper surface of the first dielectric layer is different from the aperture of the second through hole located on the lower surface of the first dielectric layer;

[0018] removing the first hard mask layer and forming a read transistor in the second through hole;

[0019] Depositing a third conductive material layer on the second insulating layer, and etching the third conductive material layer to form a contact guide, wherein the lower surface of the contact guide is conductively connected to the second gate, and the contact guide is insulated from the second semiconductor channel;

[0020] Depositing a second dielectric layer and a fourth conductive material layer in sequence on the layer where the contact guide block is located, and etching the fourth conductive material layer to form a third signal line, wherein the third signal line is a bit line of the write transistor;

[0021] Depositing a third insulating layer and a second hard mask layer in sequence on the layer where the third signal line is located, etching the second hard mask layer, the third insulating layer, the third signal line and the second dielectric layer to form a first through hole extending in a vertical direction to the upper surface of the contact guide block, wherein the aperture of the first through hole located on the upper surface of the second dielectric layer is different from the aperture of the first through hole located on the lower surface of the second dielectric layer;

[0022] removing the second hard mask layer and forming a write transistor in the first through hole;

[0023] A fifth conductive material layer is deposited on the third insulating layer, and the fifth conductive material layer is etched to form a fourth signal line contacting and connected to the first gate, wherein the fourth signal line is a word line of the write transistor.

[0024] In the storage unit of the embodiment of the present invention, the outer ring sizes at both ends of the first effective semiconductor channel and the second effective semiconductor channel are different, so that the outer ring walls of the first effective semiconductor channel and the second effective semiconductor channel are not completely perpendicular to the horizontal plane like the outer ring walls of the current vertical channels, but are arc-shaped in the vertical direction during the formation process. While ensuring the overall length of the first effective semiconductor channel and the second effective semiconductor channel, the height of the first effective semiconductor channel and the second effective semiconductor channel can be controlled to control the overall height of the write transistor and the read transistor, thereby improving the storage density of the storage unit and avoiding the short channel effect caused by directly shortening the channel length. It can effectively control leakage and ensure the performance of the storage unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 is a schematic structural diagram of a storage unit according to an embodiment of the present invention;

[0026] Figure 2 A schematic diagram of the structure of a storage unit provided in another embodiment of the present invention;

[0027] Figure 3A schematic diagram of the structure of a storage unit provided in yet another embodiment of the present invention;

[0028] Figures 4 to 19 A process flow chart of a method for manufacturing a memory device provided by an embodiment of the present invention;

[0029] Fig. 20 The figure is a flow chart of a method for manufacturing a memory device according to an embodiment of the present invention.

[0030] Description of main reference numerals:

[0031] Memory cell-100; write transistor-110; first gate-111; first gate dielectric-112; first semiconductor channel-113; first effective semiconductor channel-1131; first source and drain-114; second source and drain-115; read transistor-120; second gate-121; second gate dielectric-122; annular insulating layer-1221; second semiconductor channel-123; second effective semiconductor channel-1231; third source and drain-124; fourth source and drain-125; contact guide-130; first signal line-140; second signal line -150; third signal line -160; fourth signal line -170; first insulating layer -101; first conductive material layer -102; first dielectric layer -103; second conductive material layer -104; second insulating layer -105; first hard mask layer -106; second through hole -107; third conductive material layer -108; second dielectric layer -109; fourth conductive material layer -10a; third insulating layer -10b; second hard mask layer -10c; first through hole -10d; fifth conductive material layer -10e; semiconductor substrate -200; memory device -1000. DETAILED DESCRIPTION

[0032] In order to make the purpose, technical scheme and advantages of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention. In addition, it should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0033] In the description of the present invention, it is necessary to understand that the orientation or positional relationship indicated in the description of the direction and positional relationship is based on the orientation or positional relationship shown in the accompanying drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0034] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0035] The disclosure below provides many different embodiments or examples to realize different structures of the present invention. In order to simplify the disclosure of the present invention, the parts and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present invention. In addition, the present invention can repeat reference numbers and / or reference letters in different examples, and this repetition is for the purpose of simplification and clarity, which itself does not indicate the relationship between the various embodiments and / or settings discussed. In addition, the examples of various specific processes and materials provided by the present invention, but those of ordinary skill in the art can be aware of the application of other processes and / or the use of other materials.

[0036] In the prior art 2T0C DRAM, the channel regions of the read transistor and the write transistor in the memory cell are generally arranged vertically, and in order to avoid leakage problems caused by the short channel effect, the channel region needs to be arranged higher (i.e., longer), but the increase in height will bring problems such as wafer bending.

[0037] As the storage density requirements for DRAM become higher and higher, in addition to directly increasing the number of device stacking layers to improve storage density, it is also necessary to continuously reduce the height of each layer. Therefore, it is necessary to control the height of the channel area. However, due to the influence of the short channel effect, the channel area cannot be directly shortened to meet the requirements, resulting in the current stage. The storage density of 2T0C DRAM is difficult to effectively improve.

[0038] To solve the above problems, please refer to Figures 1 to 3 An embodiment of the present invention provides a memory cell 100 , which includes a write transistor 110 and a read transistor 120 .

[0039] The write transistor 110 includes a first gate 111, a first gate dielectric 112 surrounding the first gate 111, a first semiconductor channel 113 surrounding the first gate dielectric 112, a first source and drain 114, and a second source and drain 115; the first source and drain 114 is arranged at the first end of the first gate 111 and is located outside the first semiconductor channel 113; the second source and drain 115 is arranged at the second end of the first gate 111 and is located outside the first semiconductor channel 113.

[0040] The read transistor 120 includes a second gate 121, a second gate dielectric 122 surrounding the second gate 121, a second semiconductor channel 123 surrounding the second gate dielectric 122, a third source and drain 124 and a fourth source and drain 125; the second source and drain 115 are conductively connected to the second gate 121; the third source and drain 124 is arranged at the first end of the second gate 121 and is located on the outside of the second semiconductor channel 123; the fourth source and drain 125 is arranged at the second end of the second gate 121 and is located on the outside of the second semiconductor channel 123.

[0041] Among them, the part of the first semiconductor channel 113 located between the first source and drain 114 and the second source and drain 115 is the first effective semiconductor channel 1131, and the channel outer ring size of the part of the first effective semiconductor channel 1131 close to the first source and drain 114 is different from the channel outer ring size of the part of the first effective semiconductor channel 1131 close to the second source and drain 115.

[0042] The portion of the second semiconductor channel 123 located between the third source drain 124 and the fourth source drain 125 is a second effective semiconductor channel 1231 . The channel outer ring size of the portion of the second effective semiconductor channel 1231 close to the third source drain 124 is different from the channel outer ring size of the portion of the second effective semiconductor channel 1231 close to the fourth source drain 125 .

[0043] In the storage unit 100 of the embodiment of the present invention, the outer ring sizes at both ends of the first effective semiconductor channel 1131 and the second effective semiconductor channel 1231 are different, so that the outer ring walls of the first effective semiconductor channel 1131 and the second effective semiconductor channel 1231 are not vertical like the outer ring walls of the current vertical channels, but are arc-shaped during the formation process. While ensuring the overall length of the first effective semiconductor channel 1131 and the second effective semiconductor channel 1231, the height of the first effective semiconductor channel 1131 and the second effective semiconductor channel 1231 can be controlled to control the overall height of the write transistor 110 and the read transistor 120, thereby improving the storage density of the storage unit 100 and avoiding the short channel effect caused by directly shortening the channel length, which can effectively control leakage and ensure the performance of the storage unit 100.

[0044] This embodiment of the memory cell 100 mainly describes the structural features of the write transistor 110 and the read transistor 120. The specific formation process and materials of the structures such as the write transistor 110, the read transistor 120, the signal line below and the contact guide block 130 below are only briefly described in the embodiment of the memory cell 100. The detailed description will be expanded in detail in the embodiment of the manufacturing method of the memory device 1000 described below.

[0045] Specifically, the storage unit 100 is formed on a semiconductor substrate, specifically, the read transistor 120 and the write transistor 110 are sequentially formed on the semiconductor substrate 200, that is, the write transistor 110 is located above the read transistor 120, the first semiconductor channel 113 is located above the second semiconductor channel 123, and the central axis of the first semiconductor channel 113 coincides with the central axis of the second semiconductor channel 123.

[0046] Since the first semiconductor channel 113 and the second semiconductor channel 123 are the basic structures of the write transistor 110 and the read transistor 120, the first gate 111, the first gate dielectric 112, the first source and drain 114 and the second source and drain 115 are formed based on the formation of the first semiconductor channel 113, and the second gate 121, the second gate dielectric 122, the third source and drain 124 and the fourth source and drain 125 are formed based on the formation of the second semiconductor channel 123. The coincidence of the central axes of the two channels can make the write transistor 110 and the read transistor 120 accurately correspond, thereby making the structure of the storage unit 100 more regular, and the height and volume of the storage unit 100 can be controlled, which is conducive to miniaturization and improved storage density.

[0047] Taking the formation of the write transistor 110 as an example, the first semiconductor channel 113, the first gate dielectric 112 and the first gate 111 can all be formed by a deposition process. For example, a channel through hole can be first etched on a semiconductor stack structure (including structures such as a semiconductor substrate, a conductive material layer, a dielectric layer and an insulating layer), and the channel through hole is further etched so that it can meet the above-mentioned "different channel outer ring sizes" condition when forming the first semiconductor channel 113. A certain thickness of semiconductor material is deposited on the bottom surface and the surrounding wall of the above-mentioned channel through hole to form the first semiconductor channel 113, and then a certain thickness of gate dielectric material is deposited on the surface of the first semiconductor channel 113 to form the first gate dielectric 112, and then a gate material is deposited in the space surrounded by the first gate dielectric 112 to form the first gate 111 to form the write transistor 110.

[0048] The deposition process may be chemical vapor deposition (CVD), atomic layer deposition (ALD), molecular layer deposition (MLD), or physical vapor deposition (PVD).

[0049] The formation process of the read transistor 120 may refer to the formation process of the write transistor 110 , which will not be described in detail here.

[0050] Please continue reading Figures 1 to 3, further, a projection of the first semiconductor channel 113 on a plane perpendicular to its axis is conformal to a projection of the second semiconductor channel 123 on a plane perpendicular to its axis.

[0051] Among them, conformal can be understood as overlap.

[0052] Exemplarily, the central axis of the first semiconductor channel 113 and the central axis of the second semiconductor channel 123 are both perpendicular to the plane where the semiconductor substrate is located in the vertical direction, that is, perpendicular to the horizontal plane, then the projections of the first semiconductor channel 113 and the second semiconductor channel 123 on the plane where the semiconductor substrate is located are conformal, that is, the projections of the first semiconductor channel 113 and the second semiconductor channel 123 on the plane where the semiconductor substrate is located overlap, so that the write transistor 110 and the read transistor 120 can further correspond accurately, thereby making the structure of the storage unit 100 more regular, and the height and volume of the storage unit 100 can be further controlled, and the storage density of the storage device 1000 can be further improved.

[0053] In the embodiment of the present invention, the shape (external contour) of the first semiconductor channel 113 and the second semiconductor channel 123 may be substantially a cuboid, a cylinder, a pyramid, or other regular or irregular columnar shapes.

[0054] Since the channel walls of the first semiconductor channel 113 and the second semiconductor channel 123 are not completely parallel to their respective central axes, but are inclined or arc-shaped relative to the central axes, or in other words, the channel walls of the first semiconductor channel 113 and the second semiconductor channel 123 are not completely perpendicular to the plane where the semiconductor substrate 200 is located, and there is a certain inclination or arc in the vertical direction, the overall height of the write transistor 110 and the read transistor 120 is controlled to improve the storage density, while the channel length of the write transistor 110 and the read transistor 120 is extended to avoid the short channel effect.

[0055] The shape of the first semiconductor channel 113 may be the same as or different from the shape of the second semiconductor channel 123. Preferably, in the embodiment of the present invention, the shape of the first semiconductor channel 113 is the same as the shape of the second semiconductor channel 123, so that the shape of the memory cell 100 is more regular and the manufacturing process of the memory cell 100 is simplified.

[0056] exist Figures 1 to 3 In the illustrated embodiment, the channel walls of the first semiconductor channel 113 and the second semiconductor channel 123 may be considered to be inclined walls that are generally inclined outward (ie, outside the memory cell 100 ) in the vertical direction or arc-shaped walls that extend outward in an arc shape.

[0057] Taking the example that the channel walls of the first semiconductor channel 113 and the second semiconductor channel 123 are skewed walls, the first semiconductor channel 113 and the second semiconductor channel 123 can be approximated as a prismatic structure. At this time, the channel walls of the first semiconductor channel 113 and the channel walls of the second semiconductor channel 123 may include multiple side walls inclined in different directions, and the write transistor 110 and the read transistor 120 are roughly prism-shaped.

[0058] In a possible embodiment, based on the structural characteristics that the channel walls of the first semiconductor channel 113 and the channel walls of the second semiconductor channel 123 are outwardly inclined oblique walls or arc-shaped walls, the first semiconductor channel 113 and the second semiconductor channel 123 can also be approximated to a pyramidal or inverted truncated cone structure. At this time, the channel walls of the first semiconductor channel 113 and the channel walls of the second semiconductor channel 123 are inclined outward in a curved surface, and at the same time, the write transistor 110 and the read transistor 120 are also roughly pyramidal or inverted truncated cone structures.

[0059] Taking the channel wall of the first semiconductor channel 113 as an example, which is inclined outward, in an embodiment of the present invention, the first semiconductor channel 113 can be formed by obliquely etching the channel wall. For example, a regular channel through hole can be first etched on the semiconductor stack structure. The channel through hole can be a rectangular hole, a cylindrical hole or other columnar hole shape, etc., and then etching is started from the bottom of the channel through hole (that is, one end close to the read transistor 120).

[0060] After etching part of the inner wall of the channel through hole, continue etching the inner wall along the axial direction of the channel through hole and toward the outside of the channel through hole, so that the inner wall of the channel through hole is offset outward by a certain distance layer by layer, and thus the channel through hole with the inner wall deflected outward is formed by etching upward and outward step by step along the inner wall of the channel through hole, and at the same time, the area of ​​the lower port of the channel through hole will be smaller than the area of ​​the upper port. Then, a semiconductor material of a certain thickness is deposited on the inner wall of the channel through hole to form a first semiconductor channel 113 with a channel wall deflected outward. The outward deflection of the channel wall of the first semiconductor channel 113 can also be understood as the outward deflection of the semiconductor layer of the first semiconductor channel 113 itself.

[0061] The formation process of the second semiconductor channel 123 may refer to the formation process of the first semiconductor channel 113 , which will not be described in detail here.

[0062] It is worth noting that the “deviation” mentioned in the embodiment of the present invention does not mean that the entire wall is regularly skewed into a slanted wall, but that its outer contour is roughly skewed, that is, it is in a shape that is outwardly deflected or protrudes outward relative to the central axis of the first semiconductor channel 113 / the second semiconductor channel 123. It can also be understood that the channel wall of the first semiconductor channel 113 and the channel wall of the second semiconductor channel 123 are not walls perpendicular to the horizontal plane, but walls that are inclined outward or protruding outward.

[0063] For ease of description, Figure 2 As shown, since the channel walls of the first semiconductor channel 113 and the second semiconductor channel 123 are approximately arc-shaped from a macroscopic perspective, the following examples and descriptions will be given in which the channel walls of the first semiconductor channel 113 are arc-shaped in the central axis direction of the first semiconductor channel 113 (i.e., the vertical direction), and the channel walls of the second semiconductor channel 123 are arc-shaped in the central axis direction of the second semiconductor channel 123. That is, the "arc-shaped" mentioned below should be understood as arc-shaped in the central axis direction of the first semiconductor channel 113 and the second semiconductor channel 123.

[0064] Since the first semiconductor channel 113 is the basic structure of the write transistor 110, the first gate dielectric 112 is formed on the channel wall of the first semiconductor channel 113 and is a layered structure. The first gate 111 is formed in the first gate dielectric 112 and can be columnar. The first semiconductor channel 113 surrounds the first gate dielectric 112, and the first gate dielectric 112 surrounds the first gate 111 to achieve insulation between the first gate 111 and the first semiconductor channel 113. Therefore, the shapes of the first gate dielectric 112 and the first gate 111 are adapted to the shape of the first semiconductor, that is, the outer contours of the first gate dielectric 112 and the first gate 111 are also arc-shaped.

[0065] Since the shapes of the second semiconductor channel 123 , the second gate dielectric 122 and the second gate 121 can refer to the above description of the first semiconductor channel 113 , they are not described in detail here.

[0066] It can be understood that in order to connect multiple memory cells 100 to further form a memory device 1000 and realize the signal connection between the memory device 1000 and an external control unit, it is also necessary to design signal lines connecting multiple memory cells 100 and an external control unit, such as common write word lines, write bit lines, read word lines, and read bit lines.

[0067] In the embodiment of the present invention, the corresponding signal line or the connection structure between the write transistor 110 and the read transistor 120 (i.e., the contact guide block 130 hereinafter) in contact with the first semiconductor channel 113 and the second semiconductor channel 123 is the source and drain of the write transistor 110 and the source and drain of the read transistor 120 .

[0068] For example, the portions where the write bit line and the contact guide 130 contact the first semiconductor channel 113 are the first source drain 114 and the second source drain 115 , respectively. The first source drain 114 can be the drain or source of the write transistor 110 , and the second source drain 115 can be the source or drain of the write transistor 110 .

[0069] The portions of the read word line and the read bit line contacting the second semiconductor channel 123 are the third source drain 124 and the fourth source drain 125 , respectively. The third source drain 124 may be the source or drain of the read transistor 120 , and the fourth source drain 125 may be the drain or source of the read transistor 120 .

[0070] Since the corresponding signal lines and contact guide blocks 130 are both in contact with the outside of the write transistor 110 and the outside of the read transistor 120, the first source drain 114 and the second source drain 115 are located on the outside of the first semiconductor channel 113, that is, located at the outermost circle of the first semiconductor channel 113, and the third source drain 124 and the fourth source drain 125 are located on the outside of the second semiconductor channel 123, that is, located at the outermost circle of the first semiconductor channel 113.

[0071] See also Figures 1 to 3 Furthermore, the first source-drain electrode 114 is disposed around the first end of the first gate electrode 111 , and the third source-drain electrode 124 is disposed around the first end of the second gate electrode 121 .

[0072] The first end and the second end of the first gate 111 can be understood as the top and the bottom of the first gate 111, and the first source and drain 114 are arranged around the first end of the first gate 111, that is, it can be understood as the structural arrangement of the first source and drain 114 surrounding the top part of the first gate 111. Since the top of the first gate 111 will be designed with a signal line connected to the write transistor 110, the first semiconductor channel 113 and the first gate 111 will pass through the signal line. Therefore, the first source and drain 114 formed by the contact between the signal line and the first semiconductor channel 113 is arranged around the first gate 111.

[0073] The first end and the second end of the second gate 121 can be understood as the top and the bottom of the second gate 121, and the third source and drain 124 are arranged around the first end of the second gate 121, that is, it can be understood as the structural arrangement of the third source and drain 124 surrounding the top part of the second gate 121. Since the top of the second gate 121 will be designed with a signal line connected to the read transistor 120, the second semiconductor channel 123 and the second gate 121 will pass through the signal line. Therefore, the third source and drain 124 formed by the contact between the signal line and the second semiconductor channel 123 is arranged around the second gate 121.

[0074] Of course, the first end and the second end of the first gate 111 may also be the bottom end and the top end thereof, and the first end and the second end of the second gate 121 may also be the bottom end and the top end thereof, and are not limited to the above description.

[0075] In an embodiment of the present invention, the first effective semiconductor channel 1131 is the portion of the first semiconductor channel 113 of the write transistor 110 between the first source drain 114 and the second source drain 115, and can also be understood as the portion of the first semiconductor channel 113 between the write word line and the above-mentioned connection structure. This portion is the portion where the first source drain 114 and the second source drain 115 transmit electrical signals to the first gate 111, and the other portion of the first semiconductor channel 113 is the portion between the two signal lines connected to the write transistor 110.

[0076] The second effective semiconductor channel 1231 is the portion of the second semiconductor channel 123 of the read transistor 120 between the third source drain 124 and the fourth source drain 125, and can also be understood as the portion of the second semiconductor channel 123 between the two signal lines connected to the read transistor 120. This portion is the portion where the third source drain 124 and the fourth source drain 125 transmit electrical signals to the second gate 121, and the other portion of the second semiconductor channel 123 is the portion between the signal line and the above-mentioned connection structure.

[0077] Since the first semiconductor channel 113 and the second semiconductor channel 123 are formed by depositing a certain thickness of semiconductor material on the inner wall of the channel through hole, both have a certain thickness. Therefore, in the embodiment of the present invention, the channel outer ring size of the first effective semiconductor channel 1131 and the channel outer ring size of the second effective semiconductor channel 1231 can be understood as the outermost ring size of the first effective semiconductor channel 1131 and the outermost ring size of the second effective semiconductor channel 1231, that is, the size of a circle of surface (ring) where the first effective semiconductor channel 1131 and the second effective semiconductor channel 1231 contact the corresponding channel through hole, and the size of a circle of surface where the first effective semiconductor channel 1131 and the second effective semiconductor channel 1231 are provided with the first gate dielectric 112 and the second gate dielectric 122 can be understood as the channel inner ring size.

[0078] Similarly, the technical features such as the outer ring / outer ring size mentioned below can also be understood as above.

[0079] In the embodiment of the present invention, the channel outer ring size of the portion of the first effective semiconductor channel 1131 close to the first source and drain 114 is different from the channel outer ring size of the portion of the first effective semiconductor channel 1131 close to the second source and drain 115, which can be understood as:

[0080] The channel outer ring size of the portion of the first effective semiconductor channel 1131 close to the first source and drain 114 is larger than the channel outer ring size of the portion of the first effective semiconductor channel 1131 close to the second source and drain 115; or, the channel outer ring size of the portion of the first effective semiconductor channel 1131 close to the first source and drain 114 is smaller than the channel outer ring size of the portion of the first effective semiconductor channel 1131 close to the second source and drain 115.

[0081] In this way, in the process of forming the first effective semiconductor channel 1131, the channel wall of the first effective semiconductor channel 1131 is not perpendicular to the semiconductor substrate 200, that is, it is not parallel to the central axis of the first semiconductor channel 113. Compared with the existing channel wall perpendicular to the semiconductor substrate 200, it can achieve the purpose of extending the channel length of the first effective semiconductor channel 1131 while controlling the overall height of the write transistor 110.

[0082] In the embodiment of the present invention, the outer ring size of the second effective semiconductor channel 1231 near the third source and drain 124 is different from the outer ring size of the second effective semiconductor channel 1231 near the fourth source and drain 125, which can be understood as:

[0083] The channel outer ring size of the portion of the second effective semiconductor channel 1231 close to the third source and drain 124 is larger than the channel outer ring size of the portion of the second effective semiconductor channel 1231 close to the fourth source and drain 125; or, the channel outer ring size of the portion of the second effective semiconductor channel 1231 close to the third source and drain 124 is smaller than the channel outer ring size of the portion of the second effective semiconductor channel 1231 close to the fourth source and drain 125.

[0084] In this way, in the process of forming the second effective semiconductor channel 1231, the channel wall of the second effective semiconductor channel 1231 is not perpendicular to the semiconductor substrate 200, that is, it is not parallel to the central axis of the second semiconductor channel 123. Compared with the existing channel wall perpendicular to the semiconductor substrate 200, it can achieve the purpose of extending the channel length of the second effective semiconductor channel 1231 while controlling the overall height of the write transistor 110.

[0085] See also Figures 1 to 3 Furthermore, the outer ring size of the first effective semiconductor channel 1131 is gradually shrinking or gradually expanding, and the outer ring size of the second effective semiconductor channel 1231 is gradually shrinking or gradually expanding.

[0086] Taking the central axis of the first effective semiconductor channel 1131 and the central axis of the second effective semiconductor channel 1231 as reference and direction, the central axes of the two coincide and are in the vertical direction, exemplarily:

[0087] The outer ring size of the first effective semiconductor channel 1131 gradually decreases from top to bottom in the vertical direction, and the outer ring size of the second effective semiconductor channel 1231 gradually decreases from top to bottom in the vertical direction;

[0088] The outer ring size of the first effective semiconductor channel 1131 gradually expands from top to bottom in the vertical direction, and the outer ring size of the second effective semiconductor channel 1231 gradually shrinks from top to bottom in the vertical direction;

[0089] The outer ring size of the first effective semiconductor channel 1131 gradually shrinks from top to bottom in the vertical direction, and the outer ring size of the second effective semiconductor channel 1231 gradually expands from top to bottom in the vertical direction;

[0090] The outer ring size of the first effective semiconductor channel 1131 gradually expands from top to bottom in the vertical direction, and the outer ring size of the second effective semiconductor channel 1231 gradually expands from top to bottom in the vertical direction.

[0091] In the embodiment of the present invention, the first effective semiconductor channel 1131 and the second effective semiconductor channel 1231 have the same change trend, that is, both are gradually contracting or expanding in the same direction, so that the structure of the memory cell 100 is more regular.

[0092] In a preferred embodiment of the present invention, the outer ring size of the first effective semiconductor channel 1131 and the outer ring size of the second effective semiconductor channel 1231 gradually decrease from top to bottom in the vertical direction, or can be understood as gradually increase from bottom to top in the vertical direction.

[0093] From the perspective of etching, it is easier to etch the channel through holes corresponding to the first effective semiconductor channel 1131 and the second effective semiconductor channel 1231 to gradually expand from bottom to top in the vertical direction. Even if it is easier to etch the first effective semiconductor channel 1131 and the second effective semiconductor channel 1231 to gradually expand from bottom to top, the manufacturing difficulty of the storage unit 100 can be controlled.

[0094] See also Figure 1 and Figure 3 Furthermore, in the embodiment of the present invention, the first effective semiconductor channel 1131 and the second effective semiconductor channel 1231 are both structures that gradually expand from bottom to top in a step-like manner, such as an inverted tower shape.

[0095] The first effective semiconductor channel 1131 and the second effective semiconductor channel 1231 can be approximately in the shape of a quadrangular prism, that is, the channel walls of both include four side walls, and the four side walls are connected to form the above-mentioned channel wall, each side wall can be formed by smoothly connecting multiple planes distributed in the Z-axis direction (such as vertical planes or inclined planes), each plane can extend in the Y-axis and Z-axis directions, or extend in the X-axis and Z-axis directions, and two adjacent planes on the same side wall are staggered in the Y-axis direction or the X-axis direction, that is, the positive projections of two adjacent planes in the Z-axis direction are staggered to form a step surface, that is, the four side walls are all stepped side walls, so that the first effective semiconductor channel 1131 and the second effective semiconductor channel 1231 are roughly in the shape of an inverted tower.

[0096] When etching the channel through hole used to form the first effective semiconductor channel 1131 and the second effective semiconductor channel 1231, the bottom layer of plane can be first etched on the inner wall of the channel through hole. At this time, the four planes are connected together, approximating a rectangular space. Etching is then continued upwards to form the second layer of planes. The four planes of the second layer are connected to form a larger rectangular space until etching reaches the top of the channel through hole to achieve complete etching. Thereafter, semiconductor material is deposited in the channel through hole to form the first effective semiconductor channel 1131 and the second effective semiconductor channel 1231 in the shape of an inverted tower.

[0097] The process of forming the arc-shaped channel wall of the first effective semiconductor channel 1131 and the channel wall of the second effective semiconductor channel 1231 may refer to the above-mentioned formation process, which will not be described in detail here.

[0098] However, in comparison, etching the two channel through holes into a structure that expands in a step-like manner from bottom to top so that the first effective semiconductor channel 1131 and the second effective semiconductor channel 1231 form a structure that expands in a step-like manner from bottom to top makes it easier to control the etching amplitude and reduces the process difficulty.

[0099] See also Figures 1 to 3 Furthermore, a contact guide 130 is provided between the write transistor 110 and the read transistor 120, the second source-drain 115 and the second gate 121 are conductively connected through the contact guide 130, and the central axis of the contact guide 130 coincides with the central axis of the first semiconductor channel 113 and the central axis of the second semiconductor channel 123. The upper surface of the contact guide 130 is in contact with the first semiconductor channel 113, the lower surface of the contact guide 130 is in contact with the second gate 121, and the contact guide 130 is insulated from the second semiconductor channel 123.

[0100] Specifically, the contact guide block 130 can be a square block, a rectangular block or a circular block, etc. In the present embodiment, the contact guide block 130 is a square block structure, which can be made of a conductive material, such as a conductive metal (conductor) material or a semiconductor material, etc., and is used to conductively connect the second source and drain 115 with the second gate 121 to achieve a conductive connection between the write transistor 110 and the read transistor 120.

[0101] The central axis of the contact guide block 130 coincides with the central axis of the first semiconductor channel 113 and the second semiconductor channel 123, that is, the second semiconductor channel 123, the contact guide block 130 and the first semiconductor channel 113 accurately correspond to each other with their central axes, so that the structure of the storage unit 100 is more regular, which is conducive to promoting the miniaturization of the storage unit 100 and improving the storage density.

[0102] In the embodiment of the present invention, the portion where the contact guide block 130 is in contact with the first semiconductor channel 113 forms the second source and drain 115 of the write transistor 110, that is, it can be understood that the partial structure of the upper surface where the contact guide block 130 is in contact with the first semiconductor channel 113 constitutes the second source and drain 115, and the second source and drain 115 is a part of the contact guide block 130. The contact guide block 130 and the second source and drain 115 are integrally formed, and the two are made of the same material. The second source and drain 115 can be directly conductively connected to the second gate 121 located on the contact guide block 130 through the contact guide block 130.

[0103] Exemplarily, the second source-drain 115 can be the drain of the write transistor 110, located at the bottom of the first semiconductor channel 113 and conductively connected to the contact guide block 130, and further conductively connected to the read transistor 120 through the contact guide block 130. The first source-drain 114 can be the source of the write transistor 110, located outside the first semiconductor channel 113 and conductively connected to the signal line, thereby realizing signal access of the write transistor 110.

[0104] The contact guide 130 is insulated from the second semiconductor channel 123. For example, the contact guide 130 can be insulated from the second semiconductor channel 123 by the second gate dielectric 122 layer, or an insulating layer is provided between the contact guide 130 and the second semiconductor channel 123 to insulate the two. In this way, the short circuit problem caused by the contact guide 130 being conductively connected to the second gate 121 and the second semiconductor channel 123 at the same time can be avoided.

[0105] See also Figures 1 to 3 Furthermore, in an embodiment of the present invention, the size of the lower surface of the contact guide block 130 is larger than the outer ring size of the second gate dielectric 122, and the size of the upper surface of the contact guide block 130 is larger than or equal to the size of the contact surface of the first semiconductor channel 113 in contact with it.

[0106] Specifically, the size of the lower surface of the contact guide 130 is larger than the outer ring size of the second gate dielectric 122, which can avoid the situation where the size of the lower surface of the contact guide 130 is smaller than the outer ring size of the second gate dielectric 122, and the contact with the second gate 121 surrounded by the second gate dielectric 122 is incomplete, thereby affecting the conduction. Moreover, the contact guide 130 in this embodiment can be designed as a block-shaped rectangular parallelepiped or a cube, that is, the lower surface of the contact guide 130 is a rectangle or a square, such as a square, and the cross section of the second gate dielectric 122 is annular. In order to enable the contact guide 130 to completely cover the second gate dielectric 122, it can also be achieved by designing the size of the lower surface of the contact guide 130 to be larger than the outer ring size of the second gate dielectric 122.

[0107] In addition, in order to ensure that the contact guide block 130 is in full contact with the first semiconductor channel 113 to ensure the formation of the second source and drain 115, such as to ensure that the size of the formed second source and drain 115 is large enough to ensure the conductive connection effect, the size of the upper surface of the contact guide block 130 in this embodiment is designed to be greater than or equal to the size of the contact surface of the first semiconductor channel 113 in contact with it. Since the second end of the first semiconductor channel 113 is in contact and connected with the contact guide block 130, it can also be understood that the size of the upper surface of the contact guide block 130 is greater than or equal to the size of the second end of the first semiconductor channel 113.

[0108] In an embodiment of the present invention, the contact surface between the first semiconductor channel 113 and the contact guide block 130 is the surface of the second end of the first semiconductor channel 113, that is, the bottom surface of the first semiconductor channel 113, which is a circular surface. Preferably, the size of the upper surface of the contact guide block 130 may be slightly larger than the size of the first semiconductor channel 113. For example, the upper surface of the contact guide block 130 may be designed to be a square, and the shape of the bottom surface of the first semiconductor channel 113 may be an inscribed circle of the square surface, so as to avoid the situation where the contact guide block 130 fails to completely cover the bottom surface of the first semiconductor channel 113 due to errors in the manufacturing process.

[0109] See also Figures 1 to 3 Furthermore, the upper surface of the second gate 121 is flush with the upper surface of the second gate dielectric 122 , and the upper surface of the second semiconductor channel 123 is lower than the upper surface of the second gate 121 and the upper surface of the second gate dielectric 122 .

[0110] An annular insulating layer 1221 is provided between the lower surface of the contact guide 130 and the upper surface of the second semiconductor channel 123 . The inner ring size of the annular insulating layer 1221 is equal to the outer ring size of the second gate dielectric 122 , and the outer ring size of the annular insulating layer 1221 is equal to the outer ring size of the second semiconductor channel 123 .

[0111] In the embodiment of the present invention, the upper surface of the second gate 121 and the upper surface of the second gate dielectric 122 are both in contact with the lower surface of the contact guide 130, or in other words, both are covered by the contact guide 130. The upper surface of the second gate 121 is flush with the upper surface of the second gate dielectric 122 to ensure that the surface of the first end of the read transistor 120 (i.e., the first end of the second gate 121) is flat and regular, and also ensure that the contact surface between the contact guide 130 and the second gate 121 and the second gate dielectric 122 is flat and regular, which facilitates the contact connection of the contact guide 130.

[0112] The upper surface of the second semiconductor channel 123 is lower than the upper surface of the second gate dielectric 122, so that the space between the upper surface of the second semiconductor channel 123 and the upper surface of the second gate dielectric 122 can be used to form an insulating spacer contacting the guide block 130 and the second semiconductor channel 123, such as the annular insulating layer 1221 mentioned above.

[0113] The annular insulating layer 1221 is made of insulating material and is an annular structure. It can be formed by horizontally extending outward from the top of the second gate dielectric 122, and the inner ring size of the annular insulating layer 1221 is equal to the outer ring size of the second gate dielectric 122, and the outer ring size is equal to the outer ring size of the second semiconductor channel 123, so as to space and block part of the structure of the second semiconductor channel 123 toward the contact guide block 130, so that the second semiconductor channel 123 and the contact guide block 130 are effectively insulated, and the structure is regular and flat, which is conducive to the integration and miniaturization of the storage unit 100 and improves the storage density.

[0114] Furthermore, in the embodiment of the present invention, the annular insulating layer 1221 and the second gate dielectric 122 are integrally formed, and the materials of the two are the same.

[0115] It can be understood that the annular insulating layer 1221 is a part of the second gate dielectric 122, specifically a partial structure of the second gate dielectric 122 located between the contact guide 130 and the second semiconductor channel 123, which is an annular structure and can be formed by horizontally extending outward from the top of the second gate dielectric 122. Exemplarily, in the process of depositing the second gate dielectric 122 on the inner wall of the second semiconductor channel 123, after the second gate dielectric 122 is deposited to a certain height, an insulating material of a certain thickness is deposited on the top of the second semiconductor channel 123 to extend outward from the top of the second gate dielectric 122 to form the annular insulating layer 1221, and the annular insulating layer 1221 can be located between the second semiconductor channel 123 and the contact guide 130.

[0116] In addition, an annular insulating layer is also provided between the lower surface of the fourth signal line 170 and the upper surface of the first semiconductor channel 113. The structure and formation method of this annular insulating layer are the same as the structure and formation method of the annular insulating layer 1221 on the lower surface of the contact guide block 130, that is, the inner ring size of this annular insulating layer is equal to the outer ring size of the first gate dielectric 112, and its outer ring size is equal to the outer ring size of the first semiconductor channel 113, and this annular insulating layer and the first gate dielectric 112 are integrally formed, and the materials of the two are the same.

[0117] For details about the annular insulating layer formed between the fourth signal line 170 and the first semiconductor channel 113 , reference may be made to the above contents about the annular insulating layer 1221 on the second gate dielectric 122 , and no further description is given here.

[0118] See also Figures 1 to 3 as well as Fig.18 The memory device 1000 of the embodiment of the present invention includes a semiconductor substrate 200 and at least one memory cell 100 according to any one of the above items formed on the semiconductor substrate 200, and when there are multiple memory cells 100, the memory cells 100 are electrically connected through signal lines.

[0119] When manufacturing the memory device 1000, multiple memory cells 100 are simultaneously formed on the semiconductor substrate 200, and can be insulated from each other by an insulating structure. For example, a dielectric layer / insulating layer can be formed between adjacent memory cells 100 to achieve insulation, thereby avoiding the problem of adjacent memory cells 100 not being able to work normally due to conduction.

[0120] Among them, the storage units 100 may be adjacent in the X-axis direction and / or the Y-axis direction. To realize signal transmission between multiple storage units 100, the multiple storage units 100 may be conductively connected in different directions through different signal lines distributed in the X-axis direction or the Y-axis direction.

[0121] Please continue reading Figures 1 to 3 as well as Figure 18 to Figure 19 Furthermore, in the embodiment of the present invention, there are multiple storage units 100, and the multiple storage units 100 form a storage array structure on a horizontal plane. The overall structure of the storage array structure is regular and compact, and the volume of the storage unit 100 can be controlled, thereby improving the storage density of the storage device 1000.

[0122] Furthermore, the plurality of memory cells 100 in the memory array structure are arranged in an array in a first direction and a second direction, and the first direction intersects the second direction.

[0123] It can be understood that by arranging a plurality of storage units 100 in an array to form a storage array structure, and increasing the number of storage units 100 in an array in a first direction (such as the Y / X axis direction) and a second direction (the X / Y axis direction), a storage device 1000 in an array structure of any scale can be formed, such as a storage device 1000 in a regular shape such as a cube, a cuboid or a quadrangular prism to meet different storage capacity requirements, and the structure of the storage device 1000 is regular and compact, and the volume of the storage device 1000 can be controlled to improve the storage density.

[0124] Furthermore, in an embodiment of the present invention, the first direction intersects the second direction at an angle of 90°.

[0125] For example, if the first direction is the Y-axis direction and the second direction is the X-axis direction, the two directions intersect at 90°, and multiple storage units 100 are arranged in an array in the Y-axis direction and the X-axis direction to form a storage array structure in the shape of a rectangular parallelepiped or a cube. The resulting storage device 1000 has a regular and compact structure. On the basis of improving a single storage unit 100, the storage density is further improved from the overall structural layout of the storage device 1000.

[0126] See also Fig.19 Furthermore, the memory device 1000 of the embodiment of the present invention further includes a first signal line 140, a second signal line 150, a third signal line 160 and a fourth signal line 170, the first signal line 140 and the second signal line 150 are signal lines conductively connected to the read transistor 120, the third signal line 160 and the fourth signal line 170 are signal lines conductively connected to the write transistor 110, the first signal line 140 and the third signal line 160 extend in a first direction, i.e., along the Y-axis direction, and the second signal line 150 and the fourth signal line 170 extend in a second direction, i.e., along the X-axis direction.

[0127] Since there are multiple memory cells 100, the number of the first signal line 140, the second signal line 150, the third signal line 160 and the fourth signal line 170 are all multiple, matching the number of rows and columns in the memory array structure, specifically, the number of the first signal line 140 and the third signal line 160 matches the number of columns of the memory cells 100 in the memory array structure. The number of the second signal line 150 and the fourth signal line 170 matches the number of rows. Among them, the number of the first signal line 140 is the same as the number of the third signal line 160, and the number of the second signal line 150 and the fourth signal line 170 is the same.

[0128] For example, if the number of columns of the memory cells 100 in the memory array structure is 10, that is, the memory cells 100 arranged along the first direction (Y-axis direction) in the memory array structure are 10 columns, then the number of the first signal lines 140 and the third signal lines 160 is 10. If the number of rows of the memory cells 100 in the memory array structure is 10, that is, the memory cells 100 arranged along the second direction (X-axis direction) in the memory array structure are 10 rows, then the number of the second signal lines 150 and the fourth signal lines 170 is 10.

[0129] The first signal line 140 is arranged at intervals in the second direction (X-axis) and is in contact with the fourth source and drain 125, and multiple fourth source and drain electrodes 125 of multiple read transistors 120 arranged at intervals in the first direction (X-axis) are connected to the same first signal line 140, wherein the first signal line 140 can be a bit line or a word line of the read transistor 120.

[0130] The second signal line 150 is arranged at intervals in the first direction (Y axis) and is in contact with the third source and drain 124, and multiple third source and drain electrodes 124 of multiple read transistors 120 arranged at intervals in the second direction (Y axis) are connected to the same second signal line 150, and the second signal line 150 is a word line or a bit line of the read transistor 120.

[0131] The third signal lines 160 are arranged at intervals in the second direction and are in contact with the first source and drain electrodes 114, and the plurality of first source and drain electrodes 114 of the plurality of write transistors 110 arranged at intervals in the first direction are connected to the same third signal line 160, wherein the third signal line 160 is the bit line of the write transistor 110. The fourth signal lines 170 are arranged at intervals in the first direction (Y axis) and are in contact with the first gate electrodes 111, and the plurality of first gate electrodes 111 of the plurality of write transistors 110 arranged at intervals in the second direction are connected to the same fourth signal line 170, wherein the fourth signal line 170 is the word line of the write transistor 110.

[0132] The working principle of the memory device 1000 in the embodiment of the present invention is that in the "write" operation, the fourth signal line 170 controls the opening of the write transistor 110, and transmits the potential of the third signal line 160 to the second gate 121 of the read transistor 120, so that the potential of the second gate 121 is synchronized with the third signal line 160 to achieve the writing of "0" and "1". Then, the fourth signal line 170 controls the write transistor 110 to be turned off. In the "read" operation, it is only necessary to judge the storage state according to the level of the current of the read transistor 120.

[0133] When multiple storage cells 100 are arranged in an array, the same fourth signal line 170 can control the opening of multiple write transistors 110 arranged in the first direction, and can transfer the potentials of multiple third signal lines 160 arranged at intervals in the second direction to the second gates 121 of the corresponding read transistors 120, so as to realize batch writing of "0" and "1" and improve the read and write efficiency of the storage device 1000.

[0134] See also Fig.18 In view of the positions of each signal line and the contact guide block 130, in the embodiment of the present invention, the first effective semiconductor channel 1131 is in a shape that tapers in a step-like manner from the third signal line 160 toward the contact guide block 130, and the second effective semiconductor channel 1231 is in a shape that tapers in a step-like manner from the second signal line 150 toward the first signal line 140.

[0135] Furthermore, the material of the fourth signal line 170 can be the same as that of the first gate 111, the material of the third signal line 160 can be the same as that of the first source and drain 114, the material of the second signal line 150 can be the same as that of the third source and drain 124, and the material of the first signal line 140 can be the same as that of the fourth source and drain 125, so as to achieve good coupling between corresponding parts.

[0136] Furthermore, in the embodiment of the present invention, the first signal line 140 and the fourth source and drain electrode 125 are integrally formed and the materials of the two are the same, which can be understood as the fourth source and drain electrode 125 is a part of the first signal line 140, and is a partial structure where the first signal line 140 contacts the second semiconductor channel 123. The second signal line 150 and the third source and drain electrode 124 are integrally formed and the materials of the two are the same, which can be understood as the third source and drain electrode 124 is a part of the second signal line 150, and is a partial structure where the second signal line 150 contacts the second semiconductor channel 123. The third signal line 160 and the first source and drain electrode 114 are integrally formed and the materials of the two are the same, which can be understood as the first source and drain electrode 114 is a part of the third signal line 160, and is a partial structure where the third signal line 160 contacts the first semiconductor channel 113.

[0137] The materials of the first signal line 140, the second signal line 150, the third signal line 160, the fourth signal line 170 and the contact guide block 130 may be the same or different, for example, they may be metal materials or conductive materials, such as TiN, Ti, Au, W, Mo, In-Ti-O (ITO), In-Zn-O (IZO), Cu, Ru, Ag, Pt and the like, or any combination of the above materials.

[0138] In the embodiment of the present invention, the first signal line 140, the second signal line 150, the third signal line 160, the fourth signal line 170 and the contact guide 130 are all made of TiN. The above description of the first signal line 140, the second signal line 150, the third signal line 160, the fourth signal line 170 and the contact guide 130 is only exemplary and should not be construed as limiting the present invention.

[0139] See also Fig. 20 The method for manufacturing the memory device 1000 according to the embodiment of the present invention is used to manufacture the memory device 1000 in any of the above embodiments. The method for manufacturing the memory device 1000 comprises the following steps:

[0140] S10: providing a semiconductor substrate 200, depositing a first insulating layer 101 and a first conductive material layer 102 on the semiconductor substrate 200 in sequence, and etching the first conductive material layer 102 to form first signal lines 140. Insulating materials are filled between adjacent first signal lines 140 for insulation isolation.

[0141] Please combine Figures 4 to 5 Specifically, the material of the semiconductor substrate 200 may include a variety of semiconductor materials, such as silicon (e.g., single crystal silicon Si), silicon germanium (SiGe), silicon on insulator (SOI), germanium (Ge), gallium arsenide (GaAs), indium phosphide (InP), germanium on insulator (GOI) and silicon carbide (SIC), etc.

[0142] Alternatively, the semiconductor substrate 200 may be made of a non-conductive material such as glass, plastic, or a sapphire wafer. Alternatively, the semiconductor substrate 200 may also be made of silicon dioxide (SiO 2 ), insulating dielectric materials such as silicon nitride (SiN), etc. Alternatively, the semiconductor substrate 200 may also be other materials, such as III-V compounds such as gallium arsenide.

[0143] In yet another embodiment, the semiconductor substrate 200 may be made of semiconductor material, insulating material, conductive material or any combination thereof.

[0144] In one embodiment, the semiconductor substrate 200 may be a single-layer structure, for example, a single-layer structure made of silicon, germanium, gallium arsenide, etc.

[0145] In another embodiment, the semiconductor substrate 200 may also be a multi-layer structure, for example, a layered substrate including a stack of silicon and silicon germanium, a stack of silicon and silicon carbide, silicon on insulator or silicon germanium on insulator, etc.

[0146] In the embodiment of the present invention, the semiconductor substrate 200 is a single crystal silicon substrate, and a silicon oxide film is formed on the surface of the semiconductor substrate 200 to protect the semiconductor substrate 200 .

[0147] In some embodiments, the first insulating layer 101 and the first conductive material layer 102 may be formed by deposition methods such as chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), and molecular layer deposition (MLD).

[0148] It can be understood that any suitable material and deposition process can be used to form the first insulating layer 101 and the first conductive material layer 102 .

[0149] For example, the material of the first insulating layer 101 may be SiOx, SiNx, Al 2 O 3 , HfO 2 、ZrO 2 、TiO 2 , Y 2 O 3 The above materials may include a combination of the above materials, a laminated material, or a combined laminated material, and may also be TEOS.

[0150] In the embodiment of the present invention, the material of the first insulating layer 101 is SiN.

[0151] Exemplarily, the material of the first conductive material layer 102 can be TiN, Ti, Au, W, Mo, In-Ti-O (ITO), In-Zn-O (IZO), Al, Cu, Ru, Ag, Pt or the like, or any combination of the above materials.

[0152] In the embodiment of the present invention, the material of the first conductive material layer 102 is TiN.

[0153] In one embodiment, the first signal line 140 may be formed by dry etching, wet etching, or a combination of dry etching and wet etching. In wet etching, chlorine or fluorine-based etchants may be used to etch the first conductive material layer 102 .

[0154] In the embodiment of the present invention, when forming the first signal line 140 , a photolithography process may be used to perform patterning, and then etching may be performed to transfer the pattern to the first conductive material layer 102 .

[0155] Exemplarily, a photoresist layer can be first formed on the first conductive material layer 102, and then the photoresist layer can be etched to form a photoresist pattern, wherein the photoresist pattern is a pattern corresponding to the shape of the first signal line 140, and the first conductive material layer 102 under the photoresist layer can be further etched based on the above-mentioned photoresist pattern to transfer the photoresist pattern to the first conductive material layer 102, that is, a pattern corresponding to the above-mentioned photoresist pattern is formed on the first conductive material layer 102, and finally the photoresist pattern is removed, and the first conductive material layer 102 is etched to form the first signal line 140.

[0156] In one embodiment, in order to increase the storage density of the memory device 1000 , the first signal line 140 may be formed by using a SADP (Self-Aligned Double Patterning) process to obtain a first signal line 140 with a smaller line width.

[0157] In step S10 , the first signal line 140 formed by etching extends in the first direction (Y-axis direction).

[0158] In addition, after the first insulating layer 101 and the first conductive material layer 102 are deposited, an optional annealing process (e.g., rapid thermal annealing, oxidation densification, etc.) and / or an optional planarization process (e.g., chemical mechanical planarization) may be performed to harden and / or planarize the first layer in the isolation so that the subsequent deposition stack remains flat. This step may also be applied to the processing of each layer in the other steps described below.

[0159] In addition, after forming the stacked first insulating layer 101 and the first conductive material layer 102, a mask layer, such as a photoresist layer and / or a hard mask layer, may be formed on the upper surface of the first conductive material layer 102, so as to facilitate subsequent etching of the first conductive material layer 102 based on the mask pattern in the patterned mask layer. This step may also be applicable to the processing of each layer in the following other steps.

[0160] In one embodiment, the mask layer may be a conductive or non-conductive material and may be selected from materials including silicon nitride, silicon oxynitride, amorphous silicon, polycrystalline silicon, polycrystalline silicon germanium, metal nitrides, metal silicides, metal oxides, and metals. The mask layer may be deposited by PVD, CVD, ALD, MLD sputtering deposition, or other techniques for depositing the selected material.

[0161] Once the mask layer is deposited, it can be patterned using, for example, a photolithography mask and an etching process. Once the mask layer is patterned, one or more suitable removal processes (e.g., ashing, selective etching, combinations) can be used to remove the areas that need to be removed while ensuring that the masked areas are not removed or damaged.

[0162] S20 : ​​depositing a first dielectric layer 103 and a second conductive material layer 104 in sequence on the layer where the first signal line 140 is located, and etching the second conductive material layer 104 to form a second signal line 150 .

[0163] Please refer to Figure 6 and Figure 7 It can be understood that the layer where the first signal line 140 is located is the original first conductive material layer 102 . In order to achieve insulation isolation from the second conductive material layer 104 , the first dielectric layer 103 is first deposited on the original first conductive material layer 102 .

[0164] Likewise, the first dielectric layer 103 and the second conductive material layer 104 may be formed by deposition methods such as chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), and molecular layer deposition (MLD).

[0165] It can be understood that any suitable material and deposition process can be used to form the first dielectric layer 103 and the second conductive material layer 104, and no specific limitation is made herein.

[0166] Exemplarily, the material of the first dielectric layer 103 is an insulating oxide, such as SiOx, SiNx, Al 2 O 3 , HfO 2 、ZrO 2 、TiO 2 , Y 2 O 3 The above materials may include a combination of the above materials, a laminated material, or a combined laminated material, and may also be TEOS.

[0167] In the embodiment of the present invention, the material of the first dielectric layer 103 is SiO 2 .

[0168] For example, the material of the second conductive material layer 104 may be TiN, Ti, Au, W, Mo, In-Ti-O (ITO), In-Zn-O (IZO), Al, Cu, Ru, Ag, Pt, etc., or any combination thereof. The material of the second conductive material layer 104 may be the same as or different from that of the first conductive material layer 102.

[0169] In the embodiment of the present invention, the material of the second conductive material layer 104 is the same as that of the first conductive material layer 102 , which is TiN.

[0170] In one embodiment, the second signal line 150 may be formed by dry etching, wet etching, or a combination of dry etching and wet etching. In the wet etching, chlorine or fluorine based etchants may be used to etch the second conductive material layer 104.

[0171] In the embodiment of the present invention, when forming the second signal line 150 , a photolithography process may be used to perform patterning first, and then etching may be performed to transfer the pattern to the second conductive material layer 104 .

[0172] Exemplarily, a photoresist layer can be first formed on the second conductive material layer 104, and then the photoresist layer is etched to form a photoresist pattern, wherein the photoresist pattern is a pattern corresponding to the shape of the second signal line 150, and the second conductive material layer 104 under the photoresist layer is further etched based on the above-mentioned photoresist pattern to transfer the photoresist pattern to the second conductive material layer 104, that is, a pattern corresponding to the above-mentioned photoresist pattern is formed on the second conductive material layer 104, and finally the photoresist pattern is removed, and the second conductive material layer 104 is etched to form the second signal line 150.

[0173] In one embodiment, in order to increase the storage density of the memory device 1000 , the second signal line 150 may be formed by using a SADP (Self-Aligned Double Patterning) process to obtain a second signal line 150 with a smaller line width.

[0174] In step S20 , the second signal line 150 formed by etching is extended in the second direction (X-axis direction).

[0175] S30: depositing a second insulating layer 105 and a first hard mask layer 106 in sequence on the layer where the second signal line 150 is located, and etching the first hard mask layer 106, the second insulating layer 105, the second signal line 150 and the first dielectric layer 103 to form a second through hole 107 extending in a vertical direction to the upper surface of the first signal line 140, wherein the aperture of the second through hole 107 located on the upper surface of the first dielectric layer 103 is different from the aperture of the second through hole 107 located on the lower surface of the first dielectric layer 103.

[0176] Please refer to Figure 8 and Fig. 9 The layer where the second signal line 150 is located is the original second conductive material layer 104. The second insulating layer 105 and the first hard mask layer 106 can be formed on the original second conductive material layer 104 in sequence by deposition methods such as chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD) and molecular layer deposition (MLD).

[0177] For example, the material of the second insulating layer 105 can be SiON, SiOx, SiNx, Al 2 O 3 , HfO 2 、ZrO 2 、TiO 2 , Y 2 O3 The above materials may include a combination of the above materials, a laminated material, or a combined laminated material, and may also be TEOS.

[0178] The material of the second insulating layer 105 may be the same as or different from that of the first insulating layer 101. In the embodiment of the present invention, the material of the second insulating layer 105 is different from that of the first insulating layer 101, and is SiN.

[0179] It is worth mentioning that the first hard mask layer 106 may be a single-layer structure or a stacked structure of multiple hard mask layers. The multi-layer structure may improve the etching selectivity of the hard mask layer.

[0180] In the embodiment of the present invention, the first hard mask layer 106 is a stacked structure of multiple hard mask layers, specifically a two-layer stacked structure of a SOC layer (Spin-on Carbon) and a SiON layer, and the SOC layer is deposited on the second insulating layer 105 .

[0181] It can be understood that any suitable material and deposition process can be used to form the second insulating layer 105 and the first hard mask layer 106 , and no specific limitation is made herein.

[0182] In one embodiment, the second through hole 107 may be formed by dry etching, wet etching, or a combination of dry etching and wet etching, wherein the wet etching may be performed using an etchant based on chlorine or fluorine.

[0183] Exemplarily, the second through hole 107 may be a rectangular hole, a cylindrical hole or other columnar hole shape, and the aperture of the second through hole 107 located on the upper surface of the first dielectric layer 103 (referred to as the upper aperture of the second through hole 107) is different from the aperture of the second through hole 107 located on the lower surface of the first dielectric layer 103 (referred to as the lower aperture of the second through hole 107), and the upper aperture of the second through hole 107 may be larger or smaller than the lower aperture of the second through hole 107.

[0184] Taking the example that the upper aperture diameter of the second through hole 107 is larger than the lower aperture diameter, when etching the second through hole 107, etching starts from the bottom end of the second through hole 107 (i.e., one end of the upper surface of the first signal line 140). After etching part of the inner wall of the second through hole 107, the inner wall is further etched upward and toward the outside of the second through hole 107 along the central axis of the second through hole 107, so that the inner wall of the second through hole 107 is offset outward by a certain distance layer by layer until the upper aperture diameter of the second through hole 107 is larger than the lower aperture diameter.

[0185] Furthermore, in the embodiment of the present invention, the plasma gas for etching the second insulating layer 105 is CH 3 F, CH 2 F 2 , O2 The plasma gas used for etching the first dielectric layer 103 is C 4 F 8 and O 2 The mixed gas, plasma source power is 800~1500W, and the bias voltage is 250~500V.

[0186] S40 : removing the first hard mask layer 106 , and forming a read transistor 120 in the second through hole 107 .

[0187] The first hard mask layer 106 may be removed by a wet method, a dry method, or a combination of a wet method and a dry method, which will not be described in detail herein.

[0188] See also Fig.10 After removing the first mask layer, a specific method of forming the read transistor 120 in the second through hole 107 may be to sequentially deposit a second semiconductor channel 123 , a second gate dielectric 122 and a second gate 121 in the second through hole 107 to form the read transistor 120 .

[0189] For example, a semiconductor material of a certain thickness may be deposited on the inner surface of the second through hole 107, and then back-etching may be performed to remove part of the semiconductor material above the second insulating layer 105 and within the second through hole 107 to form a second semiconductor channel 123. Then, a gate dielectric material and a gate material of a certain thickness may be deposited on the inner surface and the upper surface of the second semiconductor channel 123, and a planarization process (such as chemical mechanical polishing (CMP)) may be used to remove the gate dielectric material and the gate material above the second insulating layer 105 to form a second gate dielectric 122 and a second gate 121.

[0190] In some embodiments, the second semiconductor channel 123 , the second gate dielectric 122 and the second gate 121 may be formed by deposition methods such as chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD) and molecular layer deposition (MLD).

[0191] Among them, the material of the second gate 121 can be a metal material or a conductive material, such as TiN, Ti, Au, W, Mo, In-Ti-O (ITO), In-Zn-O (IZO), Cu, Ru, Ag, Pt and other materials or any combination of the above materials.

[0192] In the embodiment of the present invention, the material of the second gate 121 is IZO.

[0193] The material of the second semiconductor channel 123 may be an oxide semiconductor (OS), specifically ZnO, In 2 O 3, IGZO, ITO, IWO and IAZO (In-Al-Zn-O), etc.

[0194] In the embodiment of the present invention, the material of the second semiconductor channel 123 is In—Ga—Zn—O (IGZO).

[0195] The material of the second gate dielectric 122 may be an insulating material, such as SiOx, SiNx, Al 2 O 3 , HfO 2 、ZrO 2 、TiO 2 , Y 2 O 3 Combination materials, laminated materials, and combined laminated materials with materials such as HFO or the above materials.

[0196] In the embodiment of the present invention, the material of the second gate dielectric 122 is HFO.

[0197] It is understandable that any suitable material and deposition process may be used to form the second semiconductor channel 123 , the second gate dielectric 122 and the second gate 121 , and no specific limitation is made herein.

[0198] S50: depositing a third conductive material layer 108 on the second insulating layer 105, and etching the third conductive material layer 108 to form a contact guide 130, wherein the lower surface of the contact guide 130 is conductively connected to the second gate 121, and the contact guide 130 is insulated from the second semiconductor channel 123. Insulating material is filled between adjacent contact guides 130 for insulation isolation.

[0199] Please refer to Fig.11 and Fig.12 In some embodiments, the third conductive material layer 108 can be formed by deposition methods such as chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), and molecular layer deposition (MLD).

[0200] For example, the material of the third conductive material layer 108 may be TiN, Ti, Au, W, Mo, In-Ti-O (ITO), In-Zn-O (IZO), Al, Cu, Ru, Ag, Pt, etc., or any combination thereof. The material of the third conductive material layer 108 may be the same as or different from the material of the second conductive material layer 104 and the material of the first conductive material layer 102.

[0201] In the embodiment of the present invention, the material of the third conductive material layer 108 is the same as that of the first conductive material layer 102 and the second conductive material layer 104 , which is TiN.

[0202] After the third conductive material layer 108 is deposited and formed, the third conductive material layer 108 is etched at the position corresponding to the read transistor 120 to form a contact guide block 130. The contact guide block 130 may be in a block shape, a granular shape, etc., and its lower surface is conductively connected to the second gate 121, and covers the second gate dielectric 122 and the annular insulating layer 1221, so as to achieve a close connection with the read transistor 120 and effectively insulate from the second semiconductor channel 123.

[0203] In the embodiment of the present invention, the shape of the lower surface of the contact guide 130 is adapted to the shape of the top surface of the read transistor 120, so as to ensure that the contact guide 130 is closely adapted to the read transistor 120. For example, if the top surface of the read transistor 120 is in a square shape, the shape of the lower surface of the contact guide 130 may be in a square shape, and if the top surface of the read transistor 120 is in a circular shape, the shape of the lower surface of the contact guide 130 may be in a circular shape.

[0204] In the embodiment of the present invention, the contact guide block 130 is etched into a rectangular body with square upper and lower surfaces.

[0205] In one embodiment, the contact guide block 130 may be formed by dry etching, wet etching, or a combination of dry etching and wet etching, wherein the wet etching may be performed using an etchant based on chlorine or fluorine.

[0206] In the embodiment of the present invention, the end of the read transistor 120 in contact with the contact guide block 130 is the first end of the read transistor 120, and is also the first end of the second gate 121. The end of the read transistor 120 in contact with the first signal line 140 is the second end of the read transistor 120, and is also the second end of the second gate 121. The portion of the second semiconductor channel 123 between the first signal line 140 and the second signal line 150 is the second effective semiconductor channel 1231. The second effective semiconductor channel 1231 is in a shape that gradually expands from the first signal line 140 to the second signal line 150. The portion of the first signal line 140 in contact with the second semiconductor channel 123 is the fourth source and drain 125, and the portion of the second signal line 150 in contact with the second semiconductor channel 123 is the third source and drain 124.

[0207] The outer ring size of the channel of the second effective semiconductor channel 1231 near the third source and drain 124 is different from the outer ring size of the channel near the fourth source and drain 125, that is, the outer ring size of the channel of the second effective semiconductor channel 1231 near the second signal line 150 is different from the outer ring size of the channel near the first signal line 140. Specifically, the outer ring size of the channel of the second effective semiconductor channel 1231 near the second signal line 150 is larger than the outer ring size of the channel near the first signal line 140.

[0208] In addition, the second effective semiconductor channel 1231 is the portion of the second semiconductor channel 123 located in the first dielectric layer 103, that is, the outer ring size of the channel of the second effective semiconductor channel 1231 on the upper surface of the first dielectric layer 103 is different from the outer ring size of the channel on the lower surface of the first dielectric layer 103. Specifically, the second effective semiconductor channel 1231 gradually expands from bottom to top in the first dielectric layer 103.

[0209] S60: depositing the second dielectric layer 109 and the fourth conductive material layer 10a on the layer where the contact guide block 130 is located, etching the fourth conductive material layer 10a to form a third signal line 160, the third signal line 160 is the bit line of the write transistor 110. The adjacent third signal lines 160 are filled with insulating material for insulation isolation.

[0210] See also Fig.13 and Fig.14 It can be understood that the layer where the contact guide block 130 is located is the original third conductive material layer 108 . In order to achieve insulation isolation from the fourth conductive material layer 10a , the second dielectric layer 109 is first deposited on the original third conductive material layer 108 .

[0211] Likewise, the second dielectric layer 109 and the fourth conductive material layer 10a may be formed by deposition methods such as chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), and molecular layer deposition (MLD).

[0212] It can be understood that any suitable material and deposition process can be used to form the second dielectric layer 109 and the fourth conductive material layer 10a, and no specific limitation is made herein.

[0213] Exemplarily, the material of the second dielectric layer 109 is an insulating oxide, such as SiOx, SiNx, Al 2 O 3 , HfO 2 、ZrO 2 、TiO 2 , Y 2 O 3 The above materials may include a combination of the above materials, a laminated material, or a combined laminated material, and may also be TEOS.

[0214] In the embodiment of the present invention, the material of the second dielectric layer 109 is SiO 2 .

[0215] For example, the material of the fourth conductive material layer 10a may be TiN, Ti, Au, W, Mo, In-Ti-O (ITO), In-Zn-O (IZO), Al, Cu, Ru, Ag, Pt, etc., or any combination thereof. The material of the fourth conductive material layer 10a may be the same as or different from that of the other conductive material layers.

[0216] In the embodiment of the present invention, the material of the fourth conductive material layer 10 a is the same as that of the other conductive material layers, which is TiN.

[0217] In one embodiment, the third signal line 160 may be formed by dry etching, wet etching, or a combination of dry etching and wet etching, wherein the wet etching may use a chlorine or fluorine based etchant to etch the fourth conductive material layer 10a.

[0218] In the embodiment of the present invention, when forming the third signal line 160 , a photolithography process may be used to perform patterning first, and then etching may be performed to transfer the pattern to the fourth conductive material layer 10 a .

[0219] Exemplarily, a photoresist layer can be first formed on the fourth conductive material layer 10a, and then the photoresist layer is etched to form a photoresist pattern, wherein the photoresist pattern is a pattern corresponding to the shape of the third signal line 160, and the fourth conductive material layer 10a below the photoresist layer is further etched based on the above-mentioned photoresist pattern to transfer the photoresist pattern to the fourth conductive material layer 10a, that is, a pattern corresponding to the above-mentioned photoresist pattern is formed on the fourth conductive material layer 10a, and finally the photoresist pattern is removed, and the fourth conductive material layer 10a is etched to form the third signal line 160.

[0220] In one embodiment, in order to increase the storage density of the memory device 1000 , the third signal line 160 may be formed by using a SADP (Self-Aligned Double Patterning) process to obtain a third signal line 160 with a smaller line width.

[0221] In step S60 , the third signal line 160 formed by etching is extended toward the first direction (Y-axis direction).

[0222] S70: A third insulating layer 10b and a second hard mask layer 10c are sequentially deposited on the layer where the third signal line 160 is located, and the second hard mask layer 10c, the third insulating layer 10b, the third signal line 160 and the second dielectric layer 109 are etched to form a first through hole 10d extending in a vertical direction to the upper surface of the contact guide block 130. The aperture of the first through hole 10d located on the upper surface of the second dielectric layer 109 is different from the aperture of the first through hole 10d located on the lower surface of the second dielectric layer 109.

[0223] See also Fig.15 and Fig.16 The layer where the third signal line 160 is located is the original fourth conductive material layer 10a. The third insulating layer 10b and the second hard mask layer 10c can be formed on the original fourth conductive material layer 10a in sequence by deposition methods such as chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD) and molecular layer deposition (MLD).

[0224] For example, the material of the third insulating layer 10b may be SiON, SiOx, SiNx, Al 2 O 3 , HfO 2 、ZrO 2 、TiO 2 , Y 2 O 3 The above materials may include a combination of the above materials, a laminated material, or a combined laminated material, and may also be TEOS.

[0225] The material of the third insulating layer 10b can be the same as or different from the materials of the other insulating layers. In the embodiment of the present invention, the material of the third insulating layer 10b is the same as that of the second insulating layer 105, that is, SiN.

[0226] It is worth mentioning that the second hard mask layer 10c can be a single-layer structure or a stacked structure of multiple hard mask layers. The multi-layer structure can improve the etching selectivity of the hard mask layer.

[0227] In the embodiment of the present invention, the second hard mask layer 10c is a stacked structure of multiple hard mask layers, specifically a two-layer stacked structure of a SOC layer (Spin-on Carbon) and a SiON layer, and the SOC layer is deposited on the third insulating layer 10b.

[0228] It can be understood that any suitable material and deposition process can be used to form the third insulating layer 10b and the second hard mask layer 10c, and no specific limitation is made herein.

[0229] In one embodiment, the first through hole 10d may be formed by dry etching, wet etching, or a combination of dry etching and wet etching. In the wet etching, a chlorine or fluorine-based etchant may be used to etch the second hard mask layer 10c, the third insulating layer 10b, the third signal line 160, and the second dielectric layer 109.

[0230] Exemplarily, the first through hole 10d may be a rectangular hole, a cylindrical hole or other columnar hole shape, and the aperture of the portion of the first through hole 10d located on the upper surface of the second dielectric layer 109 (referred to as the upper aperture of the first through hole 10d) is different from the aperture of the portion of the first through hole 10d located on the lower surface of the second dielectric layer 109 (referred to as the lower aperture of the first through hole 10d), and the upper aperture of the first through hole 10d may be larger or smaller than the lower aperture of the first through hole 10d.

[0231] Taking the example that the upper aperture diameter of the first through hole 10d is larger than the lower aperture diameter, when etching the first through hole 10d, etching starts from the bottom end of the first through hole 10d (i.e., the end contacting the upper surface of the guide block 130), and after etching part of the inner wall of the first through hole 10d, the inner wall is continuously etched upward and toward the outside of the first through hole 10d along the central axis of the first through hole 10d, so that the inner wall of the first through hole 10d is offset outward by a certain distance layer by layer until the upper aperture diameter of the first through hole 10d is larger than the lower aperture diameter.

[0232] Furthermore, in the embodiment of the present invention, the plasma gas for etching the third insulating layer 10b is CH 3 F, CH 2 F 2 , O 2 The plasma source power is 500-1000W, and the bias voltage is 200-500V. The plasma gas for etching the second dielectric layer 109 is C 4 F 8 and O 2 The mixed gas, plasma source power is 800~1500W, and the bias voltage is 250~500V.

[0233] S80: removing the second hard mask layer 10c, and forming a write transistor 110 in the first through hole 10d.

[0234] The second hard mask layer 10 c may be removed by a wet method, a dry method, or a combination of a wet method and a dry method, which will not be described in detail herein.

[0235] See also Fig.17 After removing the second mask layer, a specific method of forming the write transistor 110 in the first through hole 10d may be to sequentially deposit a first semiconductor channel 113, a first gate dielectric 112 and a first gate 111 in the first through hole 10d to form the write transistor 110.

[0236] For example, a semiconductor material of a certain thickness may be deposited on the inner surface of the first through hole 10d, and then back-etching may be performed to remove part of the semiconductor material above the third insulating layer 10b and within the first through hole 10d to form a first semiconductor channel 113. Then, a gate dielectric material and a gate material of a certain thickness may be deposited on the inner surface and the upper surface of the first semiconductor channel 113, and a planarization process (such as chemical mechanical polishing (CMP)) may be used to remove the gate dielectric material and the gate material above the third insulating layer 10b to form a first gate dielectric 112 and a first gate 111.

[0237] In some embodiments, the first semiconductor channel 113 , the first gate dielectric 112 , and the first gate 111 may be formed by deposition methods such as chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), and molecular layer deposition (MLD).

[0238] Among them, the material of the first gate 111 can be a metal material or a conductive material, such as TiN, Ti, Au, W, Mo, In-Ti-O (ITO), In-Zn-O (IZO), Cu, Ru, Ag, Pt and other materials or any combination of the above materials.

[0239] In the embodiment of the present invention, the material of the first gate 111 is IZO.

[0240] The material of the first semiconductor channel 113 may be an oxide semiconductor (OS), specifically ZnO, In 2 O 3 , IGZO, ITO, IWO and IAZO (In-Al-Zn-O), etc.

[0241] In the embodiment of the present invention, the material of the first semiconductor channel 113 is In—Ga—Zn—O (IGZO).

[0242] The material of the first gate dielectric 112 may be an insulating material, such as SiOx, SiNx, Al 2 O 3 , HfO 2 、ZrO 2 、TiO 2 , Y 2 O 3 Combination materials, laminated materials, and combined laminated materials with materials such as HFO or the above materials.

[0243] In the embodiment of the present invention, the material of the first gate dielectric 112 is HFO.

[0244] It is understandable that any suitable material and deposition process may be used to form the first semiconductor channel 113 , the first gate dielectric 112 and the first gate 111 , and no specific limitation is made herein.

[0245] S90 : depositing a fifth conductive material layer 10 e on the third insulating layer 10 b , and etching the fifth conductive material layer 10 e to form a fourth signal line 170 in contact with the first gate 111 . The fourth signal line 170 is a word line of the write transistor 110 .

[0246] See also Fig.18 and Fig.19 In some embodiments, the fifth conductive material layer 10e can be formed by deposition methods such as chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), and molecular layer deposition (MLD).

[0247] Exemplarily, the material of the fifth conductive material layer 10e can be TiN, Ti, Au, W, Mo, In-Ti-O (ITO), In-Zn-O (IZO), Al, Cu, Ru, Ag, Pt or the like, or any combination of the above materials.

[0248] The material of the fifth conductive material layer 10e can be the same as or different from the materials of the other metal layers. In the embodiment of the present invention, the material of the fifth conductive material layer 10e is the same as the materials of the other metal layers, which is TiN.

[0249] It can be understood that any suitable material and deposition process can be used to form the fifth conductive material layer 10e, and no specific limitation is made herein.

[0250] In one embodiment, the fourth signal line 170 may be formed by dry etching, wet etching, or a combination of dry etching and wet etching, wherein the wet etching may use a chlorine or fluorine-based etchant to etch the fifth conductive material layer 10e.

[0251] In the embodiment of the present invention, when forming the fourth signal line 170 , a photolithography process may be used to perform patterning first, and then etching may be performed to transfer the pattern to the fifth conductive material layer 10 e .

[0252] Exemplarily, a photoresist layer can be first formed on the fifth conductive material layer 10e, and then the photoresist layer is etched to form a photoresist pattern, wherein the photoresist pattern is a pattern corresponding to the shape of the fourth signal line 170, and based on the above-mentioned photoresist pattern, the fifth conductive material layer 10e under the photoresist layer is further etched to transfer the photoresist pattern to the fifth conductive material layer 10e, that is, a pattern corresponding to the above-mentioned photoresist pattern is formed on the fifth conductive material layer 10e, and finally the photoresist pattern is removed, and the fifth conductive material layer 10e is etched to form the fourth signal line 170.

[0253] In one embodiment, in order to increase the storage density of the memory device 1000 , the fourth signal line 170 may be formed by using a SADP (Self-Aligned Double Patterning) process to obtain a fourth signal line 170 with a smaller line width.

[0254] In step S90 , the fourth signal line 170 formed by etching is extended toward the second direction (X-axis direction).

[0255] In the embodiment of the present invention, the end of the write transistor 110 in contact with the fourth signal line 170 is the first end of the write transistor 110, and is also the first end of the first gate 111. The end of the write transistor 110 in contact with the contact guide block 130 is the second end of the write transistor 110, and is also the second end of the first gate 111. The portion of the first semiconductor channel 113 between the third signal line 160 and the contact guide block 130 is the first effective semiconductor channel 1131. The first effective semiconductor channel 1131 is in a shape that gradually expands from the contact guide block 130 to the third signal line 160. The portion of the contact guide block 130 in contact with the first semiconductor channel 113 is the second source and drain 115, and the portion of the third signal line 160 in contact with the first semiconductor channel 113 is the first source and drain 114.

[0256] The outer ring size of the channel of the first effective semiconductor channel 1131 near the first source and drain 114 is different from the outer ring size of the channel near the second source and drain 115, that is, the outer ring size of the channel of the first effective semiconductor channel 1131 near the third signal line 160 is different from the outer ring size of the channel near the contact guide block 130. Specifically, the outer ring size of the channel of the first effective semiconductor channel 1131 near the third signal line 160 is larger than the outer ring size of the channel near the contact guide block 130.

[0257] In addition, the first effective semiconductor channel 1131 is the portion of the first semiconductor channel 113 located in the second dielectric layer 109, that is, the outer ring size of the channel of the first effective semiconductor channel 1131 on the upper surface of the second dielectric layer 109 is different from the outer ring size of the channel on the lower surface of the second dielectric layer 109. Specifically, the first effective semiconductor channel 1131 gradually expands from bottom to top in the second dielectric layer 109.

[0258] Furthermore, in the embodiment of the present invention, step S10 may include the steps of:

[0259] S101: depositing a third hard mask layer on the first conductive material layer 102, and etching the third hard mask layer and the first conductive material layer 102 to form a stacked structure of the third hard mask layer and the first signal line 140;

[0260] Among them, the structure and formation process of the third hard mask layer can refer to the structure and formation process of the first hard mask layer 106 mentioned above, the difference is that an amorphous carbon layer and a SiON layer are sequentially deposited on the first conductive material layer 102, an SOC layer is deposited on the SiON layer, and a SiON layer is deposited on the SOC layer to form the third hard mask layer.

[0261] In one embodiment, the process of etching the third hard mask layer and the first conductive material layer 102 may be dry etching, wet etching, or a combination of dry etching and wet etching. In the wet etching, chlorine or fluorine based etchants may be used to etch the third hard mask layer and the first conductive material layer 102.

[0262] S102: removing the third hard mask layer to expose the first signal line 140 and the first insulating layer 101;

[0263] The third hard mask layer may be removed by a wet method, a dry method, or a combination of a wet method and a dry method, which will not be described in detail herein.

[0264] S103: depositing a fourth insulating layer on the first signal line 140 and on the surface of the first insulating layer 101 that is not shielded by the first signal line 140 ;

[0265] The fourth insulating layer can be formed by deposition methods such as chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), and molecular layer deposition (MLD). The material of the fourth insulating layer can be SiON, SiOx, SiNx, Al 2 O 3 , HfO 2 、ZrO 2 、TiO 2 , Y 2 O 3 The above materials may include a combination of the above materials, a laminated material, or a combined laminated material, and may also be TEOS.

[0266] In the embodiment of the present invention, the material of the fourth insulating layer is SiN.

[0267] S104 : grinding the fourth insulating layer until the first signal line 140 is exposed, and retaining the fourth insulating layer on the first insulating layer 101 .

[0268] The fourth insulating layer may be polished flat by chemical-mechanical polishing (CMP).

[0269] It can be understood that the first conductive material layer 102 can be etched to form a plurality of first signal lines 140 spaced apart along the second direction. In this step, the fourth insulating layer is used to space adjacent first signal lines 140, and the fourth insulating layer on the first insulating layer 101 is integrated with the first insulating layer 101 to ensure a smooth surface for subsequent deposition of other structures.

[0270] Furthermore, in the embodiment of the present invention, step S20 may include the steps of:

[0271] S201: depositing a fourth hard mask layer on the second conductive material layer 104, and etching the fourth hard mask layer and the second conductive material layer 104 to form a stacked structure of the fourth hard mask layer and the second signal line 150;

[0272] Among them, the structure and formation process of the fourth hard mask layer can refer to the structure and formation process of the first hard mask layer 106 mentioned above, the difference is that an amorphous carbon layer and a SiON layer are sequentially deposited on the second conductive material layer 104, an SOC layer is deposited on the SiON layer, and a SiON layer is deposited on the SOC layer to form the fourth hard mask layer.

[0273] In one embodiment, the process of etching the fourth hard mask layer and the second conductive material layer 104 can be dry etching, wet etching, or a combination of dry etching and wet etching. In the wet etching, chlorine or fluorine-based etchants can be used to etch the fourth hard mask layer and the second conductive material layer 104.

[0274] S202: removing the fourth hard mask layer to expose the second signal line 150 and the first dielectric layer 103;

[0275] The fourth hard mask layer may be removed by a wet method, a dry method, or a combination of a wet method and a dry method, which will not be described in detail herein.

[0276] S203: depositing a fifth insulating layer on the second signal line 150 and on the surface of the first dielectric layer 103 that is not shielded by the second signal line 150;

[0277] The fifth insulating layer can be formed by deposition methods such as chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), and molecular layer deposition (MLD). The material of the fifth insulating layer can be SiON, SiOx, SiNx, Al 2 O 3 , HfO 2 、ZrO 2 、TiO 2 , Y 2 O 3The above materials may include a combination of the above materials, a laminated material, or a combined laminated material, and may also be TEOS.

[0278] In the embodiment of the present invention, the material of the fifth insulating layer is SiN.

[0279] S204 : grinding the fifth insulating layer until the second signal line 150 is exposed, and retaining the fifth insulating layer on the first dielectric layer 103 .

[0280] The fifth insulating layer may be polished flat by chemical-mechanical polishing (CMP).

[0281] It can be understood that the second conductive material layer 104 can be etched to form a plurality of second signal lines 150 spaced apart along the first direction. In this step, the fifth insulating layer is used to space adjacent second signal lines 150, and the fifth insulating layer on the first dielectric layer 103 is used to isolate the first dielectric layer 103 from other layers subsequently deposited thereon.

[0282] Furthermore, in the embodiment of the present invention, the process of forming the second through hole 107 in step S30 includes the following steps:

[0283] S301: forming a first photoresist layer on the first hard mask layer 106, and etching the first photoresist layer to form a first photoresist pattern;

[0284] The portion of the first photoresist layer where the first photoresist pattern is to be formed can be formed into a designed shape by photolithography, that is, a first photoresist pattern is formed. The shape corresponding to the first photoresist pattern is the hole shape of the second through hole 107, such as a circle, a square or other shapes.

[0285] S302: etching the first hard mask layer 106 to transfer the first photoresist pattern to the first hard mask layer 106 and the second insulating layer 105;

[0286] After etching the first photoresist layer to form a first photoresist pattern, the first hard mask layer 106 and the second insulating layer 105 under the first photoresist layer are further etched based on the first photoresist pattern to transfer the first photoresist pattern to the first hard mask layer 106 and the second insulating layer 105, that is, patterns corresponding to the first photoresist pattern are formed on both the first hard mask layer 106 and the second insulating layer 105.

[0287] In one embodiment, the process of etching the first hard mask layer 106 and the second insulating layer 105 can be dry etching, wet etching, or a combination of dry etching and wet etching. In the wet etching, chlorine or fluorine based etchants can be used to etch the first hard mask layer 106 and the second insulating layer 105.

[0288] S303: removing the first photoresist pattern, etching the second signal line 150 and the first dielectric layer 103, and forming a second through hole 107 extending from the upper surface of the second insulating layer 105 to the upper surface of the first signal line 140 in a vertical direction;

[0289] In one embodiment, the process of removing the first photoresist pattern may be a wet cleaning or an ashing process.

[0290] In one embodiment, the process of etching the second signal line 150 and the first dielectric layer 103 may be dry etching, wet etching, or a combination of dry etching and wet etching. In wet etching, chlorine or fluorine based etchants may be used to etch the second signal line 150 and the first dielectric layer 103.

[0291] The specific method of etching the first dielectric layer 103 is to etch the first dielectric layer 103 step by step in a vertical direction so that the aperture of the second through hole 107 located on the upper surface of the first dielectric layer 103 is different from the aperture of the second through hole 107 located on the lower surface of the first dielectric layer 103.

[0292] If the first dielectric layer 103 is etched stepwise from bottom to top along the central axis of the second through hole 107, the aperture of the portion of the second through hole 107 located on the upper surface of the first dielectric layer 103 will be larger than the aperture of the portion of the second through hole 107 located on the lower surface of the first dielectric layer 103. If the first dielectric layer 103 is etched stepwise from bottom to top along the central axis of the second through hole 107, the aperture of the portion of the second through hole 107 located on the upper surface of the first dielectric layer 103 will be smaller than the aperture of the portion of the second through hole 107 located on the lower surface of the first dielectric layer 103.

[0293] For example, the second through hole 107 after etching is approximately in the shape of a quadrangular prism, and the aperture of the second through hole 107 located on the upper surface of the first dielectric layer 103 is larger than the aperture of the second through hole 107 located on the lower surface of the first dielectric layer 103.

[0294] The peripheral wall of the second through hole 107 after etching includes four side walls, and the four side walls are connected to form a peripheral wall. Each side wall can be formed by smoothly connecting multiple vertical planes distributed in the Z-axis direction. Each vertical plane can extend in the Y-axis and Z-axis directions, or in the X-axis and Z-axis directions, and two adjacent vertical planes on the same side wall are staggered in the Y-axis direction or the X-axis direction, that is, the positive projections of two adjacent vertical planes in the Z-axis direction are staggered to form a stepped surface, that is, the four side walls are all stepped side walls, so that the second through hole 107 after etching is roughly in the shape of an inverted tower.

[0295] Before etching, the second through hole 107 is in the shape of a rectangular parallelepiped, and its opening shape can be a square. During etching, the bottom vertical plane can be first etched on the peripheral wall of the second through hole 107, that is, etching can be started near the lower surface of the first dielectric layer 103. At this time, the four vertical planes are connected together, which is approximately a rectangular space. Etching is continued upward to form a second layer of vertical planes. The four vertical planes of the second layer are connected to form a larger rectangular space. Etching is continued upward to form the third layer, the fourth layer... until the upper surface of the first dielectric layer 103 is etched to achieve complete etching.

[0296] Furthermore, in the embodiment of the present invention, step S50 includes the steps of:

[0297] S501: depositing a fifth hard mask layer on the third conductive material layer 108, forming a third photoresist layer on the fifth hard mask layer, etching the third photoresist layer to form a third photoresist pattern, etching the fifth hard mask layer, transferring the third photoresist pattern to the fifth hard mask layer, and then removing the third photoresist pattern;

[0298] The content of depositing and forming the fifth hard mask layer may refer to the formation process of the first hard mask layer 106 to the fourth hard mask layer, and will not be described in detail here.

[0299] The portion of the third photoresist layer where the third photoresist pattern is to be formed can be formed into a designed shape by photolithography, i.e., a third photoresist pattern is formed. The shape corresponding to the third photoresist pattern is the hole shape of the through hole, such as a circle, a square or other shapes. In the embodiment of the present invention, the third photoresist pattern is a square.

[0300] After etching the third photoresist layer to form a third photoresist pattern, the fifth hard mask layer under the third photoresist layer is further etched based on the third photoresist pattern to transfer the third photoresist pattern to the fifth hard mask layer, thereby forming a pattern corresponding to the third photoresist pattern on the fifth hard mask layer.

[0301] In one embodiment, the process of removing the third photoresist pattern may be a wet cleaning or an ashing process.

[0302] S502: depositing a sixth insulating layer on the fifth hard mask layer and the third photoresist pattern, removing the sixth insulating layer on the surface of the fifth hard mask layer, and retaining the sixth insulating layer in the third photoresist pattern;

[0303] The formation and removal of the sixth insulating layer may refer to the formation and removal of the fifth insulating layer described above, and will not be described in detail here.

[0304] S503: removing the fifth hard mask layer, and etching the third conductive material layer 108 by using the remaining sixth insulating layer as a mask to form a contact guide 130, wherein the lower surface of the contact guide 130 is conductively connected to the second gate 121, and the contact guide 130 is insulated from the second semiconductor channel 123;

[0305] In this step, the shape of the contact guide block 130 formed is adapted to the shape of the upper opening of the second through hole 107 , for example, the contact guide block 130 formed is a rectangular block, and its upper and lower surfaces are both approximately square.

[0306] S504 : removing the remaining sixth insulating layer, depositing a seventh insulating layer on the contact guide 130 and the second insulating layer 105 , grinding the seventh insulating layer until the contact guide 130 is exposed, and retaining the seventh insulating layer on the second insulating layer 105 .

[0307] A plurality of contact guides 130 may be formed by etching the third conductive material layer 108 . In this step, the seventh insulating layer remaining on the second insulating layer 105 is used to separate and insulate adjacent contact guides 130 to prevent electrical connection between adjacent contact guides 130 .

[0308] Furthermore, in the embodiment of the present invention, step S60 may include the steps of:

[0309] S601: depositing a sixth hard mask layer on the fourth conductive material layer 10 a , and etching the sixth hard mask layer and the fourth conductive material layer 10 a to form a stacked structure of the sixth hard mask layer and the third signal line 160 ;

[0310] Among them, the structure and formation process of the sixth hard mask layer can refer to the structure and formation process of the first hard mask layer above, the difference is that an amorphous carbon layer and a SiON layer are sequentially deposited on the fourth conductive material layer 10a, an SOC layer is deposited on the SiON layer, and a SiON layer is deposited on the SOC layer to form the sixth hard mask layer.

[0311] S602: removing the sixth hard mask layer to expose the third signal line 160 and the second dielectric layer 109;

[0312] The sixth hard mask layer may be removed by a wet method, a dry method, or a combination of a wet method and a dry method, which will not be described in detail herein.

[0313] S603: depositing an eighth insulating layer on the third signal line 160 and on the surface of the second dielectric layer 109 that is not shielded by the third signal line 160;

[0314] The eighth insulating layer can be formed by deposition methods such as chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), and molecular layer deposition (MLD). The material of the eighth insulating layer can be SiON, SiOx, SiNx, Al 2 O 3 , HfO 2 、ZrO 2 、TiO 2 , Y 2 O 3 The above materials may include a combination of the above materials, a laminated material, or a combined laminated material, and may also be TEOS.

[0315] In the embodiment of the present invention, the material of the eighth insulating layer is SiN.

[0316] S604 : grinding the eighth insulating layer until the third signal line 160 is exposed, and retaining the eighth insulating layer on the second dielectric layer 109 .

[0317] The eighth insulating layer may be polished flat by chemical-mechanical polishing (CMP).

[0318] It can be understood that the fourth conductive material layer 10a can be etched to form a plurality of third signal lines 160 spaced apart along the first direction. In this step, the eighth insulating layer is used to space adjacent third signal lines 160, and the eighth insulating layer on the second dielectric layer 109 is used to isolate the second dielectric layer 109 from other layers subsequently deposited thereon.

[0319] Furthermore, in the embodiment of the present invention, the process of forming the first through hole 10d in step S70 includes the following steps:

[0320] S701: forming a second photoresist layer on the second hard mask layer 10c, and etching the second photoresist layer to form a second photoresist pattern;

[0321] The portion of the second photoresist layer where the second photoresist pattern is to be formed can be formed into a designed shape by photolithography, that is, a second photoresist pattern is formed. The shape corresponding to the second photoresist pattern is the hole shape of the first through hole 10d, such as a circle, a square or other shapes.

[0322] S702: etching the second hard mask layer 10c to transfer the second photoresist pattern to the second hard mask layer 10c and the third insulating layer 10b;

[0323] After etching the second photoresist layer to form a second photoresist pattern, the second hard mask layer 10c and the third insulating layer 10b under the second photoresist layer are further etched based on the second photoresist pattern, and the second photoresist pattern is transferred to the second hard mask layer 10c and the third insulating layer 10b, that is, patterns corresponding to the second photoresist pattern are formed on both the second hard mask layer 10c and the third insulating layer 10b.

[0324] In one embodiment, the process of etching the second hard mask layer 10c and the third insulating layer 10b can be dry etching, wet etching, or a combination of dry etching and wet etching. In the wet etching, chlorine or fluorine based etchants can be used to etch the second hard mask layer 10c and the third insulating layer 10b.

[0325] S703: removing the second photoresist pattern, etching the third signal line 160 and the second dielectric layer 109, and forming a first through hole 10d extending from the upper surface of the third insulating layer 10b to the upper surface of the contact guide block 130 in a vertical direction;

[0326] In one embodiment, the process of removing the second photoresist pattern may be a wet cleaning or an ashing process.

[0327] In one embodiment, the process of etching the third signal line 160 and the second dielectric layer 109 can be dry etching, wet etching, or a combination of dry etching and wet etching. In wet etching, chlorine or fluorine-based etchants can be used to etch the third signal line 160 and the second dielectric layer 109.

[0328] The specific method of etching the second dielectric layer 109 is to etch the first dielectric layer 103 step by step in the vertical direction, so that the aperture of the first through hole 10d located on the upper surface of the second dielectric layer 109 is different from the aperture of the first through hole 10d located on the lower surface of the second dielectric layer 109.

[0329] The specific formation process of the first through hole 10d may refer to the formation process of the second through hole 107 described above, and will not be described in detail here.

[0330] Furthermore, in this embodiment, step S90 may include the following steps:

[0331] S901: depositing a seventh hard mask layer on the fifth conductive material layer 10e, and etching the seventh hard mask layer and the fifth conductive material layer 10e to form a stacked structure of the seventh hard mask layer and the fourth signal line 170;

[0332] S902: removing the seventh hard mask layer to expose the fourth signal line 170 and the third insulating layer 10 b ;

[0333] S903: depositing a ninth insulating layer on the fourth signal line 170 and on the surface of the third insulating layer 10 b not shielded by the fourth signal line 170 ;

[0334] S904: grinding the ninth insulating layer until the fourth signal line 170 is exposed, and retaining the ninth insulating layer on the third insulating layer 10 b .

[0335] The specific formation process of the fourth signal line 170 may refer to the formation process of the second signal line 150 or other signal lines mentioned above, and will not be described in detail here.

[0336] In the description of this specification, the description with reference to the terms "Example 1", "Example 2", etc. means that the specific features, structures, materials or characteristics described in conjunction with the implementation or example are included in at least one implementation or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same implementation or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more implementations or examples in a suitable manner.

[0337] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A storage unit, characterized in that: include: A write transistor, the write transistor comprising a first gate, a first gate dielectric surrounding the first gate, a first semiconductor channel surrounding the first gate dielectric, a first source and a drain, and a second source and a drain; the first source and a drain are arranged at a first end of the first gate and are located outside the first semiconductor channel; the second source and a drain are arranged at a second end of the first gate and are located outside the first semiconductor channel; A read transistor, the read transistor comprising a second gate, a second gate dielectric surrounding the second gate, a second semiconductor channel surrounding the second gate dielectric, a third source and drain, and a fourth source and drain; the second source and drain are conductively connected to the second gate; the third source and drain are arranged at a first end of the second gate and are located outside the second semiconductor channel; the fourth source and drain are arranged at a second end of the second gate and are located outside the second semiconductor channel; Wherein, the portion of the first semiconductor channel located between the first source-drain electrode and the second source-drain electrode is a first effective semiconductor channel; the portion of the second semiconductor channel located between the third source-drain electrode and the fourth source-drain electrode is a second effective semiconductor channel; The channel outer ring size of the portion of the first effective semiconductor channel close to the first source and drain is different from the channel outer ring size of the portion of the first effective semiconductor channel close to the second source and drain; the channel outer ring size of the portion of the second effective semiconductor channel close to the third source and drain is different from the channel outer ring size of the portion of the second effective semiconductor channel close to the fourth source and drain.

2. The storage unit according to claim 1, characterized in that The outer ring size of the first effective semiconductor channel is gradually reduced or gradually expanded.

3. The storage unit according to claim 1, characterized in that The outer ring size of the second effective semiconductor channel is gradually reduced or gradually expanded.

4. The storage unit according to claim 1, characterized in that The write transistor is located above the read transistor, and central axes of the first semiconductor channel and the second semiconductor channel coincide with each other.

5. The storage unit according to claim 4, characterized in that A projection of the first semiconductor channel on a plane perpendicular to its central axis is conformal to a projection of the second semiconductor channel on a plane perpendicular to its central axis.

6. The storage unit according to claim 4, characterized in that A contact guide is provided between the write transistor and the read transistor, the second source and drain and the second gate are conductively connected through the contact guide, and the central axis of the contact guide coincides with the central axis of the first semiconductor channel and the central axis of the second semiconductor channel; The upper surface of the contact guide is in contact with and connected to the first semiconductor channel, the lower surface of the contact guide is in contact with and connected to the second gate, and the contact guide is insulated from the second semiconductor channel.

7. The storage unit according to claim 6, characterized in that The contact guide block and the second source and drain are integrally formed, and the two are made of the same material.

8. The storage unit according to claim 6, characterized in that The size of the lower surface of the contact guide block is larger than the outer ring size of the second gate dielectric.

9. The storage unit according to claim 8, characterized in that The upper surface of the second gate is flush with the upper surface of the second gate dielectric, and the upper surface of the second semiconductor channel is lower than the upper surface of the second gate and the upper surface of the second gate dielectric; An annular insulating layer is provided between the lower surface of the contact guide and the upper surface of the second semiconductor channel, wherein the inner ring size of the annular insulating layer is equal to the outer ring size of the second gate dielectric, and the outer ring size of the annular insulating layer is equal to the outer ring size of the second semiconductor channel.

10. The storage unit according to claim 9, characterized in that The annular insulating layer and the second gate dielectric are integrally formed, and the two are made of the same material.

11. The storage unit according to claim 6, characterized in that The size of the upper surface of the contact guide block is greater than or equal to the size of the contact surface of the first semiconductor channel in contact with the upper surface of the contact guide block.

12. The storage unit according to claim 1, characterized in that The first source and drain are disposed around a first end of the first gate, and the third source and drain are disposed around a first end of the second gate.

13. A storage device, characterized in that: include: Semiconductor substrate; as well as At least one memory cell according to any one of claims 1 to 12 is formed on the semiconductor substrate.

14. The memory device according to claim 13, wherein: There are multiple storage units, and the multiple storage units form a storage array structure on a horizontal plane.

15. The memory device according to claim 14, wherein: The plurality of storage units in the storage array structure are arranged in an array in a first direction and a second direction, and the first direction intersects the second direction.

16. The memory device according to claim 15, wherein: The first direction intersects the second direction at 90°.

17. The memory device according to claim 15, wherein: The storage device further comprises: A first signal line, a second signal line, a third signal line and a fourth signal line, wherein the first signal line and the third signal line extend in the first direction, and the second signal line and the fourth signal line extend in the second direction; The number of the first signal line, the second signal line, the third signal line and the fourth signal line are all multiple, matching the number of rows and columns in the storage array structure; wherein the number of the first signal line is the same as the number of the third signal line, and the number of the second signal line is the same as the number of the fourth signal line; The first signal lines are arranged at intervals in the second direction and are in contact with the fourth source and drain; the second signal lines are arranged at intervals in the first direction and are in contact with the third source and drain; the third signal lines are arranged at intervals in the second direction and are in contact with the first source and drain, and the third signal lines are bit lines of the write transistor; the fourth signal lines are arranged at intervals in the first direction and are in contact with the first gate, and the fourth signal lines are word lines of the write transistor.

18. The memory device according to claim 17, wherein: The first signal line and the fourth source and drain are integrally formed, and the two are made of the same material; The second signal line and the third source and drain are integrally formed, and the two are made of the same material; The third signal line and the first source and drain are formed in one piece, and the materials of the two are the same.

19. A method for manufacturing a memory device, for manufacturing the memory device according to any one of claims 13 to 18, characterized in that: The following steps are involved: Providing a semiconductor substrate, depositing a first insulating layer and a first conductive material layer in sequence on the semiconductor substrate, and etching the first conductive material layer to form a first signal line; Depositing a first dielectric layer and a second conductive material layer in sequence on the layer where the first signal line is located, and etching the second conductive material layer to form a second signal line; Depositing a second insulating layer and a first hard mask layer in sequence on the layer where the second signal line is located, etching the first hard mask layer, the second insulating layer, the second signal line and the first dielectric layer to form a second through hole extending in a vertical direction to the upper surface of the first signal line, wherein the aperture of the second through hole located on the upper surface of the first dielectric layer is different from the aperture of the second through hole located on the lower surface of the first dielectric layer; removing the first hard mask layer and forming a read transistor in the second through hole; Depositing a third conductive material layer on the second insulating layer, and etching the third conductive material layer to form a contact guide, wherein the lower surface of the contact guide is conductively connected to the second gate, and the contact guide is insulated from the second semiconductor channel; Depositing a second dielectric layer and a fourth conductive material layer in sequence on the layer where the contact guide block is located, and etching the fourth conductive material layer to form a third signal line, wherein the third signal line is a bit line of the write transistor; Depositing a third insulating layer and a second hard mask layer in sequence on the layer where the third signal line is located, etching the second hard mask layer, the third insulating layer, the third signal line and the second dielectric layer to form a first through hole extending in a vertical direction to the upper surface of the contact guide block, wherein the aperture of the first through hole located on the upper surface of the second dielectric layer is different from the aperture of the first through hole located on the lower surface of the second dielectric layer; removing the second hard mask layer and forming a write transistor in the first through hole; A fifth conductive material layer is deposited on the third insulating layer, and the fifth conductive material layer is etched to form a fourth signal line contacting and connected to the first gate, wherein the fourth signal line is a word line of the write transistor.

20. The method for manufacturing a memory device according to claim 19, wherein: The plasma gas for etching the second insulating layer and the third insulating layer is a mixed gas of CH3F, CH2F2, O2 and Ar, the plasma source power is 500-1000W, and the bias voltage is 200-500V; The plasma gas for etching the first dielectric layer and the second dielectric layer is a mixed gas of C4F8 and O2, the plasma source power is 800-1500W, and the bias voltage is 250-500V.

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