Storage device and method for manufacturing the same

Abstract

The application belongs to the technical field of semiconductor, and provides a storage device, which comprises a substrate, at least one memory device layer arranged on the substrate, and a memory device layer at least comprising a memory cell, a write word line, a write bit line, a read word line and a read bit line; the memory cell comprises a write transistor and a read transistor; the write transistor comprises a first gate electrode, a first active layer, a first gate insulating layer and a first source electrode, and the first gate electrode is vertically arranged on the substrate; the read transistor comprises a second gate electrode, a second active layer, a second gate insulating layer, a second source electrode and a second drain electrode, and the second active layer is vertically arranged on the substrate; the second gate electrode further comprises a horizontally extending part connected with a drain end of the first active layer; in the vertical direction, the write word line is located on the side of the first source electrode away from the horizontally extending part. The application further provides a preparation method of the storage device. The application effectively utilizes the space in the vertical and horizontal directions, and can improve the storage density.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, and particularly relates to a memory device and its fabrication method. Background Technology

[0002] As technology nodes shrink, DRAM (Dynamic Random Access Memory) is gradually shifting from a 1T1C (1 Transistor 1 Capacitor) structure to a 2T0C (2 Transistor 0 Transistor) structure. 2T0C DRAM includes a Write Transistor (WTR) and a Read Transistor (RTR). The drain of the Write Transistor (WTR) is connected to the gate of the Read Transistor (RTR), so that the gate capacitance of the Read Transistor (RTR) serves as the storage node (SN). This capacitor-less structure makes the structure and process of 2T0C DRAM simpler, lower in cost, and smaller in size.

[0003] However, in related technologies, since transistors with horizontal channels are used as write transistors and read transistors, the write transistor WTR and read transistor RTR are usually arranged on the same plane, resulting in a large space occupied on the plane and a small utilization of vertical space. As a result, the storage density of the 2T0C DRAM is low, which makes it difficult to meet the high storage requirements. Summary of the Invention

[0004] This invention provides a storage device that aims to solve the technical problem in the prior art where write transistors and read transistors are arranged side by side on a plane, occupying a large amount of planar space while making less use of vertical space, resulting in low storage density of the storage device.

[0005] The present invention is implemented as follows: a storage device includes:

[0006] Substrate, the substrate including an insulating surface; and

[0007] At least one storage device layer disposed on the insulating surface, the storage device layer including a storage cell, a write word line, a write bit line, a read word line, and a read bit line;

[0008] The storage unit includes a write transistor and a read transistor;

[0009] The write transistor includes a first gate electrode, a first active layer, a first gate insulating layer, and a first source electrode. The first gate electrode is vertically disposed on the substrate. The first active layer is disposed at least partially around the first gate electrode. The first gate insulating layer is disposed between the first gate electrode and the first active layer. The first source electrode is connected to the source end of the first active layer.

[0010] The read transistor includes a second gate electrode, a second active layer, a second gate insulating layer, a second source electrode, and a second drain electrode. The second active layer is vertically disposed on the substrate. The second gate electrode is disposed at least partially on the periphery of the second active layer. The second gate insulating layer is disposed between the second gate electrode and the second active layer. The second source electrode is connected to the source terminal of the second active layer, and the second drain electrode is connected to the drain terminal of the second active layer.

[0011] The second gate electrode further includes a horizontal extension, which is connected to the drain terminal of the first active layer;

[0012] The first gate electrode is connected to the write word line, the first source electrode is connected to the write bit line, the second source electrode is connected to the read word line, and the second drain electrode is connected to the read bit line.

[0013] In the vertical direction, the write word line is located on the side of the first source electrode away from the horizontal extension.

[0014] Furthermore, the first source electrode and the write bit line connected thereto are formed as one unit, the second source electrode and the read word line connected thereto are formed as one unit, and the second drain electrode and the read bit line connected thereto are formed as one unit.

[0015] Furthermore, the storage device layer includes a plurality of storage cells, which are arranged in an array in a first horizontal direction and a second horizontal direction, the first horizontal direction and the second horizontal direction intersecting each other;

[0016] Multiple write word lines and multiple read bit lines are provided. The write word lines and multiple read bit lines are arranged at intervals in the second horizontal direction and extend along the first horizontal direction. The write word lines are connected to the first gate electrodes of the multiple write transistors arranged in the first horizontal direction, and the read bit lines are connected to the second drain electrodes of the multiple read transistors arranged in the first horizontal direction.

[0017] Multiple write bit lines and multiple read word lines are provided, and they are alternately spaced in the first horizontal direction and extend along the second horizontal direction. The write bit lines are connected to the first source electrodes of the multiple write transistors arranged in the second horizontal direction, and the read word lines are connected to the second source electrodes of the multiple read transistors arranged in the second horizontal direction.

[0018] Furthermore, the second source electrode and the first source electrode are located in the same layer.

[0019] Furthermore, in the vertical direction:

[0020] The second source electrode and the first source electrode are located in the same layer, and the distance between the opposing surfaces of the second source electrode and the second gate electrode is less than the distance between the opposing surfaces of the first source electrode and the horizontal extension; or

[0021] The second drain electrode is integrally formed with the read bit line, and the distance between the opposing surfaces of the second drain electrode and the second gate electrode is smaller than the distance between the opposing surfaces of the read bit line and the second gate electrode.

[0022] Furthermore, in the storage unit:

[0023] The first active layer overlaps with the first source electrode and the orthographic projection of the horizontal extension on the substrate;

[0024] The second active layer overlaps with the orthographic projections of the second source electrode, the second gate electrode, and the second drain electrode onto the substrate.

[0025] Furthermore, in the orthographic projection onto the substrate:

[0026] The second gate electrode is parallel to the two opposite sides of the extension direction of the read bit line and overlaps with the two opposite sides of the read bit line respectively.

[0027] Furthermore, in the orthographic projection of the substrate:

[0028] The second gate electrode overlaps with the write bit line and the read word line, and the second gate electrode is parallel to the two opposite sides of the extension direction of the write bit line and the read word line, respectively overlapping with the sides of the write bit line and the read word line that overlap with the second gate electrode.

[0029] Furthermore, the first active layer is a groove-shaped structure, and the bottom end of the groove-shaped structure contacts or is embedded in the horizontal extension; or

[0030] The first active layer has a cylindrical structure, and the end of the cylindrical structure corresponding to the drain end of the first active layer extends through the horizontal extension.

[0031] Furthermore, the storage device includes multiple layers of the storage device, which are vertically stacked on the substrate;

[0032] In at least one of the multilayer storage device layers, the first active layer has a groove-shaped structure, and the bottom end of the groove-shaped structure contacts or is embedded in the horizontal extension; and in at least another layer of the multilayer storage device layer, the first active layer has a cylindrical structure, and the end of the cylindrical structure corresponding to the drain end of the first active layer penetrates the horizontal extension.

[0033] Furthermore, the storage device includes multiple layers of the storage device, which are vertically stacked on the substrate;

[0034] The storage device further includes an insulating isolation layer disposed between two adjacent storage device layers.

[0035] Furthermore, the storage device includes multiple layers of the storage device, which are vertically stacked on the substrate;

[0036] The multilayer storage device layer is divided into at least one common unit along the vertical direction, and the common unit includes two storage device layers that are adjacent in the vertical direction;

[0037] In the shared unit, the adjacent memory device layers share the write word line or the read bit line;

[0038] Furthermore, in one of the two adjacent storage device layers, the first active layer has a groove-shaped structure, and the bottom end of the groove-shaped structure contacts or is embedded in the horizontal extension portion of the first layer.

[0039] In the other of the two adjacent storage device layers, the first active layer has a cylindrical structure, and the end of the cylindrical structure corresponding to the drain end of the first active layer extends through the horizontal extension.

[0040] Furthermore, the storage device also includes an insulating isolation layer disposed between the common unit and the storage device layer adjacent to the common unit.

[0041] Furthermore, the write word line, the write bit line, the read word line, the read bit line, the first gate electrode, the first source electrode, the second gate electrode, the second source electrode, and the second drain electrode are made of the same or different materials, and include conductors;

[0042] The first active layer and the second active layer are made of the same or different materials, and include oxide semiconductors.

[0043] Furthermore, the conductor comprises at least one of aluminum, titanium, tungsten, titanium nitride, and doped polycrystalline silicon;

[0044] The oxide semiconductor includes at least one of indium oxide, tin oxide, gallium oxide, indium tin oxide, zinc oxide, indium zinc oxide, and indium gallium zinc oxide.

[0045] The present invention also provides a method for manufacturing a storage device, comprising the following steps:

[0046] S1. Provide a first substrate;

[0047] S2. Prepare at least one layer of the memory device layer on the first surface of the first substrate;

[0048] S3. The first substrate is the substrate, the first surface is the insulating surface, or the memory device layer formed in step S2 is transferred to the insulating surface of the substrate.

[0049] Furthermore, the fabrication of at least one storage device layer on the first surface includes fabricating at least one first storage device layer, wherein fabricating at least one first storage device layer includes the following steps:

[0050] S21. A first conductor layer, a first insulating layer, and a second conductor layer are sequentially prepared on the first surface. A first patterning process is performed to form a first gap penetrating the second conductor layer, the first insulating layer, and the first conductor layer to form the read bit line, the second drain electrode, and the first patterned conductor layer. A first isolation insulating layer is prepared, and the first isolation insulating layer covers the upper surface of the first patterned conductor layer.

[0051] S22. A first hole is formed penetrating the first isolation insulating layer, the first patterned conductor layer and the first insulating layer, and a second gate insulating layer and a second active layer are sequentially formed on the sidewall of the first hole;

[0052] S23. A third conductor layer is prepared on the upper surface of the first isolation insulating layer, and a second patterning process is performed to form a second gap penetrating the third conductor layer and a third gap penetrating the third conductor layer, the first isolation insulating layer, and the first patterned conductor layer to form the second gate electrode, the write bit line, the read word line, the first source electrode, and the second source electrode, and a second isolation insulating layer is prepared, the second isolation insulating layer covering the upper surface of the first source electrode;

[0053] S24. A second hole is formed penetrating the second isolation insulating layer, the first source electrode, and the first isolation insulating layer, and the first active layer, the first gate insulating layer, and the first gate electrode are sequentially formed on the sidewall of the second hole;

[0054] S25. Prepare a fourth conductor layer and perform a third patterning process on the fourth conductor layer to form the write word line, wherein the write word line is isolated from the read word line.

[0055] Furthermore, in step S22, the step of sequentially forming the second gate insulating layer and the second active layer on the sidewall of the first hole includes the following steps:

[0056] S221. Deposit a second gate insulating layer material, the second gate insulating layer material covering the upper surface of the first isolation insulating layer, the sidewall and the bottom surface of the first hole, and anisotropically etch to remove the portion of the second gate insulating layer material located on the upper surface of the first isolation insulating layer and the bottom surface of the first hole, to form a second gate insulating layer located on the sidewall of the first hole;

[0057] S222. Fill the trench formed by the sidewall of the second gate insulating layer and the bottom surface of the first hole with a second active layer material, and etch the second active layer material back until the top surface of the second active layer material is lower than the upper surface of the first isolation insulating layer to form the second active layer.

[0058] Furthermore, the step of fabricating at least one memory device layer on the first surface includes fabricating at least one first memory device layer, and the fabrication of at least one first memory device layer further includes the following steps:

[0059] S26. Prepare a first conductor layer and perform a first patterning process on the first conductor layer to form the write word line, prepare a first insulating layer to cover the write word line, prepare a second conductor layer on the surface of the first insulating layer away from the write word line and perform a second patterning process to form the write bit line, the read word line, the first source electrode and the second source electrode, and prepare a first insulating layer to cover the write bit line, the read word line, the first source electrode and the second source electrode;

[0060] S27. A third conductor layer is prepared on the surface of the first insulating layer away from the write word line;

[0061] A third patterning process is performed on the third conductor layer to form a second patterned conductor layer, the second patterned conductor layer overlapping the orthographic projections of the first source electrode and the second source electrode on the first substrate;

[0062] A third hole is formed through the second patterned conductor layer or the third conductor layer, the first isolation insulating layer, and the first source electrode. A first active layer is formed on the sidewall of the third hole. A fourth hole is formed extending from the upper surface of the second patterned conductor layer or the third conductor layer to the bottom of the third hole and exposing the write word line. A first gate insulating layer and a first gate electrode connected to the write word line are sequentially formed on the sidewall of the fourth hole.

[0063] S28. A second insulating layer is formed covering the second patterned conductor layer and the first gate electrode, and a fifth hole is formed penetrating the second insulating layer, the second patterned conductor layer, and the first isolation insulating layer and exposing the second source electrode. A second gate insulating layer and a second active layer connecting the second source electrode are sequentially formed on the sidewall of the fifth hole.

[0064] S29. A fourth conductor layer is formed on the side of the second insulating layer away from the write word line, and a third patterning process is performed to form a fourth gap through the fourth conductor layer, the second insulating layer, and the second patterned conductor layer to form the read bit line and the second gate electrode.

[0065] Furthermore, in step S28, the step of sequentially forming the second gate insulating layer and the second active layer connecting the second source electrode on the sidewall of the fifth hole includes the following steps:

[0066] S281. Deposit a second gate insulating layer material, the second gate insulating layer material covering the upper surface of the second insulating layer, the sidewall and bottom surface of the fifth hole, and anisotropically etch to remove the portion of the second gate insulating layer material located on the upper surface of the second insulating layer and the bottom surface of the fifth hole, to form a second gate insulating layer located on the sidewall of the fourth hole;

[0067] S282. Fill the trench formed by the sidewall of the second gate insulating layer and the bottom surface of the fifth hole with a second active layer material, and etch the second active layer material back until the top surface of the second active layer material is lower than the upper surface of the second insulating layer to form the second active layer.

[0068] In the storage device of this invention, both the write transistor and the read transistor are vertical channel transistors. Compared to existing horizontal channel transistors, vertical channel transistors have a higher device density. Furthermore, the write and read transistors are arranged horizontally and overlap vertically. Compared to the two vertically stacked transistors in existing 2TOC technology, this utilizes horizontal space and saves vertical space. This invention effectively increases the storage density of the storage cell by arranging the vertical channel transistors horizontally and designing them to overlap vertically, thereby improving the utilization of space in both the vertical and horizontal directions. Attached Figure Description

[0069] Figure 1 This is a perspective view of a storage device according to an embodiment of the present invention;

[0070] Figure 2a This is a schematic diagram of the structure of a storage unit according to an embodiment of the present invention;

[0071] Figure 2b This is a schematic diagram of the structure of a storage unit according to an embodiment of the present invention;

[0072] Figure 3a This is a schematic diagram of the structure of a write transistor according to an embodiment of the present invention;

[0073] Figure 3b This is a schematic diagram of the structure of a write transistor according to an embodiment of the present invention;

[0074] Figure 4 This is a schematic diagram of the structure of a read transistor according to an embodiment of the present invention;

[0075] Figure 5a This is a schematic diagram of the structure of a storage unit according to an embodiment of the present invention;

[0076] Figure 5b This is a schematic diagram of the structure of a storage unit according to an embodiment of the present invention;

[0077] Figure 6 This is a schematic diagram of the structure of a storage device according to an embodiment of the present invention;

[0078] Figure 7a This is a schematic diagram of the structure of a storage device according to an embodiment of the present invention;

[0079] Figure 7b This is a schematic diagram of the structure of a storage device according to an embodiment of the present invention;

[0080] Figure 8 This is a schematic diagram of the structure of a storage device according to an embodiment of the present invention;

[0081] Figure 9This is a schematic diagram of the structure of a storage device according to an embodiment of the present invention;

[0082] Figure 10 This is a schematic flowchart of a method for preparing a storage device according to an embodiment of the present invention;

[0083] Figure 11 , Figure 12a , Figure 12b , Figure 12c , Figure 13a , Figure 13b , Figure 14a , Figure 14b , Figure 14c , Figure 15a , Figure 15b , Figure 16a and Figure 16b This is a schematic diagram of the process flow for manufacturing a storage device according to an embodiment of the present invention;

[0084] Figure 17 This is a schematic flowchart of a method for preparing a storage device according to another embodiment of the present invention;

[0085] Figure 18 , Figure 19 , Figure 20a , Figure 20b , Figure 21 , Figure 22 , Figure 23a , Figure 23b , Figure 24 , Figure 25 , Figure 26 , Figure 27 , Figure 28 , Figure 29a , Figure 29b , Figure 30 , Figure 31 , Figure 32 , Figure 33 , Figure 34a , Figure 34b and Figure 34c This is a schematic diagram of the process flow for manufacturing a storage device according to another embodiment of the present invention;

[0086] Figure 35 This is a schematic diagram of the memory cell connection circuit according to an embodiment of the present invention.

[0087] Explanation of key figure labels:

[0088] Storage device - 1000; Semiconductor substrate - 200; Storage device layer - 100; Storage cell - 110; Write transistor - 111; First gate electrode - 1111; First active layer - 1112; First gate insulating layer - 1113; First source electrode - 1114; Read transistor - 112; Second gate electrode - 1121; Horizontal extension - 11211; Second active layer - 1122; Second gate insulating layer - 1123; Second source electrode - 1124; Second drain electrode - 1125; Write word line - 120; Write bit Line-130; Read word line-140; Read bit line-150; Insulating isolation layer-160; Common cell-300; First substrate-1; First conductor layer-2; First insulating layer-3; Second conductor layer-4; First patterned conductor layer-5; First insulating isolation layer-6; First hole-7; Third conductor layer-8; Second insulating isolation layer-9; Second hole-10; Fourth conductor layer-11; Second patterned conductor layer-12; Third hole-13; Fourth hole-14; Spacer insulating layer-15; Second insulating layer-16; Fifth hole-17. Detailed Implementation

[0089] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the invention, and should not be construed as limiting the invention. Furthermore, it should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0090] In the description of this invention, it should be understood that the orientation or positional relationship indicated in the description of direction and positional relationship is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing this invention and simplifying the description, and is not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention.

[0091] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0092] The following disclosure provides numerous different embodiments or examples for implementing various structures of the invention. To simplify the disclosure, specific examples of components and arrangements are described below. Of course, the above material is merely illustrative and not intended to limit the invention. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, examples of various specific processes and materials are provided in this invention, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0093] A 3D-DRAM memory device includes one or more memory device layers stacked in a direction perpendicular or approximately perpendicular to the substrate (e.g., the Z-axis direction), each memory device layer including multiple memory cells arranged in an array. Each memory cell may include 2TOC-DRAM, meaning the memory cell includes 2 transistors and 0 capacitors. The two transistors are a write transistor and a read transistor, respectively. The drain of the write transistor is connected to the gate of the read transistor. The read world line (RWL), read bit line (RBL), write word line (WWL), and write bit line (WBL) are respectively located at corresponding positions and connected to corresponding positions on the transistors.

[0094] For example, the gate of the write transistor is connected to the write word line, the source of the write transistor is connected to the write bit line, the source of the read transistor is connected to the read word line, and the drain of the read transistor is connected to the read bit line.

[0095] Please see Figure 1 and Figure 2a , 2b The storage device 1000 of the present invention includes a substrate 200 and at least one storage device layer 100 disposed on the substrate 200. In the embodiment shown in the figure above, the substrate 200 may include a semiconductor substrate 201 and an insulating layer 202 located on the side of the semiconductor substrate 201 near the storage device layer 100, wherein the surface of the insulating layer 202 away from the semiconductor substrate 201 is formed as an insulating surface of the substrate 200.

[0096] The semiconductor substrate 201 may include a semiconductor material, such as at least one of silicon (e.g., single-crystal silicon Si), silicon germanium (SiGe), germanium (Ge), gallium arsenide (GaAs), indium phosphide (InP), and silicon carbide (SiC).

[0097] In one embodiment, the substrate 200 may be a single-layer structure, for example, a single-layer structure made of at least one of the materials such as silicon, germanium, and gallium arsenide.

[0098] In another embodiment, the substrate 200 may also be a multilayer structure, such as a composite substrate including a stack of silicon and silicon-germanium, a stack of silicon and silicon carbide, silicon-on-insulator, germanium-on-insulator, or silicon-germanium-on-insulator.

[0099] For example, the semiconductor substrate 201 may be a single-crystal silicon substrate, and optionally, the semiconductor substrate 201 may include logic circuitry.

[0100] In other embodiments, substrate 200 is an insulating substrate. The insulating substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer. Alternatively, substrate 200 may also be an insulating dielectric material such as silicon dioxide (SiO2) or silicon nitride (SiN).

[0101] In one embodiment, the insulating layer 202 may comprise insulating materials commonly used in the art, such as silicon dioxide (SiO2) or silicon nitride (SiN). x )wait.

[0102] The memory device layer 100 includes at least a memory cell 110, a write word line 120, a write bit line 130, a read word line 140, and a read bit line 150. The memory cell 110 includes a write transistor 111 and a read transistor 112.

[0103] See Figure 2a and Figure 3a In the illustrated embodiment, the write transistor 111 includes a first gate electrode 1111, a first active layer 1112, a first gate insulating layer 1113, and a first source electrode 1114. The first gate electrode 1111 is disposed vertically on the substrate 200 along the Z-axis direction. The first active layer 1112 is disposed at least partially around the first gate electrode 1111. The first gate insulating layer 1113 is disposed between the first gate electrode 1111 and the first active layer 1112. The first source electrode 1114 is connected to the source terminal of the first active layer 1112.

[0104] See Figure 2b and Figure 3b In another embodiment of the present invention shown, the write transistor 111 includes: a first gate electrode 1111, a first active layer 1112, a first gate insulating layer 1113, and a first source electrode 1114. The first gate electrode 1111 is disposed vertically on the substrate 200 along the Z-axis direction. The first active layer 1112 is disposed at least partially around the first gate electrode 1111. The first gate insulating layer 1113 is disposed between the first gate electrode 1111 and the first active layer 1112. The first source electrode 1114 is connected to the source terminal of the first active layer 1112.

[0105] See Figure 2a , Figure 2b and Figure 4 The read transistor 112 includes a second gate electrode 1121, a second active layer 1122, a second gate insulating layer 1123, a second source electrode 1124, and a second drain electrode 1125. The second active layer 1122 is disposed vertically on the substrate 200 along the Z-axis direction. The second gate electrode 1121 is disposed on at least a portion of the periphery of the second active layer 1122. The second gate insulating layer 1123 is disposed between the second gate electrode 1121 and the second active layer 1122. The second source electrode 1124 is connected to the source terminal of the second active layer 1122, and the second drain electrode 1125 is connected to the drain terminal of the second active layer 1122.

[0106] See Figures 2a to 4 The second gate electrode 1121 also includes a horizontal extension 11211, which is connected to the drain terminal of the first active layer 1112.

[0107] In this embodiment of the invention, the second gate electrode 1121 further includes a horizontal extension 11211, which is connected to the drain terminal of the first active layer 1112 to realize the electrical connection between the write transistor 111 and the read transistor 112. That is, the horizontal extension 11211 includes the first drain electrode of the write transistor 111, which makes the structure of the memory cell 110 simple and reduces the process difficulty and production cost.

[0108] The horizontal extension 1121 is parallel or approximately parallel to the substrate 200. Preferably, the second gate electrode 1121 is parallel or approximately parallel to the substrate 200.

[0109] The first gate electrode 1111 is connected to the write word line 120, the first source electrode 1114 is connected to the write bit line 130, the second source electrode 1124 is connected to the read word line 140, and the second drain electrode 1125 is connected to the read bit line 150. In the Z-axis direction, i.e., the vertical direction, the write word line 120 is located on the side of the first source electrode 1114 away from the horizontal extension 11211. When the first source electrode 1114 and the write bit line 130 are formed integrally, the write word line 120 is located on the side of the write bit line 130 away from the horizontal extension 11211.

[0110] It should be noted that the write word line 120 and the write bit line 130 are signal lines that provide corresponding functions at corresponding locations in the storage device 100. Specifically:

[0111] The write word line 120 is electrically connected to the gate of the write transistor 111 in the memory cell 110, and during a write operation, a voltage is applied through the write word line 120 to turn on the write transistor 111. In other words, the write word line 120 is a signal line electrically connected to the gate of the write transistor 111, and a voltage is applied during a write operation to turn on the write transistor.

[0112] The write bit line 130 is electrically connected to the source of the write transistor 111 in the memory cell 110. When the write transistor 111 is turned on, a voltage is applied through the write bit line 130 to charge or discharge the memory node SN through the write transistor 111, causing the memory node SN to present a high voltage or a low voltage, representing data 1 and 0 respectively, thereby completing the write operation. In other words, the write bit line 130 is a signal line electrically connected to the source of the write transistor 111, which applies a voltage when the write transistor 111 is turned on to charge or discharge the memory node SN.

[0113] In addition, specifically regarding read word line 140 and read bit line 150:

[0114] Read word line 140 is the signal line that applies a read voltage to the second source electrode 1124 of the read transistor 112 during a read operation; read bit line 150 is the signal line that connects to the second drain electrode 1125 and, during a read operation, writes data from the read memory node SN by detecting the magnitude of the current therein; or

[0115] The read bit line 150 is the signal line that applies a read voltage to the second drain electrode 1125 of the read transistor 112 connected thereto during the read operation. The read word line 150 is the signal line that connects to the second source electrode 1124 and, during the read operation, writes data from the read memory node SN by detecting the magnitude of the current therein.

[0116] The second source electrode 1124 and the first source electrode 1114 are located on the same side of the second gate electrode 1121, and the second drain electrode 1125 is located on the side of the second gate electrode 1121 away from the first source electrode 1114. It can be understood that, for the read transistor 112, the second source electrode 1124 and the second drain electrode 1125 do not limit the channel current flow direction of the read transistor 112 during the read operation.

[0117] In a storage cell 110 of an embodiment of the storage device 1000 of the present invention, a first gate electrode 1111 of a write transistor 111 is vertically disposed on a substrate 200, a first active layer 1112 is disposed on at least a portion of the periphery of the first gate electrode 1111, a second active layer 1122 of a read transistor 112 is vertically disposed on the substrate 200, a second gate electrode 1121 is disposed on at least a portion of the periphery of the second active layer 1122, and the second gate electrode 1121 further includes a horizontal extension portion 11211, which is connected to the drain terminal of the first active layer 1112.

[0118] That is, both the write transistor 111 and the read transistor 112 in the memory cell 110 of the present invention are vertical channel transistors, which result in a higher storage density compared to the horizontal channel transistors of the prior art. Furthermore, the write transistor 111 and the read transistor 112 are arranged horizontally and overlap vertically, saving vertical space compared to the two vertically stacked vertical channel transistors in the prior art 2TOC. Therefore, the present invention effectively increases the storage density of the memory cell 110 by arranging the vertical channel transistors horizontally and designing them to overlap vertically, thereby improving the utilization of space in both the vertical and horizontal directions.

[0119] The first gate electrode 1111 can be a solid pillar structure. In other embodiments, the first gate electrode 1111 can also be a hollow structure, such as a groove or cylinder structure. In this case, a dielectric layer can be filled in the hollow of the first gate electrode 1111. The dielectric layer includes an insulating material and can be a single-layer or multi-layer structure. The dielectric layer may include an air gap, which is not specifically limited here.

[0120] The first active layer 1112 being disposed on at least a portion of the periphery of the first gate electrode 1111 can be understood as the first active layer 1112 being disposed circumferentially around the first gate electrode 1111, which may completely surround the first gate electrode 1111 or only partially surround the first gate electrode 1111.

[0121] Preferably, the first active layer 1112 completely surrounds the first gate electrode 1111, increasing the channel width of the write transistor and increasing the write current when the write transistor is turned on.

[0122] The second active layer 1122 can be a solid column structure. In other embodiments, the second active layer 1122 can also be a hollow structure, such as a groove or cylinder structure. In this case, a dielectric layer can be filled in the hollow of the second active layer 1122. The dielectric layer includes an insulating material and can be a single-layer or multi-layer structure. The dielectric layer may include an air gap, which is not specifically limited here.

[0123] The second gate electrode 1121 being disposed at least partially around the second active layer 1122 can be understood as the second gate electrode 1121 being disposed circumferentially around the second active layer 1122, which may completely surround the second active layer 1122 or partially surround the second active layer 1122.

[0124] Preferably, the second gate electrode 1121 completely surrounds the second active layer 1122, increasing the channel width of the read transistor and allowing for a larger read current during read operations, thereby improving the read margin.

[0125] like Figure 1In the illustrated embodiment, the storage device layer 100 includes a plurality of storage cells 110, which are arranged in an array within the storage device layer 100. For example, the plurality of storage cells 110 in the storage device layer 100 are arranged in an array along a first horizontal direction and a second horizontal direction.

[0126] Multiple write word lines 120 and read bit lines 150 are provided and are arranged at intervals in the second horizontal direction and extend along the first horizontal direction. The write word lines 120 are connected to the first gate electrode 1111 of the multiple write transistors 111 arranged in the first horizontal direction, and the read bit lines 150 are connected to the second drain electrode 1125 of the multiple read transistors 112 arranged in the first horizontal direction.

[0127] The write bit line 130 and the read word line 140 are fabricated in the same layer and multiple lines are provided for each. They are alternately spaced in the first horizontal direction and extend in the second horizontal direction. The write bit line 130 is connected to the first source electrode 1114 of the multiple write transistors 111 arranged in the second horizontal direction, and the read word line 140 is connected to the second source electrode 1124 of the multiple read transistors 112 arranged in the second horizontal direction.

[0128] The write bit line 130 and read word line 140 are alternately spaced in the first horizontal direction, including:

[0129] like Figure 1 In the embodiment shown, the write bit line 130 and the read word line 140 alternate.

[0130] In other embodiments, two adjacent memory cells 110 in the first horizontal direction are symmetrically arranged, and the write bit line 130 and read word line 140 connecting the two symmetrical memory cells 100 are also symmetrically arranged, that is, the write bit line 130 and read word line 140 are alternately spaced in pairs.

[0131] It is understood that the first and second horizontal directions are two directions that extend parallel or approximately parallel to the substrate 200, and the first and second horizontal directions intersect. For example, the first horizontal direction is perpendicular to the second horizontal direction, but the present invention does not specifically limit the included angle between the first and second horizontal directions, as long as they intersect.

[0132] exist Figure 1 In the embodiment shown, the first horizontal direction is the X-axis direction, and the second horizontal direction is the Y-axis direction.

[0133] Thus, a write word line 120 can be connected to a plurality of write transistors 111 spaced apart along a first horizontal direction, a write bit line 130 can be connected to a plurality of write transistors 111 spaced apart along a second horizontal direction, a read word line 140 can be connected to a plurality of read transistors 112 spaced apart along a second horizontal direction, and a read bit line 150 can be connected to a plurality of read transistors 112 spaced apart along a first horizontal direction.

[0134] Since there is a cross between the write word line 120 and the write bit line 130, and a cross between the read word line 140 and the read bit line 150, the transistor at the cross can be selected through the cross of the signal lines, thereby allowing any memory cell 110 in the memory device layer 100 to be selected for read and write operations.

[0135] In the storage cell 110, the arrangement direction of the write transistor 111 and the read transistor 112 can be the same as or different from either the first or second horizontal direction, and the present invention does not make a specific limitation.

[0136] Furthermore, in this embodiment of the invention, the write word line 120, write bit line 130, read word line 140, read bit line 150, first gate electrode 1111, first source electrode 1114, second gate electrode 1121, second source electrode 1124 and second drain electrode 1125 are made of the same or different materials and include conductors.

[0137] The conductor includes at least one of aluminum, titanium, tungsten, titanium nitride, and doped polycrystalline silicon.

[0138] In one embodiment, the material of the write bit line 130 can be the same as the material of the first source electrode 1114, the material of the read bit line 150 can be the same as the material of the second drain electrode 1125, and the material of the read word line 140 can be the same as the material of the second source electrode 1124.

[0139] Therefore, the above-mentioned components made of the same material can be fabricated in the same layer and formed as one unit. That is, the write bit line 130 can be formed as one unit with the first source electrode 1114 connected thereto, the read bit line 150 can be formed as one unit with the second drain electrode 1125 connected thereto, and the read word line 140 can be formed as one unit with the second source electrode 1124 connected thereto, which simplifies the manufacturing process and reduces production costs.

[0140] It can be understood that the write bit line 130 can be integrated with the source electrode 1114 connected thereto, the read bit line 150 can be integrated with the second drain electrode 1125 connected thereto, and the read word line 140 can be integrated with the second source electrode 1124 connected thereto. Specifically, a portion of the write bit line 130 can be formed as the first source electrode 1114, a portion of the read bit line 150 can be formed as the second drain electrode 1125, and a portion of the read word line 140 can be formed as the second source electrode 1124.

[0141] In a preferred embodiment of the present invention, the write bit line 130 is made of the same material and is fabricated in the same layer as the first source electrode 1114, the read word line 140, and the second source electrode 1124. The write bit line 130 is integrally formed with the first source electrode 1114, and the read word line 140 is integrally formed with the second source electrode 1124. Thus, the fabrication of the write bit line 130, the first source electrode 1114, the read word line 140, and the second source electrode 1124 can be completed in a single patterned film fabrication process, simplifying the manufacturing process and reducing production costs.

[0142] In addition, the material of the write word line 120 can be the same as or different from the material of the first gate electrode 1111, and the materials of the read bit line 150 and the read word line 140 can be the same as or different from the material of the second gate electrode 1121. The materials of the first gate electrode 1111 and the second gate electrode 1121 can be set according to actual needs to achieve good electrical characteristics of the write transistor 111 and the read transistor 112.

[0143] It is worth noting that when the material of the write word line 120 is the same as the material of the first gate electrode 1111, the two can be fabricated simultaneously to form a single unit.

[0144] Please combine Figure 1 , Figure 2a and Figure 2b In the storage unit 110 of this embodiment of the invention, the first active layer 1112 is disposed around the first gate electrode 1111, the first source electrode 1114 is connected to the source end of the first active layer 1112, the write bit line 130 is connected to the first source electrode 1114, and the read word line 140 is connected to the second source electrode 1124.

[0145] Therefore, the write bit line 130 and the read word line 140 can be set on the same layer, with the two spaced apart and extending in the same direction, so as to be connected to the write transistor 111 and the read transistor 112 respectively. This further reduces the height of the memory cell 110 in the Z-axis direction and allows the write bit line 130 and the read word line 140 to be fabricated in the same process step, reducing the process difficulty and production cost.

[0146] It is worth mentioning that, although Figure 1 , Figure 2a , Figure 2b ,as well as Figures 6 to 9 Not all of them are shown, but an insulating spacer layer is also filled between the write transistor 111 and the read transistor 112, and between the write word line 120, the write bit line 130, the read word line 140, the read bit line 150 and the second gate electrode 1121 (including the horizontal extension 11211). The insulating spacer layer includes insulating materials, such as silicon oxide SiO2, silicon nitride Si3N4, etc., and may also be TEOS (tetraethoxysilane) or a low dielectric constant material.

[0147] Furthermore, the first active layer 1112 and the second active layer 1122 comprise oxide semiconductor materials, and the materials of the first active layer 1112 and the second active layer 1122 may be the same or different. The oxide semiconductor materials include at least one of indium oxide (In₂O₃), tin oxide (SnO₂), gallium oxide (Ga₂O₃), indium tin oxide (ITO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), and indium zinc oxide (IZO).

[0148] In this embodiment of the invention, the materials of the first active layer 1112 and the second active layer 1122 are indium gallium zinc oxide (IGZO).

[0149] Furthermore, the first gate insulating layer 1113 and the second gate insulating layer 1123 comprise insulating materials, such as silicon oxide (SiOx) or silicon nitride (SiN). x Materials such as high dielectric constant materials, or combinations of the above materials, laminated materials, or combined laminated materials.

[0150] Please see Figure 1 , Figure 2a , Figure 2b , Figures 6 to 9 Furthermore, the storage device layer 100 includes a plurality of storage cells 110, which are arranged in an array within the storage device layer 100. For example, the plurality of storage cells 110 in the storage device layer 100 are arranged in an array in a first horizontal direction and a second horizontal direction.

[0151] Multiple write word lines 120 and read bit lines 150 are provided, and they are arranged at intervals in the second horizontal direction and extend along the first horizontal direction. The write word lines 120 are connected to the first gate electrode 1111 of the multiple write transistors 111 arranged in the first horizontal direction, and the read bit lines 150 are connected to the second drain electrode 1125 of the multiple read transistors 112 arranged in the first horizontal direction.

[0152] Multiple write bit lines 130 and read word lines 140 are provided, and they are alternately spaced in the first horizontal direction and extended in the second horizontal direction. The write bit lines 130 are connected to the first source electrode 1114 of the multiple write transistors 111 arranged in the second horizontal direction, and the read word lines 140 are connected to the second source electrode 1124 of the multiple read transistors 112 arranged in the second horizontal direction.

[0153] In some embodiments, the first source electrode 1114 and the second source electrode 1124 are located on the same layer. When the first source electrode and the write bit line 130 are formed as one piece, and the second source electrode 1124 and the read word line 140 are formed as one piece, the write bit line 130 and the read word line 140 are located on the same layer.

[0154] In some embodiments, the write bit line 130 and the read word line 140 are located on different layers, but are still alternately spaced in a first horizontal direction and extend in a second horizontal direction.

[0155] In one embodiment, the second source electrode 1124 and the first source electrode 1114 are fabricated in the same layer, that is, they are located in the same layer. In the vertical direction, the distance between the opposing surfaces of the second source electrode 1124 and the second gate electrode 1121 is less than the distance between the opposing surfaces of the first source electrode 1114 and the horizontal extension 11211.

[0156] In this way, the distance between the opposing surfaces of the first source electrode 1114 and the horizontal extension 11211 can be increased, that is, the distance between the first source electrode 1114 and the first drain electrode can be extended, increasing the impedance between the source and drain terminals of the write transistor 111, thereby reducing the leakage current.

[0157] The second source electrode 1124 and the first source electrode 1114 are located on the same layer. If the distance between the surfaces of the two electrodes near the second gate electrode 1121 and the second gate electrode 1121 is the same, the leakage current of the write transistor 111 is reduced, but the source-drain impedance when the read transistor 112 is turned on is also increased, thus reducing the read margin. By making the distance between the opposing surfaces of the second source electrode 1124 and the second gate electrode 1121 in the vertical direction smaller than the distance between the opposing surfaces of the first source electrode 1114 and the horizontal extension 11211, it is possible to simultaneously improve the leakage current of the write transistor 111 and the read margin of the memory cell 110.

[0158] like Figure 5aIn the illustrated embodiment, the distance between the opposing surfaces of the second source electrode 1124 and the second gate electrode 1121 is less than the distance between the opposing surfaces of the first source electrode 1114 and the horizontal extension 11211. That is, the distance between the surface of the second active layer 1122 away from the second gate electrode 1121 and the surface of the second gate electrode 1121 close to the first source electrode 1114 is less than the distance between the opposing surfaces of the first source electrode 1114 and the second gate electrode 1121.

[0159] For example, see Figure 5a , Figures 13a to 14c The second active layer 1122 is prepared in the first hole 7. By making the surface of the second active layer 1122 away from the second gate electrode 1121 closer to the second gate electrode 1121 than the opening of the first hole 7, that is, the second active layer 1122 only fills part of the depth of the first hole 7 from bottom to top, the first source electrode 1114 and the second source electrode 1124 can be located in the same layer, and the distance between the relative surfaces of the second source electrode 1124 and the second gate electrode 1121 is less than the distance between the relative surfaces of the first source electrode 1114 and the horizontal extension 11211.

[0160] For example, the surface of the second active layer 1122 that is away from the second gate electrode 1121 can be made closer to the second gate electrode 1121 than the opening of the first hole 7, such as... Figure 5a As shown; or, such that the surface of the second active layer 1122 away from the second gate electrode 1121 and the end of the second gate insulating layer away from the second gate electrode 1121 are both closer to the second gate electrode 1121 than the opening of the first hole 7.

[0161] In practice, the distance between the relative surfaces of the second source electrode 1124 and the second gate electrode 1121, and the distance between the relative surfaces of the first source electrode 1114 and the horizontal extension 11211 can be adjusted according to actual needs.

[0162] In addition, if the channel length of the write transistor 111 is to be increased, the thickness of the insulating spacer between the write bit line 130 and the horizontal extension 11211 can be increased to increase the distance between the first source electrode 1114 and the horizontal extension 11211.

[0163] In another embodiment, see Figure 5b and Figure 31 The read bit line 150 is integrated with the second drain electrode 1125. The second active layer 1122 is fabricated in the fifth hole 17. The surface of the second active layer 1122 that is away from the second gate electrode 1121 is closer to the second gate electrode 1121 than the opening of the fifth hole 17. That is, the second active layer 1122 only fills part of the depth of the fifth hole 17 from bottom to top.

[0164] Therefore, the distance between the opposing surfaces of the second drain electrode 1125 and the second gate electrode 1121 can be made smaller than the distance between the opposing surfaces of the read bit line 150 and the second gate electrode 1121, thereby enabling independent adjustment of the channel length of the read transistor 112 while reducing the coupling between the read bit line 150 and the second gate electrode 1121.

[0165] For example, the surface of the second active layer 1122 that is away from the second gate electrode 1121 can be made closer to the second gate electrode 1121 than the opening of the fifth hole 17, such as... Figure 5b As shown; or, by making the surface of the second active layer 1122 away from the second gate electrode 1121 and the end of the second gate insulating layer away from the second gate electrode 1121 closer to the second gate electrode 1121 than the opening of the fifth hole 17.

[0166] In practice, the distance between the relative surfaces of the second drain electrode 1125 and the second gate electrode 1121 and the distance between the relative surfaces of the first source electrode 1114 and the horizontal extension 11211 can be adjusted according to actual needs.

[0167] Please see Figures 2a to 4 , Figures 14a to 15b Furthermore, in storage unit 110:

[0168] The first active layer 1112, the first source electrode 1114, and the horizontal extension 11211 overlap on the substrate 200. The first source electrode 1114 and the horizontal extension 11211 are connected to the first active layer 1112. When the first source electrode 1114 and the write bit line 130 are formed as one, the first active layer 1112, the write bit line 130, and the horizontal extension 11211 overlap on the substrate 200.

[0169] The second active layer 1122, the second source electrode 1124, and the second drain electrode 1125 overlap on the substrate 200. The second source electrode 1124 and the second drain electrode 1125 are connected to the second active layer 1122. When the second source electrode 1124 is integrated with the read word line 140 and the second drain electrode 1125 is integrated with the read bit line 150, the second active layer 1122 overlaps with the read word line 140 and the read bit line 150 on the substrate.

[0170] Meanwhile, the structure formed by the second active layer 1122 and the second gate insulating layer 1123 overlaps with the orthographic projection of the second gate electrode 1211 on the substrate 200, such that the second gate electrode 1121 is at least partially located on the periphery of the second active layer 1122.

[0171] Optionally, the second active layer 1122 and the second gate electrode 1211 overlap on the substrate 200 by their orthogonal projections.

[0172] Preferably, the orthographic projection of the first active layer 1112 onto the substrate 200 falls within the overlapping range of the orthographic projections of the first source electrode 1114 and the horizontal extension 11211 onto the substrate 200. The orthographic projection of the structure composed of the second active layer 1122 and the second gate insulating layer 1123 onto the substrate 200 falls within the overlapping range of the orthographic projections of the second source electrode 1124, the second gate electrode 1121, and the second drain electrode 1125 onto the substrate 200.

[0173] When the first source electrode 1114 is integrated with the write bit line 130, the second source electrode 1124 is integrated with the read word line 140, and the second drain electrode 1125 is integrated with the read bit line 150, the orthographic projection of the first active layer 1112 onto the substrate 200 falls within the overlapping range of the orthographic projections of the write bit line 130 and the horizontal extension 11211 onto the substrate 200. The orthographic projection of the structure composed of the second active layer 1122 and the second gate insulating layer 1123 onto the substrate 200 falls within the overlapping range of the orthographic projections of the read word line 140, the second gate electrode 1121, and the read bit line 150 onto the substrate 200.

[0174] Please continue reading. Figures 2a to 4 , Figures 12a to 12c , Figure 14a , Figure 14b and Figures 34a to 34c Furthermore, in the orthographic projection onto substrate 200:

[0175] The second gate electrode 1121 is parallel to the two opposite sides of the read bit line 150 extending in the same direction and overlaps with the two opposite sides of the read bit line 150. The second gate electrode 1121 overlaps with the write bit line 130 and the read word line 140, and the second gate electrode 1121 is located on the two opposite sides of the write bit line 130 and the read word line 140 extending in the same direction, and overlaps with the sides of the write bit line 130 and the read word line 140 that overlap with the second gate electrode 1121.

[0176] It is understood that during the fabrication of the second gate electrode 1211, the two sides of the second gate electrode 1211 extending along the X-axis direction can be fabricated in the same patterning process as the two sides of the read bit line 150 extending along the X-axis direction. Therefore, in the orthographic projection on the substrate 200, the two opposite sides of the second gate electrode 121 parallel to the extension direction of the read bit line 150 overlap with the two opposite sides of the read bit line 150.

[0177] Furthermore, the width of the second gate electrode 1121 in the Y-axis direction is equal to the width of the read bit line 150.

[0178] Similarly, during the fabrication of the second gate electrode 1211, the two sides of the second gate electrode 1211 extending along the Y-axis can be fabricated in the same patterning process as the two sides of the write bit line 130 and the read word line 140 that are far from each other. Therefore, in the orthographic projection on the substrate 200, the second gate electrode 1121 is located on two opposite sides in the extension direction of the write bit line 130 and the read word line 140, respectively overlapping with the sides of the write bit line 130 and the read word line 140 that overlap with the second gate electrode 1121.

[0179] It is worth noting that the aforementioned overlap is not limited to complete overlap.

[0180] For example, during the fabrication of the second gate electrode 1211, the two sides of the second gate electrode 1211 extending along the X-axis direction can be fabricated in the same patterning process as the two opposite sides of the read bit line 150 extending in the same patterning process. The two sides of the second gate electrode 1211 extending along the Y-axis direction can be fabricated in the same patterning process as the two sides of the write bit line 130 and the read word line 140 that are far away from each other. However, the second gate electrode 121 is in a different layer from the read bit line 150, the write bit line 130 and the read word line 140, so there may be some error. However, this error is within the overlap range, that is, the overlap includes complete overlap and approximate overlap.

[0181] Similarly, equal widths include both completely equal and approximately equal widths.

[0182] Please see Figure 2a Figure 3a Furthermore, the first active layer 1112 is a groove-shaped structure, and the bottom end of the groove-shaped structure contacts or is embedded in the horizontal extension 11211.

[0183] The groove structure can be understood as a U-shaped bottom structure, that is, the first active layer 1112 has a surface bottom that is in contact with the horizontal extension 11211 with a large area, so as to realize the effective contact connection between the first active layer 1112 and the horizontal extension 11211 and reduce the connection impedance between the first active layer 1112 and the horizontal extension 11211; the bottom end of the groove structure is embedded in the horizontal extension 11211, which can further reduce the connection impedance and reduce the process difficulty of fabricating the memory cell 100.

[0184] Please see Figure 2b Figure 3b The first active layer 1112 has a cylindrical structure, and the drain end of the first active layer 1112 of the cylindrical structure penetrates the horizontal extension 11211. The cylindrical structure can be understood as a hollow, bottomless structure.

[0185] Preferably, in the same storage device layer 100, the first active layer 1112 is entirely a groove structure or entirely a cylindrical structure, which simplifies the manufacturing process.

[0186] Please see Figure 6 The storage device 1000 includes multiple storage device layers 100 stacked vertically (along the Z-axis direction) on a substrate 200. The storage device 1000 also includes an insulating isolation layer 160 disposed between two adjacent storage device layers 100.

[0187] The insulating isolation layer 160 is used to isolate adjacent memory device layers 100, preventing short circuits between them. Adjacent memory device layers 100 can be independently controlled and can perform read / write operations independently. The insulating isolation layer 160 can be made of insulating materials, such as silicon oxide (SiO2), trisilicon tetranitride (Si3N4), TEOS (tetraethoxysilane), or low-dielectric-constant materials. Therefore, by stacking multiple memory device layers 100 in the vertical direction to form the memory device 1000, the storage density per unit area can be increased.

[0188] It is important to note that Figure 6 In the storage device 1000 shown, each storage device layer 100 includes, as follows: Figure 3a The storage device layer 100 shown is a storage cell, but the present invention is not limited thereto. Multiple storage device layers 100 in the storage device 1000 may all include, for example, storage device layers 100. Figure 3a The storage device layer 100 of the shown storage cell may include, for example, the storage device layer 100 of the storage cell. Figure 3b The storage device layer 100 of the storage cell shown, or a portion of the storage device layers 100 in the storage device 1000, includes, as shown in the figure, storage device layer 100. Figure 3a The storage device layer 100 of the storage cell shown, and a portion of the storage device layer 100 includes, for example, storage devices such as ... Figure 3b The storage device layer 100 of the storage cell shown; the insulating isolation layer 160 is disposed between two adjacent storage device layers 100.

[0189] In different storage device layers 100, the first horizontal direction may be the same or different, and the second horizontal direction may be the same or different.

[0190] Please see Figures 7a to 9 In the illustrated embodiment, the storage device 1000 includes multiple storage device layers 100. At least one of the multiple storage device layers 100 has a first active layer 1112 with a groove-shaped structure. The bottom end of the groove-shaped structure contacts or is embedded in a horizontal extension 11211. That is, at least one storage device layer 100 includes, for example, a... Figure 3aThe storage device layer 100 of the shown storage cell, and in at least one other layer of the multi-layer storage device layer 100, the first active layer 1112 is a cylindrical structure, the cylindrical structure corresponding to the end of the drain terminal of the first active layer 1112 penetrating the horizontal extension 11211, that is, at least one storage device layer 100 includes such a storage device layer 100. Figure 3b The storage device layer 100 of the shown storage cell; the multi-layer storage device layer 100 is divided vertically into at least one shared cell 300, the shared cell 300 including two vertically adjacent storage device layers 100. In the shared cell 300, the two adjacent storage device layers 100 share a write word line 120, such as... Figure 7a As shown; or two adjacent memory device layers 100 share a read bit line 150, such as Figure 7b As shown.

[0191] Specifically, each shared unit 300 may include at least two memory cells 110 arranged in a mirror image in the vertical direction, with the two memory cells 110 sharing the same write word line 120 or read bit line 150. Compared to a memory structure that directly stacks memory cells 110 in both horizontal and vertical directions, the design of the shared unit 300 can reduce the number of write word lines 120 or read bit lines 150 without affecting the storage density of the memory device 1000, thereby simplifying the structure of the memory device 1000, reducing production costs, and further increasing the storage density of the memory device 1000.

[0192] It is worth noting that although the two memory cells 110 in the shared cell 300 are mirrored, the structures in the two memory cells 110 may not be completely identical. They are only mirrored in terms of "functional structure". That is, both memory cells 110 have corresponding structures, but the actual composition of the corresponding structures may not be the same. For example, the structures of the first active layer 1112 in the two write transistors 111 may be different.

[0193] For example, such as Figure 7a , 7b As shown, the shared unit 300 includes adjacent memory device layers 100 sharing a write word line 120 or a write bit line 150. In two adjacent memory device layers 100, one memory device layer 100 includes, for example... Figure 3a The storage device layer 100 of the shown storage cell has a slot-shaped first active layer 1112, and another storage device layer 100 includes, as shown in the figure, a first active layer 1112. Figure 3b The storage device layer 100 of the storage cell shown has a first active layer 1112 with a cylindrical structure. The end of the cylindrical structure corresponding to the drain end of the first active layer 1112 extends through a horizontal extension 11211. The two storage device layers 100 are mirror images of each other.

[0194] Please see Figure 8Furthermore, the storage device 1000 also includes an insulating isolation layer 160 disposed between the common cell 300 and the storage device layer 100 adjacent to the common cell 300. For example, the common cells 300 are vertically stacked on the substrate 200 after being spaced apart by the insulating isolation layer 160; for example, the common cells 300 and the storage device layer 100 are vertically stacked on the substrate 200 after being spaced apart by the insulating isolation layer 160.

[0195] The insulating isolation layer 160 is used to isolate the shared unit 300 and the adjacent memory device layer 100, preventing short circuits between the memory device layers 100 in the shared unit 300 and the adjacent memory device layers 100 located on both sides of the insulating isolation layer 160. The memory device layers 100 in the shared unit 300 and the adjacent memory device layers 100 can be independently controlled and independently read / write operated. The insulating isolation layer 160 can be made of insulating materials, such as silicon oxide (SiO2), trisilicon tetranitride (Si3N4), TEOS (tetraethoxysilane), or low dielectric constant materials.

[0196] In addition, since the write transistor 111 and the read transistor 112 need to be connected to the peripheral circuit to realize read and write control, it is necessary to form an electrical connection between the peripheral circuit and the write transistor 111 and the read transistor 112, that is, it is necessary to form an electrical connection between the peripheral circuit and the write word line 120, the write bit line 130, the read word line 140 and the read bit line 150.

[0197] For example, the ends of the write word line 120, write bit line 130, read word line 140 and read bit line 150 are formed into stepped structures, and vertical through holes are made to connect to the stepped structures, thereby enabling the signal lines of the storage device 1000 (i.e., write word line 120, write bit line 130, read word line 140 and read bit line 150) to be led out, which facilitates the electrical connection of the peripheral circuit.

[0198] In some embodiments, the peripheral circuit is disposed in the semiconductor substrate 201, but the present invention does not specifically limit this and the position of the peripheral circuit can be specifically set according to actual needs.

[0199] Please see Figure 9 The shared cell 300 and the memory device layer 100 adjacent to the shared cell 300 share a write word line 120 or a read bit line 150. After sharing the read bit line 150, the shared cells 300 are vertically stacked on the substrate 200.

[0200] In other embodiments, specifically, the shared unit 300 may include two storage units 110 that are vertically adjacent and mirror-arranged, the two storage units 110 sharing a read bit line 150, and two storage units 110 that are vertically adjacent and mirror-arranged in two adjacent shared units 300 sharing a write word line 120, or two storage units 110 that are vertically mirror-arranged in two shared units 300 and a storage device layer 100 adjacent to the shared unit 300 sharing a write word line 120.

[0201] Compared to a storage structure that directly stacks storage cells 110 in horizontal and vertical arrays, the design of sharing read bit lines 150 or write word lines 120 among shared cells 300 can reduce the number of write word lines 120 or read bit lines 150 without affecting the storage density of storage device 1000, thereby simplifying the structure of storage device 1000, reducing production costs, and further increasing the storage density of storage device 1000.

[0202] The method for manufacturing the storage device 1000 according to any one of the above claims includes the following steps:

[0203] Step S1: Provide a first substrate 1.

[0204] Specifically, the first substrate 1 can be a temporary substrate or substrate 200. The present invention does not specifically limit the material of the temporary substrate; if the first substrate 1 is substrate 200, then the substrate 200 here is the same as the substrate 200 in the storage device 1000 mentioned above, and its material, structure and other technical contents will not be repeated here.

[0205] Step S2: Prepare at least one memory device layer 100 on the first surface 101 of the first substrate 1.

[0206] That is, the memory device layer 100 of the memory device 1000 in the above embodiment is prepared on the first substrate 1 described above. The detailed process will be described below. In some embodiments, the first substrate 1 is a substrate 200. Preparing at least one memory device layer 100 on the first substrate 1 includes preparing at least one memory device layer 100 on the insulating surface of the substrate 200, that is, on the surface of the insulating layer 202 away from the semiconductor substrate 201.

[0207] Step S3: The first substrate 1 is the substrate 200 in the above embodiment, and the first surface 101 is the insulating surface of the substrate 200, or the memory device layer 100 formed in step S2 is transferred to the insulating surface of the substrate 200.

[0208] That is, the memory device layer 100 can be fabricated on the substrate 200, or it can be transferred onto the substrate 200 after forming a temporary substrate (i.e., the first substrate 1 serves as a temporary substrate). In some embodiments, transferring the memory device layer 100 formed in step S2 to the insulating surface of the substrate 200 includes transferring the memory device layer 100 onto the insulating layer 202 of the substrate 200. The transfer method exemplarily includes bonding, and the present invention does not specifically limit the transfer method.

[0209] Please see Figure 10 Furthermore, step S2, which involves fabricating at least one storage device layer 100 on the first surface 101, may specifically include fabricating at least one first storage device layer 100 on the first surface 101. Fabricating at least one first storage device layer 100 may specifically include the following steps:

[0210] Please see Figures 11 to 12c ( Figure 12b for Figure 12a Cross-sectional view along the AA direction. Figure 12c for Figure 12a (Cross-sectional view in the middle BB direction), Step S21: First conductor layer 2, first insulating layer 3, and second conductor layer 4 are sequentially prepared on the first surface 101. A first patterning process is performed to form a first gap penetrating the second conductor layer 4, the first insulating layer 3, and the first conductor layer 2 to form a read bit line 150, a second drain electrode 1125, and a first patterned conductor layer 5. A first isolation insulating layer 6 is prepared, and the first isolation insulating layer 6 covers the upper surface of the first patterned conductor layer 5.

[0211] In some embodiments, preparing the first conductor layer 2 on the first surface 101 includes preparing the first conductor layer directly on the first surface 101.

[0212] In some embodiments, the fabrication of the first conductor layer 2 on the first surface 101 includes, after fabricating at least one memory device layer 100 on the first surface 101 of the first substrate 1, fabricating an insulating isolation layer 160 on the upper surface of the topmost memory device layer 100, and then fabricating the first conductor layer 2 on the surface of the insulating isolation layer 160 away from the first substrate 1.

[0213] In some embodiments, the fabrication of the first conductor layer 2 on the first surface 101 includes fabricating at least one memory device layer 100 on the first surface 101 of the first substrate 1, and fabricating the conductor layer where the read bit line 150 of the topmost memory device layer 100 is located.

[0214] The first conductor layer 2 and the second conductor layer 4 may include layers of materials such as titanium nitride (TiN), titanium (Ti), gold (Au), tungsten (W), molybdenum (Mo), aluminum (Al), copper (Cu), ruthenium (Ru), silver (Ag), and platinum (Pt), or stacks of the above materials, or layers formed by any combination of the above materials, or stacks of layers formed by any combination of the above materials. The materials of the first conductor layer 2 and the second conductor layer 4 may be the same or different.

[0215] The material of the first insulating layer 3 can be silicon oxide (SiOx), silicon nitride (SiNx), TEOS, low dielectric constant materials, or combinations of the above materials, laminated materials, or combined laminated materials.

[0216] In some embodiments, the first conductor layer 2, the first insulating layer 3, and the second conductor layer 4 can be formed by deposition methods such as chemical vapor deposition (CVD), atomic layer deposition (ALD), and physical vapor deposition (PVD). It is understood that any suitable materials and deposition processes can be used to form the first insulating layer 3, the first conductor layer, and the second conductor layer 4.

[0217] In this embodiment of the invention, the first patterning process includes etching, such as dry etching, wet etching, or a combination of dry and wet etching.

[0218] See Figure 12b and Figure 12c The first gap extends along the X-axis, dividing the first conductor layer 2 and the second conductor layer 4 into multiple strip-shaped read bit lines 150 and a first patterned conductor layer 5 extending along the X-axis. The multiple read bit lines 150 and the multiple first patterned conductor layers 5 are spaced apart along the Y-axis on their respective layers. The first patterned conductor layer 5 is used to subsequently form the second gate electrode 1121. In the orthographic projection onto the first substrate 1, the opposite sides of the first patterned conductor layer 5 parallel to the extension direction of the read bit lines 150 overlap with the opposite sides of the read bit lines 150. Understandably, the second drain electrode 1125 is a part of the read bit lines 150.

[0219] In one embodiment, a first insulating layer 6 can be formed on the upper surface of the first patterned conductor layer 5 by deposition methods such as chemical vapor deposition (CVD), atomic layer deposition (ALD), and physical vapor deposition (PVD).

[0220] The material of the first insulating layer 6 can be silicon oxide (SiOx), silicon nitride (SiNx), TEOS, low dielectric constant materials, or a combination of the above materials, a multilayer material, or a combined multilayer material.

[0221] In this embodiment of the invention, the first insulating layer 6 covers the upper surface of the first patterned conductor layer 5, and its thickness can be adjusted to adjust the distance between the subsequently formed second gate electrode 1121 and the write bit line 130, thereby adjusting the channel length of the subsequently formed write transistor to meet different electrical requirements of the write transistor.

[0222] In some embodiments, the first insulating layer 6 fills the first gap to improve the structural stability of the storage device layer 100.

[0223] In some embodiments, the first insulating layer 6 does not fill the first gap, thereby creating an air gap (not shown) in the first gap, reducing crosstalk between adjacent conductors in the storage device layer 100.

[0224] It is understood that the top of the air gap is lower than the upper surface of the first insulating layer 6 to facilitate subsequent process steps. Preferably, the upper surface of the first insulating layer 6 is flat.

[0225] Please see Figure 13a and Figure 13b ( Figure 13b for Figure 13a (Cross-sectional view in the CC direction), Step S22: Form a first hole 7 through the first isolation insulating layer 6, the first patterned conductor layer 5 and the first insulating layer 3, and form a second gate insulating layer 1123 and a second active layer 1122 sequentially on the sidewall of the first hole 7.

[0226] The first hole 7 is used to accommodate the second gate insulating layer 1123 and the second active layer 1122 of the read transistor 112. The first hole 7 can be formed by an etching process, such as dry etching, wet etching, or a combination of dry etching and wet etching.

[0227] Optionally, the first hole 7 is partially embedded in the upper surface of the read bit line 150, which can reduce the difficulty of the etching process and reduce the contact resistance between the drain terminal of the read transistor and the second drain electrode 1125.

[0228] After the first hole 7 is formed, insulating material is deposited on the bottom wall and side wall of the first hole 7 to form the second gate insulating layer 1123. The deposition method can be chemical vapor deposition (CVD), atomic layer deposition (ALD) or physical vapor deposition (PVD), etc. The present invention does not make specific limitations.

[0229] In this embodiment of the invention, the insulating material used for the second gate insulating layer 1123 may include silicon oxide, silicon nitride, TEOS, or a high dielectric constant material, etc., and the invention does not make specific limitations.

[0230] Next, the insulating material on the bottom wall of the first hole 7 (i.e. the upper surface of the read bit line 150) is removed, and a semiconductor material is deposited on the surface of the second gate insulating layer 1123 to form a second active layer 1122. The second active layer 1122 is electrically connected to the read bit line 150, and the second drain electrode 1125 includes the portion of the read bit line 150 opposite to the second active layer 1122.

[0231] In some embodiments, the second active layer 1122 and the second drain electrode 1125 are in direct contact to form an electrical connection. In other embodiments, other conductor layers or doped semiconductor layers are disposed between the second active layer 1122 and the second drain electrode 1125. The present invention does not make specific limitations.

[0232] The deposition method can be chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD), etc. In some embodiments, after depositing the semiconductor material to form the second active layer 1122, the method further includes the step of removing the portion of the semiconductor material layer located outside the first hole 7.

[0233] The material of the second active layer 1122 includes oxide semiconductors, such as at least one of indium oxide (In2O3), tin oxide (SnO2), gallium oxide (Ga2O3), indium tin oxide (ITO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), and indium zinc oxide (IZO).

[0234] In this embodiment of the invention, the material of the second active layer 1122 is indium gallium zinc oxide (IGZO).

[0235] In some embodiments, the second active layer 1122 is a hollow structure, such as a groove or cylinder structure. After the second active layer 1122 is formed, an insulating material is deposited in the hollow of the second active layer 1122 to fill it, thereby forming a dielectric layer in the hollow. The dielectric layer is the same as described above and will not be repeated here.

[0236] Please see Figure 14a , Figure 14b and Figure 14c ( Figure 14b for Figure 14a Cross-sectional view along the DD direction. Figure 14c for Figure 14a(Cross-sectional view in the middle EE direction), Step S23: Prepare a third conductor layer on the upper surface of the first isolation insulating layer 6, perform a second patterning process to form a second gap penetrating the third conductor layer, and a third gap penetrating the third conductor layer, the first isolation insulating layer 6, and the first patterned conductor layer 5, so as to form a second gate electrode 1121, a write bit line 130, a read word line 140, a first source electrode 1114, and a second source electrode 1124, and prepare a second isolation insulating layer 9, which covers the upper surface of the first source electrode 1114.

[0237] The material of the third conductor layer can be a layer of titanium nitride (TiN), titanium (Ti), gold (Au), tungsten (W), molybdenum (Mo), aluminum (Al), copper (Cu), ruthenium (Ru), silver (Ag), platinum (Pt), or a stack of the above materials, or a layer formed by any combination of the above materials, or a stack of the above materials. The material of the third conductor layer can be the same as or different from any of the first conductor layer 2 and the second conductor layer 4.

[0238] In one embodiment, the third conductor layer can be prepared on the upper surface of the first insulating layer 6 by deposition methods such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD). It is understood that any suitable materials and deposition processes can be used to prepare the third conductor layer.

[0239] In this embodiment of the invention, the second patterning process can be etching, such as dry etching, wet etching, or a combination of dry and wet etching. The second patterning process forms a second slit and a third slit, which have different depths and penetrate different film layers. The second patterning process can be performed in two separate etching operations, or it can be performed in a single etching operation using a grayscale mask or a combination of stacked masks. This invention does not impose any specific limitations.

[0240] For example, the second patterning process can be divided into two etching processes, including a first etching to form a second or third slit, filling the second or third slit with an insulating material layer, and a second etching to form a third or second slit, filling the third or second slit with an insulating material layer, the insulating material layer being formed as part of a second insulating layer 9.

[0241] See Figure 14a and Figure 14b The second gap extends along the Y-axis and penetrates the third conductor layer. See [link / reference]. Figures 14a to 14cThe third gap extends along the Y-axis and penetrates the third conductor layer, the first insulating layer 6, and the first patterned conductor layer 5. The second and third gaps divide the third conductor layer into strip-shaped write bit lines 130 and read word lines 140 that extend along the Y-axis and are spaced apart along the X-axis; the third gap also divides the first patterned conductor layer 5 into multiple second gate electrodes 1121.

[0242] In addition, in the orthographic projection on the substrate 200: the two opposite sides of the second gate electrode 1121 parallel to the extension direction of the read bit line 150 overlap with the two opposite sides of the read bit line 150, and the two opposite sides of the second gate electrode 1121 parallel to the extension direction of the write bit line 130 and the read word line 140 overlap with the sides of the write bit line 130 and the read word line 140 that overlap with the second gate electrode 1121.

[0243] Preferably, the second gap extends into a portion of the depth of the first insulating layer 6, and the third gap extends into a portion of the depth of the first insulating layer 3, so as to improve the reliability of the third conductor layer and the first patterned conductor layer 5 being patterned to be disconnected, while reducing the difficulty of the etching process.

[0244] The second gate electrode 1121 is located below the write bit line 130 and the read word line 140, and multiple second gate electrodes 1121 are arrayed on the X-axis and Y-axis. The first source electrode 1114 and the second source electrode 1124 are located on the write bit line 130 and the read word line 140, respectively, and are part of the write bit line 130 and the read word line 140.

[0245] At this time, the second active layer 1122, the second gate insulating layer 1123, the second gate electrode 1121, the second source electrode 1124 and the second drain electrode 1125 together constitute the read transistor 112.

[0246] In one embodiment, a second insulating layer 9 covering the upper surface of the first source electrode 1114 can be formed by deposition methods such as chemical vapor deposition (CVD), atomic layer deposition (ALD), and physical vapor deposition (PVD).

[0247] The material of the second insulating layer 9 can be silicon oxide (SiOx), silicon nitride (SiNx), TEOS, low dielectric constant materials, or combinations, stacks, or composite stacks of the above materials. In some embodiments, the second insulating layer 9 does not completely fill the second gap, thereby forming an air gap (not shown) in the second gap to reduce crosstalk between adjacent conductors in the memory device layer 100. It is understood that the top of the air gap is lower than the upper surface of the second insulating layer 9 to facilitate subsequent process steps. Preferably, the upper surface of the second insulating layer 9 is flat.

[0248] Please see Figure 15a and Figure 15b ( Figure 15b for Figure 15a (Cross-sectional view in the middle FF direction), Step S24: Form a second hole 10 through the second isolation insulating layer 9, the first source electrode 1114 and the first isolation insulating layer 6, and form a first active layer 1112, a first gate insulating layer 1113 and a first gate electrode 1111 sequentially on the sidewall of the second hole 10.

[0249] The second hole 10 is used to accommodate the first active layer 1112, the first gate insulating layer 1113, and the first gate electrode 1111 of the write transistor 111. The second hole 10 can be formed by an etching process, such as dry etching, wet etching, or a combination of dry and wet etching. The depth of the second hole 10 reaches at least the second gate electrode 1121.

[0250] Preferably, the second hole 10 is embedded to a certain depth of the second gate electrode 1121 to increase the contact area between the drain end of the first active layer 1112 and the second gate electrode 1121, reduce the connection impedance between the drain end of the first active layer 1112 and the second gate electrode 1121, and at the same time reduce the etching process difficulty of the second hole 10.

[0251] After the second hole 10 is formed, a first active layer 1112, a first gate insulating layer 1113 and a first gate electrode 1111 are sequentially deposited on the sidewall of the second hole 10. The deposition method can be chemical vapor deposition (CVD), atomic layer deposition (ALD) or physical vapor deposition (PVD).

[0252] For example, a semiconductor material layer is deposited in the second hole 10. The portion of the semiconductor material layer outside the second hole 10 is removed to form a first active layer 1112. An insulating material layer and a conductive material layer are sequentially deposited in the second hole 10. A patterning process is performed to form a first gate insulating layer 1113 and a first gate electrode 1111. An insulating material layer is deposited and a planarization process is performed to expose the first gate electrode 1111. The remaining insulating material layer forms part of the second insulating isolation layer 9, resulting in... Figure 15a The structure shown.

[0253] The material of the first active layer 1112 may include an oxide semiconductor, such as at least one of indium oxide (In2O3), tin oxide (SnO2), gallium oxide (Ga2O3), indium tin oxide (ITO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), and indium zinc oxide (IZO).

[0254] In this embodiment of the invention, the material of the first active layer 1112 is indium gallium zinc oxide (IGZO).

[0255] In this embodiment of the invention, the material of the first gate insulating layer 1113 can be silicon oxide, silicon nitride, TEOS or a high dielectric constant material, etc., and the invention does not make specific limitations.

[0256] In this embodiment of the invention, the material of the first gate electrode 1111 can be a conductive material, such as a layer of titanium nitride TiN, titanium Ti, gold Au, tungsten W, molybdenum Mo, indium tin oxide (ITO), indium zinc oxide (IZO), copper Cu, ruthenium Ru, silver Ag, platinum Pt, or a stack of the above materials, or a layer formed by any combination of the above materials, or a stack of the above materials.

[0257] At this time, the first active layer 1112 is electrically connected to the write bit line 130 and the second gate electrode 1211, and the first source electrode 1114 includes the portion of the write bit line 130 opposite to the first active layer 1112.

[0258] In some embodiments, the first active layer 1112 and the first source electrode 1114 are in direct contact to form an electrical connection.

[0259] In other embodiments, other conductor layers or doped semiconductor layers are disposed between the first active layer 1112 and the first source electrode 1114, which is not specifically limited in this invention.

[0260] In some embodiments, the first active layer 1112 and the second gate electrode 1211 are in direct contact to form an electrical connection.

[0261] In other embodiments, other conductor layers or doped semiconductor layers are disposed between the first active layer 1112 and the second gate electrode 1211, which is not specifically limited in this invention.

[0262] In this embodiment of the invention, the first gate electrode 1111, the first gate insulating layer 1113, the first active layer 1112 and the first source electrode 1114 together constitute the write transistor 111.

[0263] like Figure 15a As shown, the first gate insulating layer 1113 and the first active layer 1112 are bottomed groove structures, which makes the first active layer 1112 and the horizontal extension 11211 have a large contact area and a small contact impedance.

[0264] In some embodiments, the first gate insulating layer 1113 and the first active layer 1112 are bottomless cylindrical structures, such that the first gate insulating layer 1113 is located between the first active layer 1112 and the first gate electrode 1111, and between the first gate electrode 1111 and the second gate electrode 1121, which provides insulation.

[0265] In some embodiments, the first gate electrode 1111 is a hollow structure, such as a groove or cylinder structure. After the second active layer 1122 is formed, an insulating material is deposited in the hollow of the first gate electrode 1111 to fill it, thereby forming a dielectric layer in the hollow. The dielectric layer is the same as described above and will not be repeated here.

[0266] Please see Figure 16a and Figure 16b ( Figure 16b for Figure 16a (Cross-sectional view in the middle GG direction), Step S25: Prepare the fourth conductor layer and perform a third patterning process on the fourth conductor layer to form write word line 120, which is isolated from read word line 140.

[0267] The fourth conductor layer can be made of materials such as titanium nitride (TiN), titanium (Ti), gold (Au), tungsten (W), molybdenum (Mo), aluminum (Al), copper (Cu), ruthenium (Ru), silver (Ag), platinum (Pt), etc., or a stack of such materials, or a layer formed by any combination of such materials, or a stack of such materials. The materials of the fourth conductor layer can be the same as or different from those of the other conductor layers.

[0268] In one embodiment, the fourth conductor layer can be prepared on the upper surface of the first insulating layer 6 by deposition methods such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD). It is understood that any suitable materials and deposition processes can be used to prepare the fourth conductor layer.

[0269] In this embodiment of the invention, the third patterning process described above can be etching, such as dry etching, wet etching, or a combination of dry and wet etching. See also Figure 16b The fourth conductor layer is etched using a third patterning process to form strip-shaped write word lines 120 extending along the X-axis, with multiple write word lines 120 spaced apart along the Y-axis. Optionally, after forming the write word lines 120 by etching the fourth conductor layer using the third patterning process, the process further includes the step of preparing an insulating isolation layer 160, which at least fills the spaces between adjacent write word lines 120.

[0270] Furthermore, in step S22, the sequential formation of the second gate insulating layer 1123 and the second active layer 1122 on the sidewall of the first hole 7 includes the following steps:

[0271] Step S221: Deposit a second gate insulating layer 1123 material. The second gate insulating layer 1123 material covers the upper surface of the first isolation insulating layer 6, the sidewall and bottom surface of the first hole 7. Anisotropic etching is performed to remove the portion of the second gate insulating layer 1123 material located on the upper surface of the first isolation insulating layer 6 and the bottom surface of the first hole 7, forming a second gate insulating layer 1123 located on the sidewall of the first hole 7.

[0272] Specifically, in this embodiment of the invention, the second active layer 1122 is formed in the inner wall of the second gate insulating layer 1123. Therefore, the second gate insulating layer 1123 needs to be prepared into a cylindrical structure first. This requires removing the second gate insulating layer 1123 deposited on the bottom surface of the first hole 7. The removal process is anisotropic etching. Preferably, the second gate insulating layer 1123 deposited on the bottom surface of the first hole 7 is removed at the same time as the second gate insulating layer 1123 deposited on the upper surface of the first isolation insulating layer 6. The second gate insulating layer 1123 formed on the side wall of the first hole 7 after the removal is completed is a cylindrical structure.

[0273] For detailed deposition process and material of the second gate insulating layer 1123, please refer to the description in step S2 above, which will not be repeated here.

[0274] Step S222: Fill the trench formed by the sidewall of the second gate insulating layer 1123 and the bottom surface of the first hole 7 with the material of the second active layer 1122, and etch back the material of the second active layer 1122 until the top surface of the material of the second active layer 1122 is lower than the upper surface of the first isolation insulating layer 6 to form the second active layer 1122.

[0275] After preparing the cylindrical second gate insulating layer 1123, the second active layer 1122 material is deposited and filled in the space enclosed by the second gate insulating layer 1123. At this time, the second active layer 1122 material is etched to a depth where its top surface is lower than the upper surface of the first insulating layer 6 by a back etching method, thus preparing the second active layer 1122 material. Figure 5a The second active layer 1122 of the illustrated embodiment allows the channel length of the readout transistor 112 to be adjusted according to the depth of the back etch.

[0276] In some embodiments, the material of the second active layer 1122 is etched back while the material of the second gate insulating layer 1123 is also etched back, so that the top surfaces of the formed second gate insulating layer 1123 and the second active layer 1122 are both lower than the upper surface of the first isolation insulating layer 6.

[0277] The material of the second active layer 1122 can be referred to the description in step S2 above, and will not be repeated here.

[0278] Please see Figure 17Furthermore, step S2, which involves fabricating at least one memory device layer 100 on the first surface 101, may specifically include fabricating at least one first memory device layer 100 on the first surface 101. The fabrication of at least one first memory device layer 100 may further include the following steps:

[0279] Please see Figures 18 to 23b Step S26: Prepare a first conductor layer 2 and perform a first patterning process on the first conductor layer 2 to form a write word line 120. Prepare a first insulating layer 3 to cover the write word line 120. Prepare a second conductor layer 4 on the surface of the first insulating layer 3 away from the write word line 120 and perform a second patterning process to form a write bit line 130, a read word line 140, a first source electrode 1114 and a second source electrode 1124. Prepare a first insulating layer 6 to cover the write bit line 130, the read word line 140, the first source electrode 1114 and the second source electrode 1124.

[0280] For example, fabricating the first conductor layer 2 includes fabricating the first conductor layer 2 on the first surface 101 of the first substrate 1, such as... Figure 18 As shown, this embodiment uses this as an example for simplification.

[0281] In some embodiments, preparing the first conductor layer 2 on the first surface 101 includes preparing the first conductor layer directly on the first surface 101.

[0282] In some embodiments, the fabrication of the first conductor layer 2 on the first surface 101 includes, after fabricating at least one memory device layer 100 on the first surface 101 of the first substrate 1, fabricating an insulating isolation layer 160 on the upper surface of the topmost memory device layer 100, and then fabricating the first conductor layer 2 on the surface of the insulating isolation layer 160 away from the first substrate 1.

[0283] In some embodiments, the fabrication of the first conductor layer 2 on the first surface 101 includes: fabricating at least one memory device layer 100 on the first surface 101 of the first substrate 1, and fabricating the conductor layer where the write word line 120 of the topmost memory device layer 100 is located.

[0284] The materials of the first conductor layer 2 and the second conductor layer 4 can be layers of materials such as titanium nitride (TiN), titanium (Ti), gold (Au), tungsten (W), molybdenum (Mo), aluminum (Al), copper (Cu), ruthenium (Ru), silver (Ag), and platinum (Pt), or stacks of the above materials, or layers formed by any combination of the above materials, or stacks of layers formed by any combination of the above materials.

[0285] The material of the first insulating layer 3 can be silicon oxide (SiOx), silicon nitride (SiNx), TEOS, low dielectric constant materials, or combinations of the above materials, multilayer materials, or combined multilayer materials. Gaps exist between adjacent write word lines 120. In some embodiments, the first insulating layer 3 fills these gaps to improve the structural stability of the memory device layer 100.

[0286] In some embodiments, the first insulating layer 3 is not completely filled in the gaps, thereby creating air gaps (not shown) to reduce crosstalk between adjacent conductors in the memory device layer 100. It is understood that the top of the air gap is lower than the upper surface of the first insulating layer 3 to facilitate subsequent process steps. Preferably, the upper surface of the first insulating layer 3 is flat.

[0287] In one embodiment, the first insulating layer 3, the first conductor layer 2, and the second conductor layer 4 can be formed by deposition methods such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD).

[0288] It is understood that any suitable materials and deposition processes can be used to form the first insulating layer 3, the first conductor layer 2 and the second conductor layer 4 respectively, and the materials of the first conductor layer 2 and the second conductor layer 4 can be the same or different.

[0289] In this embodiment of the invention, the first patterning process and the second patterning process can be etching, such as dry etching, wet etching, or a combination of dry etching and wet etching.

[0290] like Figure 20b ( Figure 20b for Figure 20a As shown in the cross-sectional schematic diagram in the middle HH direction, the first conductor layer 2 is divided into multiple write word lines 120 in the form of strips extending along the X-axis direction by the first patterning process, and the multiple write word lines 120 are distributed at intervals along the Y-axis direction.

[0291] like Figure 23b ( Figure 23b for Figure 23a As shown in the cross-sectional view (in the middle II direction), the second conductor layer 4 is divided into multiple write bit lines 130 and read bit lines 150 in strip shape extending along the Y-axis direction by a second patterning process, and the multiple write bit lines 130 and read bit lines 150 are distributed at intervals along the X-axis direction. The first source electrode 1114 is located above the write bit line 130 and is a part of the write bit line 130. The second source electrode 1124 is located on the read word line 140 and is a part of the read word line 140.

[0292] In one embodiment, the first insulating layer 6 can be prepared by deposition methods such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD).

[0293] The material of the first insulating layer 6 can be silicon oxide (SiOx), silicon nitride (SiNx), TEOS, low dielectric constant materials, or a combination of the above materials, a multilayer material, or a combined multilayer material.

[0294] There are gaps between any adjacent write bit lines 130 and read bit lines 150. In some embodiments, the first insulating layer 6 fills the gaps to improve the structural stability of the memory device layer 100.

[0295] In some embodiments, the first insulating layer 6 does not completely fill the gaps, thereby creating air gaps (not shown) to reduce crosstalk between adjacent conductors in the storage device layer 100. It is understood that the top of the air gap is lower than the upper surface of the first insulating layer 6 to facilitate subsequent process steps. Preferably, the upper surface of the first insulating layer 6 is flat.

[0296] Please see Figures 24 to 29b Step S27: Prepare a third conductor layer 8 on the surface of the first insulating layer 6 away from the write word line 120;

[0297] A third patterning process is performed on the third conductor layer 8 to form a second patterned conductor layer 12, the second patterned conductor layer 12 overlapping with the orthographic projection of the first source electrode 1114 and the second source electrode 1124 on the first substrate 1;

[0298] A third hole 13 is formed through the second patterned conductor layer 12 or the third conductor layer 8, the first isolation insulating layer 6, and the first source electrode 1114. A first active layer 1112 is formed on the sidewall of the third hole 13. A fourth hole 14 is formed extending from the upper surface of the second patterned conductor layer 12 or the third conductor layer 8 to the bottom of the third hole 13 and exposing the write word line 120. A first gate insulating layer 1113 and a first gate electrode 1111 connecting the write word line 120 are sequentially formed on the sidewall of the fourth hole 14.

[0299] It is worth mentioning that the order of some of the steps in step S27 can be reversed. That is, the step of “performing a third patterning process on the third conductor layer 8 to form a second patterned conductor layer 12” and the step of “forming a third hole 13 to form a first gate electrode 1111” can be reversed. Therefore, the above preparation steps are written as “forming a third hole 13 through the second patterned conductor layer 12 or the third conductor layer 8, the first isolation insulating layer 6, and the first source electrode 1114” and “forming a fourth hole 14 extending from the upper surface of the second patterned conductor layer 12 or the third conductor layer 8 to the bottom of the third hole 13 and exposing the write word line 120”.

[0300] If the order of the two steps above is reversed, i.e., the steps of forming the third hole 13 and the fourth hole 14 are before the steps of forming the second patterned conductor layer 12, then the above preparation steps are actually "forming the third hole 13 through the third conductor layer 8, the first isolation insulating layer 6, and the first source electrode 1114" and "forming the fourth hole 14 extending from the upper surface of the third conductor layer 8 to the bottom of the third hole 13 and exposing the write word line 120". If the preparation order provided above is used, the above preparation steps are actually "forming the third hole 13 through the second patterned conductor layer 12, the first isolation insulating layer 6, and the first source electrode 1114" and "forming the fourth hole 14 extending from the upper surface of the second patterned conductor layer 12 to the bottom of the third hole 13 and exposing the write word line 120".

[0301] For ease of description, the steps of forming the second patterned conductor layer 12 will be described first below.

[0302] The material of the third conductor layer 8 can be a layer of titanium nitride TiN, titanium Ti, gold Au, tungsten W, molybdenum Mo, aluminum Al, copper Cu, ruthenium Ru, silver Ag, platinum Pt, or a stack of the above materials, or a layer formed by any combination of the above materials, or a stack of the above materials. The material of the third conductor layer 8 can be the same as or different from any of the first conductor layer 2 and the second conductor layer 4.

[0303] In one embodiment, the third conductor layer 8 can be prepared on the upper surface of the first insulating layer 6 by deposition methods such as chemical vapor deposition (CVD), atomic layer deposition (ALD), and physical vapor deposition (PVD).

[0304] It is understandable that any suitable materials and deposition process can be used to prepare the aforementioned third conductor layer 8.

[0305] In this embodiment of the invention, the third patterning process can be etching, such as dry etching, wet etching, or a combination of dry and wet etching.

[0306] The second patterned conductor layer 12 is used to form the subsequent second gate electrode 1121 (including the horizontal extension 11211). Therefore, the second patterned conductor layer 12 overlaps with the orthographic projection of the first source electrode 1114 and the second source electrode 1124 on the first substrate 1, so that the subsequently formed second gate electrode 1121 can cover the area between the two, including the write bit line 130 and the read word line 140, in the orthographic projection. Thus, the vertical channel write transistor 111 and read transistor can be fabricated in subsequent process steps.

[0307] Optionally, after forming the second patterned conductor layer 12, a spacer insulating layer 15 is prepared, such as... Figure 25 , Figure 29b ( Figure 29b for Figure 29a As shown in the cross-sectional schematic diagram in the middle JJ direction, the second patterned conductor layer 12 extends along the Y-axis direction and is spaced apart along the X-axis direction, and the spacer insulating layer 15 fills at least between adjacent patterned conductor layers 12.

[0308] Among them, see Figure 26 The third hole 13 extends vertically downwards from the surface of the second patterned conductor layer 12 and penetrates the first source electrode 1114. That is, the third hole 13 penetrates both the second patterned conductor layer 12 and the write bit line 130. When the first active layer 1112 is deposited and formed on the sidewall of the third hole 13, the contact connection between the first active layer 1112 and the write word line 120 is achieved, i.e., the contact connection between the first active layer 1112 and the first source electrode 1114 is achieved. Figure 27 As shown.

[0309] In this embodiment of the invention, the third hole 13 can be formed by etching, such as dry etching, wet etching, or a combination of dry and wet etching. Preferably, the third hole 13 extends to a portion of the depth of the first insulating layer 3 to reduce the difficulty of the etching process.

[0310] In this embodiment of the invention, the first active layer 1112 is formed by a deposition process, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), etc.

[0311] Subsequently, the bottom of the first active layer 1112, i.e., the bottom of the third hole 13, is etched downwards to form a fourth hole 14 that extends downwards to the surface of the write word line 120, resulting in the following... Figure 28 In the structure shown, a first gate insulating layer 1113 and a first gate electrode 1111 are sequentially deposited in the fourth hole 14. The first gate electrode 1111 can then directly contact and connect with the write word line 120. Since the third hole 13 penetrates the write bit line 130 and the first gate insulating layer 1113 is fabricated along the hole wall of the fourth hole 14, short circuit between the first gate electrode 1111 and the write bit line 130 is avoided. Figure 29a As shown.

[0312] In this embodiment of the invention, the fourth hole 14 can be formed by etching, such as dry etching, wet etching, or a combination of dry and wet etching processes.

[0313] In this embodiment of the invention, the first gate insulating layer 1113 and the first gate electrode 1111 can be formed by deposition processes, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), etc.

[0314] The material of the first gate insulating layer 1113 can be silicon oxide (SiOx), silicon nitride (SiNx), aluminum oxide (Al2O3), hafnium dioxide (HfO2), zirconium dioxide (ZrO2), titanium dioxide (TiO2), yttrium oxide (Y2O3), or a combination of the above materials, a stacked material, or a combined stacked material. It can also be TEOS.

[0315] The material of the first gate electrode 1111 can be a conductive material, such as titanium nitride (TiN), titanium (Ti), gold (Au), tungsten (W), molybdenum (Mo), indium tin oxide (ITO), indium zinc oxide (IZO), copper (Cu), ruthenium (Ru), silver (Ag), platinum (Pt), or any combination of the above materials.

[0316] In this embodiment of the invention, the third hole 13 is used to accommodate the first gate electrode 1111, the first gate insulating layer 1113, and the first active layer 1112 of the write transistor 111. The first gate electrode 1111, the first gate insulating layer 1113, the first active layer 1112, and the first source electrode 1114 constitute the write transistor 111.

[0317] Please see Figures 30 to 32 Step S28: Form a second insulating layer 16 covering the second patterned conductor layer 12 and the first gate electrode 1111, form a fifth hole 17 penetrating the second insulating layer 16, the second patterned conductor layer 12, and the first isolation insulating layer 6 and exposing the second source electrode 1124, and form a second gate insulating layer 1123 and a second active layer 1122 connecting the second source electrode 1124 sequentially on the sidewall of the fifth hole 17.

[0318] The second insulating layer 16 can be formed by a deposition process, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD). In some embodiments, the coupling between the read bit line 150 and the second gate electrode 1121 can be reduced by increasing the thickness of the second insulating layer 16.

[0319] The material of the second insulating layer 16 can be silicon oxide (SiOx), silicon nitride (SiNx), TEOS, low dielectric constant materials, or a combination of the above materials, a multilayer material, or a combined multilayer material.

[0320] In this embodiment of the invention, the fifth hole 17 is used to accommodate the second active layer 1122 and the second gate insulating layer 1123 of the read transistor 112. Preferably, the fifth hole 17 extends into a portion of the depth of the second source electrode 1124. The fifth hole 17 can be formed by etching, such as dry etching, wet etching, or a combination of dry and wet etching processes.

[0321] In this embodiment of the invention, the second gate insulating layer 1123 and the second active layer 1122 can be formed by deposition processes, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), etc. When the second active layer 1122 is deposited on the sidewall of the fifth hole 17, the second active layer 1122 can directly form a contact connection with the second source electrode 1124 at the bottom of the fifth hole 17.

[0322] The material of the second active layer 1122 includes oxide semiconductors, such as at least one of indium oxide In2O3, tin oxide SnO2, gallium oxide Ga2O3, indium tin oxide ITO, indium gallium zinc oxide IGZO, indium gallium tin oxide ITZO, and zinc oxide ZnO.

[0323] In this embodiment of the invention, the material of the second active layer 1122 is indium gallium zinc oxide (IGZO).

[0324] The material of the second gate insulating layer 1123 can be silicon oxide (SiOx), silicon nitride (SiNx), aluminum oxide (Al2O3), hafnium dioxide (HfO2), zirconium dioxide (ZrO2), titanium dioxide (TiO2), yttrium oxide (Y2O3), or a combination of the above materials, a stacked material, or a combined stacked material. It can also be TEOS.

[0325] Please see Figures 33 to 34c ( Figure 34b for Figure 34a A cross-sectional view along the KK direction. Figure 34c for Figure 34a (Cross-sectional schematic diagram in the middle LL direction), Step S29: A fourth conductor layer 11 is formed on the side of the second insulating layer 16 away from the write word line 120. A third patterning process is performed to form a fourth gap through the fourth conductor layer 11, the second insulating layer 16, and the second patterned conductor layer 12 to form the read bit line 150 and the second gate electrode 1121.

[0326] Please see Figures 34a to 34c Optionally, the fourth gap is filled with an insulating layer 160.

[0327] The material of the fourth conductor layer 11 can be titanium nitride (TiN), titanium (Ti), gold (Au), tungsten (W), molybdenum (Mo), aluminum (Al), copper (Cu), ruthenium (Ru), silver (Ag), platinum (Pt), or any combination thereof.

[0328] In one embodiment, the fourth conductor layer 11 can be formed by deposition methods such as chemical vapor deposition (CVD), atomic layer deposition (ALD), and physical vapor deposition (PVD).

[0329] It is understood that any suitable materials and deposition process can be used to prepare the aforementioned fourth conductor layer 11.

[0330] In this embodiment of the invention, the third patterning process can be etching, such as dry etching, wet etching, or a combination of dry and wet etching.

[0331] The fourth gap, formed by the third patterning process, extends along the X-axis, dividing the fourth conductor layer 11 into multiple strip-shaped read bit lines 150 extending along the X-axis, such as... Figure 34b As shown, the second patterned conductor layer 12 is divided into a plurality of second gate electrodes 1121, which are arranged in an array along the X and Y directions, as shown. Figure 34c As shown.

[0332] In addition, in the orthographic projection on the substrate 200: the two opposite sides of the second gate electrode 1121 parallel to the extension direction of the read bit line 150 overlap with the two opposite sides of the read bit line 150.

[0333] The part where the read bit line 150 connects to the second gate electrode 1121 is the second drain electrode 1125.

[0334] At this time, the second active layer 1122, the second gate insulating layer 1123, the second gate electrode 1121, the second source electrode 1124 and the second drain electrode 1125 together constitute the read transistor 112.

[0335] In some embodiments, the order of some steps in the above method may be changed.

[0336] For example, see Figure 21A second conductor layer 4 is formed, and a patterning process is performed to form the second conductor layer 4 into a third patterned conductor layer. The third patterned conductor layer extends along the Y-axis. A fifth gap extending along the Y-axis is formed between adjacent third patterned conductor layers. A first insulating layer 6 is formed to fill the fifth gap and cover the third patterned conductor layer. A third conductor layer 8 is formed above the first insulating layer 6, and patterning is performed to form the third conductor layer 8 into a second patterned conductor layer 12. A sixth gap is formed between adjacent second patterned conductor layers 12, extending along the Y-axis. The sixth gap also penetrates the first insulating layer 6 and the third patterned conductor layer. The fifth and sixth gaps allow the second conductor layer 4 to be patterned to form write bit lines 130 and read word lines 140. Optionally, a spacer insulating layer 15 fills the sixth gap. This reduces the difficulty of the patterning process.

[0337] In this embodiment, the opposite sides of the second gate electrode 1121 extending along the second horizontal direction overlap with the edges of the write bit line 130 and the read word line 140 that overlap with the second gate electrode 1121 on the orthogonal projection of the first substrate 1.

[0338] Furthermore, in step S28, the sequential formation of a second gate insulating layer 1123 and a second active layer 1122 connecting the second source electrode 1124 on the sidewall of the fifth hole 17 includes the following steps:

[0339] Step S281: Deposit a second gate insulating layer 1123 material. The second gate insulating layer 1123 material covers the upper surface of the second insulating layer 16, the sidewall and bottom surface of the fifth hole 17. Anisotropic etching is performed to remove the portion of the second gate insulating layer 1123 material located on the upper surface of the second insulating layer 16 and the bottom surface of the fifth hole 17, forming a second gate insulating layer 1123 located on the sidewall of the fifth hole 17.

[0340] Specifically, in this embodiment of the invention, the second active layer 1122 is formed in the inner wall of the second gate insulating layer 1123. Therefore, the second gate insulating layer 1123 needs to be prepared into a cylindrical structure first. The second gate insulating layer 1123 deposited on the bottom surface of the fifth hole 17 needs to be removed. The removal process is anisotropic etching removal. Preferably, the second gate insulating layer 1123 deposited on the bottom surface of the fifth hole 17 is removed at the same time as the second gate insulating layer 1123 deposited on the upper surface of the first isolation insulating layer 6. After the removal is completed, the second gate insulating layer 1123 located on the side wall of the fifth hole 17 is a cylindrical structure.

[0341] The detailed deposition method and the material of the second gate insulating layer 1123 can be found in the description of step S2 above, and will not be repeated here. Furthermore, the advantages of the cylindrical second active layer 1122 have already been described above, and will not be repeated here either.

[0342] Step S282: Fill the trench formed by the sidewall of the second gate insulating layer 1123 and the bottom surface of the fifth hole 17 with the material of the second active layer 1122, and etch back the material of the second active layer 1122 until the top surface of the material of the second active layer 1122 is lower than the upper surface of the second insulating layer 16 to form the second active layer 1122.

[0343] After preparing the cylindrical second gate insulating layer 1123, the second active layer 1122 material is deposited and filled in the space enclosed by the second gate insulating layer 1123. At this time, the second active layer 1122 material is etched to a depth where its top surface is lower than the upper surface of the second insulating layer 16 by a back etching method, resulting in... Figure 5b The second active layer 1122 of the illustrated embodiment allows the channel length of the readout transistor 112 to be adjusted according to the depth of the back etch.

[0344] In some embodiments, the material of the second active layer 1122 is etched back while the material of the second gate insulating layer 1123 is also etched back, such that the top surfaces of the formed second gate insulating layer 1123 and the second active layer 1122 are both lower than the upper surface of the second insulating layer 16.

[0345] The material of the second active layer 1122 can be referred to the description in step S2 above, and will not be repeated here. Furthermore, the advantages of the cylindrical shape of the second active layer 1122 have already been described above, and will not be repeated here either.

[0346] See Figure 35 The circuit diagram showing the connection of memory cell 110, write word line 120, write bit line 130, read word line 140, and read bit line 150 is as follows:

[0347] The steps for performing a write operation on the memory cell 110 provided in one embodiment of the present invention may include: applying a voltage to the write word line 120 to turn on the write transistor 111, and applying a voltage to the write bit line 130 to charge the memory node SN, so that the memory node SN presents a high voltage or a low voltage, representing data 1 and 0 respectively; optionally, during the write operation on the memory node SN, no voltage is applied to the read word line 140.

[0348] An embodiment of the present invention provides a step for performing a read operation on the memory cell 110, which may include: when reading "1", applying a voltage to the read word line 140 to provide a voltage signal to the second source electrode 1124 electrically connected to the read word line 140. Since there is a certain charge in the memory node SN, there is a current flowing between the read bit line 150 and the read word line 140. The read operation on the memory node SN is performed by detecting the magnitude of the current in the read bit line 150; when reading "0", applying a read voltage to the read word line 140 in the read transistor. Since there is no charge in the memory node SN, there is no current flowing between the read bit line 150 and the read word line 140 or there is a small current flowing between them. No current is read on the read bit line 150, thus completing the reading process of data 0.

[0349] In the description of this specification, the references to terms such as "Embodiment 1," "Embodiment 2," etc., indicate that a specific feature, structure, material, or characteristic described in connection with an embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0350] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A storage device, characterized in that, include: Substrate, the substrate including an insulating surface; and At least one storage device layer disposed on the insulating surface, the storage device layer including a storage cell, a write word line, a write bit line, a read word line, and a read bit line; The storage unit includes a write transistor and a read transistor; The write transistor includes a first gate electrode, a first active layer, a first gate insulating layer, and a first source electrode. The first gate electrode is vertically disposed on the substrate. The first active layer is disposed at least partially around the first gate electrode. The first gate insulating layer is disposed between the first gate electrode and the first active layer. The first source electrode is connected to the source end of the first active layer. The read transistor includes a second gate electrode, a second active layer, a second gate insulating layer, a second source electrode, and a second drain electrode. The second active layer is vertically disposed on the substrate. The second gate electrode is disposed at least partially on the periphery of the second active layer. The second gate insulating layer is disposed between the second gate electrode and the second active layer. The second source electrode is connected to the source terminal of the second active layer, and the second drain electrode is connected to the drain terminal of the second active layer. The second gate electrode further includes a horizontal extension, which is connected to the drain terminal of the first active layer; The first gate electrode is connected to the write word line, the first source electrode is connected to the write bit line, the second source electrode is connected to the read word line, and the second drain electrode is connected to the read bit line. In the vertical direction, the write word line is located on the side of the first source electrode away from the horizontal extension.

2. The storage device according to claim 1, characterized in that, The first source electrode and the write bit line connected thereto are formed as one unit, the second source electrode and the read word line connected thereto are formed as one unit, and the second drain electrode and the read bit line connected thereto are formed as one unit.

3. The storage device according to claim 1 or 2, characterized in that, The storage device layer includes a plurality of storage cells arranged in an array in a first horizontal direction and a second horizontal direction, wherein the first horizontal direction and the second horizontal direction intersect. Multiple write word lines and multiple read bit lines are provided. The write word lines and multiple read bit lines are arranged at intervals in the second horizontal direction and extend along the first horizontal direction. The write word lines are connected to the first gate electrodes of the multiple write transistors arranged in the first horizontal direction, and the read bit lines are connected to the second drain electrodes of the multiple read transistors arranged in the first horizontal direction. Multiple write bit lines and multiple read word lines are provided, and they are alternately spaced in the first horizontal direction and extend along the second horizontal direction. The write bit lines are connected to the first source electrodes of the multiple write transistors arranged in the second horizontal direction, and the read word lines are connected to the second source electrodes of the multiple read transistors arranged in the second horizontal direction.

4. The storage device according to claim 1 or 2, characterized in that, The second source electrode and the first source electrode are located in the same layer.

5. The storage device according to claim 1 or 2, characterized in that, In the vertical direction: The second source electrode and the first source electrode are located in the same layer, and the distance between the opposing surfaces of the second source electrode and the second gate electrode is less than the distance between the opposing surfaces of the first source electrode and the horizontal extension; or The second drain electrode is integrally formed with the read bit line, and the distance between the opposing surfaces of the second drain electrode and the second gate electrode is smaller than the distance between the opposing surfaces of the read bit line and the second gate electrode.

6. The storage device according to claim 1 or 2, characterized in that, In the storage unit: The first active layer overlaps with the first source electrode and the orthographic projection of the horizontal extension on the substrate; The second active layer overlaps with the orthographic projections of the second source electrode, the second gate electrode, and the second drain electrode onto the substrate.

7. The storage device according to claim 2, characterized in that, In the orthographic projection on the substrate: The second gate electrode is parallel to the two opposite sides of the extension direction of the read bit line and overlaps with the two opposite sides of the read bit line respectively.

8. The storage device according to claim 2, characterized in that, In the orthographic projection of the substrate: The second gate electrode overlaps with the write bit line and the read word line, and the second gate electrode is parallel to the two opposite sides of the extension direction of the write bit line and the read word line, respectively overlapping with the sides of the write bit line and the read word line that overlap with the second gate electrode.

9. The storage device according to claim 1, characterized in that, The first active layer is a groove-shaped structure, and the bottom end of the groove-shaped structure contacts or is embedded in the horizontal extension; or The first active layer has a cylindrical structure, and the end of the cylindrical structure corresponding to the drain end of the first active layer extends through the horizontal extension.

10. The storage device according to claim 1, characterized in that, The storage device includes multiple layers of the storage device, which are vertically stacked on the substrate; In at least one of the multilayer memory device layers, the first active layer is a groove-shaped structure, and the bottom end of the groove-shaped structure contacts or is embedded in the horizontal extension; and in at least another layer of the multilayer memory device layer, the first active layer is a cylindrical structure, and the end of the cylindrical structure corresponding to the drain end of the first active layer penetrates the horizontal extension.

11. The storage device according to claim 9 or 10, characterized in that, The storage device includes multiple layers of the storage device, which are vertically stacked on the substrate; The storage device further includes an insulating isolation layer disposed between two adjacent storage device layers.

12. The storage device according to claim 1, characterized in that, The storage device includes multiple layers of the storage device, which are vertically stacked on the substrate; The multilayer storage device layer is divided into at least one common unit along the vertical direction, and the common unit includes two storage device layers that are adjacent in the vertical direction; In the shared unit, the adjacent memory device layers share the write word line or the read bit line; Furthermore, in one of the two adjacent storage device layers, the first active layer has a groove-shaped structure, and the bottom end of the groove-shaped structure contacts or is embedded in the horizontal extension portion of the first layer. In the other of the two adjacent storage device layers, the first active layer has a cylindrical structure, and the end of the cylindrical structure corresponding to the drain end of the first active layer extends through the horizontal extension.

13. The storage device according to claim 12, characterized in that, The storage device further includes an insulating isolation layer disposed between the common unit and the storage device layer adjacent to the common unit.

14. The storage device according to claim 1, characterized in that, The write word line, the write bit line, the read word line, the read bit line, the first gate electrode, the first source electrode, the second gate electrode, the second source electrode, and the second drain electrode are made of the same or different materials and include conductors; The first active layer and the second active layer are made of the same or different materials, and include oxide semiconductors.

15. The storage device according to claim 14, characterized in that, The conductor includes at least one of aluminum, titanium, tungsten, titanium nitride, and doped polycrystalline silicon; The oxide semiconductor includes at least one of indium oxide, tin oxide, gallium oxide, indium tin oxide, zinc oxide, indium zinc oxide, and indium gallium zinc oxide.

16. A method for manufacturing a storage device, used to manufacture the storage device according to any one of claims 1 to 15, characterized in that, Includes the following steps: S1. Provide a first substrate; S2. Prepare at least one layer of the memory device layer on the first surface of the first substrate; S3. The first substrate is the substrate, the first surface is the insulating surface, or the memory device layer formed in step S2 is transferred to the insulating surface of the substrate.

17. The preparation method according to claim 16, characterized in that, The step of fabricating at least one storage device layer on the first surface includes fabricating at least one first storage device layer, wherein fabricating at least one first storage device layer includes the following steps: S21. A first conductor layer, a first insulating layer, and a second conductor layer are sequentially prepared on the first surface. A first patterning process is performed to form a first gap penetrating the second conductor layer, the first insulating layer, and the first conductor layer to form the read bit line, the second drain electrode, and the first patterned conductor layer. A first isolation insulating layer is prepared, and the first isolation insulating layer covers the upper surface of the first patterned conductor layer. S22. A first hole is formed penetrating the first isolation insulating layer, the first patterned conductor layer and the first insulating layer, and a second gate insulating layer and a second active layer are sequentially formed on the sidewall of the first hole; S23. A third conductor layer is prepared on the upper surface of the first isolation insulating layer, and a second patterning process is performed to form a second gap penetrating the third conductor layer and a third gap penetrating the third conductor layer, the first isolation insulating layer, and the first patterned conductor layer to form the second gate electrode, the write bit line, the read word line, the first source electrode, and the second source electrode, and a second isolation insulating layer is prepared, the second isolation insulating layer covering the upper surface of the first source electrode; S24. A second hole is formed penetrating the second isolation insulating layer, the first source electrode, and the first isolation insulating layer, and the first active layer, the first gate insulating layer, and the first gate electrode are sequentially formed on the sidewall of the second hole; S25. Prepare a fourth conductor layer and perform a third patterning process on the fourth conductor layer to form the write word line, wherein the write word line is isolated from the read word line.

18. The preparation method according to claim 17, characterized in that, In step S22, the step of sequentially forming the second gate insulating layer and the second active layer on the sidewall of the first hole includes the following steps: S221. Deposit a second gate insulating layer material, the second gate insulating layer material covering the upper surface of the first isolation insulating layer, the sidewall and the bottom surface of the first hole, and anisotropically etch to remove the portion of the second gate insulating layer material located on the upper surface of the first isolation insulating layer and the bottom surface of the first hole, to form a second gate insulating layer located on the sidewall of the first hole; S222. Fill the trench formed by the sidewall of the second gate insulating layer and the bottom surface of the first hole with a second active layer material, and etch the second active layer material back until the top surface of the second active layer material is lower than the upper surface of the first isolation insulating layer to form the second active layer.

19. The preparation method according to claim 16, characterized in that, The step of fabricating at least one storage device layer on the first surface includes fabricating at least one first storage device layer, and the fabrication of at least one first storage device layer further includes the following steps: S26. Prepare a first conductor layer and perform a first patterning process on the first conductor layer to form the write word line, prepare a first insulating layer to cover the write word line, prepare a second conductor layer on the surface of the first insulating layer away from the write word line and perform a second patterning process to form the write bit line, the read word line, the first source electrode and the second source electrode, and prepare a first insulating isolation layer to cover the write bit line, the read word line, the first source electrode and the second source electrode; S27. A third conductor layer is prepared on the surface of the first insulating layer away from the write word line; A third patterning process is performed on the third conductor layer to form a second patterned conductor layer, the second patterned conductor layer overlapping the orthographic projections of the first source electrode and the second source electrode on the first substrate; A third hole is formed through the second patterned conductor layer or the third conductor layer, the first isolation insulating layer, and the first source electrode. A first active layer is formed on the sidewall of the third hole. A fourth hole is formed extending from the upper surface of the second patterned conductor layer or the third conductor layer to the bottom of the third hole and exposing the write word line. A first gate insulating layer and a first gate electrode connected to the write word line are sequentially formed on the sidewall of the fourth hole. S28. A second insulating layer is formed covering the second patterned conductor layer and the first gate electrode, and a fifth hole is formed penetrating the second insulating layer, the second patterned conductor layer, and the first isolation insulating layer and exposing the second source electrode. A second gate insulating layer and a second active layer connecting the second source electrode are sequentially formed on the sidewall of the fifth hole. S29. A fourth conductor layer is formed on the side of the second insulating layer away from the write word line, and a third patterning process is performed to form a fourth gap through the fourth conductor layer, the second insulating layer, and the second patterned conductor layer to form the read bit line and the second gate electrode.

20. The preparation method according to claim 19, characterized in that, In step S28, the step of sequentially forming the second gate insulating layer and the second active layer connecting the second source electrode on the sidewall of the fifth hole includes the following steps: S281. Deposit a second gate insulating layer material, the second gate insulating layer material covering the upper surface of the second insulating layer, the sidewall and bottom surface of the fifth hole, and anisotropically etch to remove the portion of the second gate insulating layer material located on the upper surface of the second insulating layer and the bottom surface of the fifth hole, to form a second gate insulating layer located on the sidewall of the fourth hole; S282. Fill the trench formed by the sidewall of the second gate insulating layer and the bottom surface of the fifth hole with a second active layer material, and etch the second active layer material back until the top surface of the second active layer material is lower than the upper surface of the second insulating layer to form the second active layer.

Images