Three-dimensional stacked non-volatile memory device

Abstract

A three-dimensionally stacked non-volatile memory device of the present invention comprises: a memory cell including a read transistor and a write transistor stacked on the read transistor; a write word line connected to a gate terminal of the write transistor; a write bit line connected to a source terminal of the write transistor; a read word line connected to a source terminal of the read transistor; and a read bit line connected to a drain terminal of the read transistor, wherein the read transistor has a recessed channel structure, an insulation layer between a semiconductor layer and a gate electrode of the read transistor includes a ferroelectric material, and the semiconductor layer of the read transistor can include an oxide semiconductor material.

Description

3D stacked non-volatile memory device

[0001] The present invention relates to a three-dimensional stacked nonvolatile memory device, and more particularly, to a three-dimensional stacked nonvolatile memory device capable of low power, high integration, and non-destructive operation using a ferroelectric material.

[0002] There is a continuous demand for increasing the performance and integration of semiconductor devices. The two-dimensional (i.e., planar) arrangement of semiconductor unit cells has reached its limit in increasing the integration of semiconductor devices. Therefore, attempts are being made to develop technologies that significantly increase the integration of semiconductor devices by integrating semiconductor unit cells three-dimensionally. In this regard, various attempts are being made to increase the integration of memory devices, such as NAND and DRAM. Furthermore, research and development is continuously being conducted to improve the performance and operating characteristics of memory devices.

[0003] Recently, a new memory device structure has been proposed, one featuring a two-transistor zero capacitor (2T0C) cell structure. 2T0C memory devices have the advantages of utilizing the gate capacitance of a read transistor as a storage element, offering a long data retention time, and allowing cells to be configured using only multiple transistors without a capacitor.

[0004] However, since the existing 2T0C memory device has a structure in which both types of word lines and two types of bit lines extend horizontally and are disconnected between cells in the vertical direction, it is difficult to integrate them by stacking them three-dimensionally.

[0005] That is, since the first word line and the first bit line are arranged to be perpendicular to each other while extending in the horizontal direction, and similarly, the second word line and the second bit line are arranged to be perpendicular to each other while extending in the horizontal direction, when the cells are stacked three-dimensionally, there is a problem that the cells are disconnected in the vertical direction, the manufacturing process is difficult, and mass production is impossible.

[0006] Accordingly, the inventor of the present invention completed the present invention after a long period of research and trial and error to solve these problems and requirements.

[0007] The present invention was created to solve the problems of the prior art as described above, and one object of the present invention is to provide a three-dimensional stacked non-volatile memory device with a 2T0C structure capable of low power, high integration, and non-destructive operation using a ferroelectric material.

[0008] Meanwhile, other unspecified purposes of the present invention will be additionally considered within a range that can be easily inferred from the detailed description and effects thereof below.

[0009] A three-dimensional stacked non-volatile memory device according to one aspect of the present invention comprises a memory cell including a read transistor and a write transistor stacked on an upper portion of the read transistor; a write word line connected to a gate terminal of the write transistor; a write bit line connected to a source terminal of the write transistor; a read word line connected to the source terminal of the read transistor; and a read bit line connected to a drain terminal of the read transistor; wherein the read transistor has a recessed channel structure, an insulating layer between a semiconductor layer of the read transistor and a gate electrode includes a ferroelectric material, and the semiconductor layer of the read transistor may include an oxide semiconductor material.

[0010] In one embodiment of the present invention, the write transistor may include a first drain electrode connected to a storage node connecting the write transistor and the read transistor; a first insulating layer on the first drain electrode; a first source electrode on the first insulating layer connected to the write bit line; a first semiconductor layer disposed inside a first trench formed in the first insulating layer and the first source electrode and formed along an inner wall of the first trench; a first gate electrode connected to the write word line and provided inside the trench of the first semiconductor layer; and a second insulating layer insulating the first gate electrode and the first semiconductor layer.

[0011] In one embodiment of the present invention, the read transistor includes a second source electrode connected to the read word line; a fourth insulating layer on the second source electrode; a second drain electrode on the fourth insulating layer connected to the read bit line; a second semiconductor layer disposed in a second trench formed in the fourth insulating layer and the second drain electrode and formed along an inner wall of the second trench; a second gate electrode connected to the first drain electrode of the write transistor through the storage node and provided within the trench of the second semiconductor layer; and a fifth insulating layer insulating the second gate electrode and the second semiconductor layer, wherein the fifth insulating layer may include a ferroelectric material.

[0012] In one embodiment of the present invention, the fifth insulating layer may include a Hf-based ferroelectric.

[0013] In one embodiment of the present invention, the fifth insulating layer may include at least one selected from the group consisting of HZO (Hafnium-Zirconium Oxide), HfLaO (Hafnium-Lanthanum Oxide), HfSiO (Hafnium-Si Oxide), and HfAlO (Hafnium-Aluminium Oxide).

[0014] In one embodiment of the present invention, the read transistor further includes a third gate electrode disposed between the second source electrode and the second drain electrode within the fourth insulating layer, and the third gate electrode can be electrically connected to the second source electrode.

[0015] In one embodiment of the present invention, the read transistor includes a semiconductor substrate having a recess; a second source electrode and a second drain electrode disposed on both sides of the recess on the semiconductor substrate and spaced apart from each other; a second semiconductor layer provided along an inner wall of the recess; a second gate electrode provided inside the recess of the second semiconductor layer and connected to the first drain electrode of the write transistor through the storage node; and an MFMI (Metal-ferroelectric-metal-interlayer) structure or an MFMFMI (Metal-ferroelectric-metal-ferroelectric-metal-interlayer) structure provided between the second gate electrode and the second semiconductor layer, wherein the MFMI structure or the MFMFMI structure has a structure in which a metal layer and a ferroelectric layer are repeatedly laminated, and an outermost ferroelectric layer of the MFMI structure or the MFMFMI structure can contact the second semiconductor layer.

[0016] In one embodiment of the present invention, the semiconductor substrate may include a silicon material.

[0017] In one embodiment of the present invention, the read transistor includes an oxide semiconductor substrate having a main portion and including an oxide semiconductor material; a second source electrode and a second drain electrode disposed on both sides of the main portion on the semiconductor substrate and spaced apart from each other; a second semiconductor layer provided along an inner wall of the main portion; a second gate electrode connected to the first drain electrode of the write transistor through the storage node and provided inside the main portion of the second semiconductor layer; and a fifth insulating layer insulating the second gate electrode and the second semiconductor layer, wherein the fifth insulating layer may include a ferroelectric material.

[0018] In one embodiment of the present invention, the read transistor includes a second source electrode connected to the read word line; a second drain electrode connected to the read bit line and spaced apart from the second source electrode; a second semiconductor layer disposed on the second source electrode and the second drain electrode, and having both ends connected to the second source electrode and the second drain electrode, respectively; a fifth insulating layer provided in a form that covers the second source electrode, the second drain electrode, and the second semiconductor layer; and a second gate electrode connected to the first drain electrode of the write transistor through the storage node and provided in a form that covers the fifth insulating layer, wherein the fifth insulating layer may include a ferroelectric material.

[0019] In one embodiment of the present invention, the semiconductor layer of the read transistor includes an amorphous oxide semiconductor material, and the amorphous oxide semiconductor material may be at least one selected from the group consisting of ITZO (Indium-Tin-Zinc Oxide), IGZO (Indium-Gallium-Zinc Oxide), InO (Indium Oxide), and ZnO (Zinc Oxide).

[0020] In one embodiment of the present invention, during a write operation, a voltage applied through the write transistor is applied to the gate of the read transistor to form a ferroelectric polarization in the insulating layer, and during a read operation, a negative voltage is applied to the gate of the write transistor to turn off the write transistor, and then a voltage is applied to the drain terminal of the read transistor to read the current of the read bit line according to the formed polarization state, thereby allowing stored data to be read.

[0021] In one embodiment of the present invention, by maintaining the potential of the storage node shared by the write transistor and the read transistor at 0 V, leakage current in the storage node can be suppressed, data loss can be reduced, and thus data retention time can be increased.

[0022] In one embodiment of the present invention, after the ferroelectric polarization is formed during the write operation, a predetermined read voltage can be transmitted to the read transistor through the write transistor to maintain the potential of the storage node at 0 V.

[0023] In one embodiment of the present invention, the storage node is not used as a charge storage for storing the data, but data is stored by a polarization state formed in the insulating layer of the read transistor, so that data loss due to charge inflow or outflow into the storage node can be prevented.

[0024] A three-dimensional stacked nonvolatile memory device according to one aspect of the present invention comprises a memory cell including a plurality of insulating films and a plurality of metal films, and a read transistor and a write transistor spaced apart from each other on a plane by a through hole penetrating the plurality of insulating films and the plurality of metal films; a write word line connected to a gate terminal of the write transistor; a write bit line connected to a source terminal of the write transistor; a read word line connected to a source terminal of the read transistor; And a read bit line connected to the drain terminal of the read transistor; and the write transistor is provided on one side of the through hole and includes a first source electrode, a first drain electrode, a first gate electrode, and a first semiconductor layer, and a second insulating layer is provided between the first gate electrode and the first semiconductor layer, the read transistor is provided on the other side of the through hole and includes a second source electrode, a second drain electrode, a second gate electrode, and a second semiconductor layer, and a fifth insulating layer is provided between the second gate electrode and the second semiconductor layer, the second source electrode is provided on the lowest metal layer among the plurality of metal layers, the first source electrode and the second gate electrode are provided on the metal layer above the second source electrode, the first gate electrode is provided on the metal layer above the first source electrode, the second drain electrode is provided on the metal layer above the first gate electrode, the first drain electrode is provided on the metal layer above the second drain electrode, and the second insulating layer and the fifth insulating layer are provided on the first The semiconductor layer and the second semiconductor layer are provided parallel to each other, and the fifth insulating layer may include a ferroelectric material.

[0025] The three-dimensional stacked non-volatile memory device according to the present invention has a 2T0C structure and utilizes a ferroelectric material to enable low power, high density, and non-destructive operation. In particular, the three-dimensional stacked non-volatile memory device according to the present invention has a long retention time (RT) unlike a typical DRAM, and thus has lower power consumption, and thus, unlike a typical DRAM, low power, high efficiency operation is possible.

[0026] In addition, the three-dimensional stacked non-volatile memory device according to the present invention does not cause destruction of information because the physical voltage application directions of the read line and the write line do not overlap, so non-destructive operation is possible, unlike a general DRAM.

[0027] In addition, the three-dimensional stacked non-volatile memory device according to the present invention can achieve a long data retention time by utilizing the characteristics of low leakage current and the non-volatile characteristics of ferroelectric through a VSN = 0V driving method.

[0028] FIG. 1 is a drawing for explaining an electronic device to which a three-dimensional stacked non-volatile memory element according to one embodiment of the present invention is applied.

[0029] FIG. 2 is a drawing for explaining the three-dimensional stacked non-volatile memory element illustrated in FIG. 1.

[0030] FIG. 3 is a circuit diagram for explaining the FeDRAM of the 2T0C structure shown in FIG. 2.

[0031] Figure 4 is a cross-sectional diagram illustrating a FeDRAM with a 2T0C structure.

[0032] Figure 5 is a circuit diagram illustrating another example of a three-dimensional stacked non-volatile memory device.

[0033] FIG. 6 is a drawing for explaining the three-dimensional stacked non-volatile memory element illustrated in FIG. 5.

[0034] FIG. 7 is a drawing for explaining a three-dimensional stacked non-volatile memory device according to one embodiment of the present invention.

[0035] FIG. 8 is a drawing for explaining a three-dimensional stacked non-volatile memory device according to one embodiment of the present invention.

[0036] FIG. 9 is a drawing for explaining a three-dimensional stacked non-volatile memory device according to one embodiment of the present invention.

[0037] FIG. 10 is a drawing for explaining a three-dimensional stacked non-volatile memory device according to one embodiment of the present invention.

[0038] FIGS. 11A and 11B illustrate a write / read operation scheme of a three-dimensional stacked non-volatile memory device according to one embodiment of the present invention.

[0039] Figures 12a and 12b are V in Figures 11a and 11b SN = This is a drawing to explain the advantages that can be obtained when driving at 0V.

[0040] It is to be understood that the attached drawings are provided for reference only to help understand the technical concept of the present invention, and the scope of the present invention is not limited thereby.

[0041] The purpose, specific advantages, and novel features of the present invention will become more apparent from the following detailed description and preferred embodiments, taken in conjunction with the accompanying drawings. In this specification, when reference numerals are assigned to components in each drawing, it should be noted that, where possible, identical components are assigned the same reference numerals even if they appear in different drawings. Furthermore, in describing the present invention, a detailed description of a related known technology will be omitted if it is determined that it may unnecessarily obscure the gist of the present invention.

[0042] In addition, the attached drawings are only intended to facilitate easy understanding of the embodiments disclosed in this specification, and the technical ideas disclosed in this specification are not limited by the attached drawings, and should be understood to include all modifications, equivalents, or substitutes included in the spirit and technical scope of the present invention.

[0043] Additionally, terms including ordinal numbers, such as first, second, etc., may be used to describe various components, but the components are not limited by the terms. The terms are used only to distinguish one component from another.

[0044]

[0045] In a preferred embodiment of the present invention, a three-dimensional stacked non-volatile memory device having a 2T0C structure is proposed and described.

[0046] A three-dimensional stacked non-volatile memory device according to a preferred embodiment of the present invention has a 2T0C structure using a ferroelectric material instead of a capacitor of a general DRAM, and since the physical voltage application directions of the read line and the write line do not overlap, information is not destroyed, enabling non-destructive operation.

[0047] A three-dimensional stacked non-volatile memory device according to a preferred embodiment of the present invention utilizes a three-dimensional vertical structure 2T0C-FeDRAM in which a FeFET (Ferroelectric FET) is placed at the bottom and an FET is placed at the top, thereby achieving a 4F 2 It can achieve very high integration and low power consumption.

[0048]

[0049] Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the attached drawings.

[0050] FIG. 1 is a diagram for explaining an electronic device to which a three-dimensional stacked nonvolatile memory device according to an embodiment of the present invention is applied. FIG. 2 is a diagram for explaining the three-dimensional stacked nonvolatile memory device illustrated in FIG. 1. FIG. 3 is a circuit diagram for explaining a FeDRAM of a 2T0C structure illustrated in FIG. 2. FIG. 4 is a cross-sectional view for explaining a FeDRAM of a 2T0C structure. FIG. 5 is a circuit diagram for explaining another example of a three-dimensional stacked nonvolatile memory device. FIG. 6 is a diagram for explaining the three-dimensional stacked nonvolatile memory device illustrated in FIG. 5. In FIG. 6, the first insulating layer, the third insulating layer, the fourth insulating layer, and the sixth insulating layer, which correspond to interlayer insulating layers, are omitted and illustrated.

[0051] Referring to FIGS. 1 to 6, a three-dimensional stacked nonvolatile memory device according to an embodiment of the present invention can be applied to various electronic devices or memory devices. For example, as illustrated in FIG. 1, a three-dimensional stacked nonvolatile memory device according to an embodiment of the present invention can be applied to HBM-PIM (High Bandwidth Memory Processing In Memory).

[0052] A three-dimensional stacked non-volatile memory device according to one embodiment of the present invention can be implemented as a plurality of memory devices having a circuit of a 2T0C structure, as illustrated in FIGS. 2 to 6, and can be stacked three-dimensionally.

[0053] To explain this in more detail, as illustrated in FIGS. 3 and 5, each memory cell may have a 2T0C structure including a write transistor (Wtr) and a ferroelectric read transistor (Rtr). The write transistor (Wtr) may be a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET). The ferroelectric read transistor (Rtr) may be a Ferroelectric Field-Effect Transistor (FeFET). Instead of the capacitor used in the existing Si CMOS-based DRAM, it may be a FeDRAM (Ferroelectric DRAM) using a ferroelectric material. The shortcomings of the existing DRAM, which inevitably have a low retention time and a destructive operation method, are solved by implementing a non-destructive path, and a ferroelectric material, which theoretically has an infinite retention time, can be used. Additionally, the ferroelectric read transistor (Rtr) may be provided as a double-gate structure transistor having a back gate electrode in which a portion of the drain electrode or read word line (RWL) overlaps with the channel.

[0054] In addition, as illustrated in FIGS. 3 and 5, a write word line (WWL), a write bit line (WBL), a read word line (RWL), and a read bit line (RBL) may be connected to each transistor as metal lines. Specifically, the write word line (WWL) may be connected to a gate terminal of the write transistor (Wtr), and the write bit line (WBL) may be connected to a source terminal of the write transistor (Wtr). The read word line (RWL) may be connected to a source terminal of the ferroelectric read transistor (Rtr), and the read bit line (RBL) may be connected to a drain terminal of the ferroelectric read transistor (Rtr).

[0055] A write transistor (Wtr) and a ferroelectric read transistor (Rtr) may be connected to each other with a storage node (SN) therebetween. Specifically, a drain terminal of the write transistor (Wtr) may be connected to a gate terminal of the ferroelectric read transistor (Rtr) at the storage node (SN).

[0056] The 2T0C structure FeDRAM utilizes ferroelectric materials, which maintain polarization in the ground state below the Curie temperature, and can be applied as an insulating layer (Cox, Rtr) of the read transistor of the FeDRAM. Due to the ferroelectric material applied as this insulating layer, information of the 2T0C FeDRAM is stored in the read transistor, and once stored, the information can be expected to be preserved for about 10 years due to the characteristics of the ferroelectric material.

[0057] As a ferroelectric material, a Hf-based ferroelectric material can be applied. For example, at least one selected from the group consisting of HZO (Hafnium-Zirconium Oxide), HfLaO (Hafnium-Lanthanum Oxide), HfSiO (Hafnium-Si Oxide), and HfAlO (Hafnium-Aluminium Oxide) can be applied.

[0058] The channel layer of each transistor may include an oxide semiconductor. For example, the channel layer of each transistor may include amorphous ITZO (Indium-Tin-Zinc Oxide). ITZO has low leakage current and high mobility, making it an advantageous material for low-power operation. Meanwhile, in one embodiment of the present invention, it has been described as an example that the channel layer of each transistor includes ITZO, but the present invention is not limited thereto. For example, the channel layer, which is a semiconductor layer of each transistor, may include various amorphous oxide semiconductors such as IGZO (Indium-Gallium-Zinc Oxide), InO (Indium Oxide), and ZnO (Zinc Oxide).

[0059] In the 2T0C structure, the metal materials used for the write word line (WWL), write bit line (WBL), read bit line (RBL), and read word line (RWL) of the FeDRAM can also be applied with various conductive materials as needed.

[0060]

[0061] Below, the stacked structure of the three-dimensional stacked non-volatile memory device of the present invention is described with reference to FIGS. 4 and 6.

[0062] As illustrated in FIGS. 3 to 6, in the three-dimensional stacked non-volatile memory device of the present invention, a first source electrode (SE1) of a write transistor (Wtr) may be connected to a write bit line (WBL), and a first gate electrode (GE1) may be connected to a write word line (WWL). A second source electrode (SE2) of a read transistor (Rtr) may be connected to a read word line (RWL), and a second drain electrode (DE2) may be connected to a read bit line (RBL). A first drain electrode (DE1) of the write transistor (Wtr) and a second gate electrode (GE2) of the read transistor (Rtr) may be connected to each other through a storage node (SN; STORAGE NODE).

[0063] The write transistor (Wtr) and the ferroelectric read transistor (Rtr) may have a three-dimensionally stacked structure. For example, as illustrated in FIG. 4, the write transistor (Wtr) may have a structure in which the ferroelectric read transistor (Rtr) is stacked on top of the ferroelectric read transistor.

[0064] A write transistor (Wtr) on a ferroelectric read transistor (Rtr) may include a first drain electrode (DE1) connected to a storage node (SN), a first insulating layer (ILD1) on the first drain electrode (DE1), a first source electrode (SE1) on the first insulating layer (ILD1), a first semiconductor layer (SCL1) disposed in a trench formed in the first insulating layer (ILD1) and the first source electrode (SE1) and formed along an inner wall of the trench, a first gate electrode (GE1) provided inside the trench of the first semiconductor layer (SCL1), a second insulating layer (ILD2) insulating the first gate electrode (GE1) and the first semiconductor layer (SCL1), and a third insulating layer (ILD3) covering the write transistor (Wtr). That is, since the first semiconductor layer (SCL1) is placed in a trench formed in the first insulating layer (ILD1) and the first source electrode (SE1) and is formed along the inner wall of the trench, the write transistor (Wtr) can have a recessed channel structure.

[0065] Here, the second insulating layer (ILD2) that insulates the first gate electrode (GE1) and the first semiconductor layer (SCL1) may be provided in a form that surrounds the first gate electrode (GE1) inside the trench. The second insulating layer (ILD2) may include a high-k material such as Al2O3. Meanwhile, in one embodiment of the present invention, it has been described as an example that the second insulating layer (ILD2) includes Al2O3, but the present invention is not limited thereto. For example, the second insulating layer (ILD2) may include various high-k materials such as HfO2 and ZrO2.

[0066] Additionally, the first source electrode (SE1) may be connected to a write bit line (WBL), and the first gate electrode (GE1) may be connected to a write word line (WWL).

[0067] The ferroelectric read transistor (Rtr) may include a second source electrode (SE2) from the bottom, a fourth insulating layer (ILD4) on the second source electrode (SE2), a second drain electrode (DE2) on the fourth insulating layer (ILD4), a second semiconductor layer (SCL2) formed in a trench formed in the fourth insulating layer (ILD4) and the second drain electrode (DE2) and formed along an inner wall of the trench, a second gate electrode (GE2) provided inside the trench of the second semiconductor layer (SCL2), a fifth insulating layer (ILD5) that insulates the second gate electrode (GE2) and the second semiconductor layer (SCL2), and a sixth insulating layer (ILD6) that covers the ferroelectric read transistor (Rtr). That is, since the second semiconductor layer (SCL1) is placed in a trench formed in the fourth insulating layer (ILD4) and the second drain electrode (DE2) and is formed along the inner wall of the trench, the ferroelectric read transistor (Rtr) can have a recessed channel structure.

[0068] In one embodiment of the present invention, a third gate electrode (GE3) is provided in the vertical direction inside the fourth insulating layer (ILD4), for example, between the second source electrode (SE2) and the second drain electrode (DE2), and the third gate electrode (GE3) can be electrically connected to the second source electrode (SE2). That is, the third gate electrode (GE3) can perform a role similar to a top gate electrode in a transistor having a dual gate structure. That is, the ferroelectric read transistor (Rtr) can have a form having a back gate in a circuit. The ferroelectric read transistor (Rtr) can be a transistor having a double gate structure.

[0069] Additionally, the second gate electrode (GE2) can be connected to the first drain electrode (DE1) through a storage node (SN) provided in a via of the sixth insulating layer (ILD6).

[0070] The second source electrode (SE2) can be connected to a read word line (RWL), and the second drain electrode (DE2) can be connected to a read bit line (RBL).

[0071] In one embodiment of the present invention, the fifth insulating layer (ILD5) that insulates the second gate electrode (GE2) and the second semiconductor layer (SCL2) is provided in a form that surrounds the second gate electrode (GE2) inside the trench, and may include a ferroelectric material. Here, a Hf-based ferroelectric may be applied as the ferroelectric material. For example, at least one selected from the group consisting of HZO (Hafnium-Zirconium Oxide), HfLaO (Hafnium-Lanthanum Oxide), HfSiO (Hafnium-Si Oxide), and HfAlO (Hafnium-Aluminium Oxide) may be applied.

[0072] In one embodiment of the present invention, the first semiconductor layer (SCL1) and the second semiconductor layer (SCL2) may include an oxide semiconductor. For example, the first semiconductor layer (SCL1) and the second semiconductor layer (SCL2) may include at least one selected from the group consisting of indium-tin-zinc oxide (ITZO), indium-gallium-zinc oxide (IGZO), indium oxide (InO), and zinc oxide (ZnO).

[0073] In one embodiment of the present invention, the write transistor (Wtr) and the ferroelectric read transistor (Rtr) may both have a structure including a gate electrode disposed inside a trench, a semiconductor layer disposed along the trench shape and including an oxide semiconductor, a source electrode connected to both upper ends of the semiconductor layer, and a drain electrode connected to a lower portion of the semiconductor layer. That is, the write transistor (Wtr) and the ferroelectric read transistor (Rtr) may have a structure including two sub-transistors that are electrically connected to each other.

[0074] In the three-dimensional stacked non-volatile memory device according to one embodiment of the present invention as described above, the write transistor (Wtr) can store a voltage for writing circuit data and reading data. In addition, the ferroelectric read transistor (Rtr) may include a ferroelectric material in the fifth insulating layer (ILD5) that insulates the second semiconductor layer (SCL2) and the second gate electrode (GE2). Therefore, the ferroelectric read transistor (Rtr) can read data stored in a polarized form.

[0075] A three-dimensional stacked non-volatile memory device having a three-dimensionally stacked structure of a write transistor (Wtr) and a ferroelectric read transistor (Rtr) as described above is 4F 2 It can achieve high integration and low power operation.

[0076] In addition, the read / write operation of the three-dimensional stacked non-volatile memory device according to one embodiment of the present invention is programmable depending on the degree of external voltage application of the polarization of the ferroelectric material. Here, the programmability of the ferroelectric material may be an effect that appears depending on the difference in the coercive field of each domain of the poly-crystalline ferroelectric material. By utilizing this, the operating voltage can be changed depending on the magnitude of the voltage, and by utilizing the characteristic of the polarization being maintained depending on the non-volatility, multi-bit data can be stored.

[0077] In addition, as described above, by introducing a ferroelectric material into the fifth insulating layer (ILD5) that insulates the second gate electrode (GE2) of the ferroelectric read transistor (Rtr) and the second semiconductor layer (SCL2) of the three-dimensional stacked nonvolatile memory device according to an embodiment of the present invention, analog characteristics of the memory can be implemented. Therefore, the three-dimensional stacked nonvolatile memory device according to an embodiment of the present invention is capable of a PIM (Process in memory) operation utilizing the analog characteristics described above, and can be applied to the next-generation memory device of HBM (High bandwidth memory).

[0078] As described above, the three-dimensional stacked non-volatile memory device according to one embodiment of the present invention can store the data read voltage applied to the storage node (SN) in the form of a charge. After measuring the current flowing through the read bit line (RBL), the voltage stored in the storage node (SN) is traced back, and the time it takes for the voltage stored in the storage node (SN) to decrease can be measured to evaluate the data retention time.

[0079] The write transistor (Wtr) and the ferroelectric read transistor (Rtr) can be operated by applying a voltage to the first gate electrode (GE1) higher than the operating voltage of the write transistor (Wtr) and the ferroelectric read transistor (Rtr). In addition, in the case of the write transistor (Wtr) that stores voltage, the length of the first semiconductor layer (SCL1) can be determined according to the height of the first gate electrode (GE1), and in the case of the ferroelectric read transistor (Rtr), the length of the second semiconductor layer (SCL2) can be determined according to the height of the second gate electrode (GE2). The performance of the three-dimensional stacked non-volatile memory device can be determined according to the lengths of the first semiconductor layer (SCL1) and the second semiconductor layer (SCL2).

[0080]

[0081] FIG. 7 is a drawing for explaining a three-dimensional stacked non-volatile memory device according to one embodiment of the present invention.

[0082] Referring to FIG. 7, a three-dimensional stacked nonvolatile memory device according to an embodiment of the present invention may have a structure similar to the three-dimensional stacked nonvolatile memory devices illustrated in FIGS. 1 to 6. However, the structure of a ferroelectric read transistor (Rtr) of the three-dimensional stacked nonvolatile memory device according to an embodiment of the present invention may be partially different from the ferroelectric read transistor (Rtr) illustrated in FIGS. 1 to 6. For example, the ferroelectric read transistor (Rtr) of the three-dimensional stacked nonvolatile memory device according to an embodiment of the present invention may have a recessed channel structure based on a semiconductor substrate (SUB1).

[0083] To explain this in more detail, the ferroelectric read transistor (Rtr) may include a semiconductor substrate (SUB1) having a main portion, a second source electrode (SE2) and a second drain electrode (DE2) arranged on both sides of the main portion on the semiconductor substrate (SUB1) and spaced apart from each other, a second semiconductor layer (SCL2) provided along an inner wall of the main portion, a second gate electrode (GE2) provided inside the second semiconductor layer (SCL2), and an MFMI (metal-ferroelectric-metal-ferroelectric-metal-interlayer) or MFMFMI (Metal-ferroelectric-metal-ferroelectric-metal-interlayer) structure (MFMFMI) provided between the second gate electrode (GE2) and the second semiconductor layer (SCL2). FIG. 7 illustrates the MFMFMFMI (Metal-ferroelectric-metal-ferroelectric-metal-interlayer) structure (MFMFMFMI) as an example.

[0084] In one embodiment of the present invention, the semiconductor substrate (SUB1) may be a silicon substrate. For example, the semiconductor substrate (SUB1) may be a bulk silicon substrate. In addition, the recessed region of the semiconductor substrate (SUB1) may be formed by depositing a metal material for forming the second source electrode (SE2) and the second drain electrode (DE2) on the semiconductor substrate (SUB1) and then performing an etching process. Meanwhile, in one embodiment of the present invention, the formation of the recessed region by depositing the metal material on the semiconductor substrate (SUB1) has been described as an example, but is not limited thereto. For example, after etching a region of the semiconductor substrate (SUB1) to form the recessed region, the second source electrode (SE2) and the second drain electrode (DE2) may be formed by depositing and patterning the metal material.

[0085] In one embodiment of the present invention, the MFMFMI structure (MFMFMI) is a structure in which a metal layer (MT) and a ferroelectric layer (FeL) are repeatedly laminated, and the second gate electrode (GE2) may have a form in which a plurality of metal layers are laminated by the metal layer (MT) of the MFMFMI structure (MFMFMI). In addition, in the MFMFMI structure (MFMFMI), the outermost ferroelectric layer (FeL) may be in contact with the second semiconductor layer (SCL2). Accordingly, the ferroelectric read transistor (Rtr) of the three-dimensional stacked non-volatile memory device according to one embodiment of the present invention can increase the memory window (MW).

[0086] In the MFMFMI structure (MFMFMI), SiO2, Al2O3 in the metal layer (MT) , When applying a dielectric layer containing dielectric materials such as HfO2 and ZrO2, memory window performance can be improved. Furthermore, in the MFMFMI structure (MFMFMI), memory window performance can be maximized by controlling the effective oxide thickness (EOT) of the ferroelectric layer (FeL).

[0087] In one embodiment of the present invention, the second semiconductor layer (SCL2) is provided as a recessed channel structure formed along the inner wall of the main portion of the semiconductor substrate (SUB1), and although the area of ​​the second semiconductor layer (SCL2) is reduced, the length of the channel can be increased. Therefore, the ferroelectric read transistor (Rtr) of the three-dimensional stacked non-volatile memory device according to one embodiment of the present invention can obtain a single-channel effect.

[0088]

[0089] FIG. 8 is a drawing for explaining a three-dimensional stacked non-volatile memory device according to one embodiment of the present invention.

[0090] Referring to FIG. 8, a three-dimensional stacked nonvolatile memory device according to an embodiment of the present invention may have a structure similar to the three-dimensional stacked nonvolatile memory devices illustrated in FIGS. 1 to 7. However, the structure of a ferroelectric read transistor (Rtr) of the three-dimensional stacked nonvolatile memory device according to an embodiment of the present invention may be partially different from the ferroelectric read transistor (Rtr) illustrated in FIGS. 1 to 7.

[0091] For example, a ferroelectric read transistor (Rtr) of a three-dimensional stacked non-volatile memory device according to one embodiment of the present invention may have a recessed channel structure based on an oxide semiconductor substrate (SUB2).

[0092] To explain this in more detail, the ferroelectric read transistor (Rtr) may include an oxide semiconductor substrate (SUB2) having a main portion, a second source electrode (SE2) and a second drain electrode (DE2) arranged on both sides of the main portion on the oxide semiconductor substrate (SUB2) and spaced apart from each other, a second semiconductor layer (SCL2) provided along an inner wall of the main portion, a second gate electrode (GE2) provided inside the second semiconductor layer (SCL2), and a fifth insulating layer (ILD5) provided between the second gate electrode (GE2) and the second semiconductor layer (SCL2).

[0093] In one embodiment of the present invention, the fifth insulating layer (ILD5) that insulates the second gate electrode (GE2) and the second semiconductor layer (SCL2) is provided in a form that surrounds the second gate electrode (GE2) inside the main body, and may include a ferroelectric material. Here, a Hf-based ferroelectric may be applied as the ferroelectric material. For example, at least one selected from the group consisting of HZO (Hafnium-Zirconium Oxide), HfLaO (Hafnium-Lanthanum Oxide), HfSiO (Hafnium-Si Oxide), and HfAlO (Hafnium-Aluminium Oxide) may be applied.

[0094] In one embodiment of the present invention, the oxide semiconductor substrate (SUB2) may be a semiconductor substrate including an oxide semiconductor material. In addition, the recessed region of the oxide semiconductor substrate (SUB2) may be formed by depositing a metal material for forming a second source electrode (SE2) and a second drain electrode (DE2) on the oxide semiconductor substrate (SUB2) and then performing an etching process. Meanwhile, in one embodiment of the present invention, the formation of the recessed region by depositing a metal material on the oxide semiconductor substrate (SUB2) has been described as an example, but is not limited thereto. For example, after etching a region of the oxide semiconductor substrate (SUB2) to form the recessed region, the second source electrode (SE2) and the second drain electrode (DE2) may be formed by depositing a metal material and patterning the metal material.

[0095] In one embodiment of the present invention, the second semiconductor layer (SCL2) is provided as a recessed channel structure formed along the inner wall of the main portion of the oxide semiconductor substrate (SUB2), and although the area of ​​the second semiconductor layer (SCL2) is reduced, the length of the channel can be increased. Therefore, the ferroelectric read transistor (Rtr) of the three-dimensional stacked non-volatile memory device according to one embodiment of the present invention can obtain a single-channel effect.

[0096] In one embodiment of the present invention, the ferroelectric read transistor (Rtr) can be manufactured through a back-end of line (BEOL) process. Accordingly, the ferroelectric read transistor (Rtr) of the three-dimensional stacked non-volatile memory device according to one embodiment of the present invention can have a large memory window (MW).

[0097] In one embodiment of the present invention, since the ferroelectric read transistor (Rtr) has a recessed channel structure formed on an oxide semiconductor substrate (SUB2), unlike the recessed channel structure formed on a semiconductor substrate (SUB1) including a silicon material as illustrated in FIG. 7, an interface layer between a fifth insulating layer (ILD5) including a ferroelectric material and a second semiconductor layer (SCL2) including an oxide semiconductor material can be omitted. Therefore, the ferroelectric read transistor (Rtr) according to one embodiment of the present invention can prevent problems of retention and deterioration of memory window performance due to charge trapping.

[0098]

[0099] FIG. 9 is a drawing for explaining a three-dimensional stacked non-volatile memory device according to one embodiment of the present invention.

[0100] Referring to FIG. 9, a three-dimensional stacked nonvolatile memory device according to an embodiment of the present invention may include a write transistor (Wtr) and a ferroelectric read transistor (Rtr), like the three-dimensional stacked nonvolatile memory devices illustrated in FIGS. 1 to 8.

[0101] However, the three-dimensional stacked non-volatile memory device according to an embodiment of the present invention illustrated in FIG. 9 may have a structure in which the write transistor (Wtr) and the ferroelectric read transistor (Rtr) are not vertically stacked, but are spaced apart from each other on a plane, for example, spaced apart from each other on the left and right. That is, on a plane, the write transistor (Wtr) and the ferroelectric read transistor (Rtr) may be spaced apart from each other.

[0102] To explain this in more detail, a write transistor (Wtr) of a three-dimensional stacked non-volatile memory device according to one embodiment of the invention is provided on one side of a through hole, and includes a first source electrode (SE1), a first drain electrode (DE1), a first gate electrode (GE1), and a first semiconductor layer (SCL1), and a second insulating layer (ILD2) may be provided between the first gate electrode (GE1) and the first semiconductor layer (SCL1).

[0103] A ferroelectric read transistor (Rtr) is provided on the other side of the through hole and includes a second source electrode (SE2), a second drain electrode (DE2), a second gate electrode (GE2), and a second semiconductor layer (SCL2), and a fifth insulating layer (ILD5) may be provided between the second gate electrode (GE2) and the second semiconductor layer (SCL2).

[0104] In addition, a three-dimensional stacked non-volatile memory device according to an embodiment of the present invention may have a structure in which a plurality of insulating layers (ILD) and a plurality of metal layers are alternately stacked. A through hole (TH) may be provided at the center of the structure in which a plurality of insulating layers (ILD) and a plurality of metal layers are alternately stacked. That is, a write transistor (Wtr) and a ferroelectric read transistor (Rtr) may be divided into left and right sides by the through hole (TH). In addition, a first semiconductor layer (SCL1) may be provided on the left side of the inner wall of the through hole (TH), and a second semiconductor layer (SCL2) may be provided on the right side of the inner wall of the through hole (TH).

[0105] The second source electrode (SE2) may be provided in the lowest metal layer among the metal layers described above, the first source electrode (SE1) may be provided in the left metal layer among the metal layers above the second source electrode (SE2), the second gate electrode (GE2) may be provided in the right metal layer among the metal layers above the second source electrode (SE2), the first gate electrode (GE1) may be provided in the left metal layer among the metal layers above the first source electrode (SE1), the second drain electrode (DE2) may be provided in the right metal layer among the metal layers above the first gate electrode (GE1), and the first drain electrode (DE1) may be provided in the left metal layer among the metal layers above the second drain electrode (DE2).

[0106] Additionally, a second insulating layer (ILD2) may be provided between the first gate electrode (GE1) and the first semiconductor layer (SCL1), and a fifth insulating layer (ILD5) may be provided between the second gate electrode (GE2) and the second semiconductor layer (SCL2). Here, the second insulating layer (ILD2) and the fifth insulating layer (ILD5) may be provided parallel to the first semiconductor layer (SCL1) and the second semiconductor layer (SCL2).

[0107] Additionally, the second insulating layer (ILD2) may include at least one selected from the group consisting of SiO2, Al2O3, HfO2, and ZrO2.

[0108] The fifth insulating layer (ILD5) may include a ferroelectric material. As the ferroelectric material, a Hf-based ferroelectric may be applied. For example, the fifth insulating layer (ILD5) may include at least one selected from the group consisting of HZO (Hafnium-Zirconium Oxide), HfLaO (Hafnium-Lanthanum Oxide), HfSiO (Hafnium-Si Oxide), and HfAlO (Hafnium-Aluminium Oxide).

[0109] According to an embodiment of the present invention as described above, a three-dimensional stacked non-volatile memory device can be manufactured by alternately stacking a plurality of insulating layers (ILD) and a plurality of metal layers, etching is performed in a vertical direction to form a through hole (TH), forming a second insulating layer (ILD2) and a fifth insulating layer (ILD5) on a portion of the inner wall of the through hole (TH), and then forming a first semiconductor layer (SCL1) and a second semiconductor layer (SCL2) along the inner wall of the through hole (TH), thereby manufacturing a write transistor (Wtr) and a ferroelectric read transistor (Rtr).

[0110] Therefore, the three-dimensional stacked non-volatile memory device according to one embodiment of the present invention can reduce the number of masks by reducing the number of etching processes.

[0111] In addition, in a three-dimensional stacked non-volatile memory device according to one embodiment of the present invention, since a first semiconductor layer (SCL1) and a second semiconductor layer (SCL2) are formed along the inner wall of a through hole (TH), the length of the channel can be determined according to the thickness of a structure in which a plurality of insulating layers (ILDs) and a plurality of metal layers are alternately stacked.

[0112]

[0113] FIG. 10 is a drawing for explaining a three-dimensional stacked non-volatile memory device according to one embodiment of the present invention.

[0114] Referring to FIG. 10, a three-dimensional stacked nonvolatile memory device according to an embodiment of the present invention may include a three-dimensionally stacked write transistor (Wtr) and a ferroelectric read transistor (Rtr) similar to the three-dimensional stacked nonvolatile memory devices illustrated in FIGS. 1 to 8.

[0115] However, the structure of the ferroelectric read transistor (Rtr) of the three-dimensional stacked non-volatile memory device according to one embodiment of the present invention may be partially different from the ferroelectric read transistor (Rtr) illustrated in FIGS. 1 to 8.

[0116] To explain this in more detail, the ferroelectric read transistor (Rtr) may include a second source electrode (SE2) and a second drain electrode (DE2) which are arranged at the bottom and spaced apart from each other, a second semiconductor layer (SCL2) which is provided on the second source electrode (SE2) and the second drain electrode (DE2) and has both ends connected to the second source electrode (SE2) and the second drain electrode (DE2), a fifth insulating layer (ILD5) which is provided in a form that covers the second source electrode (SE2), the second drain electrode (DE2), and the second semiconductor layer (SCL2), and a second gate electrode (GE2) which is provided in a form that covers the fifth insulating layer (ILD5).

[0117] In one embodiment of the present invention, the fifth insulating layer (ILD5) that is provided in a form that covers the second semiconductor layer (SCL2) and insulates the second gate electrode (GE2) and the second semiconductor layer (SCL2) may include a ferroelectric material. For example, the fifth insulating layer (ILD5) may include at least one selected from the group consisting of HZO (Hafnium-Zirconium Oxide), HfLaO (Hafnium-Lanthanum Oxide), HfSiO (Hafnium-Si Oxide), and HfAlO (Hafnium-Aluminium Oxide).

[0118] The second gate electrode (GE2) can be directly connected to the first drain electrode (DE1) of the write transistor (Wtr) from above. That is, the three-dimensional stacked non-volatile memory device according to an embodiment of the present invention illustrated in FIG. 10 has a structure in which a storage node is omitted, and a portion of the second gate electrode (GE2) or the first drain electrode (DE1) can function as a storage node.

[0119] The FinFET process can be used to manufacture the ferroelectric read transistor (Rtr) of the three-dimensional stacked nonvolatile memory device according to one embodiment of the present invention as described above. Therefore, a miniaturization process of the three-dimensional stacked nonvolatile memory device is possible.

[0120]

[0121] Figures 11a and 11b illustrate a write / read operation scheme of a three-dimensional stacked non-volatile memory device according to one embodiment. This can be applied to various three-dimensional stacked non-volatile memory devices including the write transistor (Wtr) and the ferroelectric read transistor (Rtr) described above with reference to Figures 3 and 4. For convenience of explanation below, the ferroelectric read transistor may be referred to as a read FeFET or more simply as an FeFET.

[0122] Referring to FIGS. 11a and 11b, for the write operation (Program step), a voltage higher than the operating voltage is applied to the gate of the write transistor to turn the write transistor on (WWL = 2V). Next, the drain voltage of the write transistor is adjusted to control the voltage applied to the gate of the read FeFET (WBL = 6.1V to 7.9V). At this time, data writing is performed, thereby applying a voltage to the ferroelectric and storing the polarization. Here, the Vth of the FeFET can be determined.

[0123] Next, write operation - V read Looking at the Write phase, the storage node voltage (V SN ) to the FeFET, the read voltage is applied to the write transistor drain (WWL = 2 V, WBL = 0 V). That is, the read voltage (V read ) is applied to the drain of the write transistor, so that V can be used as a reference value in subsequent read operations. readis transmitted.

[0124] And, looking at the read operation, a negative voltage is applied to the gate of the write transistor to turn it off (WWL = -2V), and then a voltage is applied to the drain of the read FeFET to read the drain current. That is, when a voltage is applied to the drain of the read transistor, data is read through the difference in the drain current (I_RBL) according to the stored polarization state. At this time, V SN = Note that the read is performed while the voltage is maintained at 0V.

[0125] Figures 12a and 12b are V in Figures 11a and 11b SN = This is a drawing to explain the advantages that can be obtained when driving at 0V.

[0126] First, as illustrated in Figure 12a, the existing 2T0C DRAM stores charges in a storage node (SN) during the process of storing data, and thus has a limit to the data retention time due to data loss caused by leakage current of the read / write transistor.

[0127] In comparison, as shown in FIG. 12b, a 2T0C FeDRAM according to one embodiment stores data by polarization of a ferroelectric and V SN = By maintaining it at 0V, the influence of charge loss in the storage node (SN) is reduced, and leakage current can be minimized as there is no voltage difference between the source / drain of the write transistor.

[0128] That is, the leakage current can be reduced and the data retention time can be increased through the 2T0C FeDRAM driving method according to one embodiment.

[0129] Continuing with reference to FIGS. 12a and 12b, the advantages of the 2T0C FeDRAM according to one embodiment compared to the conventional 2T0C DRAM are as follows: (1) The FeFET read Tr is V after voltage is applied. thYou can adjust and save V SN =0 condition can also work, (2) W tr Non-overlapping I due to reduced leakage current RBL characteristics can be achieved, which leads to longer retention time and various multi-bit advantages. (3) V caused by reduced stress stability th Additional I due to change RBL To mitigate the degradation, an optimized hetero a-ITZO / a-IGZO structure (where a is morphous) with excellent stress stability is applied, which improves the retention time while improving the I RBL It can greatly reduce degradation.

[0130] [Revised 23.07.2025 under Rule 91] Figure 13 shows a comparison of a 2T0C FeDRAM according to one embodiment with conventional DRAMs.

[0131] [Correction pursuant to Rule 91, July 23, 2025][Deleted]

[0132] [Correction under Rule 91 23.07.2025] As shown in Figure 13, V SN = 0V setting prevents charge leakage from Wtr, allowing data to be retained for a long time. A retention time of more than 2000 seconds has been experimentally confirmed, and theoretically, the possibility of almost infinite retention is confirmed. Since the leakage current of Wtr is almost zero, the I flowing during reading RBL This remains constant for a long time. This provides the basis for maintaining a clear distinction between each state in a multi-level state (e.g., 19 states). I RBL Since this is maintained stably, the read margin is widened and interference between states is reduced when implementing a multi-level cell (MCL), enabling precise multi-bit operations.

[0133]

[0134] The present invention is not limited to the embodiments described above, and may include new embodiments that combine at least two of the above embodiments or combine at least one of the above embodiments with a known technology.

[0135] Although the present invention has been described in detail through specific examples, this is intended to specifically explain the present invention, and the present invention is not limited thereto, and it will be apparent that modifications and improvements can be made by those skilled in the art within the technical spirit of the present invention.

[0136] All simple modifications or changes of the present invention fall within the scope of the present invention, and the specific scope of protection of the present invention will be made clear by the appended claims.

[0137] [Explanation of symbols]

[0138] WWL: Write Wordline

[0139] WBL: Write Bitline

[0140] RWL: Read Wordline

[0141] RBL: Read Bitline

[0142] Wtr: Write Transistor

[0143] SE1: First source electrode

[0144] DE1: First drain electrode

[0145] GE1: First gate electrode

[0146] SCL1: First semiconductor layer

[0147] Rtr: Ferroelectric Read Transistor

[0148] SE2: Second source electrode

[0149] DE2: Second drain electrode

[0150] GE2: Second gate electrode

[0151] SCL2: Second semiconductor layer

[0152] SN: Storage Node

[0153] GE3: Third gate electrode

[0154] ILD1: First insulation layer

[0155] ILD2: Second insulation layer

[0156] ILD3: Third insulation layer

[0157] ILD4: Fourth insulation layer

[0158] ILD5: Fifth insulation layer

Claims

1. A memory cell including a read transistor and a write transistor stacked on top of the read transistor; A write word line connected to the gate terminal of the above write transistor; A write bit line connected to the source terminal of the above write transistor; a read word line connected to the source terminal of the read transistor; and a read bit line connected to the drain terminal of the read transistor; The above read transistor has a recessed channel structure, and the insulating layer between the semiconductor layer and the gate electrode of the read transistor includes a ferroelectric material. A three-dimensional stacked non-volatile memory device in which the semiconductor layer of the above read transistor includes an oxide semiconductor material.

2. In paragraph 1, The above write transistor is A first drain electrode connected to a storage node connecting the write transistor and the read transistor; A first insulating layer on the first drain electrode; A first source electrode on the first insulating layer connected to the write bit line; A first semiconductor layer disposed inside a first trench formed in the first insulating layer and the first source electrode and formed along an inner wall of the first trench; A first gate electrode connected to the above write word line and provided inside a trench of the first semiconductor layer; and A three-dimensional stacked non-volatile memory device comprising a second insulating layer that insulates the first gate electrode and the first semiconductor layer.

3. In paragraph 2, The above read transistor is A second source electrode connected to the above read word line; A fourth insulating layer on the second source electrode; A second drain electrode on the fourth insulating layer connected to the read bit line; A second semiconductor layer disposed within a second trench formed in the fourth insulating layer and the second drain electrode and formed along an inner wall of the second trench; A second gate electrode connected to the first drain electrode of the write transistor through the storage node and provided inside a trench of the second semiconductor layer; and A fifth insulating layer that insulates the second gate electrode and the second semiconductor layer, The above fifth insulating layer is a three-dimensional layered non-volatile memory device including a ferroelectric material.

4. In paragraph 3, The above fifth insulating layer is a three-dimensional layered non-volatile memory device including a Hf-based ferroelectric.

5. In paragraph 4, A three-dimensional stacked non-volatile memory device, wherein the fifth insulating layer includes at least one selected from the group consisting of HZO (Hafnium-Zirconium Oxide), HfLaO (Hafnium-Lanthanum Oxide), HfSiO (Hafnium-Si Oxide), and HfAlO (Hafnium-Aluminium Oxide).

6. In paragraph 3, The above read transistor is Further comprising a third gate electrode disposed between the second source electrode and the second drain electrode within the fourth insulating layer; A three-dimensional stacked non-volatile memory element in which the third gate electrode is electrically connected to the second source electrode.

7. In paragraph 2, The above read transistor is A semiconductor substrate having a main body; A second source electrode and a second drain electrode are arranged on both sides of the semiconductor substrate and spaced apart from each other; A second semiconductor layer provided along the inner wall of the above-mentioned portion; A second gate electrode connected to the first drain electrode of the write transistor through the storage node and provided inside the main portion of the second semiconductor layer; and It includes an MFMI (Metal-ferroelectric-metal-interlayer) structure or an MFMFMI (Metal-ferroelectric-metal-ferroelectric-metal-interlayer) structure provided between the second gate electrode and the second semiconductor layer, A three-dimensional stacked non-volatile memory device in which the MFMI structure or the MFMFMI structure has a structure in which a metal layer and a ferroelectric layer are repeatedly stacked, and the outermost ferroelectric layer of the MFMI structure or the MFMFMI structure is in contact with the second semiconductor layer.

8. In paragraph 7, The above semiconductor substrate is a three-dimensional layered non-volatile memory device including a silicon material.

9. In paragraph 2, The above read transistor is An oxide semiconductor substrate having a substrate and including an oxide semiconductor material; A second source electrode and a second drain electrode are arranged on both sides of the semiconductor substrate and spaced apart from each other; A second semiconductor layer provided along the inner wall of the above-mentioned portion; A second gate electrode connected to the first drain electrode of the write transistor through the storage node and provided inside the main portion of the second semiconductor layer; and A fifth insulating layer that insulates the second gate electrode and the second semiconductor layer, The above fifth insulating layer is a three-dimensional layered non-volatile memory device including a ferroelectric material.

10. In paragraph 2, The above read transistor is A second source electrode connected to the above read word line; A second drain electrode connected to the read bit line and spaced apart from the second source electrode; A second semiconductor layer disposed on the second source electrode and the second drain electrode, and having both ends connected to the second source electrode and the second drain electrode, respectively; A fifth insulating layer provided in a form that covers the second source electrode, the second drain electrode, and the second semiconductor layer; and A second gate electrode is connected to the first drain electrode of the write transistor through the storage node and is provided in a form that covers the fifth insulating layer. The above fifth insulating layer is a three-dimensional layered non-volatile memory device including a ferroelectric material.

11. In paragraph 1, The semiconductor layer of the above read transistor includes an amorphous oxide semiconductor material, A three-dimensional layered non-volatile memory device, wherein the amorphous oxide semiconductor material is at least one selected from the group consisting of ITZO (Indium-Tin-Zinc Oxide), IGZO (Indium-Gallium-Zinc Oxide), InO (Indium Oxide), and ZnO (Zinc Oxide).

12. In paragraph 1, During a write operation, a voltage applied through the write transistor is applied to the gate of the read transistor, thereby forming a ferroelectric polarization in the insulating layer. A three-dimensional stacked non-volatile memory device that reads stored data by applying a voltage to the drain terminal of the read transistor to turn off the write transistor by applying a negative voltage to the gate of the write transistor during a read operation, thereby reading the current of the read bit line according to the formed polarization state.

13. In paragraph 12, A three-dimensional stacked non-volatile memory device that suppresses leakage current in the storage node, reduces data loss, and thus increases data retention time by maintaining the potential of the storage node shared by the write transistor and the read transistor at 0 V.

14. In paragraph 13, A three-dimensional stacked non-volatile memory device, which, after the ferroelectric polarization is formed during the write operation, transmits a predetermined read voltage to the read transistor through the write transistor, thereby maintaining the potential of the storage node at 0 V.

15. In paragraph 13, A three-dimensional stacked non-volatile memory device configured such that the storage node is not used as a charge storage for storing the data, but data is stored by a polarization state formed in the insulating layer of the read transistor, thereby preventing data loss due to charge inflow or outflow into the storage node.

16. A memory cell including a plurality of insulating films and a plurality of metal films, and including a read transistor and a write transistor spaced apart from each other on a plane by a through hole penetrating the plurality of insulating films and the plurality of metal films; A write word line connected to the gate terminal of the above write transistor; A write bit line connected to the source terminal of the above write transistor; a read word line connected to the source terminal of the read transistor; and a read bit line connected to the drain terminal of the read transistor; The above writing transistor is provided on one side of the through hole and includes a first source electrode, a first drain electrode, a first gate electrode, and a first semiconductor layer, and a second insulating layer is provided between the first gate electrode and the first semiconductor layer. The above read transistor is provided on the other side of the through hole and includes a second source electrode, a second drain electrode, a second gate electrode, and a second semiconductor layer, and a fifth insulating layer is provided between the second gate electrode and the second semiconductor layer. The second source electrode is provided in the lowest metal layer among the plurality of metal layers, the first source electrode and the second gate electrode are provided in the metal layer above the second source electrode, the first gate electrode is provided in the metal layer above the first source electrode, the second drain electrode is provided in the metal layer above the first gate electrode, and the first drain electrode is provided in the metal layer above the second drain electrode. The second insulating layer and the fifth insulating layer are provided parallel to the first semiconductor layer and the second semiconductor layer, The above fifth insulating layer is a three-dimensional layered non-volatile memory device including a ferroelectric material.

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