A semiconductor structure and a method of fabricating the same

Abstract

The application provides a semiconductor structure and a preparation method thereof, and is applied to the technical field of semiconductors. In the application, the shapes and areas of the insulating structures in the peripheral region of the substrate and the units are different, so that different isolation effects are achieved, and peeling of part of the insulating structures is avoided.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a semiconductor structure and a preparation method thereof. BACKGROUND

[0002] With the trend of miniaturization of various electronic products, the design of dynamic random access memory (DRAM) cells must also meet the requirements of high integration and high density. For a DRAM cell with a recessed gate structure, it can obtain a longer carrier channel length in the same semiconductor substrate to reduce the leakage of the capacitor structure, so it has gradually replaced the DRAM cell with only a planar gate structure. Generally, a DRAM cell with a recessed gate structure includes a transistor component and a charge storage component to receive voltage signals from bit lines and word lines. However, due to the limitations of process technology, the existing DRAM cell with a recessed gate structure still has many defects, and further improvement and effective improvement of the performance and reliability of the related memory component are needed. SUMMARY

[0003] The purpose of the present application is to provide a semiconductor structure and a preparation method thereof, by setting part of the insulating structure in the first area and the second area to different shapes, and setting the insulating structure in the second area to a second insulating structure with a large block rectangular pattern and covering the entire base of the second area, to achieve different insulation effects and avoid peeling of part of the insulating structure.

[0004] In a first aspect, to solve the above technical problems, the present application provides a preparation method of a semiconductor structure, which can at least include:

[0005] providing a base, the base including a first area, a second area and a third area;

[0006] forming a first surrounding pattern, the first surrounding pattern including a plurality of strip patterns, the strip patterns extending in a first direction and across the base of the first area and the second area, and the plurality of strip patterns including a connected one end portion, the connected one end portion also extending in the first direction to the base of the third area;

[0007] forming a dielectric layer on the base and filling the gap between adjacent first surrounding patterns;

[0008] forming a hard mask layer comprising a plurality of second surrounding patterns on the dielectric layer in the first region and the second region, the second surrounding patterns being staggered with the first surrounding patterns, the second surrounding patterns comprising a long axis extending in a second direction perpendicular to the first direction and a short axis extending in the first direction;

[0009] forming a barrier layer on the dielectric layer and the hard mask layer, the barrier layer having openings exposing the second surrounding patterns in the second region;

[0010] removing the second surrounding patterns corresponding to the openings with the barrier layer as a mask;

[0011] removing part of the dielectric layer and the first surrounding patterns with the remaining hard mask layer as a mask to form a recess exposing the substrate in the first region and the second region;

[0012] forming an insulating layer filling the recess.

[0013] Optionally, the first surrounding patterns can comprise a plurality of bit line patterns and a spacer pattern surrounding the bit line patterns, the bit line patterns comprising the connected end portions.

[0014] Optionally, the end portions can comprise insulating material.

[0015] Optionally, the spacer pattern can have a ring frame shape.

[0016] Optionally, before forming the first surrounding patterns, the method can further comprise:

[0017] forming a plurality of word line structures arranged in the substrate in the first region and staggered with the plurality of bit line patterns.

[0018] Optionally, the word line structures can further comprise an insulating cap layer, and the insulating layer filling the recess contacts the insulating cap layer.

[0019] Optionally, a bottom surface of the recess in the first region can be higher than a bottom surface of the recess in the second region.

[0020] Optionally, a top surface of the spacer pattern in the first region and a top surface of the spacer pattern in the second region can be at different levels.

[0021] Optionally, a top surface of the spacer pattern in the first region can be higher than a top surface of the spacer pattern in the second region.

[0022] In a second aspect, based on the same inventive concept, the present application further provides a semiconductor structure, which can at least comprise:

[0023] a substrate, the substrate comprising a first region and a second region;

[0024] a plurality of word line structures, extending along a second direction and disposed in the substrate of the first region mutually separated in a first direction perpendicular to the second direction;

[0025] a plurality of bit line patterns, extending along the first direction and disposed on the word line structures mutually separated in the second direction;

[0026] a plurality of first insulating structures, located on the word line structures of the first region, the first insulating structures comprising annular frame-shaped patterns, the first insulating structures further comprising long axes extending in the second direction and short axes extending in the first direction;

[0027] a second insulating structure, located on the substrate of the second region, the second insulating structure comprising a bulk rectangular pattern, the second insulating structure further comprising long sides extending in the second direction and short sides extending in the first direction, wherein the length of the short sides is greater than the length of the short axes.

[0028] Optionally, the length of the long sides can be greater than the length of the long axes.

[0029] Optionally, in a third direction perpendicular to the substrate, the bottom surface of the second insulating structure can be lower than the bottom surface of the first insulating structure.

[0030] Optionally, the word line structures can comprise an insulating cover layer, and the first insulating structures can directly contact the insulating cover layer.

[0031] In the present application, by additionally depositing a barrier layer with openings and removing all second surrounding patterns on the second region based on the barrier layer, the shapes of the voids for forming insulating structures on the first region and the second region are adjusted to be different, and the voids for forming insulating structures on the second region are increased, so that insulating structures with different shapes are formed in the first region and the second region, and the insulating structure in the second region is set as a second insulating structure with a bulk rectangular pattern and covering the entire substrate of the second region, thereby achieving different insulation effects and avoiding peeling of part of the insulating structure. BRIEF DESCRIPTION OF DRAWINGS

[0032] The accompanying drawings are included to provide a further understanding of the present application, and constitute a part of the specification, illustrate the present application and, together with the specific embodiments described below, serve to explain the present application, but do not constitute a limitation on the present application. In the drawings:

[0033] Figure 1 Flowchart of the preparation method of the semiconductor structure provided in an embodiment of the present application;

[0034] Figures 2 to 16 The preparation method of the semiconductor structure provided in an embodiment of the present application is shown in the structural schematic diagram in the preparation process.

[0035] In the drawings, the same components are designated by the same reference numerals, and the drawings are not drawn according to the actual scale.

[0036] 100 - substrate, 101 - first region, 102 - second region, 103 - third region, 110 - trench isolation, 120 - word line structure, 121 - gate dielectric layer, 122 - work function layer, 123 - conductive layer, 124 - insulating cap layer, 130 - insulating layer, 140 - bit line pattern (strip pattern), 141 - first bit line pattern, 142 - second bit line pattern, 143 - third bit line pattern (adjacent one end portion), 150 - spacer pattern, 160 - first surrounding pattern, 200 - dielectric layer, 300 - hard mask layer, 170 - second surrounding pattern, 170a - short axis of the second surrounding pattern, 170b - long axis of the second surrounding pattern, 400 - barrier layer, 210 - recess, 211 - first recess, 212 - second recess, H - height difference of the bottom surface of the first recess and the second recess, 500 - insulating layer, 501 - first insulating structure, 502 - second insulating structure, 501a - long axis of the first insulating structure, 501b - short axis of the first insulating structure, 502a - long side of the second insulating structure, 502b - short side of the second insulating structure, D1 - first direction, D2 - second direction, D3 - third direction.

[0037] In the drawings, the same components are designated by the same reference numerals, and the drawings are not drawn according to the actual scale. DETAILED DESCRIPTION

[0038] In order to make the technical solutions and advantages of the embodiments of the present application clearer, the technical solutions of the present application will be further described in detail below with reference to the drawings and embodiments. Although the exemplary implementation methods of the present application are shown in the drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the implementation described herein. On the contrary, these implementations are provided in order to enable a more thorough understanding of the present application and to enable the scope of the present application to be fully conveyed to those skilled in the art.

[0039] The application is described in more detail in the following paragraphs with reference to the drawings. The advantages and features of the present application will become more fully apparent from the following description and appended claims. It is to be understood that the drawings are designed solely for purposes of illustration to facilitate the ease of understanding of the present application. It should be noted that the drawings are in extremely simplified form and that none of them is drawn to precise scale; each is merely intended to be illustrative. It should be understood that the meaning of "on", "over", and "above" in the present application should be interpreted in the broadest sense, such that "on" means not only "on" something without intervening characteristic or layer (i.e., directly on something) but also means "on" something with intervening characteristic or layer.

[0040] For the convenience of understanding, the first direction D1, the second direction D2 and the third direction D3 are defined in the following, wherein the first direction D1 is parallel to the surface of the substrate 100; the third direction D3 is perpendicular to the surface of the substrate 100, and the second direction D2 is perpendicular to the plane in which the first direction D1 and the third direction D3 lie.

[0041] Please refer to Figure 1 The flowchart shown is a flowchart of the preparation method of the semiconductor structure provided in an embodiment of the present application. As shown in Figure 1 The preparation method of the semiconductor structure provided in the embodiment of the present application at least includes the following steps:

[0042] Step S101, providing a substrate, the substrate including a first region, a second region and a third region;

[0043] Step S102, forming a first surrounding pattern, the first surrounding pattern including a plurality of strip patterns, the strip patterns extending in a first direction and across the substrate of the first region and the second region, and the plurality of strip patterns including a connected one end portion, the connected one end portion also extending in the first direction to the substrate of the third region;

[0044] Step S103, forming a dielectric layer, the dielectric layer being located on the substrate and filling into the gap between the adjacent first surrounding patterns;

[0045] Step S104, forming a hard mask layer, the hard mask layer including a plurality of second surrounding patterns, the second surrounding patterns being located on the dielectric layer of the first region and the second region and interleaving with the first surrounding patterns, the second surrounding patterns including a long axis extending in a second direction perpendicular to the first direction and a short axis extending in the first direction;

[0046] Step S105, forming a barrier layer on the dielectric layer and the hard mask layer, the barrier layer having an opening exposing the second surrounding pattern of the second region in the barrier layer;

[0047] Step S106, removing the second surrounding pattern corresponding to the opening by taking the barrier layer as a mask;

[0048] Step S107, removing part of the medium layer and the first surrounding pattern by taking the remaining hard mask layer as a mask, to form a groove of the substrate exposing the first region and the second region;

[0049] Step S108, forming an insulating layer to fill the groove.

[0050] In order to enable those skilled in the art to easily understand the preparation method of the semiconductor structure in the embodiments of the present application, the preparation method of the semiconductor structure proposed by the present application will be further described in the following with reference to the structural schematic diagrams of each structure in the preparation process. Among them, Figures 2 to 16 is a structural schematic diagram of the semiconductor structure in the preparation process of the preparation method of the semiconductor structure provided in the embodiments of the present application.

[0051] Please refer to Figure 2 and Figure 3 , Figure 2 is a partial top view schematic diagram of the semiconductor structure in an embodiment of the present application, Figure 3 is a sectional view schematic diagram of the semiconductor structure along the AA line shown in Figure 2 .

[0052] The above step S101 is performed: a substrate 100 is provided, the substrate 100 includes a first region 101, a second region 102 and a third region 103; the first region 101 is, for example, a cell region with relatively high component density as a component of a semiconductor memory, and the second region 102 and the third region 103 are, for example, both periphery regions with relatively low component density as components of a semiconductor memory. Among them, the substrate 100 is any suitable substrate material known in the art, for example, it can be a silicon substrate, a silicon-containing substrate or a silicon-on-insulator substrate or a substrate composed of other suitable materials, etc., but not limited thereto; the first region 101, the second region 102 and the third region 103 can be arranged in sequence along the first direction D1, but not limited thereto.

[0053] In one embodiment, a plurality of trench isolations 110 can be formed in the substrate 100 and arranged in a sequence along the first direction Dl, wherein one of the trench isolations 110 has a larger width than the other trench isolations 110 and is located at one side of all the other trench isolations 110, and this trench isolation 110 is located in the second region 102 and the third region 103 to define a peripheral region and a cell region of the substrate 100. In particular, the trench isolation 110 can include a single layer or multiple layers of dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbonitride doped with nitrogen, low dielectric constant dielectric materials such as fluorosilicate glass, carbon silicate, spin-on silicon glass, porous low dielectric constant dielectric materials, organic polymer dielectric materials, or a combination thereof, but not limited to. In addition, a plurality of word line structures 120 can be formed in the substrate 100 of the first region 101. The plurality of word line structures 120 are arranged in a sequence along the first direction Dl and in a strip shape extending along the second direction D2, and can include a gate dielectric layer 121 (e.g., high dielectric constant), a work function layer 122 (e.g., titanium nitride), a conductive layer 123 (e.g., tungsten), and an insulating cap layer 124 (e.g., oxide or nitride), but not limited to. Further, an insulating layer 130 can be formed on the substrate 100, and the insulating layer 130 can be a single layer structure, such as a silicon oxide layer or a silicon nitride layer (as shown in Figure 2 ), or a composite layer (not shown), such as an ONO composite layer composed of a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer, but not limited to.

[0054] Please continue to refer to Figure 2 and Figure 3 , the step S102 is performed: forming a first surrounding pattern 160 on the first region 101, the second region 102, and the third region 103 of the substrate 100; wherein the first surrounding pattern 160 can include a plurality of bit line patterns 140 and a spacer pattern 150 surrounding the bit line patterns 140; in particular, the bit line patterns 140 can include a first bit line pattern 141, a second bit line pattern 142, and a third bit line pattern 143 on the substrate 100 of the first region 101, the second region 102, and the third region 103, respectively; wherein the first bit line pattern 141 and the second bit line pattern 142 both extend along the first direction Dl and their short ends are connected at the junction of the first region 101 and the second region 102 (as shown in Figure 2The first bit line pattern 141 and the second bit line pattern 142 after the short end portions are connected can be collectively referred to as a strip-shaped pattern, and the plurality of bit line patterns 140 included in the first surrounding pattern 160 can be divided into a plurality of strip-shaped patterns arranged along the second direction D2, and the plurality of second bit line patterns 142 in the plurality of strip-shaped patterns can extend to the substrate 100 in the first direction D1 and be connected at one end portion of the third region 103 as the third bit line pattern 143. In this way, the spacer pattern 150 for isolating the first bit line pattern 141, the second bit line pattern 142, and the third bit line pattern 143 and arranged on the sidewalls thereof can be in the form of a ring-shaped frame. In an embodiment, the first bit line pattern 141 in the first region 101 can include, in detail, a semiconductor layer (not shown, for example, including doped polysilicon, doped amorphous silicon, and the like), a barrier layer (not shown, for example, titanium and / or titanium nitride), a metal layer (not shown, for example, tungsten), and a cap layer (not shown, for example, silicon oxide or silicon nitride) stacked in sequence, and the second bit line pattern 142 in the second region 102 and the third bit line pattern 143 in the third region 103 can include, in detail, an insulating material such as silicon oxide or silicon nitride. The top surfaces of the spacer pattern 150 in the first region 101 and the second region 102 are at different levels, for example Figure 16 The top surface of the spacer pattern 150 in the first region 101 can be higher than the top surface of the spacer pattern 150 in the second region 102, and the spacer structure on the sidewall of the bit line structure formed based on the spacer pattern 150 can include a single layer of dielectric material (such as Figure 3 For example, a silicon oxide layer or a silicon nitride layer, and can also include a plurality of layers of dielectric material (not shown), for example, a combination of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, or nitrogen-doped silicon carbide, but is not limited thereto.

[0055] Please refer to Figure 4 and Figure 5 as shown, Figure 4 is a partial top view schematic diagram of a semiconductor structure in an embodiment of the present application, Figure 5 is Figure 4 a sectional view schematic diagram of the semiconductor structure along the AA line as shown.

[0056] The step S103 is performed by forming a dielectric layer 200 on the first region 101, the second region 102 and the third region 103 of the substrate 100 by a deposition process such as physical vapor deposition, chemical vapor deposition, atomic layer deposition, etc., so as to fill the gap between the adjacent first surrounding patterns 160 on the substrate 100. In an embodiment, the top surface of the dielectric layer 200 can be higher than the top surface of the plurality of bit line patterns 140 in the first surrounding pattern 160, so as to bury the film layer structure on the substrate 100. The material of the dielectric layer 200 can be, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, or a combination of nitrogen-doped silicon carbide.

[0057] Please refer to Figure 6 and Figure 7 , which are a partial top view of a semiconductor structure in an embodiment of the present application, Figure 6 is a sectional view of the semiconductor structure shown in Figure 7 . Figure 6

[0058] The step S104 is performed by forming a hard mask layer 300 (material: silicon oxide or silicon nitride) containing a plurality of second surrounding patterns 170 on the dielectric layer 200, so as to prepare for the setting position of the first insulating structure 501 and the second insulating structure 502 to be formed subsequently. In an embodiment, the hard mask layer 300 has the plurality of second surrounding patterns 170 on part of the first region 101 and the second region 102. The plurality of second surrounding patterns 170 are all in the shape of a closed ring frame and are arranged in sequence along the first direction D1. The second surrounding pattern 170 can include a short axis 170a extending in the first direction D1 and a long axis 170b extending in the second direction D2. For example, the length of the long axis 170b of the plurality of second surrounding patterns 170 on the first region 101 can be smaller than the length of the long axis 170b of the plurality of second surrounding patterns 170 on the second region 102, but is not limited thereto.

[0059] Please refer to Figure 8 and Figure 9 , which are a partial top view of a semiconductor structure in an embodiment of the present application, Figure 8 is a sectional view of the semiconductor structure shown in Figure 9 . Figure 8

[0060] ​​The step S105 is performed to form a barrier layer 400 (material such as oxide or nitride) on the first region 101 and the third region 103 of the substrate 100; in particular, the barrier layer 400 covers the hard mask layer 300 and fills the gaps in the second surrounding patterns 170 in the hard mask layer 300, so that all the second surrounding patterns 170 on the first region 101 and all the hard mask layer 300 on the third region 103 are shielded by the barrier layer 400 when viewed from a top view; in addition, the barrier layer 400 has an opening to expose all the film layer structures on the second region 102, such as the second surrounding patterns 170 and the dielectric layer 200 between the second surrounding patterns 170 of the hard mask layer 300 on the second region 102.

[0061] Please refer to Figure 10 and Figure 11 , as shown in Figure 10 is a partial top view of a semiconductor structure in an embodiment of the present application, Figure 11 is Figure 10 is a cross-sectional view of the semiconductor structure along the AA line. The step S106 is performed to remove all the second surrounding patterns 170 on the second region 102 exposed by the opening in the barrier layer 400 by using an etching process such as dry etching or wet etching, and then remove the barrier layer 400 by using an etching process such as dry etching. It should be understood that the embodiment of the present application does not directly perform the steps S107 and S108 to form the first insulating structures 501 in the shape of annular frames on the word line structure 120 and the second region 102 after forming the hard mask layer 300 with the second surrounding patterns 170, but adds the steps of depositing the barrier layer 400 with the opening and removing all the second surrounding patterns 170 on the second region 102 based on the barrier layer 400, so that the shapes of the gaps reserved for forming the insulating structures on the first region 101 and the second region 102 are different through the added steps S105 and S106, and the shapes of the insulating structures formed on the first region 101 and the second region 102 are different, so as to achieve different isolation effects and avoid the problem of peeling of some insulating structures.

[0062] Please refer to Figure 12 and Figure 13 , as shown in Figure 11 , as shown in Figure 12 is a partial top view of a semiconductor structure in an embodiment of the present application,Figure 13 for Figure 12 The diagram shows a cross-sectional view of the semiconductor structure along line AA. Performing step S107: using the remaining hard mask layer 300 covering the first region 101 and the third region 103 as a mask, an etching process is performed downwards along the third direction D3 on the dielectric layer 200 not covered by the hard mask layer 300 and the first surrounding pattern 160 filled by the dielectric layer 200, to remove a portion of the dielectric layer 200 and the first surrounding pattern 160, forming a groove 210 exposing the substrate 100 of the first region 101 and the second region 102. Specifically, since the remaining hard mask layer 300 after performing step S106 consists of multiple second surrounding patterns 170 with gaps and annular frame shape on the first region 101, during the etching process of step S107 based on the remaining hard mask layer 300, the dielectric layer 200 and the first surrounding patterns 160 on the second region 102 are completely removed, the dielectric layer 200 on the third region 103 is not removed, and all portions of the first surrounding patterns 160 on the first region 101 are removed, thereby forming the following... Figure 13 The first groove 211 located on the second region 102 and the plurality of second grooves 212 located on the first region 101 respectively aligned with the word line structure 120 below them are shown. In one embodiment, by controlling the process parameters of the etching process in step S107, the bottom surfaces of the first groove 211 and the second groove 212 can be located at different horizontal heights, that is, there is a height difference H between the bottom surfaces of the first groove 211 and the second groove 212 along the third direction D3, where H>0; for example, the first groove 211 located on the second region 102 can be inserted into the wider trench isolation 110 located in the substrate 100 of the second region 102, and the second groove 212 located on the first region 101 can be inserted into the corresponding word line structure 120 located in the trench isolation 110 of the first region 101; wherein, the bottom surface of the second groove 212 located in the first region 101 can be higher than the bottom surface of the first groove 211 located in the second region 102, and the bottom surface of the second groove 212 located in the first region 101 can also be higher than the bottom surface of the insulating capping layer 124 of the corresponding word line structure 120 (in conjunction with Figure 3 (As shown).

[0063] Please refer to Figures 14 to 16 As shown, Figure 14 This is a partial top view of a semiconductor structure according to an embodiment of the present invention. Figure 15 for Figure 14 The diagram shows a cross-sectional view of the semiconductor structure along the tangent line AA. Figure 16 for Figure 14The semiconductor structure shown is a cross-sectional view along the BB cut line and the CC cut line. The step S108 is performed: using a deposition process to fill the insulating layer 500 (material such as nitride) in the first recess 211 located on the second region 102 and in the plurality of second recesses 212 located on the first region 101, to form a plurality of first insulating structures 501 in the shape of a ring frame on the first region 101 and in alignment with the word line structure 120, and to form a second insulating structure 502 on the second region 102. In an embodiment, the first insulating structure 501 located on the word line structure 120 of the first region 101 can include a ring frame pattern, which specifically includes a long axis 501a extending in the second direction D2 and a short axis 501b extending in the first direction D1; the second insulating structure 502 located on the substrate 100 of the second region 102 can include a large block rectangular pattern, which can include a long side 502a extending in the second direction D2 and a short side 502b extending in the first direction D1; wherein the length of the short side 502b is greater than the length of the short axis 501b, and the length of the long side 502a is greater than the length of the long axis 501a; and in the third direction D3, the bottom surface of the second insulating structure 502 can be lower than the bottom surface of the first insulating structure 501, but not limited thereto. In this arrangement, the insulating layer 500 filled in each of the second recesses 212 on the first region 101 in the embodiment of the present application is in direct contact with the insulating cap layer 124 of the corresponding word line structure 120, respectively.

[0064] In summary, the preparation method of the semiconductor structure provided by the present application includes forming a blocking layer on the dielectric layer and the hard mask layer, the blocking layer having an opening exposing the second surrounding pattern of the second region, removing the second surrounding pattern corresponding to the opening with the blocking layer as a mask, removing part of the dielectric layer and the first surrounding pattern with the remaining hard mask layer as a mask to form a recess of the substrate exposing the first region and the second region, and filling the recess with an insulating layer. The present application adjusts the shapes of the voids for forming the insulating structures on the first region and the second region to be different by adding a blocking layer with an opening and removing all the second surrounding patterns on the second region based on the blocking layer, increases the voids for forming the insulating structures on the second region, forms the insulating structures with different shapes in the first region and the second region, sets the insulating structure in the second region as a second insulating structure in the shape of a large block rectangular pattern covering the entire substrate of the second region, and achieves different insulation effects to avoid peeling of part of the insulating structure.

[0065] The above merely provides the preferred embodiments of the application, and not intended to limit the protection scope of the application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the application shall fall within the protection scope of the application.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, the substrate comprising a first region, a second region, and a third region; A first surrounding pattern is formed, the first surrounding pattern including a plurality of strip patterns, the strip patterns extending in a first direction and spanning the base of the first region and the second region, and the plurality of strip patterns including a connected end, the connected end also extending in the first direction to the base of the third region; A dielectric layer is formed on the substrate and fills the gaps between adjacent first surrounding patterns; A hard mask layer is formed, the hard mask layer including a plurality of second surrounding patterns, the second surrounding patterns being located on the dielectric layer of the first region and the second region and intersecting with the first surrounding pattern, the second surrounding pattern including a long axis extending in a second direction perpendicular to the first direction and a short axis extending in the first direction; A barrier layer is formed on the dielectric layer and the hard mask layer, and the barrier layer has an opening that exposes the second surrounding pattern of the second region; Using the barrier layer as a mask, remove the second surrounding pattern corresponding to the opening; Using the remaining hard mask layer as a mask, a portion of the dielectric layer and the first surrounding pattern are removed to form a groove that exposes the substrate in the first and second regions; An insulating layer is formed and filled into the groove.

2. The method for preparing the semiconductor structure according to claim 1, characterized in that, The first surrounding pattern includes: a plurality of bit line patterns and a gap wall pattern surrounding the bit line patterns, the bit line patterns including the connected end.

3. The method for preparing the semiconductor structure as described in claim 2, characterized in that, The end portion includes insulating material.

4. The method for preparing a semiconductor structure as described in claim 2, characterized in that, The gap wall pattern is in the shape of a ring frame.

5. The method for preparing a semiconductor structure as described in claim 2, characterized in that, Before forming the first surrounding pattern, the process also includes: Multiple word line structures are formed, which are arranged separately within the base of the first region and intersect with the multiple bit line patterns.

6. The method for preparing a semiconductor structure as described in claim 5, characterized in that, The word line structure also includes an insulating cover layer, and the insulating layer filling the groove contacts the insulating cover layer.

7. The method for preparing a semiconductor structure as described in claim 1, characterized in that, The bottom surface of the groove located in the first region is higher than the bottom surface of the groove located in the second region.

8. The method for preparing a semiconductor structure as described in claim 2, characterized in that, The gap wall pattern is at different horizontal heights on its top surface in the first region and the second region.

9. The method for preparing a semiconductor structure as described in claim 8, characterized in that, The top surface of the gap wall pattern located in the first region is higher than the top surface of the gap wall pattern located in the second region.

10. A semiconductor structure, characterized in that, include: A substrate, the substrate comprising a first region and a second region; Multiple character line structures are arranged within the base of the first region, extending along a second direction and separated from each other in a first direction perpendicular to the second direction; Multiple bit line patterns are arranged on the word line structure, extending along the first direction and spaced apart from each other in the second direction; Multiple first insulating structures are located on the word line structure in the first region. Each first insulating structure includes an annular frame pattern and further includes a long axis extending in the second direction and a short axis extending in the first direction. A second insulating structure is located on the substrate of the second region. The second insulating structure includes a large rectangular pattern and a long side extending in the second direction and a short side extending in the first direction, wherein the length of the short side is greater than the length of the short axis.

11. The semiconductor structure as claimed in claim 10, characterized in that, The length of the longer side is greater than the length of the longer axis.

12. The semiconductor structure as claimed in claim 10, characterized in that, In a third direction perpendicular to the substrate, the bottom surface of the second insulating structure is lower than the bottom surface of the first insulating structure.

13. The semiconductor structure as described in claim 10, characterized in that, The word line structure includes an insulating cover layer, and the first insulating structure is in direct contact with the insulating cover layer.

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