Semiconductor device and preparation method thereof
By setting the support layer and hard mask layer on the boundary of the capacitor array of DRAM, the problem of susceptibility to etching is solved, and the reliability and performance of semiconductor devices are improved.
Patent Information
- Application Number
- CN202411661613.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-19
- Publication Date
- 2025-02-18
AI Technical Summary
When preparing dynamic random access memory (DRAM), the capacitance array boundaries of the concave gate structure are susceptible to etching, resulting in reduced device reliability.
By providing the first and second support layers at the boundaries of the capacitance array and forming a hard mask layer on the second support layer, the boundaries of the capacitance array are protected from etching damage.
It effectively improves the reliability of semiconductor devices and prevents etching damage to the boundary of capacitor arrays, thereby improving the performance and reliability of the device.
Smart Images
Figure CN119486134A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for preparing the same. Background Art
[0002] With the development of high integration of semiconductor devices, the design of semiconductor devices must also meet the requirements of high integration and high density. For dynamic random access memory (DRAM) with a recessed gate structure, since it can obtain a longer carrier channel length in the same semiconductor substrate to reduce the leakage of the capacitor structure, it has gradually replaced the dynamic random access memory with only a planar gate structure under the current mainstream development trend. Generally speaking, a dynamic random access memory with a recessed gate structure is composed of a large number of memory cells gathered to form a storage area for storing information, and each memory cell can be composed of a transistor and a capacitor in series to receive voltage information from a word line and a bit line. In response to the development of semiconductor devices, the density of memory cells in the storage area must be continuously improved, resulting in the increasing difficulty and complexity of the related manufacturing process and design, resulting in a decrease in the performance and reliability of the memory. For example, when preparing a capacitor array, the boundary of the capacitor array is easily affected by etching during etching, thereby affecting the reliability of the device. Summary of the invention
[0003] The object of the present invention is to provide a semiconductor device and a method for manufacturing the same, so as to improve the reliability of the semiconductor device.
[0004] In order to achieve the above object, the present invention provides a semiconductor device, comprising:
[0005] substrate;
[0006] A capacitor array, comprising a plurality of lower electrodes, wherein the lower electrodes are all located on the substrate;
[0007] a first supporting layer and a second supporting layer, wherein the first supporting layer is located between two adjacent lower electrodes in the capacitor array and is in physical contact with the two adjacent lower electrodes, and the second supporting layer is located at a boundary of the capacitor array and is in physical contact with the lower electrodes located at the boundary of the capacitor array; and
[0008] The hard mask layer is located on the second supporting layer and contacts the second supporting layer.
[0009] Optionally, a bottom surface of the hard mask layer is higher than a top surface of the first supporting layer.
[0010] Optionally, a top surface of the second supporting layer is higher than a top surface of the first supporting layer.
[0011] Optionally, in a direction parallel to the substrate, the hard mask layer is ring-shaped, and the hard mask layer surrounds the capacitor array.
[0012] Optionally, the hard mask layer is made of different materials from the first supporting layer and the second supporting layer.
[0013] Optionally, the material of the hard mask layer includes semiconductor material.
[0014] Optionally, a capacitor dielectric layer is further included, which at least covers the lower electrode, the first supporting layer, the second supporting layer and the hard mask layer, and the capacitor dielectric layer is in contact with the hard mask layer.
[0015] The present invention also provides a method for preparing a semiconductor device, comprising:
[0016] providing a substrate;
[0017] forming a first supporting layer and a second supporting layer on the substrate;
[0018] forming a hard mask layer on the second supporting layer and in contact with the second supporting layer;
[0019] forming a capacitor array, including a plurality of lower electrodes, wherein the lower electrodes are all located on the substrate;
[0020] The first supporting layer is located between two adjacent lower electrodes in the capacitor array and is in physical contact with the two adjacent lower electrodes, and the second supporting layer is located at the boundary of the capacitor array and is in physical contact with the lower electrode located at the boundary of the capacitor array.
[0021] Optionally, the step of forming the hard mask layer, the first supporting layer and the second supporting layer includes:
[0022] A second supporting material layer, an undoped semiconductor layer and a patterned photoresist layer are sequentially formed on the substrate, wherein the patterned photoresist layer exposes a portion of the undoped semiconductor layer;
[0023] Using the patterned photoresist layer as a mask, doping the exposed undoped semiconductor layer to form a doped semiconductor layer;
[0024] Patterning the doped semiconductor layer and removing the undoped semiconductor layer;
[0025] Using the doped semiconductor layer as a mask, the second supporting material layer is sequentially etched to expose the substrate; the second supporting material layer retained in the center after etching serves as the first supporting layer, the second supporting material layer retained at the periphery serves as the second supporting layer, and the doped semiconductor layer retained on the second supporting layer serves as the hard mask layer.
[0026] Optionally, the exposed undoped semiconductor layer is doped with P-type ions to form the doped semiconductor layer.
[0027] Optionally, patterning the doped semiconductor layer includes patterning the central doped semiconductor layer, and thinning the central doped semiconductor layer after patterning, so that the top surface of the peripheral doped semiconductor layer is higher than the top surface of the central doped semiconductor layer.
[0028] Optionally, the step of forming the hard mask layer, the first supporting layer and the second supporting layer includes:
[0029] A second supporting material layer, an undoped semiconductor layer and a patterned photoresist layer are sequentially formed on the substrate, wherein the patterned photoresist layer exposes a portion of the undoped semiconductor layer;
[0030] Using the patterned photoresist layer as a mask, doping the exposed undoped semiconductor layer to form a doped semiconductor layer;
[0031] Patterning the undoped semiconductor layer and removing the doped semiconductor layer;
[0032] Using the undoped semiconductor layer as a mask, the second supporting material layer is sequentially etched to expose the substrate; the second supporting material layer retained in the center after etching serves as the first supporting layer, the second supporting material layer retained at the periphery serves as the second supporting layer, and the undoped semiconductor layer retained on the second supporting layer serves as the hard mask layer.
[0033] Optionally, the exposed undoped semiconductor layer is subjected to N-type ion doping to form the doped semiconductor layer.
[0034] Optionally, patterning the undoped semiconductor layer includes patterning the central undoped semiconductor layer and thinning the central undoped semiconductor layer after patterning, so that the top surface of the peripheral undoped semiconductor layer is higher than the top surface of the central undoped semiconductor layer.
[0035] Optionally, when forming the second supporting material layer, the undoped semiconductor layer and the patterned photoresist layer, a first oxide layer, a first supporting material layer and a second oxide layer are sequentially formed between the substrate and the second supporting material layer from bottom to top; when etching is performed using the doped semiconductor layer as a mask, the second oxide layer, the first supporting material layer and the first oxide layer are also sequentially etched to expose the substrate.
[0036] Optionally, after forming the hard mask layer, the first supporting layer and the second supporting layer, the lower electrode is formed on the substrate; and after forming the lower electrode, a capacitor dielectric layer is formed to at least cover the lower electrode, the first supporting layer, the second supporting layer and the hard mask layer, and the capacitor dielectric layer is in contact with the hard mask layer.
[0037] Optionally, a bottom surface of the hard mask layer is higher than a top surface of the first supporting layer, and a top surface of the second supporting layer is higher than a top surface of the first supporting layer.
[0038] Optionally, in a direction parallel to the substrate, the hard mask layer is ring-shaped, and the hard mask layer surrounds the capacitor array.
[0039] In the semiconductor device and preparation method thereof provided by the present invention, the first supporting layer is located between two adjacent lower electrodes in the capacitor array and is in physical contact with the two adjacent lower electrodes, and the second supporting layer is located at the boundary of the capacitor array and is in physical contact with the lower electrode located at the boundary of the capacitor array. By arranging a hard mask layer located on the second supporting layer and in contact with the second supporting layer, the boundary of the capacitor array can be protected and the boundary of the capacitor array can be prevented from being damaged by etching, thereby improving the reliability of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS
[0040] Figure 1 A partial top view of a semiconductor device provided by an embodiment of the present invention.
[0041] Figure 2 A schematic cross-sectional view of a semiconductor device provided according to an embodiment of the present invention.
[0042] Figure 3 to Figure 9 The cross-sectional schematic diagram shows corresponding steps of the method for preparing a semiconductor device provided in the first embodiment of the present invention.
[0043] Figure 10 to Figure 14 It is a cross-sectional schematic diagram of corresponding steps of the method for preparing a semiconductor device provided in the second embodiment of the present invention.
[0044] Wherein, the accompanying drawings are marked as follows:
[0045] 10-substrate; 10A-storage area; 10B-peripheral area; 20-gate structure; 30-storage node plug; 41-first insulating layer; 42-second insulating layer; 50-lower electrode; 60-first supporting material layer; 60a-middle supporting layer; 61-first oxide layer; 62-second oxide layer; 70-second supporting material layer; 71-first supporting layer; 72-second supporting layer; 80-hard mask layer; 80a-undoped semiconductor layer; 80b-doped semiconductor layer; 90-perforation; 91-capacitor dielectric layer; 92-upper electrode; 100-patterned photoresist layer; 110-interlayer dielectric layer; 120-plug. DETAILED DESCRIPTION
[0046] In order to make the purpose, advantages and features of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different scales are used.
[0047] Figure 1 A partial top view of the semiconductor device provided in this embodiment, Figure 2 A cross-sectional schematic diagram of a semiconductor device provided in this embodiment, Figure 2 for Figure 1 The cross-sectional diagram along the section line A1A2 is provided for the purpose of explaining the present embodiment clearly. Figure 1 Only part of the structure is shown. Please refer to Figure 1 and Figure 2 The present embodiment provides a semiconductor device, which may be a dynamic random access memory, including: a substrate 10, a capacitor array, a first support layer 71, a second support layer 72 and a hard mask layer 80, wherein the substrate 10 may be a silicon substrate, a gallium arsenide substrate, a germanium substrate, a germanium silicon substrate, a fully depleted silicon substrate on an insulating layer, but is not limited thereto; the substrate 10 includes a storage area 10A and a peripheral area 10B, the peripheral area 10B surrounds the storage area 10A, and a plurality of gate structures 20 are arranged in the substrate 10, specifically, the gate structure 20 is arranged in both the storage area 10A and the peripheral area 10B, and the gate structure 20 is a buried gate structure.
[0048] A plurality of storage node plugs 30 are disposed on the substrate 10. Specifically, storage node plugs 30 are disposed on both the storage area 10A and the peripheral area 10B. Figure 2The storage node plugs 30 are staggered with the gate structure 20. A first insulating layer 41 and a second insulating layer 42 are sequentially formed from bottom to top between adjacent storage node plugs 30 located on the storage area 10A, a first insulating layer 41 is formed between adjacent storage node plugs 30 located on the peripheral area 10B, and the storage node plugs 30 located on the peripheral area 10B are covered with a second insulating layer 42.
[0049] The capacitor array includes a plurality of lower electrodes 50, each of which is located on the substrate 10, specifically, on the storage node plug 30 on the storage area 10A and in contact with the storage node plug 30 on the storage area 10A. The lower electrode 50 is columnar. Figure 1 The lower electrode 50 is cylindrical in shape, but may also be other cylindrical shapes; Figure 2 The width of the lower electrode 50 may be less than or equal to the width of the storage node plug 30 .
[0050] The first supporting layer 71 is located between two adjacent lower electrodes 50 in the capacitor array and is in physical contact with the two adjacent lower electrodes 50. The first supporting layer 71 is located on the storage area 10A. Specifically, the first supporting layer 71 is in physical contact with part of the side surfaces of the tops of the two adjacent lower electrodes 50, and the top surface of the first supporting layer 71 can be flush with the top surface of the lower electrode 50.
[0051] The second supporting layer 72 is located at the boundary of the capacitor array and is in physical contact with the lower electrode 50 located at the boundary of the capacitor array. The second supporting layer 72 is located on the peripheral area 10B. Specifically, the second supporting layer 72 is in physical contact with a portion of the side surface of the top of the lower electrode 50 located at the boundary of the capacitor array, and the top surface of the second supporting layer 72 is higher than the top surface of the first supporting layer 71. The top surface of the second supporting layer 72 is flush with the top surface of the lower electrode 50; in a direction parallel to the substrate 10 ( Figure 2 In the lateral direction, the second support layer 72 is ring-shaped, and the second support layer 72 surrounds the capacitor array. Figure 1 The second supporting layer 72 is blocked by the hard mask layer 80 .
[0052] The hard mask layer 80 is located on the second support layer 72 and contacts the second support layer 72. The hard mask layer 80 is located on the peripheral area 10B. The bottom surface of the hard mask layer 80 is higher than the top surface of the first support layer 71. In the direction parallel to the substrate 10, the hard mask layer 80 is annular, and the hard mask layer 80 surrounds the capacitor array (such as Figure 1 In this embodiment, the hard mask layer 80 is made of different materials from the first support layer 71 and the second support layer 72. The first support layer 71 and the second support layer 72 are preferably made of the same material. The material of the hard mask layer 80 includes a semiconductor material, which may be a doped semiconductor material or an undoped semiconductor material. The width of the frame of the annular hard mask layer 80 is greater than the width of the lower electrode 50 (the width refers to Figure 1The hard mask layer 80 protects the boundary of the capacitor array and prevents the boundary of the capacitor array from being affected by etching during the process of forming the lower electrode 50, so as to improve the reliability of the device.
[0053] Furthermore, the semiconductor device also includes an intermediate support layer 60a, which is located between two adjacent lower electrodes 50 in the capacitor array and is in physical contact with a portion of the side surface between the two adjacent lower electrodes 50, and is located at the boundary of the capacitor array and is in physical contact with a portion of the side surface between the lower electrode 50 located at the boundary of the capacitor array. The intermediate support layer 60a is located on the storage area 10A and the peripheral area 10B; the material of the intermediate support layer 60a may be different from the material of the first support layer 71 and the second support layer 72.
[0054] Furthermore, the semiconductor device also includes a capacitor dielectric layer 91, which covers at least the lower electrode 50, the first support layer 71, the second support layer 72 and the hard mask layer 80, and the capacitor dielectric layer 91 also covers the intermediate support layer 60a and the second insulating layer 42 (the capacitor dielectric layer 91 conformally covers the surfaces of all the above-mentioned process layers), and the capacitor dielectric layer 91 is in contact with the hard mask layer 80.
[0055] Furthermore, the semiconductor device also includes an upper electrode 92, an interlayer dielectric layer 110 and a plug 120, wherein the upper electrode 92 covers the capacitor dielectric layer 91 and wraps the lower electrode 50, the first support layer 71, the second support layer 72, the hard mask layer 80 and the intermediate support layer 60a, the interlayer dielectric layer 110 covers and wraps the upper electrode 92, and the plug 120 is located above the upper electrode 92 and penetrates the interlayer dielectric layer 110 to be electrically connected to the upper electrode 92.
[0056] The present invention also provides a method for preparing a semiconductor device, which is used to prepare the above-mentioned semiconductor device, comprising:
[0057] Step S1: providing a substrate;
[0058] Step S2: forming a first supporting layer and a second supporting layer on the substrate, and forming a hard mask layer on the second supporting layer and in contact with the second supporting layer;
[0059] Step S3: forming a capacitor array, including a plurality of lower electrodes, wherein the lower electrodes are all located on the substrate;
[0060] The first support layer is located between two adjacent lower electrodes in the capacitor array and is in physical contact with the two adjacent lower electrodes, and the second support layer is located at the boundary of the capacitor array and is in physical contact with the lower electrode located at the boundary of the capacitor array.
[0061] Two embodiments are provided below to illustrate the method for preparing the semiconductor device provided by the present invention.
[0062] Embodiment 1
[0063] Figure 3 to Figure 9 The cross-sectional diagram of the corresponding steps of the method for preparing the semiconductor device provided in this embodiment. Figure 3 to Figure 9 The method for preparing the semiconductor device provided in this embodiment is described in detail.
[0064] Please refer to Figure 3 , perform step S1: provide a substrate 10, the substrate 10 can be a silicon substrate, a gallium arsenide substrate, a germanium substrate, a germanium silicon substrate, a fully depleted silicon substrate on an insulating layer, but is not limited thereto; the substrate 10 includes a storage area 10A and a peripheral area 10B, the peripheral area 10B surrounds the storage area 10A, and a plurality of gate structures 20 are arranged in the substrate 10, specifically, the gate structure 20 is arranged in both the storage area 10A and the peripheral area 10B, and the gate structure 20 is a buried gate structure.
[0065] A plurality of storage node plugs 30 are disposed on the substrate 10. Specifically, storage node plugs 30 are disposed on both the storage area 10A and the peripheral area 10B. Figure 2 The storage node plugs 30 are staggered with the gate structure 20. A first insulating layer 41 and a second insulating layer 42 are sequentially formed from bottom to top between adjacent storage node plugs 30 located on the storage area 10A, a first insulating layer 41 is formed between adjacent storage node plugs 30 located on the peripheral area 10B, and the storage node plugs 30 located on the peripheral area 10B are covered with a second insulating layer 42.
[0066] Performing step S2: forming a hard mask layer, a first supporting layer and a second supporting layer comprises:
[0067] Please refer to Figure 3 , a first oxide layer 61, a first supporting material layer 60, a second oxide layer 62, a second supporting material layer 70, an undoped semiconductor layer 80a and a patterned photoresist layer 100 are formed in sequence from bottom to top and are located on the substrate 10 (on the storage node plug 30 and the second insulating layer 42), and the patterned photoresist layer 100 exposes a portion of the undoped semiconductor layer 80a, specifically, the patterned photoresist layer 100 exposes the undoped semiconductor layer 80a on the storage area 10A and a portion of the undoped semiconductor layer 80a on the peripheral area 10B.
[0068] Please refer to Figure 3 and Figure 4 Using the patterned photoresist layer 100 as a mask, the exposed undoped semiconductor layer 80a is doped with P-type ions to form a doped semiconductor layer 80b (the doping direction is shown by the arrow in the figure), and the thickness of the doped semiconductor layer 80b is the same as that of the undoped semiconductor layer 80a.
[0069] Please refer to Figure 5 , patterning the doped semiconductor layer 80b, specifically including patterning the central doped semiconductor layer 80b (the doped semiconductor layer 80b on the storage area 10A) to expose a portion of the second support material layer 70 (the second support material layer 70 on the storage area 10A), and thinning the patterned central doped semiconductor layer 80b, so that the top surface of the peripheral doped semiconductor layer 80b (the doped semiconductor layer 80b on the peripheral area 10B) is higher than the top surface of the central doped semiconductor layer 80b; and at the same time, thinning the undoped semiconductor layer 80a, so that the top surface of the undoped semiconductor layer 80a is lower than the top surface of the peripheral doped semiconductor layer 80b. Please refer to Figure 6 , remove the undoped semiconductor layer 80a.
[0070] Please refer to Figure 6 and Figure 7 , using the doped semiconductor layer 80b as a mask, the second supporting material layer 70, the second oxide layer 62, the first supporting material layer 60 and the first oxide layer 61 are etched in sequence to expose the substrate 10 (the storage node plug 30 and the second insulating layer 42). After etching, the second supporting material layer retained in the center (the second supporting material layer retained on the storage area 10A) serves as the first supporting layer 71, the second supporting material layer retained in the periphery (the second supporting material layer retained on the peripheral area 10B) serves as the second supporting layer 72, the doped semiconductor layer retained on the second supporting layer 72 serves as the hard mask layer 80, and the retained first supporting material layer serves as the intermediate supporting layer 60a. Since the top surface of the peripheral doped semiconductor layer 80b is higher than the top surface of the central doped semiconductor layer 80b, that is, the thickness of the peripheral doped semiconductor layer 80b is higher than the thickness of the central doped semiconductor layer 80b, during etching, the peripheral and central doped semiconductor layers 80b are etched and lost at the same time. After etching, the doped semiconductor layer 80b is not retained on the first supporting layer 71, and the doped semiconductor layer 80b is retained on the second supporting layer 72.
[0071] In this embodiment, the hard mask layer 80 is located on the second supporting layer 72 and contacts the second supporting layer 72, the bottom surface of the hard mask layer 80 is higher than the top surface of the first supporting layer 71, and the top surface of the second supporting layer 72 is higher than the top surface of the first supporting layer 71. In the direction parallel to the substrate 10, the hard mask layer 80 is ring-shaped, and the hard mask layer 80 surrounds the capacitor array formed subsequently.
[0072] Please refer to Figure 8, perform step S3: form a capacitor array, the capacitor array includes a plurality of lower electrodes 50, the lower electrodes 50 are located on the substrate 10, specifically, are located on the storage node plug 30 and are in contact with the storage node plug 30, the lower electrodes 50 are columnar, and the top surface of the lower electrode 50 is flush with the top surface of the first support layer 71; then remove part of the first support layer 71, the second oxide layer 62, the middle support layer 60a and the first oxide layer 61 between adjacent lower electrodes 50 to form a through hole 90, and the bottom of the through hole 90 exposes the second insulating layer 42. After the lower electrode 50 is formed, the first supporting layer 71 is located between two adjacent lower electrodes 50 in the capacitor array and is in physical contact with part of the side surface of the top of the two adjacent lower electrodes 50, the second supporting layer 72 is located at the boundary of the capacitor array and is in physical contact with part of the side surface of the top of the lower electrode 50 located at the boundary of the capacitor array, the intermediate supporting layer 60a is located between two adjacent lower electrodes 50 in the capacitor array and is in physical contact with part of the side surface between the two adjacent lower electrodes 50, and the intermediate supporting layer 60a is located at the boundary of the capacitor array and is in physical contact with part of the side surface between the lower electrode 50 located at the boundary of the capacitor array.
[0073] For further information, please refer to Fig. 9 , remove the first oxide layer 61 and the second oxide layer 62. Please refer to Figure 2 After the first oxide layer 61 and the second oxide layer 62 are formed and removed, a capacitor dielectric layer 91 is formed to at least cover the lower electrode 50, the first support layer 71, the second support layer 72 and the hard mask layer 80, and the capacitor dielectric layer 91 also covers the middle support layer 60a and the second insulating layer 42, and the capacitor dielectric layer 91 is in contact with the hard mask layer 80; then, an upper electrode 92 is formed to cover the capacitor dielectric layer 91 and wrap the lower electrode 50, the first support layer 71, the second support layer 72, the hard mask layer 80 and the middle support layer 60a, an interlayer dielectric layer 110 is formed to cover and wrap the upper electrode 92, and a plug 120 is formed to be located above the upper electrode 92 and penetrate the interlayer dielectric layer 110 to be electrically connected to the upper electrode 92.
[0074] Embodiment 2
[0075] Figure 10 to Figure 14 The cross-sectional schematic diagram of the corresponding steps of the method for preparing the semiconductor device provided in this embodiment. The difference between this embodiment and the method for preparing the semiconductor device provided in Embodiment 1 is that the steps of forming the hard mask layer, the first supporting layer and the second supporting layer are different (Step S2 is different), and the other steps are the same. For other steps, please refer to the description of Embodiment 1. The following is a detailed description of Step S2.
[0076] Performing step S2: forming a hard mask layer, a first supporting layer and a second supporting layer comprises:
[0077] Please refer to Fig.10, a first oxide layer 61, a first supporting material layer 60, a second oxide layer 62, a second supporting material layer 70, an undoped semiconductor layer 80a and a patterned photoresist layer 100 are formed in sequence from bottom to top and are located on the substrate 10 (on the storage node plug 30 and the second insulating layer 42), and the patterned photoresist layer 100 exposes a portion of the undoped semiconductor layer 80a, specifically, the patterned photoresist layer 100 exposes a portion of the undoped semiconductor layer 80a on the peripheral area 10B.
[0078] Please refer to Fig.10 and Fig.11 Using the patterned photoresist layer 100 as a mask, the exposed undoped semiconductor layer 80a is doped with N-type ions to form a doped semiconductor layer 80b (the doping direction is shown by the arrow in the figure), and the thickness of the doped semiconductor layer 80b is the same as that of the undoped semiconductor layer 80a.
[0079] Please refer to Fig.12 , the undoped semiconductor layer 80a is patterned, specifically including patterning the central undoped semiconductor layer 80a (the undoped semiconductor layer 80a on the storage area 10A), and thinning the central undoped semiconductor layer 80a after patterning, so that the top surface of the peripheral undoped semiconductor layer 80a (the undoped semiconductor layer 80a on the peripheral area 10B) is higher than the top surface of the central undoped semiconductor layer 80a; and at the same time, the doped semiconductor layer 80b is thinned, so that the top surface of the doped semiconductor layer 80b is lower than the top surface of the peripheral undoped semiconductor layer 80a. Please refer to Fig.13 , remove the doped semiconductor layer 80b.
[0080] Please refer to Fig.13 and Fig.14, using the undoped semiconductor layer 80a as a mask, the second supporting material layer 70, the second oxide layer 62, the first supporting material layer 60 and the first oxide layer 61 are etched in sequence to expose the substrate 10 (the storage node plug 30 and the second insulating layer 42). After etching, the second supporting material layer retained in the center (the second supporting material layer retained on the storage area 10A) serves as the first supporting layer 71, the second supporting material layer retained in the periphery (the second supporting material layer retained on the peripheral area 10B) serves as the second supporting layer 72, the undoped semiconductor layer retained on the second supporting layer 72 serves as the hard mask layer 80, and the retained first supporting material layer serves as the intermediate supporting layer 60a. Since the top surface of the peripheral undoped semiconductor layer 80a is higher than the top surface of the central undoped semiconductor layer 80a, that is, the thickness of the peripheral undoped semiconductor layer 80a is higher than the thickness of the central undoped semiconductor layer 80a, during etching, the peripheral and central undoped semiconductor layers 80a are etched and lost at the same time. After etching, the undoped semiconductor layer 80a is not retained on the first supporting layer 71, and the undoped semiconductor layer 80a is retained on the second supporting layer 72.
[0081] In summary, in the semiconductor device and its preparation method provided by the present invention, the first supporting layer is located between two adjacent lower electrodes in the capacitor array and is in physical contact with the two adjacent lower electrodes, and the second supporting layer is located at the boundary of the capacitor array and is in physical contact with the lower electrode located at the boundary of the capacitor array. By setting a hard mask layer located on the second supporting layer and in contact with the second supporting layer, the boundary of the capacitor array can be protected and the boundary of the capacitor array can be prevented from being damaged by etching, thereby improving the reliability of the semiconductor device.
[0082] The above is only a preferred embodiment of the present invention and does not limit the present invention in any way. Any technician in the relevant technical field, without departing from the scope of the technical solution of the present invention, makes any form of equivalent replacement or modification to the technical solution and technical content disclosed in the present invention, which does not depart from the content of the technical solution of the present invention and still falls within the protection scope of the present invention.
Claims
1. A semiconductor device, characterized in that: include: substrate; A capacitor array, comprising a plurality of lower electrodes, wherein the lower electrodes are all located on the substrate; A first supporting layer and a second supporting layer, wherein the first supporting layer is located between two adjacent lower electrodes in the capacitor array and is in physical contact with the two adjacent lower electrodes, and the second supporting layer is located at a boundary of the capacitor array and is in physical contact with the lower electrodes located at the boundary of the capacitor array; as well as The hard mask layer is located on the second supporting layer and contacts the second supporting layer.
2. The semiconductor device according to claim 1, wherein A bottom surface of the hard mask layer is higher than a top surface of the first supporting layer.
3. The semiconductor device according to claim 1, wherein The top surface of the second supporting layer is higher than the top surface of the first supporting layer.
4. The semiconductor device according to claim 1, wherein In a direction parallel to the substrate, the hard mask layer is in a ring shape, and the hard mask layer surrounds the capacitor array.
5. The semiconductor device according to claim 1, wherein: The hard mask layer is made of different materials from the first supporting layer and the second supporting layer.
6. The semiconductor device according to claim 5, characterized in that The material of the hard mask layer includes semiconductor material.
7. The semiconductor device according to claim 1, wherein: It also includes a capacitor dielectric layer, which at least covers the lower electrode, the first supporting layer, the second supporting layer and the hard mask layer, and the capacitor dielectric layer is in contact with the hard mask layer.
8. A method for preparing a semiconductor device, characterized in that: include: providing a substrate; forming a first supporting layer and a second supporting layer on the substrate; forming a hard mask layer on the second supporting layer and in contact with the second supporting layer; forming a capacitor array, including a plurality of lower electrodes, wherein the lower electrodes are all located on the substrate; The first supporting layer is located between two adjacent lower electrodes in the capacitor array and is in physical contact with the two adjacent lower electrodes, and the second supporting layer is located at the boundary of the capacitor array and is in physical contact with the lower electrode located at the boundary of the capacitor array.
9. The method for preparing a semiconductor device according to claim 8, wherein: The steps of forming the hard mask layer, the first supporting layer and the second supporting layer include: A second supporting material layer, an undoped semiconductor layer and a patterned photoresist layer are sequentially formed on the substrate, wherein the patterned photoresist layer exposes a portion of the undoped semiconductor layer; Using the patterned photoresist layer as a mask, doping the exposed undoped semiconductor layer to form a doped semiconductor layer; Patterning the doped semiconductor layer and removing the undoped semiconductor layer; Using the doped semiconductor layer as a mask, the second supporting material layer is sequentially etched to expose the substrate; the second supporting material layer retained in the center after etching serves as the first supporting layer, the second supporting material layer retained at the periphery serves as the second supporting layer, and the doped semiconductor layer retained on the second supporting layer serves as the hard mask layer.
10. The method for preparing a semiconductor device according to claim 9, characterized in that: The exposed undoped semiconductor layer is subjected to P-type ion doping to form the doped semiconductor layer.
11. The method for preparing a semiconductor device according to claim 9, wherein: Patterning the doped semiconductor layer includes patterning the central doped semiconductor layer and thinning the central doped semiconductor layer after patterning, so that the top surface of the peripheral doped semiconductor layer is higher than the top surface of the central doped semiconductor layer.
12. The method for preparing a semiconductor device according to claim 8, wherein: The steps of forming the hard mask layer, the first supporting layer and the second supporting layer include: A second supporting material layer, an undoped semiconductor layer and a patterned photoresist layer are sequentially formed on the substrate, wherein the patterned photoresist layer exposes a portion of the undoped semiconductor layer; Using the patterned photoresist layer as a mask, doping the exposed undoped semiconductor layer to form a doped semiconductor layer; Patterning the undoped semiconductor layer and removing the doped semiconductor layer; Using the undoped semiconductor layer as a mask, the second supporting material layer is sequentially etched to expose the substrate; the second supporting material layer retained in the center after etching serves as the first supporting layer, the second supporting material layer retained at the periphery serves as the second supporting layer, and the undoped semiconductor layer retained on the second supporting layer serves as the hard mask layer.
13. The method for preparing a semiconductor device according to claim 12, wherein: The exposed undoped semiconductor layer is subjected to N-type ion doping to form the doped semiconductor layer.
14. The method for preparing a semiconductor device according to claim 12, wherein: Patterning the undoped semiconductor layer includes patterning the central undoped semiconductor layer and thinning the central undoped semiconductor layer after patterning, so that the top surface of the peripheral undoped semiconductor layer is higher than the top surface of the central undoped semiconductor layer.
15. The method for preparing a semiconductor device according to claim 9 or 12, characterized in that: When forming the second supporting material layer, the undoped semiconductor layer and the patterned photoresist layer, a first oxide layer, a first supporting material layer and a second oxide layer are sequentially formed between the substrate and the second supporting material layer from bottom to top; when etching is performed using the doped semiconductor layer as a mask, the second oxide layer, the first supporting material layer and the first oxide layer are also sequentially etched to expose the substrate.
16. The method for preparing a semiconductor device according to claim 8, wherein: After forming the hard mask layer, the first supporting layer and the second supporting layer, the lower electrode is formed on the substrate; and after forming the lower electrode, a capacitor dielectric layer is formed to at least cover the lower electrode, the first supporting layer, the second supporting layer and the hard mask layer, and the capacitor dielectric layer is in contact with the hard mask layer.
17. The method for preparing a semiconductor device according to claim 8, wherein: A bottom surface of the hard mask layer is higher than a top surface of the first supporting layer, and a top surface of the second supporting layer is higher than a top surface of the first supporting layer.
18. The method for preparing a semiconductor device according to claim 8, wherein: In a direction parallel to the substrate, the hard mask layer is in a ring shape, and the hard mask layer surrounds the capacitor array.