A method for improving the uniformity of NAND block word lines and select tubes

Abstract

The present invention discloses a method for improving the uniformity of NAND block word lines and select tubes, and relates to the field of semiconductor manufacturing technology. The method uses photolithography and etching to produce a word line sacrificial layer, a sidewall process to produce the word line, and photolithography and etching to produce a select tube gate. It is required that the edge of the select tube gate falls exactly on the word line, and the number of word lines covered by the select tube is different. Then, the word line sacrificial layer is removed, and the select tube gate is subsequently etched. To ensure edge accuracy and consistency, the edge of the portion where the select tube and the word line overlap is defined by the edge of the word line. Then, according to the design and the corresponding process flow, the distance between the select tube and the word line is determined by controlling the pattern of the word line exposure layer. Finally, the edge word line is designed to be covered by the select tube, and the unevenness of the edge word line is transferred to the internal word line, thereby optimizing the overall uniformity.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, in particular to a method for improving the uniformity of NAND block word lines and selection tubes. Background Art

[0002] Within a NAND block, word lines and select transistors serve as gates for the block's series channels. However, due to their different channel sizes, they are defined and manufactured using two independent lithography layers. Therefore, the distance between the word lines and select transistors at the edge of the block is affected by the alignment of the two lithography layers, resulting in uniformity issues. Furthermore, in current manufacturing methods, word lines adjacent to select transistors are located at the edge of the word line lithography layer pattern, leading to uniformity issues in the word line pattern and critical line-to-line spacing dimensions adjacent to the select transistors.

[0003] From the attached Figure 2 As can be seen, because the select transistors and word lines are independently defined by two lithography layers in existing processes, there is an alignment misalignment between the two lithography layers. Using advanced lithography tools, this misalignment can be on the order of a few to 10 nanometers. In more advanced NAND processes, the distance between word lines and the distance between word lines and select transistors is on the order of 20 nanometers or even less. Therefore, the misalignment between the two lithography layers has a significant impact on the distance between word lines and the distance between word lines and select transistors.

[0004] From the attached Figure 1 To the attached Figure 3 As can be seen, in existing processes, word lines adjacent to select transistors are edge-shaped during word line fabrication. In advanced NAND processes, due to various process capability variations, word lines at the edges, or the distance between them, are prone to poor critical dimension uniformity, and the word line morphology is often inconsistent with that of other word lines. Summary of the Invention

[0005] The object of the present invention is to provide a method for improving the uniformity of NAND block word lines and select transistors to solve the problems raised in the prior art.

[0006] To achieve the above object, the present invention provides the following technical solutions:

[0007] The method for improving the uniformity of NAND block word lines and select tubes includes the following steps:

[0008] Step 1: In the NAND block, there are word lines and select transistors, both of which are the gates of the NAND block series channel. Use photolithography technology to transfer the pattern of the select transistor gate to the substrate material, and then use etching technology to convert the pattern into a three-dimensional structure;

[0009] Step 2: During the layout design phase, the edge of the selector gate is set on the geometric centerline of the word line, and the gate and word line are made symmetrical during the processing;

[0010] Step 3: Cover different numbers of word lines on the select tube gate according to the design requirements of NAND;

[0011] Step 4: Remove the word line sacrificial layer. The sacrificial layer is a temporary layer used to protect the word line in subsequent processing steps. After removing the sacrificial layer, the word line is independent of other structures.

[0012] Step 5: Perform subsequent etching on the select transistor gate. After etching is completed, the pattern of the select transistor gate is transferred to the substrate material, and the head and tail word lines are cut off;

[0013] Step 6: After the etching and word line cutting steps are completed, the final pattern of the select tube is defined by exposing the pattern of the select tube at the edge away from the word line direction;

[0014] Step 7: For the portion where the select tube overlaps with the word line, the final pattern of the select tube is defined by the edge of the word line that overlaps with the exposure pattern of the select tube in the direction close to the word line.

[0015] Step 8: Based on the results of Steps 7 and 8, the distance between the final pattern of the select tube and the word line is defined by the word line exposure layer. The distance between the select tube and the word line is controlled by adjusting the size and position of the exposure layer.

[0016] Step 9: After the exposure layer position and size are adjusted, the edge word lines are covered with selection tubes to transfer the unevenness of the edge word lines to the internal word lines.

[0017] The method of transferring the pattern of the selector gate to the substrate material using the photolithography technology and then converting the pattern into a three-dimensional structure using the etching technology includes the following steps:

[0018] Step 1.1: Making an insulating layer: Select a base material, clean it, and perform surface treatment. Then, make a layer of insulating material on the base material to serve as the insulating layer for the selector gate.

[0019] Step 1.2: Fabricate a photolithography mask: First, use an electronic design automation tool to design the pattern of the selector gate and generate a photolithography mask pattern. Then, fabricate the photolithography mask based on the designed pattern.

[0020] Step 1.3: Photolithography: Place the fabricated photomask on the substrate and perform photolithography using light sources of different wavelengths, depending on the photolithography requirements, to chemically change the photoresist in the areas corresponding to the mask pattern.

[0021] Step 1.4: Development step: Place the exposed substrate material into a developer to dissolve the exposed portion of the photoresist to form the pattern of the selector gate;

[0022] Step 1.5: Etching step: Place the developed substrate material in an etching solution. According to the design requirements, use the etching solution to erode the pattern area on the substrate material and transfer the pattern defined by the photoresist to the substrate material.

[0023] Setting the edge of the selector gate on the geometric center line of the word line and making the gate symmetrical with the word line during the processing includes the following steps:

[0024] Step 2.1: Design the wordline pattern and select transistor gate pattern: First, design the wordline pattern in electronic design automation software so that the geometric centerline of the wordline is clear and measurable. Then, design the select transistor gate pattern in the EDA software so that its edge is aligned with the geometric centerline of the wordline pattern.

[0025] Step 2.2: Photolithography alignment: Use the high-precision alignment system of the photolithography machine to align the substrate material with the photolithography mask on the photolithography machine to accurately align the word line with the select tube gate pattern.

[0026] The method of covering different numbers of word lines on the select tube gate comprises the following steps:

[0027] Step 3.1: Determine the coverage strategy: Select the design of the transistor gate pattern as described in step 2.1 so that it can cover different numbers of word lines as needed;

[0028] Step 3.2: Implement word line coverage: The coverage method is: form a first word line on the selection tube gate, and the first word line covers a partial area of ​​the selection tube gate, and the partial area refers to setting the coverage ratio and width according to design requirements, rather than full coverage; form a second word line on the first word line, the second word line covers a partial area of ​​the first word line, and the width of the second word line is different from that of the first word line; form a third word line on the second word line, the third word line covers a partial area of ​​the second word line, and the width of the third word line is different from that of the second word line; repeat the above steps until the required number of word lines are formed on the selection tube gate.

[0029] The method of removing the word line sacrificial layer to make the word line independent of other structures includes the following steps:

[0030] Step 4.1: Sacrificial layer design: After completing the selection transistor gate coverage in the previous step, design and form a sacrificial layer above the word line according to the design requirements;

[0031] Step 4.2: Formation of sacrificial layer and protective layer: After the sacrificial layer design steps are completed, a sacrificial layer is formed on the word line using chemical vapor deposition and physical vapor deposition methods based on the design results. After the sacrificial layer is formed, a protective layer needs to be formed on the sacrificial layer.

[0032] Step 4.3: Removing the sacrificial layer: The sacrificial layer is removed using a plasma etching process. The removal method comprises the following steps: first, determining the etching rate and the position of the sacrificial layer, and monitoring the etching rate and depth while performing the etching process;

[0033] The subsequent etching of the selector gate, transferring the pattern of the selector gate to the substrate material after the etching is completed, and cutting the head and tail word lines include the following steps:

[0034] Step 5.1: Selector Grid Pattern Transfer: Based on the selector grid already formed on the substrate material, electron beam lithography is used to prepare the selector grid pattern. The selector grid is then etched using plasma etching technology to transfer the pattern to the substrate material to form the desired three-dimensional structure.

[0035] Step 5.2: Word line cutting: According to the design requirements, first determine the specific location of the word line cutting, then set the cutting path and mode in the cutting area, adjust the cutting parameters, and finally use plasma cutting technology to perform the cutting operation.

[0036] After the etching and word line cutting steps are completed, the final pattern of the select tube is defined by the select tube exposure pattern at the edge away from the word line direction, including the following:

[0037] Step 6.1: Exposure pattern preparation: First, according to the design requirements of the selection tube, use CAD tools to design the outer edge pattern of the selection tube that meets the design requirements. Then, evenly apply photoresist on the substrate material, and use a drying process to control the thickness and quality of the photoresist.

[0038] Step 6.2: Exposure and Development: After the exposure pattern is prepared, the photoresist-coated substrate is exposed using a photolithography machine. The exposure dose and resolution are controlled to match the outer edge pattern of the selected tube with the designed pattern. After exposure, the substrate is placed in a developer for development.

[0039] Step 6.3: Select tube edge etching: After the exposure and development steps are completed, according to the design requirements, the edge of the select tube gate away from the word line direction needs to be etched; and the shape and size of the select tube gate are controlled by adjusting the etching rate.

[0040] The method of defining the final pattern of the select tube by the edge of the word line overlapping the select tube exposure pattern in the direction close to the word line for the portion where the select tube overlaps with the word line includes the following steps:

[0041] Step 7.1: Photolithography: Place a mask with the selector tube exposure pattern on the wafer for exposure. Then, place the exposed wafer in a developer to form the selector tube pattern. Finally, use an etchant to etch away the portion not protected by the photoresist, forming the selector tube structure on the wafer.

[0042] Step 7.2: Alignment and overlap check: In the overlapping area of ​​the select tube and the word line, and in the direction close to the word line, the pattern of the select tube matches the edge of the word line. The high-precision alignment system of the lithography machine is required to confirm the position alignment of the select tube exposure pattern and the word line, and check the overlap between the two.

[0043] The final pattern of the selection tube and the distance between the word lines are defined by the word line exposure layer and include the following steps:

[0044] Step 8.1: Adjust the size of the exposure layer pattern: Based on the design requirements, use electron beam lithography technology to control the size of the exposure layer pattern according to the design parameters. Then, use computer-aided design software to accurately design the exposure layer pattern. Utilizing the high resolution capability of the lithography machine, transfer the designed pattern to the exposure layer. Calculate the size of the exposure layer pattern using the following formula:

[0045] L=D+σ L

[0046] Where D represents the distance between the selection tube and the word line according to the design requirements, L represents the size of the exposure layer pattern, σ L Represents the margin reserved to take into account process deviations;

[0047] Taking into account the optical diffraction effect during the photolithography process, the size of the exposure layer pattern is corrected using the following formula:

[0048] L′=L+λsin(t)

[0049] Where L′ represents the corrected exposure layer pattern size, λ represents the lithography wavelength, and t represents the diffraction angle;

[0050] Step 8.2: Adjust the exposure layer pattern position: After the exposure layer pattern size is designed, fine-tune the exposure layer position in the horizontal and vertical directions. Then, use the alignment system of the lithography machine to mechanically position and align the two layers to control the spacing. Phase-shift exposure technology is also used to confirm the pattern position and spacing.

[0051] For fine-tuning the exposure layer position, the new exposure layer position is calculated using the following formula:

[0052] X′=X+σ X

[0053] Where X is the original exposure layer position, X′ is the new exposure layer position, σ X is the fine-tuning amount;

[0054] Taking into account the accuracy and error of the lithography machine alignment system, the following formula is used to correct the position of the exposure layer:

[0055] X″=X′+ε

[0056] Where X″ represents the position of the corrected exposure layer, and ε represents the error of the alignment system of the lithography machine;

[0057] However, phase-shift exposure is achieved by adjusting the exposure dose and phase, and the position of the pattern after exposure is calculated using the following formula:

[0058] X″′=X″+I·cos(ψ)

[0059] Where X″′ represents the position of the pattern after exposure, I represents the exposure dose, and ψ represents the phase shift.

[0060] Covering the edge word lines with selection transistors to transfer the unevenness of the edge word lines to the inner word lines includes the following steps:

[0061] Step 9.1: Edge word line design: After the exposure layer size and position are adjusted and the distance between the final tube pattern and the word line is confirmed, the layout and shape of the edge word line are designed according to the design requirements;

[0062] Step 9.2: Selector Layout: After the edge word line design is completed, the size and shape of the selector tubes are planned according to the edge word line design requirements, and the position and layout of the selector tubes are further arranged;

[0063] Step 9.3: Non-uniformity Transfer Mechanism: After completing the edge word line design and select tube layout according to the above steps, after the edge word lines are covered by the select tubes, use electrical testing methods to perform non-uniformity analysis on the edge word lines and select tubes to confirm the existing non-uniformity characteristics and distribution;

[0064] Step 9.4: Transfer to internal word lines: Based on the analysis results of the non-uniformity mechanism, the non-uniformity is transferred by establishing a physical connection between the edge word lines and the internal word lines.

[0065] Compared with the prior art, the present invention has the following beneficial effects:

[0066] 1. Improve the uniformity of word lines at the edge of NAND blocks: Through specific technical means, the differences between edge word lines can be reduced, making them more evenly distributed in the NAND block. This method can effectively improve the uniformity of word lines at the edge of NAND blocks.

[0067] 2. Improve the uniformity of the distance between the word lines and select tubes at the edge of the NAND block: By precisely controlling the position of the word lines and select tubes, the deviation of the distance can be reduced, thereby improving the performance and consistency of the entire NAND block. This method can not only improve the uniformity of the word lines, but also improve the uniformity of the distance between the word lines and select tubes at the edge of the NAND block.

[0068] 3. Improve the performance and reliability of NAND flash memory: The uniformity of word lines and select tubes is crucial to the performance and reliability of NAND flash memory. Through the application of this method, the non-uniformity between word lines and select tubes can be reduced, the failure risk of storage cells can be reduced, and the accuracy and stability of data reading and writing can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0069] Figure 1 A schematic diagram of the structure of making word lines and word line sacrificial layers in a method for improving the uniformity of NAND block word lines and select tubes according to the present invention;

[0070] Figure 2 A schematic diagram of the structure of the gate of the select tube in a method for improving the uniformity of the NAND block word line and the select tube of the present invention;

[0071] Figure 3 A schematic diagram of the structure of subsequent tube gate etching and head and tail word line cutting in a method for improving the uniformity of NAND block word lines and select tubes of the present invention;

[0072] Figure 4 A schematic diagram of the structure of improving the fabrication of word lines and word line sacrificial layers in a method for improving the uniformity of NAND block word lines and select transistors according to the present invention;

[0073] Figure 5 A schematic diagram of the structure of the improved selection tube gate in a method for improving the uniformity of NAND block word lines and selection tubes of the present invention;

[0074] Figure 6 A schematic diagram of a structure in which a word line sacrificial layer is removed in a method for improving the uniformity of NAND block word lines and select transistors according to the present invention;

[0075] Figure 7 The present invention is a structural schematic diagram of improving subsequent tube gate etching and head and tail word line cutting in a method for improving the uniformity of NAND block word lines and select tubes. DETAILED DESCRIPTION

[0076] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0077] Example: Figure 1-Figure 7 As shown, the present invention provides a technical solution, a method for improving the uniformity of NAND block word lines and select tubes, comprising the following steps:

[0078] Step 1: In the NAND block, there are word lines and select transistors, both of which are the gates of the NAND block series channel. Use photolithography technology to transfer the pattern of the select transistor gate to the substrate material, and then use etching technology to convert the pattern into a three-dimensional structure;

[0079] Step 2: During the layout design phase, the edge of the selector gate is set on the geometric centerline of the word line, and the gate and word line are made symmetrical during the processing;

[0080] Step 3: Cover different numbers of word lines on the select tube gate according to the design requirements of NAND;

[0081] Step 4: Remove the word line sacrificial layer. The sacrificial layer is a temporary layer used to protect the word line in subsequent processing steps. After removing the sacrificial layer, the word line is independent of other structures.

[0082] Step 5: Perform subsequent etching on the select transistor gate. After etching is completed, the pattern of the select transistor gate is transferred to the substrate material, and the head and tail word lines are cut off;

[0083] Step 6: After the etching and word line cutting steps are completed, the final pattern of the select tube is defined by exposing the pattern of the select tube at the edge away from the word line direction;

[0084] Step 7: For the portion where the select tube overlaps with the word line, the final pattern of the select tube is defined by the edge of the word line that overlaps with the exposure pattern of the select tube in the direction close to the word line.

[0085] Step 8: Based on the results of Steps 7 and 8, the distance between the final pattern of the select tube and the word line is defined by the word line exposure layer. The distance between the select tube and the word line is controlled by adjusting the size and position of the exposure layer.

[0086] Step 9: After the exposure layer position and size are adjusted, the edge word lines are covered with selection tubes to transfer the unevenness of the edge word lines to the internal word lines.

[0087] The method of transferring the pattern of the selector gate to the substrate material using the photolithography technology and then converting the pattern into a three-dimensional structure using the etching technology includes the following steps:

[0088] Step 1.1: Making an insulating layer: Select a base material, clean it, and perform surface treatment. Then, make a layer of insulating material on the base material to serve as the insulating layer for the selector gate.

[0089] Step 1.2: Fabricate a photolithography mask: First, use an electronic design automation tool to design the pattern of the selector gate and generate a photolithography mask pattern. Then, fabricate the photolithography mask based on the designed pattern.

[0090] Step 1.3: Photolithography: Place the fabricated photomask on the substrate and perform photolithography using light sources of different wavelengths, depending on the photolithography requirements, to chemically change the photoresist in the areas corresponding to the mask pattern.

[0091] Step 1.4: Development step: Place the exposed substrate material into a developer to dissolve the exposed portion of the photoresist to form the pattern of the selector gate;

[0092] Step 1.5: Etching step: Place the developed substrate material in an etching solution. According to the design requirements, use the etching solution to erode the pattern area on the substrate material and transfer the pattern defined by the photoresist to the substrate material.

[0093] Setting the edge of the selector gate on the geometric center line of the word line and making the gate symmetrical with the word line during the processing includes the following steps:

[0094] Step 2.1: Design the wordline pattern and select transistor gate pattern: First, design the wordline pattern in electronic design automation software so that the geometric centerline of the wordline is clear and measurable. Then, design the select transistor gate pattern in the EDA software so that its edge is aligned with the geometric centerline of the wordline pattern.

[0095] Step 2.2: Photolithography alignment: Use the high-precision alignment system of the photolithography machine to align the substrate material with the photolithography mask on the photolithography machine to accurately align the word line with the select tube gate pattern.

[0096] The method of covering different numbers of word lines on the select tube gate comprises the following steps:

[0097] Step 3.1: Determine the coverage strategy: Select the design of the transistor gate pattern as described in step 2.1 so that it can cover different numbers of word lines as needed;

[0098] Step 3.2: Implement word line coverage: Figure 5 、 Figure 6As shown, the selection tube pattern covers the enhanced protection word line, and the edge word line and the selection tube ensure that the morphology, size, distance, uniformity and edge roughness meet the process requirements. The covering method is: forming a first word line on the selection tube gate, and the first word line covers a part of the area of ​​the selection tube gate, and the part of the area refers to setting the coverage ratio and width according to the design requirements, rather than full coverage; forming a second word line on the first word line, the second word line covers a part of the area of ​​the first word line, and the width of the second word line is different from that of the first word line; forming a third word line on the second word line, the third word line covers a part of the area of ​​the second word line, and the width of the third word line is different from that of the second word line; repeating the above steps until the required number of word lines are formed on the selection tube gate.

[0099] The method of removing the word line sacrificial layer to make the word line independent of other structures includes the following steps:

[0100] Step 4.1: Sacrificial layer design: Figure 1 、 Figure 4 、 Figure 5 As shown, due to the sparse exposure environment, regular edge word lines are prone to process defects such as line collapse, overexposure, and sidewall formation defects, causing the edge word line morphology, size, uniformity, and edge roughness to exceed the allowable range. After completing the selection tube gate coverage in the previous step, a sacrificial layer is designed and formed above the word line according to design requirements.

[0101] Step 4.2: Formation of sacrificial layer and protective layer: After the sacrificial layer design steps are completed, a sacrificial layer is formed on the word line using chemical vapor deposition and physical vapor deposition methods based on the design results. After the sacrificial layer is formed, a protective layer needs to be formed on the sacrificial layer.

[0102] Step 4.3: Remove the sacrificial layer: Figure 2 As shown, a plasma etching process is used to remove the sacrificial layer; the removal method steps are as follows: first, the etching rate and the position of the sacrificial layer are determined, and while performing the etching process, the etching rate and depth are monitored; Figure 4 As shown, after the sacrificial layer is removed, the independent word line is exposed, and then a protective layer is added on the word line. The advantage is that the regular edge word line has an improved exposure environment due to the existence of the enhanced protective word line, and the process defects such as line inversion, overexposure, and side wall formation defects that appeared in the original process are significantly improved, ensuring that the morphology, size, uniformity, distance and edge roughness of the regular edge word line are within a controllable range.

[0103] The subsequent etching of the selector gate, transferring the pattern of the selector gate to the substrate material after the etching is completed, and cutting the head and tail word lines include the following steps:

[0104] Step 5.1: Select the tube grid pattern to transfer: First, as Figure 1 、 Figure 2 As shown, after removing the sacrificial layer, the selector gate is formed on the substrate material, and the pattern of the selector gate is prepared using electron beam lithography technology. Then, the selector gate is etched using plasma etching technology, and the pattern is transferred to the substrate material to form the desired three-dimensional structure.

[0105] Step 5.2: Word line cutting: Figure 3 、 Figure 4 、 Figure 7 As shown in the figure, due to the existence of enhanced protection word lines, the process defects of regular edge word lines, such as line collapse, overexposure, and sidewall formation defects that occurred in the original process, are significantly improved; then, according to the design requirements, the specific location of the word line cut is first determined, and then the cutting path and mode are set in the cutting area, and the cutting parameters are adjusted, and finally the cutting operation is performed using plasma cutting technology.

[0106] After the etching and word line cutting steps are completed, the final pattern of the select tube is defined by the select tube exposure pattern at the edge away from the word line direction, including the following:

[0107] Step 6.1: Exposure pattern preparation: First, according to the design requirements of the selection tube, use CAD tools to design the outer edge pattern of the selection tube that meets the design requirements. Then, evenly apply photoresist on the substrate material, and use a drying process to control the thickness and quality of the photoresist.

[0108] Step 6.2: Exposure and Development: After the exposure pattern is prepared, the photoresist-coated substrate is exposed using a photolithography machine. The exposure dose and resolution are controlled to match the outer edge pattern of the selected tube with the designed pattern. After exposure, the substrate is placed in a developer for development.

[0109] Step 6.3: Select tube edge etching: After the exposure and development steps are completed, according to the design requirements, the edge of the select tube gate away from the word line direction needs to be etched; and the shape and size of the select tube gate are controlled by adjusting the etching rate.

[0110] The method of defining the final pattern of the select tube by the edge of the word line overlapping the select tube exposure pattern in the direction close to the word line for the portion where the select tube overlaps with the word line includes the following steps:

[0111] Step 7.1: Photolithography: Place a mask with the selector tube exposure pattern on the wafer for exposure. Then, place the exposed wafer in a developer to form the selector tube pattern. Finally, use an etchant to etch away the portion not protected by the photoresist, forming the selector tube structure on the wafer.

[0112] Step 7.2: Alignment and overlap check: In the overlapping area of ​​the select tube and the word line, and in the direction close to the word line, the pattern of the select tube matches the edge of the word line. The high-precision alignment system of the lithography machine is required to confirm the position alignment of the select tube exposure pattern and the word line, and check the overlap between the two.

[0113] The final pattern of the selection tube and the distance between the word lines are defined by the word line exposure layer and include the following steps:

[0114] Step 8.1: Adjust the size of the exposure layer pattern: Based on the design requirements, use electron beam lithography technology to control the size of the exposure layer pattern according to the design parameters. Then, use computer-aided design software to accurately design the exposure layer pattern. Utilizing the high resolution capability of the lithography machine, transfer the designed pattern to the exposure layer. Calculate the size of the exposure layer pattern using the following formula:

[0115] L=D+σ L

[0116] Where D represents the distance between the selection tube and the word line according to the design requirements, L represents the size of the exposure layer pattern, σ L Represents the margin reserved to take into account process deviations;

[0117] Taking into account the optical diffraction effect during the photolithography process, the size of the exposure layer pattern is corrected using the following formula:

[0118] L′=L+λsin(t)

[0119] Where L′ represents the corrected exposure layer pattern size, λ represents the lithography wavelength, and t represents the diffraction angle;

[0120] The above formula takes into account factors such as process deviation. To ensure that the final pattern size meets the design requirements, a correction term is added to adjust the size of the exposed layer pattern to compensate for the size change caused by diffraction.

[0121] Assuming that the design requires a distance of 100 nm between the selector and the word line, with a reserved margin of 10 nm, a photolithography wavelength of 193 nm, and a diffraction angle of 0.1 radian, the size of the exposed pattern is:

[0122] L=D+σ L

[0123] =100+10

[0124] =110nm

[0125] The corrected exposure layer graphic size is:

[0126] L′=L+λsin(t)

[0127] =110+193·sin(0.1)

[0128] ≈116nm

[0129] Through electron beam lithography technology and the high resolution capability of the lithography machine, precise control of pattern size is achieved, while corrections are made considering the optical diffraction effect to ensure more accurate spacing control;

[0130] Step 8.2: Adjust the exposure layer pattern position: After the exposure layer pattern size is designed, fine-tune the exposure layer position in the horizontal and vertical directions. Then, use the alignment system of the lithography machine to mechanically position and align the two layers to control the spacing. Phase-shift exposure technology is also used to confirm the pattern position and spacing.

[0131] For fine-tuning the exposure layer position, the new exposure layer position is calculated using the following formula:

[0132] X′=X+σ X

[0133] Where X is the original exposure layer position, X′ is the new exposure layer position, σ X is the fine-tuning amount;

[0134] Taking into account the accuracy and error of the lithography machine alignment system, the following formula is used to correct the position of the exposure layer:

[0135] X″=X′+ε

[0136] Where X″ represents the position of the corrected exposure layer, and ε represents the error of the alignment system of the lithography machine;

[0137] However, phase-shift exposure is achieved by adjusting the exposure dose and phase, and the position of the pattern after exposure is calculated using the following formula:

[0138] X″′=X″+I·cos(ψ)

[0139] Where X″′ represents the position of the pattern after exposure, I represents the exposure dose, and ψ represents the phase shift.

[0140] This formula indicates that the position and spacing control of the pattern is optimized by phase-shift exposure, and the position of the pattern after exposure is adjusted by adding a term related to the exposure dose and phase;

[0141] Assume that the exposure layer needs to be adjusted 5nm to the right in the horizontal direction, the alignment error of the lithography machine is 1nm, the exposure dose is 100mj / cm2, and the phase offset is 0.2 radians. The position of the new exposure layer should be:

[0142] X′=X+σ X

[0143] =X+5

[0144] =5nm

[0145] X″=X′+ε

[0146] =5+1

[0147] =6nm

[0148] X″′=X″+I·cos(ψ)

[0149] =6+100·cos(0.2)

[0150] ≈103nm

[0151] Through the precise mechanical positioning and alignment of the lithography machine alignment system and the change of phase offset exposure, the position of the exposure layer can be fine-tuned, thereby more accurately controlling the spacing between the selection tube and the word line.

[0152] Covering the edge word lines with selection transistors to transfer the unevenness of the edge word lines to the inner word lines includes the following steps:

[0153] Step 9.1: Edge word line design: After the exposure layer size and position are adjusted and the distance between the final tube pattern and the word line is confirmed, the layout and shape of the edge word line are designed according to the design requirements;

[0154] Step 9.2: Selector Layout: After the edge word line design is completed, the size and shape of the selector tubes are planned according to the edge word line design requirements, and the position and layout of the selector tubes are further arranged;

[0155] Step 9.3: Non-uniformity Transfer Mechanism: After completing the edge word line design and select tube layout according to the above steps, after the edge word lines are covered by the select tubes, use electrical testing methods to perform non-uniformity analysis on the edge word lines and select tubes to confirm the existing non-uniformity characteristics and distribution;

[0156] Consider a sample of NAND flash memory chips. First, use a four-point probe method to test the resistance of the edge word lines of each chip. During the test, ensure that the probes are in good contact with the word lines and record the resistance value at each test point. Repeatedly test the edge word lines of each chip and organize and store the test data.

[0157] Then, data analysis is performed to calculate the statistical parameters such as the average value, standard deviation, maximum value, and minimum value of the edge word line resistance of each chip. By comparing the statistical parameters of different chips, the degree of non-uniformity of the edge word line resistance is evaluated;

[0158] Assuming that the resistance non-uniformity of the edge word lines is caused by process deviation during the manufacturing process, the resistance value is higher in the edge area of ​​the chip and lower in the inner area.

[0159] Step 9.4: Transfer to internal word lines: Based on the analysis results of the non-uniformity mechanism, the non-uniformity is transferred by establishing a physical connection between the edge word lines and the internal word lines.

[0160] Based on the above nonuniformity analysis results, it was assumed that the resistance variation range of the edge word lines was 100Ω to 200Ω, and the target resistance variation range of the internal word lines was 50Ω to 100Ω. Based on the results analysis, it was decided to use a resistor network transfer mechanism to achieve nonuniformity transfer. The resistor network can simulate the resistance variation of the edge word lines by adjusting the resistance value and map it to the internal word lines.

[0161] Based on the above assumed data, a proportional coefficient K can be defined so that

[0162] K = (variation range of internal word line resistance) / (variation range of edge word line resistance)

[0163] Substituting the data, we can get

[0164] K=(100Ω-50Ω) / (200Ω-100Ω)=0.5

[0165] Then for each resistance value R of the edge word line, we can calculate the resistance value r of the internal word line by the following formula:

[0166] r=R·K

[0167] Assuming the resistance of the edge word line is 150Ω, the resistance of the inner word line is:

[0168] r=150Ω·0.5=75Ω

[0169] In this way, we can calculate the resistance value of the corresponding internal word line based on the resistance value of the edge word line, thereby achieving the transfer of unevenness.

[0170] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above and that the invention can be embodied in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered in all respects as illustrative and non-restrictive, and the scope of the invention is defined by the appended claims, not the foregoing description, and all variations within the meaning and range of equivalents of the claims are intended to be included therein. Any reference sign in a claim should not be construed as limiting the claim to which it relates.

Claims

1. A method for improving the uniformity of NAND block word lines and select transistors, characterized by: The following steps are involved: Step 1: In the NAND block, there are word lines and select transistors, both of which are the gates of the NAND block series channel. Use photolithography technology to transfer the pattern of the select transistor gate to the substrate material, and then use etching technology to convert the pattern into a three-dimensional structure; Step 2: During the layout design phase, the edge of the selector gate is set on the geometric centerline of the word line, and the gate and word line are made symmetrical during the processing; Step 3: Cover different numbers of word lines on the select tube gate according to the design requirements of NAND; Step 4: Remove the word line sacrificial layer. The sacrificial layer is a temporary layer used to protect the word line in subsequent processing steps. After removing the sacrificial layer, the word line is independent of other structures. Step 5: Perform subsequent etching on the select transistor gate. After etching is completed, the pattern of the select transistor gate is transferred to the substrate material, and the head and tail word lines are cut off; Step 6: After the etching and word line cutting steps are completed, the final pattern of the select tube is defined by exposing the pattern of the select tube at the edge away from the word line direction; Step 7: For the portion where the select tube overlaps with the word line, the final pattern of the select tube is defined by the edge of the word line that overlaps with the exposure pattern of the select tube in the direction close to the word line. Step 8: Based on the results of Steps 7 and 8, the distance between the final pattern of the select tube and the word line is defined by the word line exposure layer. The distance between the select tube and the word line is controlled by adjusting the size and position of the exposure layer. Step 9: After the exposure layer position and size are adjusted, the edge word lines are covered with selection tubes to transfer the unevenness of the edge word lines to the internal word lines.

2. The method for improving the uniformity of NAND block word lines and select transistors according to claim 1, characterized in that: The method of transferring the pattern of the selector gate to the substrate material using the photolithography technology and then converting the pattern into a three-dimensional structure using the etching technology includes the following steps: Step 1.1: Making an insulating layer: Select a base material, clean it, and perform surface treatment. Then, make a layer of insulating material on the base material to serve as the insulating layer for the selector gate. Step 1.2: Fabricate a photolithography mask: First, use an electronic design automation tool to design the pattern of the selector gate and generate a photolithography mask pattern. Then, fabricate the photolithography mask based on the designed pattern. Step 1.3: Photolithography: Place the fabricated photomask on the substrate and perform photolithography using light sources of different wavelengths, depending on the photolithography requirements, to chemically change the photoresist in the areas corresponding to the mask pattern. Step 1.4: Development step: Place the exposed substrate material into a developer to dissolve the exposed portion of the photoresist to form the pattern of the selector gate; Step 1.5: Etching step: Place the developed substrate material in an etching solution. According to the design requirements, use the etching solution to erode the pattern area on the substrate material and transfer the pattern defined by the photoresist to the substrate material.

3. The method for improving the uniformity of NAND block word lines and select transistors according to claim 1, characterized in that: Setting the edge of the selector gate on the geometric center line of the word line and making the gate symmetrical with the word line during the processing includes the following steps: Step 2.1: Design the wordline pattern and select transistor gate pattern: First, design the wordline pattern in electronic design automation software so that the geometric centerline of the wordline is clear and measurable. Then, design the select transistor gate pattern in the EDA software so that its edge is aligned with the geometric centerline of the wordline pattern. Step 2.2: Photolithography alignment: Use the high-precision alignment system of the photolithography machine to align the substrate material with the photolithography mask on the photolithography machine to accurately align the word line with the select tube gate pattern.

4. The method for improving the uniformity of NAND block word lines and select transistors according to claim 3, characterized in that: The method of covering different numbers of word lines on the select tube gate comprises the following steps: Step 3.1: Determine the coverage strategy: According to step 2.1 of claim 3, the design of the gate pattern of the selection tube is selected so that it can cover different numbers of word lines as needed; Step 3.2: Implement word line coverage: Form a first word line on the select tube gate, and the first word line covers a partial area of ​​the select tube gate. The partial area refers to setting the coverage ratio and width according to design requirements, rather than full coverage; Form a second word line on the first word line, and the second word line covers a partial area of ​​the first word line, and the width of the second word line is different from that of the first word line; Form a third word line on the second word line, and the third word line covers a partial area of ​​the second word line, and the width of the third word line is different from that of the second word line; Repeat the above steps until the required number of word lines are formed on the select tube gate.

5. The method for improving the uniformity of NAND block word lines and select transistors according to claim 1, wherein: The method of removing the word line sacrificial layer to make the word line independent of other structures includes the following steps: Step 4.1: Sacrificial layer design: After completing the selection transistor gate coverage in the previous step, design and form a sacrificial layer above the word line according to the design requirements; Step 4.2: Formation of sacrificial layer and protective layer: After the sacrificial layer design steps are completed, a sacrificial layer is formed on the word line using chemical vapor deposition and physical vapor deposition methods based on the design results. After the sacrificial layer is formed, a protective layer needs to be formed on the sacrificial layer. Step 4.3: Removing the sacrificial layer: Use a plasma etching process to remove the sacrificial layer; the removal method steps are as follows: first determine the etching rate and the position of the sacrificial layer, and monitor the etching rate and depth while performing the etching process; after the sacrificial layer is removed, further remove the protective layer to expose the independent word lines.

6. The method for improving the uniformity of NAND block word lines and select transistors according to claim 1, characterized in that: The subsequent etching of the selector gate, transferring the pattern of the selector gate to the substrate material after the etching is completed, and cutting the head and tail word lines include the following steps: Step 5.1: Selector Grid Pattern Transfer: First, based on the selector grid already formed on the substrate material, the selector grid pattern is prepared using electron beam lithography. Then, the selector grid is etched using plasma etching technology to transfer the pattern to the substrate material to form the desired three-dimensional structure. Step 5.2: Word line cutting: According to the design requirements, first determine the specific location of the word line cutting, then set the cutting path and mode in the cutting area, adjust the cutting parameters, and finally use plasma cutting technology to perform the cutting operation.

7. The method for improving the uniformity of NAND block word lines and select transistors according to claim 1, characterized in that: After the etching and word line cutting steps are completed, the final pattern of the select tube is defined by the select tube exposure pattern at the edge away from the word line direction, including the following: Step 6.1: Exposure pattern preparation: First, according to the design requirements of the selection tube, use CAD tools to design the outer edge pattern of the selection tube that meets the design requirements. Then, evenly apply photoresist on the substrate material, and use a drying process to control the thickness and quality of the photoresist. Step 6.2: Exposure and Development: After the exposure pattern is prepared, use a photolithography machine to expose the photoresist-coated substrate material, control the exposure dose and resolution, and match the outer edge pattern of the selected tube with the designed pattern; After exposure, the substrate material is placed in a developer solution for development operation; Step 6.3: Select tube edge etching: After the exposure and development steps are completed, the edges of the select tube gate away from the word line direction need to be etched according to the design requirements; The shape and size of the selector gate are controlled by adjusting the etching rate.

8. The method for improving the uniformity of NAND block word lines and select transistors according to claim 1, characterized in that: The method of defining the final pattern of the select tube by the edge of the word line overlapping the select tube exposure pattern in the direction close to the word line for the portion where the select tube overlaps with the word line includes the following steps: Step 7.1: Photolithography: Place a mask with the selector tube exposure pattern on the wafer for exposure. Then, place the exposed wafer in a developer to form the selector tube pattern. Finally, use an etchant to etch away the portion not protected by the photoresist, forming the selector tube structure on the wafer. Step 7.2: Alignment and overlap check: In the overlapping area of ​​the select tube and the word line, and in the direction close to the word line, the pattern of the select tube matches the edge of the word line. The high-precision alignment system of the lithography machine is required to confirm the position alignment of the select tube exposure pattern and the word line, and check the overlap between the two.

9. The method for improving the uniformity of NAND block word lines and select transistors according to claim 1, characterized in that: The final pattern of the selection tube and the distance between the word lines are defined by the word line exposure layer and include the following steps: Step 8.1: Adjust the size of the exposure layer pattern: Based on the design requirements, use electron beam lithography technology to control the size of the exposure layer pattern according to the design parameters. Then, use computer-aided design software to accurately design the exposure layer pattern. Utilizing the high resolution capability of the lithography machine, transfer the designed pattern to the exposure layer. Calculate the size of the exposure layer pattern using the following formula: L=D+σ L Where D represents the distance between the selection tube and the word line according to the design requirements, L represents the size of the exposure layer pattern, σ L Represents the margin reserved to take into account process deviations; Taking into account the optical diffraction effect during the photolithography process, the size of the exposure layer pattern is corrected using the following formula: L′=L+λsin(t) Where L′ represents the corrected exposure layer pattern size, λ represents the lithography wavelength, and t represents the diffraction angle; Step 8.2: Adjust the exposure layer pattern position: After the exposure layer pattern size is designed, fine-tune the exposure layer position in the horizontal and vertical directions. Then, use the alignment system of the lithography machine to mechanically position and align the two layers to control the spacing. Phase-shift exposure technology is also used to confirm the pattern position and spacing. For fine-tuning the exposure layer position, the new exposure layer position is calculated using the following formula: X′=X+σ X Where X is the original exposure layer position, X′ is the new exposure layer position, σ X is the fine-tuning amount; Taking into account the accuracy and error of the lithography machine alignment system, the following formula is used to correct the position of the exposure layer: X″=X′+ε Where X″ represents the position of the corrected exposure layer, and ε represents the error of the alignment system of the lithography machine; However, phase-shift exposure is achieved by adjusting the exposure dose and phase, and the position of the pattern after exposure is calculated using the following formula: X″′=X″+I·cos(ψ) Where X″′ represents the position of the pattern after exposure, I represents the exposure dose, and ψ represents the phase shift.

10. The method for improving the uniformity of NAND block word lines and select transistors according to claim 1, characterized in that: Covering the edge word lines with selection transistors to transfer the unevenness of the edge word lines to the inner word lines includes the following steps: Step 9.1: Edge word line design: After the exposure layer size and position are adjusted and the distance between the final tube pattern and the word line is confirmed, the layout and shape of the edge word line are designed according to the design requirements; Step 9.2: Selector Layout: After the edge word line design is completed, the size and shape of the selector tubes are planned according to the edge word line design requirements, and the position and layout of the selector tubes are further arranged; Step 9.3: Non-uniformity Transfer Mechanism: After completing the edge word line design and select tube layout according to the above steps, after the edge word lines are covered by the select tubes, use electrical testing methods to perform non-uniformity analysis on the edge word lines and select tubes to confirm the existing non-uniformity characteristics and distribution; Step 9.4: Transfer to internal word lines: Based on the analysis results of the non-uniformity mechanism, the non-uniformity is transferred by establishing a physical connection between the edge word lines and the internal word lines.

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