Semiconductor structure and its preparation method

Abstract

This invention provides a semiconductor structure and its fabrication method. By optimizing the device structure and setting the spacing between adjacent memory cells to be less than a preset spacing threshold, the device area is reduced. The source regions of each memory cell are connected by a doped layer to form a source line, requiring only one lead-out structure at one end of the source line, avoiding the fabrication process of multiple source-contact structures and reducing process risk. Each drain region is led out through a drain contact structure, and the drain contact structures of each memory cell are connected to form a bit line. The source lines and bit lines are perpendicularly distributed, improving process feasibility and reducing device area.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] Flash memory (also known as flash storage) is an electrically erasable programmable read-only memory (EEPROM) with characteristics such as non-volatility, fast read / write speeds, shock resistance, low power consumption, and small size. It is currently widely used in embedded systems. SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) flash memory is a simple and highly reliable memory. Its storage cells typically consist of a 2T structure composed of select transistors (SG) and memory transistors (MG), and it is widely used in embedded flash memory.

[0003] In the existing SONOS structure flash memory cell, a drain contact structure (DCT) is formed above the drain region on one side of the select transistor (SG), and an active contact structure (SCT) is formed above the source region between two adjacent memory transistors (MG). The drain contact structures (DCT) in each memory cell are connected to form a bit line (BL), and the source contact structures (SCT) in each memory cell are connected to form a source line (SL).

[0004] In pursuit of smaller memory cell area and lower manufacturing cost, the layout of forming source contact structures (SCTs) above the source regions between two adjacent memory cells (MGs) increases the memory cell area; and since a source contact structure (SCT) needs to be formed above the source regions between every two adjacent memory cells (MGs), the large number of these structures also increases process risk. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a semiconductor structure and its fabrication method, which can reduce the area of ​​memory cells and reduce process risks by optimizing the device structure.

[0006] To address the aforementioned problems, this invention provides a method for fabricating a semiconductor structure, comprising the following steps: forming a substrate, the substrate including a substrate, wherein an active region extending along a first direction and spaced apart along a second direction is defined in the substrate by a shallow trench isolation structure, a drain region and a source region are formed in the active region, and memory cells composed of select transistors and storage transistors are symmetrically arranged on the surface of the active region, the spacing between adjacent memory cells being less than a preset spacing threshold, wherein the first direction and the second direction are both parallel to the surface of the substrate, and the first direction intersects the second direction; etching away the shallow trench isolation structure in the region between adjacent memory cells to expose the substrate in that region; performing ion implantation on the region between adjacent memory cells to form a doped layer as a source line, the doped layer being continuously distributed along the second direction and connecting the source regions of each memory cell; and forming a drain contact structure above the drain region and contacting the drain region, and forming a connecting line as a bit line, the connecting line being continuously distributed along the first direction and connecting the drain contact structures in each memory cell.

[0007] To address the above problems, the present invention also provides a semiconductor structure, which is prepared using the preparation method described in the present invention.

[0008] The above technical solution reduces the device area by optimizing the device structure and setting the spacing between adjacent memory cells to be less than a preset spacing threshold. Each memory cell's source region is connected by a doped layer to form a source line, requiring only one lead-out structure at one end of the source line, avoiding the fabrication process of multiple source-contact structures and reducing process risk. Each drain region is led out through a drain contact structure, and the drain contact structures of each memory cell are connected to form a bit line. The source lines and bit lines are perpendicularly distributed, improving process feasibility and reducing the device area. Attached Figure Description

[0009] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 This is a schematic diagram of the flash memory layout of the existing SONOS architecture;

[0011] Figure 2 For along Figure 1 A sectional view of line A-A' in the middle;

[0012] Figure 3 This is a schematic diagram of the steps in a method for preparing a semiconductor structure according to an embodiment of the present invention;

[0013] Figure 4 This is a schematic diagram of the layout of a semiconductor structure according to an embodiment of the present invention;

[0014] Figure 5 The substrate edge provided in one embodiment of the present invention Figure 4 A sectional view of line B-B' in the middle;

[0015] Figure 6 The following is an embodiment of the present invention describing the formation of the ONO layer and the gate oxide layer: Figure 4 A sectional view of line B-B' in the middle;

[0016] Figure 7 The rear edge of the gate layer formation as described in one embodiment of the present invention Figure 4 A sectional view of line B-B' in the middle;

[0017] Figure 8 As described in one embodiment of the present invention, the protective sidewall is formed along the rear edge. Figure 4 A sectional view of line B-B' in the middle;

[0018] Figure 9 This is an embodiment of the present invention describing the etching removal of the leading edge of a shallow trench isolation structure. Figure 4 A sectional view of the C-C' line in the middle;

[0019] Figure 10 The etching removal of the shallow trench isolation structure according to an embodiment of the present invention is described below. Figure 4 A sectional view of the C-C' line in the middle;

[0020] Figure 11 The following describes the formation of the doped layer in one embodiment of the present invention. Figure 4 A sectional view of the C-C' line in the middle;

[0021] Figure 12 The following describes the formation of the leaky contact structure and the trailing edge of the connecting line in one embodiment of the present invention. Figure 4 A sectional view of line B-B' in the middle;

[0022] Figure 13 The formation of the lead-out structure is described in one embodiment of the present invention. Figure 4 A cross-sectional view of line C-C' in the middle. Detailed Implementation

[0023] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0024] like Figures 1-2 The existing SONOS structure flash memory shown has a 2T structure consisting of a select transistor (SG) and a memory transistor (MG), with the device formed on a silicon substrate. A shallow trench isolation structure (STI) is formed on the silicon substrate to isolate an active region AA. The active region AA has a strip-shaped structure, and an active region 101 and a drain region 102 are formed in the active region AA. An ONO layer 11 is formed between the first gate layer 13 of the memory transistor (MG) and the active region AA, and a gate oxide layer 12 is formed between the second gate layer 14 of the select transistor (SG) and the active region AA. Protective sidewalls 15 are formed on the sidewalls of both the select transistor (SG) and the memory transistor (MG). The first gate layer 13 and the second gate layer 14 are both made of polysilicon. A drain contact structure (DCT) 16 is formed above the drain region 102 on one side of the selector transistor (SG), and an active contact structure (SCT) 17 is formed above the source region 101 between two adjacent memory transistors (MG). The drain contact structures 16 in each memory cell are connected to form a bit line (not shown), and the source contact structures 17 in each memory cell are connected to form a source line (not shown).

[0025] The existing SONOS structure flash memory, with its source contact structure formed above the source region between two adjacent memory transistors, increases the memory cell area; furthermore, the large number of source contact structures required above the source region between each pair of adjacent memory transistors also increases process risk. To reduce the memory cell area and mitigate process risk, this invention provides a semiconductor structure and its fabrication method.

[0026] Please refer to the following: Figures 3 to 13 ,in, Figure 3 This is a schematic diagram of the steps in a method for preparing a semiconductor structure according to an embodiment of the present invention; Figure 4 This is a schematic diagram of the layout of a semiconductor structure according to an embodiment of the present invention;

[0027] Figure 5 The substrate edge provided in one embodiment of the present invention Figure 4 A sectional view of line B-B' in the middle; Figure 6 The following is an embodiment of the present invention describing the formation of the ONO layer and the gate oxide layer: Figure 4 A sectional view of line B-B' in the middle; Figure 7 The rear edge of the gate layer formation as described in one embodiment of the present invention Figure 4 A sectional view of line B-B' in the middle; Figure 8 As described in one embodiment of the present invention, the protective sidewall is formed along the rear edge. Figure 4 A sectional view of line B-B' in the middle; Figure 9 This is an embodiment of the present invention describing the etching removal of the leading edge of a shallow trench isolation structure. Figure 4 A sectional view of the C-C' line in the middle; Figure 10The etching removal of the shallow trench isolation structure according to an embodiment of the present invention is described below. Figure 4 A sectional view of the C-C' line in the middle;

[0028] Figure 11 The following describes the formation of the doped layer in one embodiment of the present invention. Figure 4 A sectional view of the C-C' line in the middle; Figure 12 The following describes the formation of the leaky contact structure and the trailing edge of the connecting line in one embodiment of the present invention. Figure 4 A sectional view of line B-B' in the middle; Figure 13 The formation of the lead-out structure is described in one embodiment of the present invention. Figure 4 A cross-sectional view of line C-C' in the middle.

[0029] like Figure 3 As shown, the semiconductor structure fabrication method described in this embodiment includes the following steps: S1, forming a substrate, the substrate including a substrate, wherein an active region extending along a first direction and spaced apart along a second direction is defined in the substrate by a shallow trench isolation structure, a drain region and a source region are formed in the active region, and memory cells composed of select transistors and memory transistors are symmetrically arranged on the surface of the active region, the spacing between two adjacent memory transistors being less than a preset spacing threshold; S2, etching away the shallow trench isolation structure in the region between two adjacent memory transistors to expose the substrate in that region; S3, performing ion implantation on the region between two adjacent memory transistors to form a doped layer as a source line, the doped layer being continuously distributed along the second direction and connecting the source regions of each memory cell; and S4, forming a drain contact structure above the drain region and contacting the drain region, and forming a connecting line as a bit line, the connecting line being continuously distributed along the first direction and connecting the drain contact structure in each memory cell.

[0030] For ease of explanation, in the following embodiments, the first direction D1 and the second direction D2 are both parallel to the substrate surface and intersect each other; the third direction D3 is perpendicular to the substrate surface (the third direction D3 is the device stacking direction) and intersects both the first direction D1 and the second direction D2. Specifically, the first direction D1 is the X-axis direction in the Cartesian coordinate system, the second direction D2 is the Y-axis direction in the Cartesian coordinate system, and the third direction D3 is the Z-axis direction in the Cartesian coordinate system.

[0031] Please refer to step S1 and Figure 8 A substrate is formed, the substrate including a substrate 40, wherein the substrate 40 is isolated by a shallow trench isolation structure STI (see reference). Figure 9As shown, an active region AA is defined, extending along a first direction D1 and spaced apart along a second direction D2. A drain region 402 and a source region 403 are formed within the active region AA. Symmetrically arranged memory cells, consisting of select transistors (SG) and memory transistors (MG), are formed on the surface of the active region. The spacing W1 between two adjacent memory transistors (MG) is less than a preset spacing threshold. This embodiment optimizes the device structure by setting the spacing W1 between two adjacent memory transistors (MG) to be less than the preset spacing threshold, thereby reducing the device area and lowering process risks.

[0032] In this embodiment, the step of forming the substrate specifically includes: (1) providing a substrate 40, the substrate 40 including a front side and a back side distributed opposite to each other, the front side of the substrate 40 being defined by a shallow trench isolation structure STI with active regions AA extending along a first direction D1 and spaced apart along a second direction D2, wherein drain regions 402 and source regions 403 are formed in the active regions AA, such as Figure 9 as well as Figure 5 As shown; (2) The ONO layer 41 of the storage transistor and the gate oxide layer 42 of the select transistor are formed on the surface of the active region AA, respectively, as shown. Figure 6 As shown; (3) depositing and etching polysilicon material to form the first gate layer 43 of the memory transistor on the surface of the ONO layer 41 and the second gate layer 44 of the select transistor on the surface of the gate oxide layer 42, as shown. Figure 7 As shown; (4) A protective sidewall 45 is formed on the sidewall of the selection tube and the storage tube, as shown. Figure 8 As shown.

[0033] The substrate 40 is used to support the device structure above it, and the device structure can also be formed in the substrate 40. In this embodiment, the substrate 40 may include a silicon (Si) substrate, a germanium (Ge) substrate, a silicon germanide (SiGe) substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate, etc.; the substrate 40 may also be a multilayer structure, such as a silicon / silicon-germanium multilayer, etc. This embodiment uses a silicon substrate as an example for illustration.

[0034] In this embodiment, the step of providing the substrate 40 specifically includes: (11) defining an active region AA extending along a first direction D1 and spaced along a second direction D2 on the front side of the substrate 40 by a shallow trench isolation structure STI; (12) performing a first ion implantation to form a deep well isolation layer 401 of a first conductivity type in the substrate 40 to isolate and protect the active region AA; (13) performing a second ion implantation to form a well region (not shown) of a second conductivity type in the active region AA; and (14) performing a third ion implantation to form a drain region 402 and a source region 403 of the first conductivity type in the well region. Specifically, the first conductivity type is P-type and the second conductivity type is N-type. N-type ion implantation is performed on the substrate to form a deep-well isolation layer. The shallow trench isolation structure (STI) and the deep-well isolation layer work together to effectively isolate and protect the active region AA. P-type ion implantation is performed in the active region to form a P-type well to adjust the threshold voltage. N-type ion implantation is performed in the P-type well to form a drain region 402 and a source region 403. The drain region 402 and the source region 403 are separated by a distance and are parallel to each other. The P-type well between the drain region 402 and the source region 403 forms a channel region. In other embodiments, the first conductivity type may be N-type and the second conductivity type may be P-type. In other embodiments, the drain region 402 and the source region 403 may also be formed in the P-type well under the self-alignment of the protective sidewall 45 of the select tube and the storage tube.

[0035] In this embodiment, the active region AA is a strip structure, and the shallow trench isolation structure STI is also a strip structure, which is arranged alternately with the active region AA.

[0036] In some embodiments, the ONO layer 41, the gate oxide layer 42, and the protective sidewall 45 are all formed using a thermal oxidation process.

[0037] In this embodiment, the steps of forming the ONO layer 41 of the memory transistor and the gate oxide layer 42 of the select transistor on the surface of the active region AA specifically include: (21) forming a first silicon oxide layer, a second silicon nitride layer and a third silicon oxide layer sequentially on the surface of the active region AA using a thermal oxidation process, and forming a tunnel oxide layer 411, a trap nitride layer 412 and a barrier oxide layer 413 as the ONO layer 41 by photolithography and etching; (22) forming a gate oxide material layer on the surface of the active region AA using a thermal oxidation process, and forming the gate oxide layer 42 by photolithography and etching, such as Figure 6As shown. The ONO layer 41 is formed from bottom to top by a stacked tunneling oxide layer 411, a trap nitride layer 412, and a barrier oxide layer 413. The memory transistor is formed from bottom to top by a stacked silicon substrate, a tunneling oxide layer, a trap nitride layer, a barrier oxide layer, and polysilicon; the select transistor is formed from bottom to top by a stacked silicon substrate, a gate oxide layer, and polysilicon. The thicknesses of the first silicon oxide (e.g., silicon dioxide) layer and the third silicon oxide (e.g., silicon dioxide) layer can both be less than the thickness of the second silicon nitride layer. The first silicon oxide layer covers the top surface of the substrate 40, which can prevent subsequent processes from damaging the top surface of the substrate 40. Silicon nitride is a commonly used and relatively good etching mask layer and barrier layer, which can protect the surface of the substrate 40 from damage.

[0038] In this embodiment, the step of forming a protective sidewall 45 on the sidewalls of the select tube and the storage tube specifically includes: growing a silicon dioxide layer on the sidewalls of the select tube and the storage tube as the protective sidewall 45 using a rapid thermal oxidation process, such as... Figure 8 As shown.

[0039] Please refer to step S2 and Figure 10 The shallow trench isolation structure (STI) in the region between two adjacent memory tubes is etched away to expose the substrate 40 in that region.

[0040] In this embodiment, the step of etching away the shallow trench isolation structure (STI) in the region between two adjacent memory transistors to expose the substrate 40 in that region specifically includes: (1) forming a photomask on the substrate surface, the photomask having an opening for exposing the shallow trench isolation structure in the region between two adjacent memory transistors; (2) using the photomask as a shield, etching away the shallow trench isolation structure in the region between two adjacent memory transistors along the opening to expose the substrate in that region. Specifically, the etching away of the shallow trench isolation structure in the region between two adjacent memory transistors is performed using a dry etching process.

[0041] In some embodiments, a mask layer and a photoresist layer can be formed on the substrate surface. The space between two adjacent memory transistors (MGs) on the photoresist layer is opened by photolithography, while other areas are covered, forming a patterned photoresist layer with a pattern that exposes the shallow trench isolation structure in the area between two adjacent memory transistors. The patterned photoresist layer is used as a mask to etch the mask layer, forming a patterned mask layer with an opening that exposes the shallow trench isolation structure in the area between two adjacent memory transistors. The shallow trench isolation structure (STI) in the opening area is cleanly etched by dry etching using the patterned mask layer as a mask, while the silicon substrate is not damaged or is minimally damaged.

[0042] Please refer to step S3 and Figure 11Ion implantation is performed on the region between two adjacent memory cells to form a doped layer 49 as a source line (SL). The doped layer 49 is continuously distributed along the second direction D2 and connects the source regions 403 of each memory cell (see reference). Figure 4 as well as Figure 12 Specifically, by ion implantation doping of the substrate in the space between the two memory cells (MGs) (after STI etching), the exposed substrate 40 surface, the sidewalls of the deep well isolation layer 401, and the active region AA sidewalls are doped to form a doped layer 49 as a source line (SL). The doped layer 49 is continuously distributed along the second direction D2 and connects the source regions 403 of each memory cell, avoiding the formation of multiple source-contact structures above the source regions between adjacent memory cells (MGs), thus reducing process risk; and the spacing W1 between adjacent memory cells (MGs) is less than a preset spacing threshold, reducing the device area.

[0043] In some embodiments, the resistance value of the source line is lower than a preset resistance threshold in the second direction D2. That is, by ion implantation doping, the surface of the substrate 40 exposed after etching between the two memory transistors (MG), the sidewall of the deep well isolation layer 401, and the sidewall of the active region AA are doped to a low resistance value to form a doped layer 49 as a source line (SL).

[0044] In some embodiments, the method further includes: forming a lead-out structure 47 in contact with the source line above one end of the source line in the second direction D2, such as... Figure 13 As shown. That is, in this embodiment, only one lead-out structure 47 needs to be formed at one end of the source line, avoiding the fabrication process of multiple source-contact structures and reducing process risks. Specifically, the lead-out structure 47 can be formed at the far end of the source line on an active region AA.

[0045] Please refer to step S4 and Figure 12 A drain contact structure 46 is formed above the drain region 402 and contacts the drain region 402, and a connecting line 48 is formed as a bit line (BL). The connecting line 48 is continuously distributed along the first direction D1 and connects the drain contact structure 46 in each memory cell.

[0046] In this embodiment, the source regions of each memory cell are connected by a doped layer 49 to form a source line (SL); each drain region is led out through a drain contact structure 46, and the drain contact structures 46 of each memory cell are connected to form a bit line (BL). In this embodiment, the source line (SL) and the bit line (BL) are perpendicularly distributed. The lead-out structure 47 and the drain contact structure 46 can be metallic structures of the material system.

[0047] The semiconductor structure fabrication method described in this embodiment can be applied to SONOS-structured flash memory, which has a simple structure and high reliability.

[0048] Based on the same inventive concept, an embodiment of the present invention also provides a semiconductor structure, which is prepared by the method described above.

[0049] Please refer to the following: Figure 4 , Figure 12 , Figure 13 This is a schematic diagram of a semiconductor structure provided in an embodiment of the present invention. Specifically, the semiconductor structure provided in this embodiment is prepared by the method described above in the present invention, and includes: a substrate 40, an active region AA, a drain region 402, a source region 403, a doped layer 49, a lead-out structure 47, a drain contact structure 46, and a connecting line 48.

[0050] In some embodiments, the substrate 40 has an active region AA extending along a first direction D1 and spaced apart along a second direction D2, defined by a shallow trench isolation structure STI; a drain region 402 and a source region 403 are formed in the active region AA; and symmetrically arranged memory cells, consisting of select transistors (SG) and memory transistors (MG), are formed on the surface of the active region. The spacing W1 between two adjacent memory transistors (MG) is less than a preset spacing threshold.

[0051] In some embodiments, a deep-well isolation layer is formed on the substrate by N-type ion implantation. The shallow trench isolation structure (STI) and the deep-well isolation layer work together to effectively isolate and protect the active region AA. A P-type well is formed in the active region by P-type ion implantation to adjust the threshold voltage. A drain region 402 and a source region 403 are formed in the P-type well by N-type ion implantation. The drain region 402 and the source region 403 are separated by a distance and are parallel to each other. The P-type well between the drain region 402 and the source region 403 forms a channel region. The active region AA has a strip structure, and the shallow trench isolation structure (STI) also has a strip structure and is arranged alternately with the active region AA.

[0052] In some embodiments, the ONO layer 41 is formed from bottom to top by a stacked tunneling oxide layer 411, a trap nitride layer 412, and a barrier oxide layer 413. The memory transistor is formed from bottom to top by a stacked silicon substrate, a tunneling oxide layer, a trap nitride layer, a barrier oxide layer, and polysilicon; the select transistor is formed from bottom to top by a stacked silicon substrate, a gate oxide layer, and polysilicon.

[0053] In some embodiments, the region between two adjacent memory cells is formed by ion implantation to create a doped layer 49 as a source line (SL). The doped layer 49 is continuously distributed along the second direction D2 and connects the source regions 403 of each memory cell. The shallow trench isolation structure (STI) in the region between two adjacent memory cells is etched away to form a groove on the substrate 40 exposing this region. The substrate in the space between two memory cells (the groove is formed after the STI is etched clean) is doped by ion implantation, and the exposed surface of the substrate 40, the sidewalls of the deep well isolation layer 401, and the sidewalls of the active region AA are doped to form the doped layer 49 as the source line (SL). An exit structure 47 is formed above one end of the source line in the second direction D2, contacting the source line.

[0054] In some embodiments, a drain contact structure 46 is formed above the drain region 402 and contacts the drain region 402, and a connecting line 48 is formed as a bit line (BL). The connecting line 48 is continuously distributed along the first direction D1 and connects the drain contact structure 46 in each memory cell.

[0055] In this embodiment, the semiconductor structure is a SONOS structure flash memory. SONOS structure flash memory is a simple and highly reliable memory, whose memory cells are typically a 2T structure composed of select transistors (SG) and memory transistors (MG), and is widely used in embedded flash memory.

[0056] By ion implanting the substrate in the space between two memory cells (after STI etching), the exposed substrate 40 surface, the sidewall of the deep well isolation layer 401, and the sidewall of the active region AA are doped to form a doped layer 49 as a source line (SL). The doped layer 49 is continuously distributed along the second direction D2 and connects the source regions 403 of each memory cell, avoiding the formation of multiple source-contact structures above the source regions between two adjacent memory cells (MG), thus reducing process risk; and the spacing W1 between two adjacent memory cells (MG) is less than a preset spacing threshold, reducing the device area.

[0057] Specifically, the substrate 40 is isolated by a shallow trench isolation structure (STI) (see reference). Figure 9 As shown, an active region AA is defined, extending along a first direction D1 and spaced apart along a second direction D2; a drain region 402 and a source region 403 are formed in the active region AA; and symmetrically arranged memory cells composed of select transistors (SG) and memory transistors (MG) are formed on the surface of the active region.

[0058] In the semiconductor structure fabricated in this embodiment, by optimizing the device structure and setting the spacing W1 between two adjacent memory transistors (MGs) to be less than a preset spacing threshold, the device area is reduced. The source regions of each memory cell are connected by a doped layer to form a source line, requiring only one lead-out structure at one end of the source line, avoiding the fabrication process of multiple source-contact structures and reducing process risk. Each drain region is led out through a drain contact structure, and the drain contact structures of each memory cell are connected to form a bit line. The source line (SL) and bit line (BL) are perpendicularly distributed, improving process feasibility and reducing the device area.

[0059] In the above description, descriptions of well-known components and technologies have been omitted to avoid unnecessarily obscuring the concept of the present invention. In the various embodiments described above, each embodiment focuses on its differences from other embodiments; similar or identical parts between embodiments can be referred to mutually.

[0060] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising a…" does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element. Additionally, embodiments and features thereof in this invention can be combined with each other without conflict.

[0061] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, The method includes the following steps: forming a substrate, the substrate including a substrate, wherein active regions extending along a first direction and spaced apart along a second direction are defined in the substrate by a shallow trench isolation structure, a deep well isolation layer is formed in the substrate below the active regions, drain regions and source regions are formed in the active regions, and memory cells composed of select transistors and memory transistors are symmetrically arranged on the surface of the active regions, the spacing between adjacent memory transistors is less than a preset spacing threshold, wherein the first direction and the second direction are both parallel to the surface of the substrate, and the first direction and the second direction intersect; etching away the shallow trench isolation structure in the region between adjacent memory transistors to expose the substrate in that region; and separating the region between adjacent memory transistors. Sub-implantation forms a doped layer as a source line. The doped layer is continuously distributed along a second direction and connects the source regions of each memory cell. The continuous distribution of the doped layer along the second direction specifically includes: the doped layer as a source line continuously covering the substrate surface, deep well isolation layer sidewall, and active region sidewall exposed after etching away the shallow trench isolation structure in the area between two adjacent memory cells; and forming a drain contact structure above the drain region and contacting the drain region, and forming a connecting line as a bit line. The connecting line is continuously distributed along a first direction and connects the drain contact structure in each memory cell. The continuous distribution of the connecting line along the first direction specifically includes: the connecting line as a bit line connecting the drain region in the memory cell and bridging the adjacent memory cells.

2. The method according to claim 1, characterized in that, The step of forming the substrate specifically includes: providing a substrate, the substrate including a front side and a back side distributed opposite to each other, the front side of the substrate defining an active region extending along a first direction and spaced apart along a second direction by a shallow trench isolation structure, wherein a drain region and a source region are formed in the active region; forming an ONO layer of the memory transistor and a gate oxide layer of the select transistor on the surface of the active region respectively; depositing and etching polysilicon material to form a first gate layer of the memory transistor on the surface of the ONO layer and a second gate layer of the select transistor on the surface of the gate oxide layer respectively; and forming protective sidewalls on the sidewalls of the select transistor and the memory transistor.

3. The method according to claim 2, characterized in that, The step of providing a substrate specifically includes: defining an active region extending along a first direction and spaced apart along a second direction on the front side of the substrate by means of a shallow trench isolation structure; performing a first ion implantation to form a deep well isolation layer of a first conductivity type in the substrate to isolate and protect the active region; performing a second ion implantation to form a well region of a second conductivity type in the active region; and performing a third ion implantation to form a drain region and a source region of a first conductivity type in the well region.

4. The method according to claim 3, characterized in that, The first conductivity type is P-type, and the second conductivity type is N-type; or the first conductivity type is N-type, and the second conductivity type is P-type.

5. The method according to claim 2, characterized in that, The steps of forming the ONO layer of the memory transistor and the gate oxide layer of the select transistor on the surface of the active region specifically include: forming a first silicon oxide layer, a second silicon nitride layer and a third silicon oxide layer sequentially on the surface of the active region using a thermal oxidation process, and forming a tunneling oxide layer, a trap nitride layer and a barrier oxide layer as the ONO layer by photolithography and etching; forming a gate oxide material layer on the surface of the active region using a thermal oxidation process, and forming the gate oxide layer by photolithography and etching.

6. The method according to claim 2, characterized in that, The step of forming a protective sidewall on the sidewalls of the select tube and the storage tube specifically includes: growing a silicon dioxide layer on the sidewalls of the select tube and the storage tube as the protective sidewall using a rapid thermal oxidation process.

7. The method according to claim 1, characterized in that, The step of etching away the shallow trench isolation structure in the region between two adjacent memory transistors to expose the substrate in that region specifically includes: forming a photomask on the surface of the substrate, the photomask having an opening for exposing the shallow trench isolation structure in the region between two adjacent memory transistors; using the photomask as a shield, etching away the shallow trench isolation structure in the region between two adjacent memory transistors along the opening to expose the substrate in that region.

8. The method according to claim 1 or 7, characterized in that, The etching process used to remove the shallow trench isolation structure in the area between two adjacent memory tubes employs a dry etching process.

9. The method according to claim 1, characterized in that, In the second direction, the resistance value of the source line is lower than a preset resistance threshold.

10. The method according to claim 1, characterized in that, The method further includes: forming a lead-out structure in contact with the source line above one end of the source line in the second direction.

11. A semiconductor structure, characterized in that, The semiconductor structure is prepared by the semiconductor structure preparation method according to any one of claims 1 to 10.

12. The semiconductor structure according to claim 11, characterized in that, The semiconductor structure is a SONOS structure flash memory.

Images