FeRAM storage unit preparation method based on FDSOI technology and electronic equipment
By using the FDSOI process to prepare substrates and other structures in FeRAM memory cells, the problems of reduced performance and increased power consumption of FeRAM memory cells during process reduction are solved, and higher durability and lower power consumption are achieved.
Patent Information
- Application Number
- CN202411461873.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-18
- Publication Date
- 2025-02-18
AI Technical Summary
In the field of semiconductor technology, FeRAM memory cells face problems such as decreasing ferroelectric performance and residual polarization strength, increasing manufacturing process complexity and increased chip power consumption when the process is reduced.
Using the FeRAM memory cell preparation method based on the FDSOI process, the substrate is prepared by the FDSOI process, the gate oxide layer is grown on the substrate, and the gate, source and drain are prepared thereon, and iron connected to the source is finally prepared. Capacitor.
This method effectively reduces the impact on ferroelectric performance and residual polarization strength, reduces manufacturing cost and chip power consumption, and improves the durability and performance of FeRAM memory cells.
Smart Images
Figure CN119486145A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular to a method for preparing a FeRAM storage unit based on a FDSOI process and an electronic device. Background Art
[0002] Among related technologies, with the continuous advancement of semiconductor technology, ferroelectric random access memory (FeRAM) has the potential to become one of the key technologies for next-generation storage solutions. Compared with traditional non-volatile memories such as Flash and EEPROM, the read time of ferroelectric random access memory is 10-50 times faster, the erase time is 5-50 times faster, and the number of writes is 10 times faster. 10 Compared with other new non-volatile memories, the erasure time of ferroelectric random access memory is faster than PRAM and NRAM, the write power consumption is better than MRAM, PRAM and RRAM, and the number of write times is also more than other new non-volatile memories.
[0003] At present, FeRAM chips are manufactured using Bulk CMOS, and their structure is as follows: Figure 2 As the process size decreases, the following problems will arise:
[0004] First, the ferroelectric layer needs to be thinner to accommodate smaller transistor sizes, which can affect its ferroelectric properties and residual polarization strength;
[0005] Second, the complexity of the manufacturing process increases due to the reduction in process size, which may increase the manufacturing cost;
[0006] Third, due to the short channel effect, as the process size decreases, leakage current will increase, thereby increasing the power consumption of the chip.
[0007] In summary, the technical problems existing in the relevant technologies need to be improved. Summary of the invention
[0008] The main purpose of the embodiments of the present application is to propose a method for preparing a FeRAM storage unit based on the FDSOI process and an electronic device, which can effectively reduce the impact on ferroelectric properties and residual polarization strength, and reduce manufacturing costs and chip power consumption.
[0009] To achieve the above object, an embodiment of the present application provides a method for preparing a FeRAM memory cell based on a FDSOI process, the method comprising the following steps:
[0010] Prepare the substrate by FDSOI process;
[0011] growing a gate oxide layer on the substrate;
[0012] preparing a gate on the gate oxide layer;
[0013] Prepare a source electrode and a drain electrode on both sides of the gate;
[0014] A ferroelectric capacitor is prepared, wherein the ferroelectric capacitor is connected to the source electrode.
[0015] In some embodiments, the step of preparing the substrate by using a FDSOI process includes:
[0016] preparing a silicon substrate;
[0017] preparing a buried oxide layer on the silicon substrate;
[0018] A top silicon layer is formed on the buried oxide layer, and a thickness of the top silicon layer is adjusted by the FDSOI process.
[0019] In some embodiments, after preparing the substrate by the FDSOI process, the method further comprises the following steps:
[0020] The substrate is cleaned and polished.
[0021] In some embodiments, after cleaning and polishing the substrate, the method further comprises the following steps:
[0022] A channel is formed above the top silicon layer, and the gate oxide layer is an insulating layer between the gate and the channel.
[0023] In some embodiments, the step of preparing a gate on the gate oxide layer includes:
[0024] depositing a gate material over the gate oxide layer;
[0025] The gate material is processed by photolithography and etching processes to obtain the gate.
[0026] In some embodiments, preparing a source and a drain on both sides of the gate includes:
[0027] Ion implantation of source and drain is performed in the top silicon layer on both sides of the gate to obtain the source and drain.
[0028] In some embodiments, the step of preparing a ferroelectric capacitor comprises:
[0029] The lower electrode of the ferroelectric capacitor is prepared by sputtering and subjected to rapid thermal annealing;
[0030] depositing a layer of iron film on the upper side of the lower electrode;
[0031] The lower electrode of the ferroelectric capacitor is prepared on the iron film by sputtering, and the lower electrode is connected to the source electrode.
[0032] To achieve the above object, another aspect of an embodiment of the present application provides a FeRAM memory cell, the FeRAM memory cell is prepared by the above method, and the FeRAM memory cell includes a FDSOI transistor and a ferroelectric capacitor;
[0033] The FDSOI transistor comprises a substrate, a gate oxide layer, a gate, a source and a drain; the gate oxide layer is located above the substrate, the gate is located above the gate oxide layer, the source penetrates the gate and is connected to a source doping region next to the substrate, and the drain penetrates the gate and is connected to a drain doping region next to the substrate;
[0034] The ferroelectric capacitor comprises an upper electrode, an iron film and a lower electrode; the iron film is located above the upper electrode, the lower electrode is located above the iron film, and the lower electrode is connected to the source electrode.
[0035] In some embodiments, the FeRAM memory cell further includes a channel; the channel is located between the substrate and the gate oxide layer.
[0036] To achieve the above objective, another aspect of an embodiment of the present application provides an electronic device, which includes the above FeRAM storage unit.
[0037] The embodiments of the present application include at least the following beneficial effects: The present application provides a method for preparing a FeRAM memory cell based on the FDSOI process and an electronic device. The method of the present application prepares a substrate through the FDSOI process, grows a gate oxide layer on the substrate, prepares a gate on the gate oxide layer, prepares a source and a drain on both sides of the gate, and prepares a ferroelectric capacitor connected to the source, so that the FDSOI process can be used to optimize the transistor structure, thereby improving the durability of the FeRAM memory cell, reducing the leakage current and static power consumption of the FeRAM memory cell, effectively reducing the impact on the ferroelectric performance and residual polarization strength, and reducing the manufacturing cost. BRIEF DESCRIPTION OF THE DRAWINGS
[0038] Figure 1 It is a flow chart of a method for preparing a FeRAM storage unit based on the FDSOI process provided in an embodiment of the present application;
[0039] Figure 2 It is a schematic diagram of the structure of the FeRAM chip prepared by the existing process;
[0040] Figure 3 It is a schematic diagram of the structure of the FeRAM storage unit provided in an embodiment of the present application. DETAILED DESCRIPTION
[0041] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application is further described in detail below in conjunction with the accompanying drawings and examples. It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the embodiments of the present application, they are only examples of devices and methods consistent with some aspects of the embodiments of the present application.
[0042] It is understood that the terms "first", "second", etc. used in this application can be used to describe various concepts in this article, but unless otherwise specified, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another concept. For example, without departing from the scope of the embodiment of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the words "if" and "if" as used herein can be interpreted as "at the time of" or "when" or "in response to determination".
[0043] The terms "at least one", "multiple", "each", "any", etc. used in this application, at least one includes one, two or more, multiple includes two or more, each refers to each of the corresponding multiple, and any refers to any one of the multiple.
[0044] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.
[0045] Before describing the embodiments of the present application in detail, some nouns and terms involved in the embodiments of the present application are first described. The nouns and terms involved in the embodiments of the present application are subject to the following interpretations:
[0046] Bulk CMOS refers to an integrated circuit (IC) manufacturing process, where CMOS is an abbreviation for Complementary Metal Oxide Semiconductor. This process is commonly used to manufacture field effect transistors (FETs) in integrated circuits, especially complementary metal oxide semiconductor field effect transistors (CMOS FETs). In bulk CMOS processes, bulk refers to manufacturing transistors inside the silicon wafer, rather than on the surface. This process usually involves forming the source, drain, and gate in the bulk of the silicon wafer, rather than in a thin film on the surface.
[0047] Among related technologies, with the continuous advancement of semiconductor technology, ferroelectric random access memory (FeRAM) has the potential to become one of the key technologies for next-generation storage solutions. Compared with traditional non-volatile memories such as Flash and EEPROM, the read time of ferroelectric random access memory is 10-50 times faster, the erase time is 5-50 times faster, and the number of writes is 10 times faster. 10 Compared with other new non-volatile memories, the erasure time of ferroelectric random access memory is faster than PRAM and NRAM, the write power consumption is better than MRAM, PRAM and RRAM, and the number of write times is also more than other new non-volatile memories.
[0048] The process node of ferroelectric memory has gradually developed from 0.5μm to 130nm and 90nm. With the further development of the process, the traditional Bulk CMOS process faces many challenges, such as Figure 2 As shown in FIG. 1 , the FeRAM memory cell prepared by the Bulk CMOS process includes a substrate, a source doped region, a source, a drain doped region, a drain and a gate. In the application process, the source is connected to the ferroelectric capacitor as a plate line (PL), the drain is used as a bit line (BL), and the gate is used as a word line (WL). However, when the FeRAM memory cell (Ferroelectric Random Access Memory) is prepared by the Bulk CMOS process, the following problems will occur as the process is reduced:
[0049] First, the ferroelectric layer needs to be thinner to accommodate smaller transistor sizes, which can affect its ferroelectric properties and residual polarization strength;
[0050] Second, the complexity of the manufacturing process increases due to the reduction in process size, which may increase the manufacturing cost;
[0051] Third, due to the short channel effect, as the process size decreases, leakage current will increase, thereby increasing the power consumption of the chip.
[0052] In view of this, the present application provides a method for preparing a FeRAM memory cell based on an FDSOI process and an electronic device. The method prepares a substrate through an FDSOI process, grows a gate oxide layer on the substrate, prepares a gate on the gate oxide layer, prepares a source and a drain on both sides of the gate, and prepares a ferroelectric capacitor connected to the source, so that the FDSOI process can be used to optimize the transistor structure, thereby improving the durability of the FeRAM memory cell, reducing the leakage current and static power consumption of the FeRAM memory cell, effectively reducing the impact on ferroelectric performance and residual polarization strength, and reducing manufacturing costs.
[0053] Figure 1is an optional flow chart of a method for preparing a FeRAM storage unit based on the FDSOI process provided in an embodiment of the present application. Figure 1 The method may include but is not limited to steps S101 to S106.
[0054] Step S110, preparing a substrate by using a FDSOI process;
[0055] Step S120, growing a gate oxide layer on the substrate;
[0056] Step S130, preparing a gate on the gate oxide layer;
[0057] Step S140, preparing a source electrode and a drain electrode on both sides of the gate;
[0058] Step S150: preparing a ferroelectric capacitor, wherein the ferroelectric capacitor is connected to the source electrode.
[0059] In an embodiment of the present application, the process of preparing a substrate by a FDSOI (Fully Depleted Silicon on Insulator) process can be achieved by selecting an SOI wafer of suitable quality as the substrate. Specifically, a silicon substrate is first prepared, a buried oxide layer is prepared on the silicon substrate, and a top silicon layer is prepared on the buried oxide layer. The thickness of the top silicon layer is adjusted by the FDSOI process to achieve a full power exhaustion mode. After the substrate is prepared by the FDSOI process, the substrate is cleaned and polished to ensure that the surface is free of impurities and defects, laying a good foundation for subsequent processes. In addition, after the substrate is cleaned and polished, a channel is prepared above the top silicon layer.
[0060] It is understandable that when growing the gate oxide layer on the substrate, a high-quality gate oxide layer may be grown on the top silicon layer as an insulating layer between the gate and the channel.
[0061] In an embodiment of the present application, in the process of preparing a gate on a gate oxide layer, a gate material may be first deposited on the gate oxide layer, and then the gate material may be processed by photolithography and etching processes to obtain a gate. The gate material may be a polysilicon material. Then a source and a drain are prepared on both sides of the gate. Specifically, ions of the source and drain may be implanted into the top silicon on both sides of the gate to form a source-drain region, and then the source-drain regions on both sides of the top silicon are used as source-level doping regions and drain-level doping regions, respectively, and the source-drain regions located in the gate region are used as source and drain, respectively.
[0062] In the embodiment of the present application, when preparing a ferroelectric capacitor, the lower electrode of the ferroelectric capacitor can be prepared by sputtering and subjected to rapid thermal annealing, a layer of iron film is deposited on the lower electrode, and then the lower electrode of the ferroelectric capacitor is prepared on the iron film by sputtering. The lower electrode is connected to the source electrode to form the core part of the FRAM storage unit.
[0063] In summary, the method provided in the embodiments of the present application has the following beneficial effects:
[0064] First, improve durability. This embodiment optimizes the transistor structure through FDSOI technology to improve the durability of the FeRAM storage unit and withstand multiple erase and write cycles.
[0065] Second, reduce power consumption. This embodiment optimizes the transistor structure through FDSOI technology to reduce leakage current and static power consumption.
[0066] Third, performance improvement: This embodiment improves the subthreshold characteristics of transistors through FDSOI technology, reduces the static power consumption of the circuit, and increases the device frequency.
[0067] Fourth, reduce interference. This embodiment uses FDSOI technology to reduce noise and interference in the circuit, thereby improving the integrity and reliability of data during FeRAM application.
[0068] Reference Figure 3 , the present application embodiment provides a FeRAM storage unit, the FeRAM storage unit through Figure 1 Specifically, Figure 3 As shown, the FeRAM storage unit includes an FDSOI transistor and a ferroelectric capacitor; the FDSOI transistor includes a substrate, a gate oxide layer 320, a gate 330, a source 341 and a drain 342; the gate oxide layer 320 is located above the substrate, the gate 330 is located above the gate oxide layer 320, the source 341 penetrates the gate 330 and is connected to a source doping region 343 next to the substrate, and the drain 342 penetrates the gate 330 and is connected to a drain doping region 344 next to the substrate; the ferroelectric capacitor includes an upper electrode 361, an iron film 362 and a lower electrode 363; the iron film 362 is located above the upper electrode 361, the lower electrode 363 is located above the iron film 362, and the lower electrode 363 is connected to the source.
[0069] It is understandable that if Figure 3 As shown, the substrate includes a silicon substrate 311, a buried oxide layer (BOX layer) 312 and a top silicon layer (SOI layer) 313, wherein the buried oxide layer 312 is located above the silicon substrate 311, and the top silicon layer 313 is located above the buried oxide layer 312. The FeRAM memory cell also includes a channel 350; the channel 350 is located between the substrate and the gate oxide layer 320.
[0070] It can be understood that the contents of the above method embodiments are all applicable to this unit embodiment, the functions specifically implemented by this unit embodiment are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.
[0071] In addition, an embodiment of the present application further provides an electronic device, the electronic device comprising Figure 3 The FeRAM memory cell is shown in FIG. Figure 1 Prepared by the method shown.
[0072] It can be understood that the contents of the above method embodiments are all applicable to the present device embodiments, the functions specifically implemented by the present device embodiments are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.
[0073] The embodiments described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. Those skilled in the art will appreciate that with the evolution of technology and the emergence of new application scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.
[0074] Those skilled in the art will appreciate that the technical solutions shown in the figures do not constitute a limitation on the embodiments of the present application, and may include more or fewer steps than shown in the figures, or a combination of certain steps, or different steps.
[0075] The device embodiments described above are merely illustrative, and the units described as separate components may or may not be physically separated, that is, they may be located in one place or distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
[0076] Those skilled in the art will appreciate that all or some of the steps in the methods disclosed above, and the functional modules / units in the systems and devices may be implemented as software, firmware, hardware, or a suitable combination thereof.
[0077] The terms "first", "second", "third", "fourth", etc. (if any) in the specification of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.
[0078] It should be understood that in the present application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.
[0079] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the above units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.
[0080] The units described above as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
[0081] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.
[0082] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including multiple instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (Read-Only Memory, referred to as ROM), random access memory (Random Access Memory, referred to as RAM), disk or optical disk and other media that can store programs.
[0083] The preferred embodiments of the present invention are described above with reference to the accompanying drawings, but the scope of the rights of the present invention is not limited thereto. Any modification, equivalent substitution and improvement made by a person skilled in the art without departing from the scope and essence of the present invention should be within the scope of the rights of the present invention.
Claims
1. A method for preparing a FeRAM storage unit based on FDSOI process, characterized in that: The method comprises the following steps: Prepare the substrate by FDSOI process; growing a gate oxide layer on the substrate; preparing a gate on the gate oxide layer; Prepare a source electrode and a drain electrode on both sides of the gate; A ferroelectric capacitor is prepared, wherein the ferroelectric capacitor is connected to the source electrode.
2. The method according to claim 1, characterized in that: The method of preparing the substrate by using the FDSOI process comprises: preparing a silicon substrate; preparing a buried oxide layer on the silicon substrate; A top silicon layer is prepared on the buried oxide layer, and the thickness of the top silicon layer is adjusted by the FDSOI process.
3. The method according to claim 2, characterized in that After the substrate is prepared by the FDSOI process, the method further comprises the following steps: The substrate is cleaned and polished.
4. The method according to claim 3, characterized in that After the substrate is cleaned and polished, the method further comprises the following steps: A channel is formed above the top silicon layer, and the gate oxide layer is an insulating layer between the gate and the channel.
5. The method according to claim 2, characterized in that: The step of preparing a gate on the gate oxide layer comprises: depositing a gate material over the gate oxide layer; The gate material is processed by photolithography and etching processes to obtain the gate.
6. The method according to claim 2, characterized in that The step of preparing a source electrode and a drain electrode on both sides of the gate comprises: Ion implantation of source and drain is performed in the top silicon layer on both sides of the gate to obtain the source and drain.
7. The method according to claim 1, characterized in that The method for preparing a ferroelectric capacitor comprises: The lower electrode of the ferroelectric capacitor is prepared by sputtering and subjected to rapid thermal annealing; depositing a layer of iron film on the upper side of the lower electrode; The lower electrode of the ferroelectric capacitor is prepared on the iron film by sputtering, and the lower electrode is connected to the source electrode.
8. A FeRAM storage cell, characterized in that: The FeRAM memory cell is prepared by the method according to any one of claims 1 to 7, and the FeRAM memory cell comprises a FDSOI transistor and a ferroelectric capacitor; The FDSOI transistor comprises a substrate, a gate oxide layer, a gate, a source and a drain; the gate oxide layer is located above the substrate, the gate is located above the gate oxide layer, the source penetrates the gate and is connected to a source doping region next to the substrate, and the drain penetrates the gate and is connected to a drain doping region next to the substrate; The ferroelectric capacitor comprises an upper electrode, an iron film and a lower electrode; the iron film is located above the upper electrode, the lower electrode is located above the iron film, and the lower electrode is connected to the source electrode.
9. The FeRAM memory cell according to claim 8, characterized in that: The FeRAM storage cell further comprises a channel; the channel is located between the substrate and the gate oxide layer.
10. An electronic device, characterized in that: The electronic device comprises the FeRAM storage unit according to claim 8 or 9.