Deep trench silicon capacitor and preparation method thereof

Abstract

The invention provides a deep trench silicon capacitor and a preparation method thereof. The deep trench silicon capacitor provided by the invention comprises a substrate, a periodic conductive layer, an insulation protection layer, a first electrode and a second electrode, and the upper surface of the substrate is provided with a trench; a periodic conducting layer is sequentially deposited on the groove in the direction away from the lower surface of the substrate, an insulating protection layer is deposited on the periodic conducting layer and the upper surface to fill the groove, and two through holes are formed in the insulating protection layer to expose the two ends of the periodic conducting layer; wherein the periodic conductive layer comprises a plurality of first metal layers, a plurality of dielectric layers and a plurality of second metal layers; the first electrode is arranged on the periodic conductive layer and is connected with the first metal layer through the first through hole; the second electrode is arranged on the periodic conductive layer and is connected with the second metal layer through the second through hole. According to the deep trench silicon capacitor and the preparation method thereof provided by the invention, the storable capacitance value is remarkably improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a deep trench silicon capacitor and a method for preparing the same. Background Art

[0002] In the rapid development of integrated circuits, capacitors, as important passive devices, are widely used in filtering, energy storage, and storage. As the performance requirements of integrated circuits continue to increase, the demand for the capacitance value of capacitors is increasing.

[0003] The planar MIM (Metal-Insulator-Metal) capacitor is a capacitor with a simple structure, consisting of two layers of metal with a dielectric layer in between. Its manufacturing process is relatively simple, but due to area limitations, the capacitance value is not high, and it is difficult to meet the needs of high-integration, high-performance integrated circuits. In order to solve the problem of low capacitance value of MIM capacitors, a capacitor containing grooves is proposed. The grooves of the capacitor significantly increase the effective capacitance area of ​​the capacitor area.

[0004] However, the existing preparation process of deep trench capacitors is not only very complicated, but also the manufacturing cost is high. Therefore, how to develop capacitors with simple process and low cost has become a problem that needs to be solved urgently. Summary of the invention

[0005] In view of this, the present application provides a deep trench silicon capacitor and a method for manufacturing the same, which significantly improves the capacitance value that can be stored.

[0006] Specifically, the present application is implemented through the following technical solutions: The first aspect of the present application provides a deep trench silicon capacitor, the deep trench silicon capacitor comprising a substrate, a periodic conductive layer, an insulating protection layer, a first electrode and a second electrode, wherein: A groove is formed on the upper surface of the substrate; when viewed from a direction away from the substrate, the groove and the upper surface form an inverted trapezoidal shape that is smaller at the bottom and larger at the top, and the sidewall angle of the inverted trapezoid is an acute angle; The periodic conductive layer is deposited on the groove in a direction away from the lower surface of the substrate, and an insulating protective layer is deposited on the periodic conductive layer and the upper surface to fill the groove, and two through holes are provided on the insulating protective layer to expose two ends of the periodic conductive layer; The periodic conductive layer includes multiple first metal layers, multiple dielectric layers and multiple second metal layers; the dielectric layer is used to isolate the first metal layer and the second metal layer; The first electrode is disposed on the periodic conductive layer and connected to the first metal layer via a first through hole; the second electrode is disposed on the periodic conductive layer and connected to the second metal layer via a second through hole.

[0007] A second aspect of the present application provides a method for manufacturing a deep trench silicon capacitor, the method being applied to the deep trench silicon capacitor described in the first aspect, the method comprising: Forming a barrier layer on a substrate, and etching the barrier layer to form a groove pattern based on a photolithography process; the substrate is made of a first material; Based on the target etching liquid, the first material is etched according to the groove pattern to obtain an inverted trapezoidal groove; the target etching liquid has a higher than a first specified value for different crystal orientations of the first material, and the method for etching the first material is an anisotropic wet etching method; Alternately depositing multiple layers of first metal material, multiple layers of dielectric material and multiple layers of second metal material on the groove to obtain a periodic conductive layer; Etching the first metal material on one side, and etching the second metal material on the other side; Depositing a protective material on the etched substrate to form an insulating protective layer; The insulating protection layer is etched to obtain two through holes, and a first electrode and a second electrode are formed on the through holes to obtain the prepared deep trench silicon capacitor.

[0008] The first aspect of the present application provides a deep trench silicon capacitor, which is made by an anisotropic wet etching method, and combined with a multilayer film deposition technology, a deep trench silicon capacitor with a high capacitance value is realized. The effective capacitance area of ​​the capacitor region is effectively increased by the deep trench structure, so that the capacitance of the deep trench silicon capacitor can be much higher than that of the traditional flat MIM capacitor, even more than 1000 times higher. Further, by reducing the difficulty of the manufacturing process, the depth and sidewall uniformity of the groove of the deep trench silicon capacitor are well controlled, reducing the problem of poor uniformity of the capacitance value of the deep trench silicon capacitor on the wafer, thereby improving the yield of the deep trench silicon capacitor. Further, because the sidewall angle of the inverted trapezoid is an acute angle, the film can be more easily and completely coated on the groove during the deposition process, with better step coverage, avoiding the generation of voids, and helping to deposit thicker and more layers of film, improving the stability and reliability of the deep trench silicon capacitor. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 A schematic diagram of a deep trench silicon capacitor according to an exemplary embodiment of the present application; Figure 2 A schematic diagram of a groove according to an exemplary embodiment of the present application; Figure 3 A schematic diagram of a periodic conductive layer shown in an exemplary embodiment of the present application; Figure 4 A schematic diagram of a through hole shown in an exemplary embodiment of the present application; Figure 5 A schematic diagram of a first embodiment of a method for manufacturing a deep trench silicon capacitor according to an exemplary embodiment of the present application; Figure 6 A schematic diagram of a substrate shown as an exemplary embodiment of the present application; Figure 7 A schematic diagram of a barrier layer shown as an exemplary embodiment of the present application; Figure 8 A schematic diagram of a groove pattern shown in an exemplary embodiment of the present application; Fig. 9 A schematic diagram of a trench after etching according to an exemplary embodiment of the present application; Fig.10 A schematic diagram of a periodic conductive layer according to another exemplary embodiment of the present application; Fig.11 A schematic diagram of a first etching region shown in an exemplary embodiment of the present application; Fig.12 A schematic diagram of an etching result of a first metal material shown in an exemplary embodiment of the present application; Fig.13 A schematic diagram of a second etching region shown in an exemplary embodiment of the present application; Fig.14 A schematic diagram of the etching result of the second metal material shown in an exemplary embodiment of the present application; Fig.15 A schematic diagram of a periodic conductive layer etching result shown in an exemplary embodiment of the present application; Fig.16 This is a schematic diagram of an insulating protective layer according to an exemplary embodiment of the present application.

[0010] Description of reference numerals: 1: base; 2: Periodic conductive layer; 3: Insulation protection layer; 4: first electrode; 5: second electrode; 11: Groove; 21: first metal layer; 22: dielectric layer; 23: second metal layer; 31: first through hole; 32: Second through hole. DETAILED DESCRIPTION

[0011] Here, exemplary embodiments are described in detail, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application.

[0012] The terms used in this application are only for the purpose of describing specific embodiments and are not intended to limit this application. The singular forms of "a", "said" and "the" used in this application are also intended to include plural forms, unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used in this article refers to and includes any or all possible combinations of one or more associated listed items.

[0013] It should be understood that although the terms first, second, third, etc. may be used in the present application to describe various information, these information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0014] Specific embodiments are given below to introduce the deep trench silicon capacitor provided by the present application in detail.

[0015] The deep trench silicon capacitor provided in this embodiment includes a substrate 1, a periodic conductive layer 2, an insulating protection layer 3, a first electrode 4 and a second electrode 5, wherein: A groove 11 is formed on the upper surface of the substrate 1; viewed from a direction away from the substrate 1, the groove 11 and the upper surface form an inverted trapezoidal shape that is smaller at the bottom and larger at the top, and the sidewall angle of the inverted trapezoid is an acute angle; The periodic conductive layer 2 is deposited on the groove 11 in a direction away from the lower surface of the substrate 1, and an insulating protective layer 3 is deposited on the periodic conductive layer 2 and the upper surface to fill the groove 11, and two through holes are provided on the insulating protective layer 3 to expose two ends of the periodic conductive layer; The periodic conductive layer 2 includes multiple first metal layers 21, multiple dielectric layers 22 and multiple second metal layers 23; the dielectric layer 22 is used to isolate the first metal layer 21 and the second metal layer 23; the number of the first metal layer 21 and the number of the second metal layer 23 differ by at most one layer; The first electrode 4 is disposed on the periodic conductive layer 2 and connected to the first metal layer 21 via a first through hole 31 ; the second electrode 5 is disposed on the periodic conductive layer 2 and connected to the second metal layer 23 via a second through hole 32 .

[0016] Figure 1 This is a schematic diagram of a deep trench silicon capacitor according to an exemplary embodiment of the present application. Figure 1 The substrate 1 refers to the basic part of the entire deep trench silicon capacitor structure. On the basis of the substrate 1, all subsequent process steps will be carried out to form a deep trench silicon capacitor.

[0017] Furthermore, the specific material of the substrate 1 is determined according to actual needs, and is not limited in this embodiment. In specific implementation, the substrate 1 can be made of a silicon wafer.

[0018] Optionally, the substrate 1 is made of a silicon wafer with a 100 crystal orientation.

[0019] Furthermore, the trench 11 formed on the substrate 1 by etching and other processes is the core part of the deep trench silicon capacitor structure. The depth, width, shape and other parameters of the trench 11 have an important influence on the performance of the deep trench silicon capacitor.

[0020] Figure 2 This is a schematic diagram of a groove according to an exemplary embodiment of the present application. Figure 2 , looking downward from the upper surface of the substrate 1 , the opening of the groove 11 on the upper surface is larger than the bottom, presenting a shape of being smaller at the bottom and larger at the top.

[0021] It should be noted that the groove 11 can be made based on the anisotropic wet etching method. In this way, the depth and sidewall uniformity of the groove 11 are ensured to be good by the anisotropic wet etching method. Compared with the traditional deep silicon etching process, it is often difficult to maintain the consistency of the depth, opening size and groove sidewall on the whole wafer, resulting in the shortcomings of poor uniformity of capacitance value and low yield. The anisotropic wet etching effectively solves this problem by accurately controlling the etching process. At the same time, compared with the traditional deep silicon etching process, the anisotropic wet etching method simplifies the process flow, reduces the process difficulty, and can more easily achieve uniformity control without sacrificing the depth and sidewall quality of the groove 11, thereby improving the yield and production efficiency of the product. It is understandable that the anisotropic wet etching method indirectly improves the process window of the entire process by improving the uniformity of the groove 11 and the deposition quality of the film. In this way, under the same process conditions, higher quality products can be obtained, while reducing the sensitivity to process parameters and improving the flexibility and stability of the capacitor.

[0022] Optionally, at least one side surface of the groove on the long side of the substrate is an ascending slope, so that the groove presents a morphology of being small at the bottom and large at the top in the short side direction; and the sidewall angle is 54.7 degrees.

[0023] Specifically, the sidewall angle is the angle between the sidewall of the groove 11 and the upper surface of the substrate 1. It can be understood that the sidewall angle is an acute angle, and by setting the sidewall angle to 54.7 degrees, when a film is deposited on the groove 11, the film will be more easily and completely coated on the groove 11, which is conducive to obtaining better step coverage and avoiding the generation of voids when depositing the film, and thicker and more layers of film can be deposited.

[0024] Furthermore, the substrate 1 includes an upper surface and a lower bottom surface, the size and shape of the upper surface are the same as the size and shape of the lower bottom surface, and the upper surface and the ground are parallel to each other. The angle between the left hypotenuse of the groove 11 and the upper surface is an acute angle, and the angle between the right hypotenuse of the groove 11 and the upper surface is also an acute angle. The two hypotenuses and the upper surface form a groove that is larger at the top and smaller at the bottom, and the bottom plane of the groove 11 is also parallel to the upper surface.

[0025] Optionally, each layer of the first metal layer 21 and the second metal layer 23 are arranged in parallel, and the first metal layer 21 and the second metal layer 23 are inverted trapezoidal, and the length of one end of the first hypotenuse of each first metal layer 21 close to the upper surface of the substrate 1 is shorter than that of the second metal layer 23, and the length of one end of the second hypotenuse of each first metal layer 21 close to the upper surface of the substrate 1 is shorter than that of the second metal layer 23, and the first hypotenuse of each first metal layer 21 is flush with the upper surface through an insulating medium, and the second hypotenuse of each second metal layer 23 is flush with the upper surface through an insulating medium.

[0026] Specifically, the left hypotenuse of the first metal layer 21 and the second metal layer 23 is the first hypotenuse, and the length of the first metal layer 21 close to the upper surface of the substrate 1 in the first hypotenuse is shorter than the length of the second metal layer 23 at the first hypotenuse; the left hypotenuse of the first metal layer 21 and the second metal layer 23 is the second hypotenuse, and the length of the second metal layer 23 close to the upper surface of the substrate 1 in the second hypotenuse is shorter than the length of the first metal layer 21 at the first hypotenuse.

[0027] For further information, please refer to Figure 1 The periodic conductive layer 2 is composed of alternating metal layers and dielectric layers 22, forming a structure similar to a multilayer capacitor. It should be noted that these layers are repeated periodically in the vertical direction to increase the capacitance value.

[0028] Furthermore, the periodic conductive layer 2 may be formed by alternating two metals, and the different metals are separated by a dielectric layer 22 .

[0029] It should be noted that the number of the first metal layer 21 and the second metal layer 23 is determined according to the capacitance value required in actual use. In specific implementation, when a higher capacitance value is required, more first metal layers 21 and second metal layers 23 can be set to meet the actual use requirements.

[0030] Optionally, the metal materials of the first metal layer and the second metal layer have different etching selectivities for two metal etching solutions.

[0031] Specifically, the specific materials of the first metal layer 21 and the second metal layer 23 are determined according to actual needs, and are not limited in this embodiment. In specific implementation, the first metal layer 21 and the second metal layer 23 can be made of different metal materials, which are selected according to their chemical stability and reaction rate in a specific etching solution. For example, the first metal layer 21 can be made of aluminum (Al), and the second metal layer 23 can be made of titanium (Ti).

[0032] It should be noted that the first metal layer 21 and the second metal layer 23 have different etching selectivities. In other words, under the same etching conditions, the first metal layer 21 is etched at different rates relative to the second metal layer 23. In this embodiment, materials with greatly different etching selectivities need to be selected to make the first metal layer 21 and the second metal layer 23, so as to ensure that when one material is etched, the other material is less affected.

[0033] Furthermore, the specific material of the dielectric layer 22 is determined according to actual needs, and is not limited in this embodiment.

[0034] Optionally, the dielectric layer 22 is composed of one or more of silicon oxide, silicon nitride, silicon oxynitride, magnesium oxide, aluminum oxide, hafnium oxide, tantalum oxide, and barium strontium titanate.

[0035] Specifically, by selecting an insulating material to make the dielectric layer 22 , it is possible to prevent the first metal layer 21 and the second metal layer 23 from being short-circuited with each other, so as to form a capacitor structure.

[0036] Figure 3 This is a schematic diagram of a periodic conductive layer shown in an exemplary embodiment of the present application. Figure 3 , a periodic conductive layer 2 and an insulating protection layer 3 are sequentially filled on the groove 11 so that the groove 11 is completely filled.

[0037] Furthermore, the insulating protection layer 3 is deposited on the periodic conductive layer 2 and is used to protect the underlying periodic conductive layer 2 to prevent the electrical properties of the periodic conductive layer 2 from being affected.

[0038] Furthermore, the through-hole is a hole made on the insulating protection layer 3, which is used to connect the underlying periodic conductive layer 2 with an external circuit.

[0039] It should be noted that the position and size of the through hole are set according to the shape and position of the periodic conductive layer. In specific implementation, since the groove 11 is an inverted trapezoidal morphology with a small bottom and a large top, each layer of the periodic conductive layer 2 includes two left and right oblique edges and a horizontal edge at the bottom. Therefore, in order to connect the electrode to each layer of the periodic conductive layer 2, the through hole can be set just above the oblique edge of the groove 11.

[0040] Furthermore, through holes are formed by etching on the insulating protection layer 3, which allow current to flow from the electrode through the periodic conductive layer 2 to the first metal layer 21 and the second metal layer 23, thereby achieving electrical connection between the electrode and the internal structure of the capacitor.

[0041] Figure 4 This is a schematic diagram of a through hole according to an exemplary embodiment of the present application. Figure 4 , the first through hole 31 is located above the hypotenuse on the left, and the second through hole 32 is located above the hypotenuse on the right.

[0042] Optionally, the first through hole 31 and the second through hole 32 are arranged in the insulating protection layer 3 deposited at a position where no groove is opened on the upper surface of the substrate 1, and the length of each layer of the first metal layer 21 at the first through hole 31 is shorter than the length of the second metal layer 23; the length of each layer of the second metal layer 23 at the second through hole 32 is shorter than the length of the first metal layer 21.

[0043] For details, please continue to refer to Figure 4 , the first metal layer 21 on the left hypotenuse of the periodic conductive layer 2 is selectively etched so that the length of the first metal layer 21 on the left hypotenuse is shorter than the length of the second metal layer 23. Similarly, the second metal layer 23 on the right hypotenuse of the periodic conductive layer 2 is selectively etched so that the length of the second metal layer 23 on the right hypotenuse is shorter than the length of the first metal layer 21.

[0044] Furthermore, the length of the first metal layer 21 at the first through hole 31 is shorter than that of the second metal layer 23, so when the first electrode 4 is deposited in the first through hole 31, the first electrode 4 can directly contact the second metal layer 23 without contacting the first metal layer 21; similarly, the length of the second metal layer 23 at the second through hole 32 is shorter than that of the first metal layer 21, so when the second electrode 5 is deposited in the second through hole 32, the second electrode 5 can directly contact the first metal layer 21 without contacting the second metal layer 23.

[0045] It can be understood that since the length of the first metal layer 21 on the left hypotenuse is shorter than the length of the second metal layer 23, when the insulating protective layer 3 is deposited, the first metal layer 21 will be filled with the insulating protective layer 3, resulting in the first metal layer 21 being unable to contact the first electrode 4, and the first metal layer 21 and the first electrode 4 will not be energized; similarly, since the length of the second metal layer 23 on the right hypotenuse is shorter than the length of the first metal layer 21, when the insulating protective layer 3 is deposited, the second metal layer 23 will be filled with the insulating protective layer 3, resulting in the second metal layer 23 being unable to contact the second electrode 5, and the second metal layer 23 and the second electrode 5 will not be energized.

[0046] The deep trench silicon capacitor provided in this embodiment has an insulating protective layer deposited on the periodic conductive layer to protect the internal conductive layer from the influence of the external environment. At the same time, there are two through holes on the insulating protective layer to expose the two ends of the periodic conductive layer. This design ensures that the first electrode and the second electrode can be accurately connected to the metal layer below, so as to achieve good electrical connection. Further, the effective capacitance area of ​​the capacitor is increased by the design of the deep groove, so that the capacitance value is much higher than the traditional flat MIM capacitor. Further, the design of the periodic conductive layer ensures the conductivity of the capacitor and the stability of the capacitance value, and the setting of the insulating protective layer and the through hole ensures good connection and electrical isolation between the electrode and the internal metal layer. In this way, the combined effect of the various aspects of the deep trench silicon capacitor achieves high capacitance, low process difficulty and good electrical performance.

[0047] Corresponding to the aforementioned embodiment of a deep trench silicon capacitor, the present application also provides an embodiment of a method for manufacturing a deep trench silicon capacitor.

[0048] Figure 5 This is a schematic diagram of a method for manufacturing a deep trench silicon capacitor according to an exemplary embodiment of the present application. Figure 5 , the method provided in this embodiment includes: S501, forming a barrier layer on a substrate, and etching the barrier layer to form a groove pattern based on a photolithography process; the substrate is made of a first material.

[0049] Specifically, the specific material of the first material is determined according to actual needs, and is not limited in this embodiment.

[0050] In specific implementation, a silicon wafer with a crystal orientation of 100 may be selected as the first material, and better groove uniformity can be obtained through the silicon wafer with this crystal orientation during the anisotropic wet etching process.

[0051] Figure 6 This is a schematic diagram of a substrate according to an exemplary embodiment of the present application. Figure 6 , the first material is made into a rectangular parallelepiped as a substrate.

[0052] S502, etching the first material according to the groove pattern based on a target etching solution to obtain an inverted trapezoidal groove; the target etching solution has a higher than a first specified value for different crystal orientations of the first material, and the method for etching the first material is an anisotropic wet etching method.

[0053] Specifically, the target etching solution matches the first material and is used to etch the first material.

[0054] It should be noted that the specific composition of the target etching solution is determined according to actual needs, and is not limited in this embodiment. In specific implementation, a material with an etching selectivity ratio of more than 100 for different crystal directions in a silicon wafer can be used as the target etching solution. For example, in one embodiment, the target etching solution is potassium hydroxide KOH. For another example, in another embodiment, the target etching solution is tetramethylamino hydroxide TMAH.

[0055] During specific implementation, in this step, a barrier layer needs to be formed on the substrate first. Figure 7 This is a schematic diagram of a barrier layer shown in an exemplary embodiment of the present application. Figure 7 , forming a barrier layer on the substrate. It should be noted that the specific material of the barrier layer is determined according to actual needs, and is not limited in this embodiment. In specific implementation, silicon oxide, silicon dioxide or other materials with a high etching selectivity ratio with silicon can be used to make the barrier layer.

[0056] Furthermore, the pattern of the trench can be defined on the barrier layer. In specific implementation, the pattern of the trench is formed according to the upper surface shape of the trench required by the deep trench silicon capacitor. Figure 8 This is a schematic diagram of a groove pattern shown in an exemplary embodiment of the present application. Figure 8 , the upper surface of the groove is rectangular, so the barrier layer on the groove forms a rectangular groove pattern.

[0057] In specific implementation, a photolithography process can be used to define a groove pattern on a photoresist, and then the photoresist is used as a mask layer of the barrier layer to etch the barrier layer. It should be noted that the barrier layer can be etched based on dry etching or wet etching, which is not limited in this embodiment.

[0058] Furthermore, after the etching of the barrier layer is completed, the photoresist is removed, and the barrier layer is used as a hard mask layer of the substrate, and anisotropic wet etching is performed based on the target etching solution. Fig. 9 This is a schematic diagram of a trench after etching according to an exemplary embodiment of the present application. Fig. 9 After etching, an inverted trapezoidal groove with a larger top and a smaller bottom appears on the substrate, and the side wall angle of the groove is 54.7 degrees.

[0059] Furthermore, after the groove is obtained, the barrier layer is removed, and the groove morphology obtained after removal is as follows: Figure 2 In specific implementation, the barrier layer may be etched based on dry etching or wet etching, which is not limited in this embodiment.

[0060] S503 , alternately depositing multiple layers of first metal material, multiple layers of dielectric material, and multiple layers of second metal material on the groove to obtain a periodic conductive layer.

[0061] Specifically, multiple layers of first metal material, multiple layers of dielectric material and multiple layers of second metal material can be alternately deposited based on a physical vapor deposition (PVD) method, or multiple layers of first metal material, multiple layers of dielectric material and multiple layers of second metal material can be alternately deposited based on a chemical vapor deposition (CVD) method. This is not limited in this embodiment.

[0062] Furthermore, the first metal material and the second metal material have different etching selectivity ratios for two different etching solutions, respectively. It should be noted that the specific materials of the first metal material and the second metal material are determined according to actual needs, and are not limited in this embodiment. In specific implementation, for example, in one embodiment, aluminum can be selected as the first metal material and titanium can be selected as the second metal material. For another example, in another embodiment, chromium can be selected as the first metal material and platinum can be selected as the second metal material. For another example, in yet another embodiment, molybdenum can be selected as the first metal material and copper can be selected as the second metal material.

[0063] A specific embodiment is given below to introduce the formation process of the periodic conductive layer in detail: (1) The first metal material, the dielectric material and the second metal material are alternately deposited based on physical vapor deposition or chemical vapor deposition to obtain the periodic conductive layer.

[0064] (2) Depositing the protective material on the periodic conductive layer to obtain a structure with a flat upper surface.

[0065] Specifically, a layer of protective material is deposited on the periodic conductive layer. It should be noted that the specific material of the protective material is selected according to actual needs, and is not limited in this embodiment. In specific implementation, silicon dioxide can be selected as the protective layer. Fig.10 This is a schematic diagram of a periodic conductive layer shown in another exemplary embodiment of the present application. Fig.10 , forming a protective layer on the periodic conductive layer.

[0066] Further, the multilayer film material and the protective layer are ground until the upper surface of the substrate is exposed. Figure 3 shown.

[0067] It should be noted that a grinder may be used to grind the protective layer on the periodic conductive layer, or a chemical mechanical grinding device may be used to grind the protective layer on the periodic conductive layer, which is not limited in this embodiment.

[0068] S504: Etch the first metal material on one side, and etch the second metal material on the other side.

[0069] Specifically, etching is performed using etching solutions with high selectivity to the first metal material and the second metal material, respectively. Thus, due to the high selectivity, only one metal is etched away during the etching process, while the other metal and the dielectric layer are retained.

[0070] A specific embodiment is given below to introduce in detail the process of etching the first metal material and the second metal material: (1) A first etching region and a second etching region are defined on the periodic conductive layer; the first etching region and the second etching region are used to expose the first metal layer and the second metal layer.

[0071] (2) etching the first etching region and the second etching region in sequence based on a first metal etching solution and a second metal etching solution; wherein an etching selectivity ratio of the first metal etching solution for etching the first metal material and the second metal material is greater than a first preset ratio, and an etching selectivity ratio of the second metal etching solution for etching the second metal material and the first metal material is greater than a second preset ratio.

[0072] Specifically, a photoresist is formed on the periodic conductive layer, and the left periodic conductive layer is exposed through the photoresist. Fig.11 This is a schematic diagram of the first etching area shown in an exemplary embodiment of the present application. Fig.11 , a first etching area on the left side is defined on the photoresist based on a photolithography process.

[0073] It should be noted that the specific values ​​of the first preset ratio and the second preset ratio are set according to actual needs, and are not limited in this embodiment. In specific implementation, the first preset ratio and the second preset ratio can be set to 5:1. For example, in one embodiment, when the first metal etching solution is used for etching, the first preset ratio is 6:1. Since the etching selectivity is relatively large, the first metal material is mainly etched, and the second metal material is less etched; similarly, when the second metal etching solution is used for etching, the second preset ratio is 7:1. Since the etching selectivity is relatively large, the second metal material is mainly etched, and the first metal material is less etched.

[0074] Furthermore, the photoresist is used as an etching mask layer, and an etching solution having a high etching selectivity ratio to the first metal material is selected for etching, so that the first metal material is etched by the etching solution, while the second metal material and the dielectric material are retained. Fig.12 This is a schematic diagram of the etching result of the first metal material shown in an exemplary embodiment of the present application. Fig.12 , in the first etching area, the first metal material is etched.

[0075] Furthermore, a photoresist is formed on the periodic conductive layer, and the right periodic conductive layer is exposed through the photoresist. Fig.13 This is a schematic diagram of a second etching area according to an exemplary embodiment of the present application. Fig.13 , a second etching area on the left side is defined on the photoresist based on the photolithography process.

[0076] Similarly, using the photoresist as an etching mask layer, an etchant having a high etching selectivity ratio to the second metal material is selected for etching, so that the second metal material is etched by the etchant, while the first metal material and the dielectric material are retained. Fig.14 This is a schematic diagram of the etching result of the second metal material shown in an exemplary embodiment of the present application. Fig.14 , in the second etching area, the second metal material is etched.

[0077] Further, the photoresist is removed to obtain a periodic conductive layer after etching. Fig.15 shown. Fig.15 This is a schematic diagram showing the etching result of a periodic conductive layer according to an exemplary embodiment of the present application.

[0078] S505 , depositing a protective material on the etched substrate to form an insulating protective layer.

[0079] Specifically, a layer of protective material is deposited on the etched substrate to cover the entire device surface to form an insulating protective layer, which protects the internal conductive layer from the influence of the external environment.

[0080] It should be noted that the specific material of the protective material is determined according to actual needs, and is not limited in this embodiment. For example, in one embodiment, silicon dioxide can be selected as the protective material.

[0081] Fig.16 This is a schematic diagram of an insulating protective layer shown in an exemplary embodiment of the present application. Fig.16 The periodic conductive layer is covered by an insulating protective layer to prevent interference from external electrical signals of the capacitor.

[0082] S506, etching the insulating protection layer to obtain two through holes, forming a first electrode and a second electrode on the through holes, and obtaining the prepared deep trench silicon capacitor.

[0083] Specifically, a photolithography process is used to define openings on the left and right sides of the insulating protective layer, and then a photoresist is used as a mask layer of the insulating protective layer to etch and remove the insulating protective layer at the opening. It should be noted that the insulating protective layer can be removed by wet etching or dry etching, which is not limited in this embodiment.

[0084] Furthermore, after removing the photoresist, the bottoms of the through holes of the left and right insulating protection layers will expose the first metal layer and the second metal layer respectively. Figure 4 shown.

[0085] For further information, please refer to Figure 4 , because the first metal layer at the first through hole is etched, only the second metal layer is exposed at the first through hole, while the first metal layer is not exposed; similarly, the second metal layer at the second through hole is etched, resulting in only the first metal layer being exposed at the second through hole, while the second metal layer is not exposed. Therefore, after electrodes are formed on the first through hole and the second through hole, the first electrode corresponding to the first through hole only contacts the second metal layer, and the second electrode corresponding to the second through hole only contacts the first metal layer.

[0086] In specific implementation, Figure 4 An odd number of layers are deposited on the provided deep trench silicon capacitor, and then the region of the first electrode and the region of the second electrode are defined based on a photolithography process. Then, the redundant metal layer is removed by etching, leaving the first electrode at the first through hole and the second electrode at the second through hole, so as to obtain a prepared deep trench silicon capacitor such as Figure 1 shown.

[0087] It should be noted that the excess metal layer may be etched based on a wet etching technique or may be etched based on a dry etching technique, which is not limited in this embodiment.

[0088] The deep trench silicon capacitor manufacturing method provided in this embodiment effectively increases the effective capacitance area of ​​the capacitor region by forming a deep trench structure, thereby significantly improving the capacitance value of the capacitor. Further, the groove is made by anisotropic wet etching method, so that the depth and sidewall uniformity of the groove are good, the process difficulty is reduced, and the consistency of the capacitor capacitance value on the entire wafer is improved, thereby improving the yield of the product. Further, since the groove sidewall angle is 54.7°, when the film is deposited in the groove, the film can be more easily and completely coated on the groove, avoiding the generation of pores, ensuring the step coverage of the film, and facilitating the deposition of thicker and more layers of film. Further, by using a high selectivity metal etching solution, different metal layers can be etched off on different sides respectively without the need for complex alignment and punching processes, thereby simplifying the entire process flow and improving production efficiency. Further, the deposition of the insulating protective layer and the production process of the first electrode and the second electrode ensure the electrical performance and reliability of the capacitor, so that the prepared deep trench silicon capacitor has better application potential. In this way, deep trench silicon capacitors with high capacitance, high consistency and high reliability can be easily prepared.

[0089] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A deep trench silicon capacitor, characterized in that: The deep trench silicon capacitor comprises a substrate, a periodic conductive layer, an insulating protection layer, a first electrode and a second electrode, wherein: A groove is formed on the upper surface of the substrate; when viewed from a direction away from the substrate, the groove and the upper surface form an inverted trapezoidal shape that is smaller at the bottom and larger at the top, and the sidewall angle of the inverted trapezoid is an acute angle; The periodic conductive layer is deposited on the groove in a direction away from the lower surface of the substrate, and an insulating protective layer is deposited on the periodic conductive layer and the upper surface to fill the groove, and two through holes are provided on the insulating protective layer to expose two ends of the periodic conductive layer; The periodic conductive layer includes multiple first metal layers, multiple dielectric layers and multiple second metal layers; the dielectric layer is used to isolate the first metal layer from the second metal layer; the number of the first metal layer and the number of the second metal layer differ by at most one layer; The first electrode is disposed on the periodic conductive layer and connected to the first metal layer via a first through hole; the second electrode is disposed on the periodic conductive layer and connected to the second metal layer via a second through hole.

2. The deep trench silicon capacitor according to claim 1, characterized in that: The first through hole and the second through hole are arranged in the insulating protection layer deposited at a position on the upper surface of the substrate where no groove is opened, and the length of each first metal layer at the first through hole is shorter than the length of the second metal layer; the length of each second metal layer at the second through hole is shorter than the length of the first metal layer.

3. The deep trench silicon capacitor according to claim 1, wherein: The first metal layer and the second metal layer of each layer are arranged in parallel, and the first metal layer and the second metal layer are in an inverted trapezoid. The length of one end of the first hypotenuse of each first metal layer close to the upper surface of the substrate is shorter than that of the second metal layer, and the length of one end of the second hypotenuse of each first metal layer close to the upper surface of the substrate is shorter than that of the second metal layer. The first hypotenuse of each first metal layer is flush with the upper surface through an insulating medium, and the second hypotenuse of each second metal layer is flush with the upper surface through an insulating medium.

4. The deep trench silicon capacitor according to claim 1, wherein: At least one side surface of the groove on the substrate on the long side is an ascending slope, so that the groove presents a morphology of being small at the bottom and large at the top in the short side direction; the sidewall angle is 54.7 degrees.

5. The deep trench silicon capacitor according to claim 1, wherein: The metal materials of the first metal layer and the second metal layer have different etching selectivities for two metal etching solutions.

6. The deep trench silicon capacitor according to claim 1, wherein: The substrate is made of a silicon wafer with a 100-degree crystal orientation, and the dielectric layer is composed of one or more of silicon oxide, silicon nitride, silicon oxynitride, magnesium oxide, aluminum oxide, hafnium oxide, tantalum oxide, and barium strontium titanate.

7. A method for manufacturing a deep trench silicon capacitor, characterized in that: The method is applied to the deep trench silicon capacitor according to any one of claims 1 to 6, and the method comprises: Forming a barrier layer on a substrate, and etching the barrier layer to form a groove pattern based on a photolithography process; the substrate is made of a first material; Using a target etching liquid to etch the first material according to the groove pattern to obtain an inverted trapezoidal groove; the target etching liquid has a higher than a first specified value for different crystal orientations of the first material, and the method for etching the first material is an anisotropic wet etching method; Alternately depositing multiple layers of first metal material, multiple layers of dielectric material and multiple layers of second metal material on the groove to obtain a periodic conductive layer; Etching the first metal material on one side, and etching the second metal material on the other side; Depositing a protective material on the etched substrate to form an insulating protective layer; The insulating protection layer is etched to obtain two through holes, and a first electrode and a second electrode are formed on the through holes to obtain the prepared deep trench silicon capacitor.

8. The method according to claim 7, characterized in that The first metal material and the second metal material have different etching selectivities; and the step of alternately depositing multiple layers of the first metal material, multiple layers of the dielectric material, and multiple layers of the second metal material on the groove to obtain a periodic conductive layer comprises: Alternately depositing the first metal material, the dielectric material and the second metal material based on physical vapor deposition or chemical vapor deposition to obtain the periodic conductive layer; The protective material is deposited on the periodic conductive layer to obtain a structure with a flat upper surface.

9. The method according to claim 7, characterized in that: The etching of the first metal material on one side and the etching of the second metal material on the other side includes: Defining a first etching region and a second etching region on the periodic conductive layer; the first etching region and the second etching region are used to expose the first metal layer and the second metal layer; The first etching region and the second etching region are etched in sequence based on a first metal etching solution and a second metal etching solution; wherein the etching selectivity ratio of the first metal etching solution for etching the first metal material and the second metal material is greater than a first preset ratio, and the etching selectivity ratio of the second metal etching solution for etching the second metal material and the first metal material is greater than a second preset ratio.

10. The method according to claim 7, characterized in that The step of etching the insulating protection layer to obtain two through holes, forming a first electrode and a second electrode on the through holes, and obtaining the prepared deep trench silicon capacitor comprises: Determine the position of the through hole based on the oblique side of the groove, and etch the insulating protection layer until the first metal material and the second metal material are exposed; Electrode material is deposited, and excess electrode material is etched away to generate the first electrode and the second electrode on the left and right sides.

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