Semiconductor device and preparation method thereof

Abstract

The invention discloses a semiconductor device and a preparation method thereof, and the device comprises the components of a semiconductor structure which is provided with a first metal layer; a first isolation layer covering the first metal layer; the MIM capacitor structure comprises a lower pole plate, a dielectric layer and an upper pole plate, the lower pole plate covers part of the first isolation layer, so that an exposed area is formed on the surface of the first isolation layer, the dielectric layer covers the lower pole plate, and the upper pole plate covers part of the dielectric layer; the second isolation layer covers the MIM capacitor structure and the exposed region; and a second metal layer covering the second isolation layer, the lower electrode plate is connected with the first metal layer through a first via hole arranged in the first isolation layer. The upper electrode plate is connected with the second metal layer through a second via hole arranged in the second isolation layer. According to the invention, the connection between the upper pole plate and the metal layer above and the connection between the lower pole plate and the metal layer below are realized through the via holes arranged at different sides, so that the horizontal cross-sectional areas of the upper pole plate and the lower pole plate are closer, and the waste of MIM capacitance is avoided.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor device manufacturing, and in particular to a semiconductor device and a method for preparing the same. Background Art

[0002] As an important component of semiconductor devices, MIM (Metal insulator metal) capacitors have the advantages of high Q value and linearity, small loss, and high withstand voltage. They are widely used in radio frequency integrated circuits and hybrid integrated circuits.

[0003] Existing MIM capacitor structures such as Figure 1 As shown, it includes a lower plate 10a, an upper plate 30a, and a dielectric layer 20a located between the upper plate 30a and the lower plate 10a, and interconnects the upper and lower plates with other metal layers through vias arranged on the same side, and connecting vias of other metal layers are realized by etching with a high aspect ratio. However, in its manufacturing process, there are usually the following problems:

[0004] 1. When microchannel interconnection technology is used to connect the lower plate, in order to avoid the risk of damage to the dielectric layer caused by the etching process of the microchannel and thus causing capacitor leakage current, the right end of the lower plate is usually extended beyond the right end of the upper plate by a large distance, but this will result in a waste of capacitor capacitance and reduce the capacitance of the capacitor.

[0005] 2. MIM capacitors are usually grown between two metal layers. Due to the flatness requirements of the upper and lower plates and the need for MIM structure, the thickness between the two metal layers usually reaches more than 6kA. Therefore, high aspect ratio etching of interconnected microchannels and simultaneous etching of multiple depths have become the main technical challenges in the preparation of MIM capacitors. Summary of the invention

[0006] The object of the present invention is to provide a semiconductor device and a method for preparing the same. The method of the present invention realizes the connection between an upper electrode plate and a metal layer above it, and the connection between a lower electrode plate and a metal layer below it through via holes arranged on different sides, so that the horizontal cross-sectional areas of the upper electrode plate and the lower electrode plate are closer, thereby solving the problem of MIM capacitor capacitance waste in the prior art. At the same time, the present invention performs electrical connection of different metal layers by forming a third via hole and a fourth via hole that are connected by segmented etching, thereby avoiding high aspect ratio etching and reducing the difficulty of copper filling.

[0007] In order to achieve the above object, the present invention first provides a semiconductor device, comprising:

[0008] A semiconductor structure having a first metal layer formed thereon;

[0009] a first isolation layer covering the first metal layer;

[0010] The MIM capacitor structure comprises: a lower plate, a dielectric layer and an upper plate, wherein the lower plate covers a portion of the first isolation layer so that an exposed area is formed on the surface of the first isolation layer, the dielectric layer covers the lower plate, and the upper plate covers a portion of the dielectric layer;

[0011] A second isolation layer covering the MIM capacitor structure and the exposed area; and

[0012] a second metal layer covering the second isolation layer;

[0013] Wherein, the lower electrode plate is electrically connected to the first metal layer through a first via hole provided in the first isolation layer;

[0014] The upper electrode plate is electrically connected to the second metal layer through a second via hole provided in the second isolation layer;

[0015] The first metal layer is electrically connected to the second metal layer through a third via and a fourth via that are connected. The third via is located in the exposed area and penetrates the first isolation layer. The fourth via penetrates the second isolation layer.

[0016] Optionally, one end of the lower electrode plate close to the exposed area exceeds one end of the upper electrode plate close to the exposed area to form a exceeding area, and the length of the exceeding area is less than 20% of the length of the upper electrode plate.

[0017] Optionally, the length of the excess area is less than 10% of the length of the upper plate.

[0018] Optionally, the thickness of the dielectric layer covering the excess area is smaller than the thickness of the dielectric layer between the upper electrode plate and the lower electrode plate.

[0019] Optionally, the material of the upper electrode plate and the lower electrode plate includes: titanium nitride.

[0020] Optionally, the dielectric layer is made of a high dielectric material, including any one of aluminum oxide, hafnium oxide, and zirconium oxide.

[0021] Optionally, the material of the first isolation layer and the second isolation layer includes: tetraethyl orthosilicate.

[0022] Optionally, an etch stop layer is further included between the first metal layer and the first isolation layer.

[0023] Optionally, the material of the etch stop layer includes: NDC layer.

[0024] Optionally, the aspect ratio of the third conductive hole is 1:1-1:2, and the aspect ratio of the fourth conductive hole is 1:2-1:4.

[0025] Another aspect of the present invention provides a method for preparing a semiconductor device, comprising the following steps:

[0026] Step S1, providing a semiconductor structure, wherein a first metal layer is formed on the semiconductor structure;

[0027] Step S2, manufacturing a first isolation layer, wherein the first isolation layer covers the first metal layer;

[0028] Step S3, making a first conductive hole, wherein the first conductive hole penetrates the first isolation layer;

[0029] Step S4, sequentially forming a lower plate, a dielectric layer and an upper plate constituting a MIM capacitor structure on the first isolation layer, wherein the lower plate covers a portion of the first isolation layer, so that an exposed area is formed on the surface of the first isolation layer;

[0030] Step S5, manufacturing a second isolation layer, wherein the second isolation layer covers the MIM capacitor structure and the exposed area;

[0031] Step S6, making a second conductive hole, wherein the second conductive hole penetrates the second isolation layer.

[0032] Optionally, the step S3 further includes: making a third conductive hole, wherein the third conductive hole penetrates the first isolation layer;

[0033] After step S4, the exposed area exposes the third conductive hole;

[0034] The step S6 further includes: making a fourth conductive hole, wherein the fourth conductive hole penetrates the second isolation layer and is connected to the third conductive hole.

[0035] Optionally, the method further includes: step S7, manufacturing a second metal layer, wherein the second metal layer is located above the second isolation layer;

[0036] The second metal layer is interconnected with the upper electrode plate through a second conductive hole, and the second metal layer is interconnected with the first metal layer through a third conductive hole and a fourth conductive hole.

[0037] Optionally, sequentially forming a lower plate, a dielectric layer, and an upper plate constituting a MIM capacitor structure on the first isolation layer specifically includes:

[0038] Sequentially forming a lower plate metal layer, a dielectric material layer and an upper plate metal layer on the first isolation layer;

[0039] Etching and removing a portion of the upper plate metal layer, the dielectric material layer and the lower plate metal layer, so that the remaining upper plate metal layer, the dielectric material layer and the lower plate metal layer constitute the upper plate, the dielectric layer and the lower plate;

[0040] Wherein, the upper electrode plate covers a portion of the dielectric layer, and the dielectric layer covers the lower electrode plate.

[0041] Optionally, one end of the lower electrode plate close to the exposed area exceeds one end of the upper electrode plate close to the exposed area to form a exceeded area, and the length of the exceeded area is less than 20% of the length of the upper electrode plate;

[0042] The thickness of the dielectric layer covering the exceeding area is smaller than the thickness of the dielectric layer between the upper electrode plate and the lower electrode plate.

[0043] Optionally, the method further includes: forming an etch stop layer after the first metal layer is formed and before the first isolation layer is formed.

[0044] Compared with the prior art, the beneficial effects of the technical solution of the present invention include at least:

[0045] 1. The present invention provides a semiconductor device, the semiconductor device includes a MIM capacitor structure, which is different from the existing MIM capacitor structure that realizes the interconnection between the upper and lower plates and other metal layers through the via holes set on the same side. The present invention realizes the interconnection between the upper and lower plates and other metal layers through the via holes set on different sides. Specifically, the upper plate of the present invention is connected to the metal layer above the upper plate through the via hole above it, and the lower plate is connected to the metal layer below the lower plate through the via hole below it, so that the horizontal cross-sectional area of ​​the upper plate and the lower plate are closer, which solves the problem of MIM capacitor capacitance waste in the prior art and increases the MIM capacitor capacitance. At the same time, since the etching process of the via hole connecting the lower plate of the present invention does not cause damage to the dielectric layer above the lower plate, the reliability and stability of the MIM capacitor are effectively improved, and the overall performance of the semiconductor device is further improved.

[0046] 2. Compared with the prior art method of forming a via hole penetrating the isolation layer by one etching to realize the interconnection of different metal layers, the present invention forms a third via hole and a fourth via hole that are connected by segmented etching to realize the electrical connection of different metal layers, so that the aspect ratio of the third via hole and the fourth via hole is reduced, thereby significantly reducing the etching difficulty, and also reducing the difficulty of filling the conductive material (such as copper) in the subsequent via hole. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 It is a schematic diagram of the structure of an existing semiconductor device including a MIM capacitor structure.

[0048] Figure 2A schematic diagram of the structure of a semiconductor device provided by an embodiment of the present invention.

[0049] Figure 3 The present invention is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0050] Figures 4A-4I It is a schematic diagram of a structural cross-section during the process of preparing a semiconductor device according to a preparation method according to an embodiment of the present invention.

[0051] Figure 5 The present invention is a flow chart of a method for manufacturing a semiconductor device according to another embodiment of the present invention.

[0052] Figures 6A-6I It is a schematic cross-sectional view of the structure during the process of preparing a semiconductor device according to a preparation method according to another embodiment of the present invention.

[0053] Figure ID:

[0054] Semiconductor device 100, lower plate 10a, dielectric layer 20a, upper plate 30a, semiconductor structure 10, first metal layer 20, first isolation layer 30, exposed area 301, lower plate metal layer 41, dielectric material layer 42, upper plate metal layer 43, MIM capacitor structure 40, lower plate 401, dielectric layer 402, upper plate 403, excess area 4011, second isolation layer 50, second metal layer 60, first via hole 71, second via hole 72, third via hole 73, fourth via hole 74, via hole 7'. DETAILED DESCRIPTION

[0055] The technical solution of the present invention will be described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0056] It should be noted that all directional indications in the embodiments of the present invention (such as up, down, left, right, front, back, etc.) are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0057] As described in the background technology, the upper plate and the lower plate in the existing MIM capacitor structure are electrically connected to different metal layers on the same side (i.e., above the upper plate). Therefore, when the lower plate is connected using microchannel interconnection technology, the etching process of the microchannel will damage the dielectric layer, thereby causing capacitor leakage current. To solve this problem, the prior art will extend the right end of the lower plate beyond the right end of the upper plate by a large distance to avoid damaging the dielectric layer when etching to form the microchannel, but this will cause a waste of capacitor capacitance. In addition, the high aspect ratio etching of the microchannel and the simultaneous etching of multiple depths are also the main technical difficulties in the preparation of MIM capacitors.

[0058] In order to solve the above technical problems, the present invention proposes a new semiconductor device, which includes a MIM capacitor structure. Different from the existing structure in which the upper and lower plates are interconnected with other metal layers through conductive holes arranged on the same side, the present invention realizes the connection of the upper plate with the metal layer above it and the connection of the lower plate with the metal layer below it through conductive holes arranged on different sides. Therefore, on the one hand, the etching process of the via hole connecting the lower plate of the present invention will not cause damage to the dielectric layer above the lower plate, which effectively improves the reliability and stability of the MIM capacitor; on the other hand, since the via hole connecting the lower plate of the present invention is not located above the lower plate, there is no need to control the area of ​​the upper plate covering the lower plate, so that the lower plate exposes a sufficient area for etching and connection of the via hole. In other words, compared with the prior art, the horizontal cross-sectional area of ​​the upper plate and the lower plate of the MIM capacitor structure in the present invention is closer, which solves the problem of MIM capacitor capacitance waste in the prior art, increases the MIM capacitor capacitance, improves the overall performance of the semiconductor device, and electrically connects the first metal layer to the second metal layer through the connected third and fourth via holes, so that the third via hole is located in the exposed area and passes through the first isolation layer, and the fourth via hole passes through the second isolation layer, which can greatly reduce the difficulty of high aspect ratio etching and copper filling, and reduce the process difficulty and cost. Detailed description is as follows.

[0059] An embodiment of the present invention provides a semiconductor device 100, the structure of which is shown in FIG. Figure 2 As shown, including:

[0060] The semiconductor structure 10 may be a structure in which a functional layer is pre-formed in a substrate. For example, for a mos (Metal-Oxide-Semiconductor) structure, various doping regions, such as a source region, a drain region, a channel, etc., may be pre-formed, and corresponding source electrodes, drain electrodes, and gate electrodes may be formed accordingly. Finally, a first metal layer 20 is formed on the semiconductor structure 10;

[0061] A first isolation layer 30, which covers the first metal layer 20 and is used to isolate the first metal layer 20 and the subsequently formed MIM capacitor structure 40 to prevent the current from flowing directly between the two and avoid short circuit;

[0062] The MIM capacitor structure 40 comprises: a lower plate 401, a dielectric layer 402 and an upper plate 403, wherein the lower plate 401 covers a portion of the first isolation layer 30, so that an exposed area 301 is formed on the surface of the first isolation layer 30, that is, the horizontal cross-sectional area of ​​the lower plate 401 is smaller than the horizontal cross-sectional area of ​​the first isolation layer 30, and the exposed area 301 is subsequently connected to different metal layers (the first metal layer 20 and the second metal layer 60 in this embodiment) through a conductive hole; the dielectric layer 402 covers the lower plate 401, and the upper plate 403 covers a portion of the dielectric layer 402;

[0063] A second isolation layer 50, which covers the MIM capacitor structure 40 and the exposed area 301, and is used to isolate the MIM capacitor structure 40 from a subsequently formed second metal layer 60 to prevent current from directly passing therebetween; and

[0064] The second metal layer 60 covers the second isolation layer 50 .

[0065] In the present invention, the lower electrode plate 401 is electrically connected to the first metal layer 20 via a first conductive hole 71 provided in the first isolation layer 30 ; the upper electrode plate 403 is electrically connected to the second metal layer 60 via a second conductive hole 72 provided in the second isolation layer 50 .

[0066] It should be emphasized that, different from the existing Figure 1The present invention is a MIM capacitor structure that realizes the connection of the upper plate and the lower plate with different metal layers by means of the via holes set on different sides. Specifically, the upper plate 403 is connected to the second metal layer 60 above the upper plate through the second via hole 71 above it; the lower plate 401 is connected to the first metal layer 20 below the lower plate through the first via hole 71 below it. Therefore, the etching process of the first via hole 71 of the present invention will not damage the dielectric layer 402 above the lower plate 401, which effectively improves the reliability and stability of the MIM capacitor; more importantly, since the first via hole 71 is not located above the lower plate 401, there is no need to set the difference between the horizontal cross-sectional areas of the upper and lower plates to be larger as in the prior art, so that a sufficient area is exposed above the lower plate to etch the via hole and to avoid the problem of damaging the dielectric layer above the lower plate during the etching of the via hole. In other words, compared with the prior art, the semiconductor device provided by the present invention increases the area of ​​the upper plate 403 covering the lower plate 401, so that the horizontal cross-sectional areas of the upper plate 403 and the lower plate 401 are closer, thereby increasing the capacitance of the MIM capacitor, avoiding the problem of MIM capacitor capacitance waste in the prior art, and improving the overall performance of the semiconductor device.

[0067] In some embodiments, the ratio of the horizontal cross-sectional areas of the upper electrode plate 403 and the lower electrode plate 401 is 1:1-1:1.2 (excluding 1:1), and further, the ratio of the horizontal cross-sectional areas of the upper electrode plate 403 and the lower electrode plate 401 is 1:1.1.

[0068] In some embodiments, one end of the lower plate 401 close to the exposed area 301 exceeds one end of the upper plate 403 close to the exposed area 301 to form a protruding area 4011, which is used to avoid the two ends (i.e. Figure 2 The distance between the right end of the lower plate 401 and the right end of the upper plate 403 is too short, which damages the dielectric layer 402 between the upper plate 403 and the lower plate 401, reducing the reliability and stability of the MIM capacitor. However, if the distance between the two ends is too long, the MIM capacitance will be wasted. As an example, the length of the excess area 4011 is not greater than 20% of the length of the upper plate 403; in other examples, the length of the excess area 4011 is not greater than 10% of the length of the upper plate. Furthermore, in some embodiments, the length of the lower plate 401 is greater than 100nm.

[0069] In some embodiments, the thickness of the dielectric layer 402 covering the excess area 4011 is smaller than the thickness of the dielectric layer 402 between the upper electrode plate 403 and the lower electrode plate 401 .

[0070] In the present invention, the first metal layer 20 is electrically connected to the second metal layer 60 through the connected third via 73 and the fourth via 74, the third via 73 is located in the exposed area 301 and penetrates the first isolation layer 30, and the fourth via 74 penetrates the second isolation layer 50. It can be understood that, compared with the completely connected via formed by one etching through the second isolation layer 50 and the first isolation layer 30, the present invention uses segmented etching to make the third via 73 and the fourth via 74 have a smaller aspect ratio, and the etching difficulty is significantly reduced, while also reducing the difficulty of filling the subsequent via with a conductive material (such as copper).

[0071] In some embodiments, the aspect ratio of the third via hole 73 is 1:1-1:2 (in this embodiment Figure 2 The aspect ratio of the fourth via hole 74 is 1:2-1:4 (in this embodiment Figure 2 Example 1: 4). Compared with the prior art method of forming a via hole penetrating the isolation layer by etching once to achieve metal layer interconnection, this embodiment electrically connects the first metal layer 20 to the second metal layer 60 through the connected third via hole 73 and the fourth via hole 74, so that the third via hole 73 is located in the exposed area 301 and penetrates the first isolation layer 30, and the fourth via hole 74 penetrates the second isolation layer 50, which can greatly avoid high aspect ratio etching and reduce the difficulty of subsequent copper filling. An example, such as Figure 1 In the example of the existing structure, a typical value of the aspect ratio of the via hole 7' is 1:6. However, by using the structure and process of this embodiment, the aspect ratio of the via hole can be reduced to, for example, 1:4, which greatly reduces the difficulty of high aspect ratio etching and copper filling.

[0072] In some embodiments, the third conductive hole 73 and the fourth conductive hole 74 are arranged with the same central axis, which helps to ensure that the filling material can smoothly form a continuous conductive path in the third conductive hole 73 and the fourth conductive hole 74, thereby improving the conductivity of the circuit and the signal transmission efficiency.

[0073] As an example, the material of the upper electrode plate 403 and the lower electrode plate 401 includes: titanium nitride, and the thickness of the upper electrode plate 403 and the lower electrode plate 401 is 450 angstroms to 550 angstroms.

[0074] The material of the dielectric layer 402 is a high dielectric material, so as to improve the capacitance of the MIM capacitor structure. As an example, the material of the dielectric layer 402 includes: any one of aluminum oxide, hafnium oxide, and zirconium oxide, and its thickness can be selected according to the capacitance requirement of the MIM capacitor, for example, the thickness of the dielectric layer 402 is 110 angstroms to 150 angstroms.

[0075] As an example, the material of the first isolation layer 30 and the second isolation layer 50 includes: tetraethyl orthosilicate. The thickness of the first isolation layer 30 is 1500 angstroms to 1700 angstroms.

[0076] In some embodiments, the overall thickness of the first isolation layer 30 , the MIM capacitor structure 40 , and the second isolation layer 50 is 5000 angstroms to 7000 angstroms.

[0077] In some embodiments, an etch stop layer is further included between the first metal layer 20 and the first isolation layer 30, which helps to accurately control the etching depth and range and protect the first metal layer 20 from being damaged. As an example, the material of the etch stop layer includes: a doped silicon nitride (Nitride Doped Silicon Carbide, NDC) layer, and the thickness of the etch stop layer is 400 angstroms to 600 angstroms.

[0078] An embodiment of the present invention provides a method for manufacturing a semiconductor device, such as Figures 3 to 4A -4I, including:

[0079] Step 101, providing a semiconductor structure 10, on which a first metal layer 20 is formed, the structure of which is shown in FIG. Figure 4A .

[0080] The semiconductor structure 10 may be a structure in which a functional layer is pre-formed in a substrate. For example, for a MOS structure, various doping regions, such as a source region, a drain region, a channel, etc., may be pre-formed, and corresponding source electrodes, drain electrodes, and gate electrodes may be formed accordingly. Finally, the first metal layer 20 is deposited on the semiconductor structure 10 to form the first metal layer 20.

[0081] Step 102, making a first isolation layer 30, the first isolation layer 30 covers the first metal layer 20, the structure of which is shown in FIG. Figure 4B .

[0082] In this step, a first isolation layer 30 is formed on the surface of the first metal layer 20. As an example, the material of the first isolation layer 30 includes: tetraethyl orthosilicate, which can be formed by chemical vapor deposition of tetraethyl orthosilicate to form the first isolation layer 30, and the thickness of the first isolation layer 30 is 1500 angstroms to 1700 angstroms.

[0083] In some embodiments, after the first metal layer 20 is formed in step 101 and before the first isolation layer 30 is formed in this step, an etching stop layer is formed. The material of the etching stop layer includes an NDC layer, and the thickness of the etching stop layer is 400 angstroms to 600 angstroms.

[0084] Step 103, making a first conductive hole 71, the first conductive hole 71 passes through the first isolation layer 30, the structure of which is shown in FIG. Figure 4C .

[0085] As an example, a photoresist (PR) layer may be first fabricated and patterned on the first isolation layer 30, the PR layer being used as a barrier material, and then a first via hole 71 may be etched in the first isolation layer 30 by a plasma etching method, the first via hole 71 passing through the first isolation layer 30 and extending to the first metal layer 20. After etching, the PR layer is removed, and the first via hole 71 is filled with a conductive material for electrically connecting the first metal layer 20 with the lower plate metal layer 41, and the conductive material may be metallic copper.

[0086] Step 104, a lower plate 401, a dielectric layer 402 and an upper plate 403 constituting a MIM capacitor structure 40 are sequentially formed on the first isolation layer 30, wherein the lower plate 401 covers a portion of the first isolation layer 30, so that an exposed area 301 is formed on the surface of the first isolation layer 30. The structure is shown in FIG. Figures 4D-4F .

[0087] Specifically, first, a lower plate metal layer 41, a dielectric material layer 42 and an upper plate metal layer 43 are sequentially formed on the first isolation layer 30. Figure 4D .

[0088] Then, by forming a PR layer and etching, a portion of the upper plate metal layer 43 and the dielectric material layer 42 are removed, and the remaining upper plate metal layer constitutes the upper plate 403. The structure is shown in FIG. Figure 4E .

[0089] It should be noted that after this operation, the upper surface of the lower electrode metal layer 41 is not exposed, and the area not covered by the upper electrode 403 is still covered with a partial thickness of the dielectric material layer remaining after etching, so as to avoid damage to the surface of the lower electrode metal layer 41 when the dielectric material layer in this area is completely etched away.

[0090] A portion of the lower plate metal layer 41 and the residual dielectric material layer covering the portion are further removed by forming a PR layer and etching, and the remaining dielectric material layer and the lower plate metal layer 41 constitute the dielectric layer 402 and the lower plate 401 respectively.

[0091] Finally, the upper plate 403, the dielectric layer 402 and the lower plate 401 form a MIM capacitor structure 40. The upper plate 403 covers part of the dielectric layer 402, the dielectric layer 402 covers the lower plate 401, and the lower plate 401 covers part of the first isolation layer 30, so that an exposed area 301 is formed on the surface of the first isolation layer 30. The structure is shown in FIG. Figure 4F .

[0092] It should be noted that the lower electrode 401 is close to the end of the exposed area 301 (i.e. Figure 4G The right end of the middle lower electrode plate 401) exceeds the end of the upper electrode plate 403 close to the exposed area 301 (i.e. Figure 4G The right end of the upper plate 403 in the middle) forms an overrun area 4011, which is used to avoid damage to the dielectric layer 402 between the upper plate 403 and the lower plate 401 due to the short distance between the two ends during the etching process of forming the lower plate 401, but a too long distance between the two ends will cause waste of MIM capacitance. As an example, the length of the overrun area 4011 is not greater than 20% of the length of the upper plate 403; in other examples, the length of the overrun area 4011 is not greater than 10% of the length of the upper plate.

[0093] Step 105, making a second isolation layer 50, the second isolation layer 50 covers the MIM capacitor structure 40 and the exposed area 301, the structure of which is shown in FIG. Figure 4G .

[0094] As an example, the material of the second isolation layer 50 includes: tetraethyl orthosilicate. The second isolation layer 50 can be formed by manufacturing tetraethyl orthosilicate through chemical vapor deposition.

[0095] Step 106, making a second via hole 72, the second via hole passes through the second isolation layer 50, the structure of which is shown in FIG. Figure 4H .

[0096] The second via hole 72 is formed by forming a PR layer and etching, and is filled with a conductive material. The second via hole penetrates the second isolation layer 50 and extends to the upper electrode plate 403 .

[0097] Step 107, manufacturing a second metal layer 60, wherein the second metal layer 60 is located above the second isolation layer 50, and the structure is shown in FIG. Fig. 4I .

[0098] The second metal layer 60 is electrically connected to the upper electrode plate 403 through the second via 72 .

[0099] In the semiconductor device formed by the preparation method of this embodiment, the lower plate 401 is electrically connected to the first metal layer 20 through the first via hole 71 below, and the upper plate 403 is electrically connected to the second metal layer 60 through the second via hole 72 above. Compared with the prior art, the horizontal cross-sectional areas of the upper plate 403 and the lower plate 401 in this embodiment are closer, thereby increasing the capacitance of the MIM capacitor and avoiding the problem of capacitance waste. In addition, since the etching process of the first via hole 71 will not cause damage to the dielectric layer 402 above the lower plate 401, the reliability and stability of the MIM capacitor can be effectively improved, and the overall performance of the semiconductor device can be further improved.

[0100] Furthermore, an embodiment of the present invention also provides another method for preparing a semiconductor device, such as Figures 5 to 6A Compared with the preparation method of the above embodiment, the semiconductor device formed by the preparation method of this embodiment realizes the interconnection between the first metal layer 20 and the second metal layer 60, including:

[0101] Step 201, providing a semiconductor structure 10, on which a first metal layer 20 is formed, the structure of which is shown in FIG. Fig. 6A .

[0102] Step 202, making a first isolation layer 30, the first isolation layer 30 covers the first metal layer 20, the structure of which is shown in FIG. Figure 6B .

[0103] Step 203, making a first conductive hole 71 and a third conductive hole 73, wherein the first conductive hole 71 and the third conductive hole 73 penetrate the first isolation layer 30, and the structure is shown in FIG. Figure 6C .

[0104] In some embodiments, the aspect ratio of the third via hole 73 is 1:1-1:2.

[0105] Step 204, a lower plate 401, a dielectric layer 402 and an upper plate 403 constituting a MIM capacitor structure 40 are sequentially formed on the first isolation layer 30, wherein the lower plate 401 covers a portion of the first isolation layer 30, so that an exposed area 301 is formed on the surface of the first isolation layer 30. The structure is shown in FIG. Figure 6D-6F .

[0106] The exposed area 301 exposes the top of the third via hole 73 .

[0107] Step 205, making a second isolation layer 50, the second isolation layer 50 covers the MIM capacitor structure 40 and the exposed area 301, the structure of which is shown in FIG. Figure 6G .

[0108] Step 206, making a second conductive hole 72 and a fourth conductive hole 74, wherein the second conductive hole 72 penetrates the second isolation layer 50, and the fourth conductive hole 74 penetrates the second isolation layer 50 and communicates with the third conductive hole 73. Figure 6H .

[0109] In some embodiments, the fourth via hole 74 has a depth-to-width ratio of 1:2-1:4.

[0110] In some embodiments, the third conductive hole 73 and the fourth conductive hole 74 are arranged coaxially.

[0111] Step 207, making a second metal layer 60, the second metal layer 60 is located above the second isolation layer 50, the structure of which is shown in FIG. Fig.6I .

[0112] In the semiconductor device formed by the preparation method of this embodiment, the second metal layer 60 is interconnected with the first metal layer 20 through the connected third via 73 and the fourth via 74. Compared with the prior art method of forming a via hole penetrating the second isolation layer 50 and the first isolation layer 30 by etching once to realize the interconnection of two metal layers, such as Figure 1 Taking the via hole 7' of the prior art structure as an example, the present invention makes the aspect ratio of the third via hole 73 and the fourth via hole 74 smaller by segmented etching, and the etching difficulty is significantly reduced, and the difficulty of filling the subsequent via hole with conductive material (such as copper) is also reduced.

[0113] In summary, the present invention realizes the connection between the upper plate and the metal layer above it, and the lower plate and the metal layer below it through the via holes set on the same side, so that the horizontal cross-sectional areas of the upper plate and the lower plate are closer, which solves the problem of MIM capacitor capacitance waste in the prior art and increases the MIM capacitor capacitance. At the same time, since the etching process of the via hole connecting the lower plate of the present invention does not damage the dielectric layer above the lower plate, the reliability and stability of the MIM capacitor are effectively improved, and the overall performance of the semiconductor device is improved; in addition, the present invention forms a third via hole and a fourth via hole connected by segmented etching to electrically connect different metal layers, which can greatly reduce the difficulty of high aspect ratio etching and copper filling, and reduce the process difficulty and cost.

[0114] Although the content of the present invention has been described in detail through the above preferred embodiments, it should be appreciated that the above description should not be considered as a limitation of the present invention. After reading the above content, it will be apparent to those skilled in the art that various modifications and substitutions of the present invention will occur. Therefore, the protection scope of the present invention should be limited by the appended claims.

Claims

1. A semiconductor device, comprising: A semiconductor structure having a first metal layer formed thereon; a first isolation layer covering the first metal layer; The MIM capacitor structure comprises: a lower plate, a dielectric layer and an upper plate, wherein the lower plate covers a portion of the first isolation layer so that an exposed area is formed on the surface of the first isolation layer, the dielectric layer covers the lower plate, and the upper plate covers a portion of the dielectric layer; A second isolation layer covering the MIM capacitor structure and the exposed area; and a second metal layer covering the second isolation layer; Characterized in that the lower electrode plate is electrically connected to the first metal layer through a first via hole provided in the first isolation layer; The upper electrode plate is electrically connected to the second metal layer through a second via hole provided in the second isolation layer; The first metal layer is electrically connected to the second metal layer through a third via and a fourth via that are connected. The third via is located in the exposed area and penetrates the first isolation layer. The fourth via penetrates the second isolation layer.

2. The semiconductor device according to claim 1, wherein One end of the lower electrode plate close to the exposed area exceeds one end of the upper electrode plate close to the exposed area to form a exceeding area, and the length of the exceeding area is less than 20% of the length of the upper electrode plate.

3. The semiconductor device according to claim 2, wherein: The length of the excess area is less than 10% of the length of the upper plate.

4. The semiconductor device according to claim 2, wherein: The thickness of the dielectric layer covering the exceeding area is smaller than the thickness of the dielectric layer between the upper electrode plate and the lower electrode plate.

5. The semiconductor device according to claim 1, wherein: The material of the upper electrode plate and the lower electrode plate includes: titanium nitride.

6. The semiconductor device according to claim 1, wherein: The dielectric layer is made of a high dielectric material, including any one of aluminum oxide, hafnium oxide, and zirconium oxide.

7. The semiconductor device according to claim 1, wherein: The materials of the first isolation layer and the second isolation layer include: tetraethyl orthosilicate.

8. The semiconductor device according to claim 1, wherein An etch stop layer is also included between the first metal layer and the first isolation layer.

9. The semiconductor device according to claim 8, characterized in that The material of the etch stop layer includes: NDC layer.

10. The semiconductor device according to claim 1, wherein The aspect ratio of the third conductive hole is 1:1-1:2, and the aspect ratio of the fourth conductive hole is 1:2-1:

4.

11. A method for preparing a semiconductor device, characterized in that: The following steps are involved: Step S1, providing a semiconductor structure, wherein a first metal layer is formed on the semiconductor structure; Step S2, manufacturing a first isolation layer, wherein the first isolation layer covers the first metal layer; Step S3, making a first conductive hole, wherein the first conductive hole penetrates the first isolation layer; Step S4, sequentially forming a lower plate, a dielectric layer and an upper plate constituting a MIM capacitor structure on the first isolation layer, wherein the lower plate covers a portion of the first isolation layer, so that an exposed area is formed on the surface of the first isolation layer; Step S5, manufacturing a second isolation layer, wherein the second isolation layer covers the MIM capacitor structure and the exposed area; Step S6, making a second conductive hole, wherein the second conductive hole penetrates the second isolation layer.

12. The method for preparing a semiconductor device according to claim 11, wherein: The step S3 further includes: making a third conductive hole, wherein the third conductive hole penetrates the first isolation layer; After step S4, the exposed area exposes the third conductive hole; The step S6 further includes: making a fourth conductive hole, wherein the fourth conductive hole penetrates the second isolation layer and is connected to the third conductive hole.

13. The method for preparing a semiconductor device according to claim 12, wherein: Also includes: Step S7, manufacturing a second metal layer, wherein the second metal layer is located above the second isolation layer; The second metal layer is interconnected with the upper electrode plate through a second conductive hole, and the second metal layer is interconnected with the first metal layer through a third conductive hole and a fourth conductive hole.

14. The method for preparing a semiconductor device according to claim 11, wherein: The step of sequentially forming a lower plate, a dielectric layer and an upper plate constituting a MIM capacitor structure on the first isolation layer specifically includes: Sequentially forming a lower plate metal layer, a dielectric material layer and an upper plate metal layer on the first isolation layer; Etching and removing a portion of the upper plate metal layer, the dielectric material layer and the lower plate metal layer, so that the remaining upper plate metal layer, the dielectric material layer and the lower plate metal layer constitute the upper plate, the dielectric layer and the lower plate; Wherein, the upper electrode plate covers a portion of the dielectric layer, and the dielectric layer covers the lower electrode plate.

15. The method for preparing a semiconductor device according to claim 14, characterized in that: One end of the lower electrode plate close to the exposed area exceeds one end of the upper electrode plate close to the exposed area to form a exceeded area, and the length of the exceeded area is less than 20% of the length of the upper electrode plate; The thickness of the dielectric layer covering the exceeding area is smaller than the thickness of the dielectric layer between the upper electrode plate and the lower electrode plate.

16. The method for preparing a semiconductor device according to claim 11, wherein: Also includes: After the first metal layer is formed and before the first isolation layer is formed, an etch stop layer is formed.

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