Buffer layer structure, mHEMT device and mHBT device

Abstract

The present invention discloses a buffer layer structure, which comprises: a gallium arsenide substrate; an InAlAs buffer layer and an InAlP or InGaP buffer layer sequentially stacked on the gallium arsenide substrate; wherein, during a manufacturing process, the lattice parameter of the InAlAs buffer layer is gradually increased from the lattice parameter of gallium arsenide to a predetermined lattice parameter by increasing the In component from 0% to a first predetermined content, and during a manufacturing process, the lattice parameter of the InAlP or InGaP buffer layer is gradually increased from the predetermined lattice parameter to the lattice parameter of indium phosphide by increasing the In component from a second predetermined content to 100%; wherein, the InAlAs buffer layer does not undergo phase separation when its In component is the first predetermined content, and the InAlP or InGaP buffer layer does not undergo phase separation when its In component is the second predetermined content.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductors, and in particular, relates to a buffer layer structure and an mHEMT device and an mHBT device having the buffer layer structure. Background Art

[0002] Gallium arsenide (GaAs) semiconductors are widely used in the microwave and radio frequency fields due to their high electron mobility, including for the manufacture of heterojunction bipolar transistors (HBT) and high electron mobility transistors (HEMT). The advantages of GaAs semiconductors include large size (up to 8 inches), low cost and good mechanical properties. However, the maximum electron mobility of GaAs materials is 8500 cm 2 / V·s, making the cutoff frequency of its electronic devices lower than 100GHz.

[0003] In order to obtain higher frequency devices, indium phosphide (InP) semiconductor materials with higher mobility are usually used, and their cutoff frequency can reach 1THz. However, the size of InP substrates is relatively small (up to 4 inches) and it is expensive, more than twice that of GaAs substrates. In order to take advantage of the low cost and large size of GaAs substrates and the high performance of InP devices, InP electronic devices are usually made on GaAs substrates, thus developing metamorphic devices, such as pseudomorphic heterojunction bipolar transistors (mHBTs) or pseudomorphic high electron mobility transistors (mHEMTs).

[0004] However, due to the different lattice parameters of InP substrate (lattice parameter 5.8697Å) and GaAs substrate (lattice parameter 5.6533Å), InP material grown directly on GaAs substrate will produce more defects, including threading dislocations, stacking faults, cracks, etc., which greatly affect the performance of the device. Therefore, a buffer layer is usually grown between the GaAs substrate and the InP device to transition the lattice parameter from 5.6533Å of GaAs to 5.8697Å of InP, gradually releasing stress, reducing defect density, and confining various dislocations within the buffer layer. Therefore, the quality of the buffer layer largely determines the performance of pseudocrystalline devices.

[0005] In the prior art, an InAlAs buffer layer is usually used, and the In component is increased from 0% to 52%, thereby achieving the lattice parameters of InP, such as Figure 1As shown. However, for any pseudomorphic alloy, two group III elements are more likely to phase separate when the ratio is close, resulting in more threading dislocations and stacking faults. In the prior art, when InAlAs transitions to the lattice parameters of InP, the In component is 52%, which is close to the Al component of 48%, so it is easy to produce defects, which damages the device performance and long-term reliability. Therefore, a new buffer layer structure is needed to reduce the defect density and improve the performance of pseudomorphic devices. Summary of the invention

[0006] In order to solve the above-mentioned problems existing in the prior art, the present invention provides a buffer structure which can avoid the situation where the proportions of group III elements in a gradient ternary alloy buffer layer are close, inhibit the phase separation of the ternary alloy buffer layer, thereby reducing the defect density, and improving the performance and reliability of pseudomorphic devices, as well as an mHEMT device and an mHBT device having the buffer structure.

[0007] According to one aspect of the present invention, a buffer layer structure is provided, which comprises: a gallium arsenide substrate; an InAlAs buffer layer and an InAlP or InGaP buffer layer sequentially stacked on the gallium arsenide substrate; wherein, during a manufacturing process, the lattice parameter of the InAlAs buffer layer is gradually increased from the lattice parameter of gallium arsenide to a predetermined lattice parameter by increasing the In component from 0% to a first predetermined content, and during a manufacturing process, the lattice parameter of the InAlP or InGaP buffer layer is gradually increased from the predetermined lattice parameter to the lattice parameter of indium phosphide by increasing the In component from a second predetermined content to 100%; wherein, the InAlAs buffer layer does not undergo phase separation when its In component is the first predetermined content, and the InAlP or InGaP buffer layer does not undergo phase separation when its In component is the second predetermined content.

[0008] In an example of the buffer layer structure provided in the above aspect, the first predetermined content is 25%, and the predetermined lattice parameter is 5.7615Å.

[0009] In an example of the buffer layer structure provided in the above aspect, the second predetermined content is 76%.

[0010] In an example of the buffer layer structure provided in the above aspect, a method of increasing the In component includes a continuous gradient method or a step gradient method.

[0011] According to another aspect of the present invention, an mHEMT device is provided, which includes: the above-mentioned buffer layer structure; an InAlAs barrier layer on the InAlP or InGaP buffer layer of the buffer layer structure; an InGaAs channel layer on the InAlAs barrier layer; an InAlAs space layer on the InGaAs channel layer; a Delta doped layer on the InAlAs space layer; an InAlAs Schottky layer on the Delta doped layer; an InP stop layer on the InAlAs Schottky layer; and an InGaAs contact layer on the InP stop layer.

[0012] According to another aspect of the present invention, an mHBT device is provided, which includes: the above-mentioned buffer layer structure; an InP sub-collector region on the InAlP or InGaP buffer layer of the buffer layer structure; an InP collector region on the InP sub-collector region; an InGaAs collector region on the InP collector region; an InGaAs base region on the InGaAs collector region; an InP emitter region on the InGaAs base region; and an InGaAs contact layer on the InP emitter region.

[0013] Beneficial effects: The buffer layer structure of the present invention avoids the situation where the proportions of group III elements are close in the buffer layer by reasonably selecting the buffer layer, which can better inhibit phase separation and reduce defect density, thereby improving the performance and reliability of pseudocrystalline devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The above and other aspects, features and advantages of the embodiments of the present invention will become more apparent through the following description in conjunction with the accompanying drawings, in which:

[0015] Figure 1 The relationship between the lattice parameter and the band gap width of III-V compound semiconductors; the change of the In component in the InAlAs buffer layer used in the prior art pseudocrystalline device is shown by the red arrow;

[0016] Figure 2 is a schematic structural diagram of a buffer layer structure according to an embodiment of the present invention;

[0017] Figure 3 is the relationship between the lattice parameter and the band gap width of the III-V compound semiconductor; wherein the change of the In component in the InAlAs buffer layer of the buffer layer structure according to the embodiment of the present invention is shown by a red arrow, and the change of the In component in the InAlP or InGaP buffer layer is shown by a green arrow;

[0018] Figure 4 is a graph of measured transfer characteristics of mHEMT devices respectively manufactured using the prior art and the buffer layer structure according to an embodiment of the present invention;

[0019] Figure 5 is a schematic structural diagram of an mHEMT device according to an embodiment of the present invention;

[0020] Figure 6 is a schematic structural diagram of an mHBT device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0021] Hereinafter, specific embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention may be implemented in many different forms, and the present invention should not be construed as being limited to the specific embodiments set forth herein. On the contrary, these embodiments are provided to explain the principles of the present invention and their practical applications, so that other persons skilled in the art can understand the various embodiments of the present invention and various modifications suitable for specific intended applications.

[0022] As used herein, the term "including" and its variations represent open terms, meaning "including but not limited to". The terms "based on", "according to", etc. mean "based at least in part on", "based at least in part on". The terms "embodiment", "one example", "one embodiment" and "an embodiment" mean "at least one embodiment". The terms "another embodiment", "another embodiment", "another example", "yet another example" mean "at least one other embodiment". The terms "first", "second", etc. may refer to different or the same objects. Other definitions may be included below, whether explicit or implicit. Unless the context clearly indicates otherwise, the definition of a term is consistent throughout the specification.

[0023] It should also be noted that, in order to avoid obscuring the present invention due to unnecessary details, only structures and / or processing steps closely related to the solutions according to the present invention are shown in the drawings, while other details that are not very relevant are omitted.

[0024] As described in the background art, the prior art pseudocrystalline device uses a single InAlAs buffer layer, and increases the lattice parameter by increasing the In component in InAlAs, such as Figure 1 As shown. According to Vegard's law, the lattice parameter of an alloy is equal to the linear superposition of its constituent materials. When the In component is 52%, the lattice parameter of InAlAs is equal to the lattice parameter of InP, 5.8697Å. At this time, the ratio of In and Al elements in InAlAs is close, and phase separation is most likely to occur during the composition gradient, resulting in In-rich regions and Al-rich regions, which leads to the generation of various defects.

[0025] In order to avoid this phenomenon, the present invention provides a buffer layer structure, which includes a gallium arsenide substrate and an InAlAs buffer layer and an InAlP or InGaP buffer layer sequentially stacked on the gallium arsenide substrate, a gallium arsenide substrate; an InAlAs buffer layer and an InAlP or InGaP buffer layer sequentially stacked on the gallium arsenide substrate; wherein, during the manufacturing process, the lattice parameter of the InAlAs buffer layer is gradually increased from the lattice parameter of gallium arsenide to the predetermined lattice parameter by increasing the In component from 0% to a first predetermined content, and during the manufacturing process, the lattice parameter of the InAlP or InGaP buffer layer is gradually increased from the predetermined lattice parameter to the lattice parameter of indium phosphide by increasing the In component from a second predetermined content to 100%; wherein, the InAlAs buffer layer does not undergo phase separation when its In component is the first predetermined content, and the InAlP or InGaP buffer layer does not undergo phase separation when its In component is the second predetermined content.

[0026] The following is combined with Figure 2 Embodiments according to the present invention are described in detail. Figure 2 is a schematic structural diagram of a buffer layer structure according to an embodiment of the present invention.

[0027] Reference Figure 2 The buffer layer structure according to the embodiment of the present invention includes: a gallium arsenide substrate 10; an InAlAs buffer layer 11 and an InAlP or InGaP buffer layer 12A sequentially stacked on the gallium arsenide substrate 10.

[0028] Furthermore, during the manufacturing process, the lattice parameter of the InAlAs cache layer 11 is gradually increased from the lattice parameter of the gallium arsenide substrate 10 to the predetermined lattice parameter by increasing the In component from 0% to the first predetermined content, and during the manufacturing process, the lattice parameter of the InAlP or InGaP cache layer 12A is gradually increased from the predetermined lattice parameter to the lattice parameter of indium phosphide (InP) by increasing the In component from the second predetermined content to 100%; wherein, the InAlAs cache layer 11 does not undergo phase separation when its In component is the first predetermined content, and the InAlP or InGaP cache layer 12A does not undergo phase separation when its In component is the second predetermined content.

[0029] Figure 3 It is the relationship between the lattice parameter and the band gap width of III-V compound semiconductors; wherein, the change of the In component in the InAlAs buffer layer of the buffer layer structure according to an embodiment of the present invention is shown by a red arrow, and the change of the In component in the InAlP or InGaP buffer layer is shown by a green arrow.

[0030] Reference Figure 3For the InAlAs buffer layer 11, the In component is gradually changed during the manufacturing process (for example, gradually increasing from 0% content) so that the lattice parameter of the InAlAs buffer layer 11 reaches a predetermined lattice parameter between the GaAs lattice parameter and the InP lattice parameter (for example, 5.7615Å). At this time, the In component of the InAlAs buffer layer 11 is a first predetermined content corresponding to the predetermined lattice parameter (for example, the In component content is 25%, and the Al component content is 75% at this time), so that the alloy composition of the InAlAs cache layer 11 is closer to AlAs, and therefore phase separation is not easy to occur.

[0031] Then switch to the InAlP or InGaP cache layer 12A. When the lattice parameter is a predetermined lattice parameter (e.g., 5.7615Å), the corresponding In component is a second predetermined content (e.g., 74%). However, the In component is increased to 100%. At this time, the lattice parameter of the InAlP or InGaP cache layer 12A reaches 5.8697Å, that is, the alloy composition of the InAlP or InGaP cache layer 12A is closer to InP, so phase separation is not easy to occur.

[0032] Therefore, the buffer layer structure according to the embodiment of the present invention can effectively suppress phase separation and reduce defect density by reasonably selecting the buffer layer so that the proportion of group III elements in the buffer layer is not close, thereby improving the performance and reliability of pseudocrystalline devices.

[0033] In order to better demonstrate the effect of the buffer layer structure according to the embodiment of the present invention, the inventors fabricated two pseudocrystalline mHEMT devices on a GaAs substrate, one using the InAlAs buffer layer of the prior art, and the other using the InAlAs buffer layer and InAlP buffer layer proposed in the embodiment of the present invention.

[0034] Figure 4 The diagram is a graph of measured transfer curves of mHEMT devices respectively manufactured using the prior art and the buffer layer structure according to the embodiment of the present invention.

[0035] Reference Figure 4 , the mHEMT device with the buffer layer structure according to the embodiment of the present invention has a steep cutoff and a small leakage after the device is pinched off; while the mHEMT device with the traditional InAlAs buffer layer has many defects, the device has obvious subthreshold characteristics, and the leakage after pinching off is large. This fully demonstrates that after adopting the buffer layer structure according to the embodiment of the present invention, the material quality and device performance have been greatly improved.

[0036] Figure 5 is a schematic structural diagram of an mHEMT device according to an embodiment of the present invention.

[0037] Reference Figure 5 , the mHEMT device according to an embodiment of the present invention comprises:

[0038] GaAs substrate 10, which is 500 μm thick and semi-insulating;

[0039] The InAlAs buffer layer 11 on the GaAs substrate 10 has a thickness of 300 nm, and the In component is increased from 0% to 25% in a linear gradient manner (or continuous gradient manner), and is doped with O, and the doping concentration is 5×10 19 cm -3 ;

[0040] The InAlP buffer layer 12 on the InAlAs buffer layer 11 has a thickness of 300 nm, and the In component is increased from 76% to 100% in a linear gradient manner, and is doped with O at a doping concentration of 5×10 19 cm -3 ;

[0041] The InAlAs barrier layer 13 on the InAlP buffer layer 12 has a thickness of 100 nm, an In composition of 52%, and is non-doped;

[0042] An InGaAs channel layer 14 on the InAlAs barrier layer 13, having a thickness of 10 nm, an In composition of 75%, and being non-doped;

[0043] The InAlAs space layer 15 on the InGaAs channel layer 14 has a thickness of 5 nm, an In composition of 52%, and is non-doped;

[0044] The Delta doped layer 16 on the InAlAs spacer layer 15 has a thickness of 1 nm and is doped with Si at a doping concentration of 2×10 19 cm -3 ;

[0045] The InAlAs Schottky layer 17 on the Delta doped layer 16 has a thickness of 50 nm, an In component of 52%, is doped with Si, and has a doping concentration of 5×10 17 cm -3 ;

[0046] The InP stop layer 18 on the InAlAs Schottky layer 17 has a thickness of 2 nm and is doped with Si with a doping concentration of 1×10 18 cm -3 ;

[0047] The first InGaAs contact layer 19 on the InP stop layer 18 has a thickness of 50 nm and is doped with Si with a doping concentration of 1×10 19 cm -3 .

[0048] According to the embodiment of the present invention, the buffer layer of InAlAs mHEMT is manufactured by using InAlAs buffer layer and InAlP buffer layer. Firstly, the material quality is improved. Then, O is doped in the buffer layer to increase the resistivity of the buffer layer, reduce device leakage, and improve device performance.

[0049] Figure 6 is a schematic structural diagram of an mHBT device according to an embodiment of the present invention.

[0050] Reference Figure 6 , the mHBT device according to an embodiment of the present invention comprises:

[0051] GaAs substrate 10, which is 500 μm thick and semi-insulating;

[0052] The InAlAs buffer layer 11 on the GaAs substrate 10 has a thickness of 500 nm, an In component that increases from 0% to 25% in a step-by-step manner, and is non-doped;

[0053] The InGaP buffer layer 12' on the InAlAs buffer layer 11 has a thickness of 500nm, an In component that increases from 76% to 100% in a step-by-step manner, and is non-doped;

[0054] The InP sub-collector region 13' on the InGaP buffer layer 12' has a thickness of 500nm and is doped with Si at a doping concentration of 2×10 18 cm -3 ;

[0055] The InP collector region 14' on the InP sub-collector region 13' has a thickness of 300 nm and is doped with Si at a doping concentration of 5×10 16 cm -3 ;

[0056] The InGaAs collector region 15' on the InP collector region 14' has a thickness of 200nm, an In component of 53%, and is doped with Si at a doping concentration of 2×10 16 cm -3 ;

[0057] The InGaAs base region 16' on the InGaAs collector region 15' has a thickness of 50nm, an In component of 53%, and is doped with C at a doping concentration of 1×10 20 cm -3 ;

[0058] The InP emitter region 17' on the InGaAs base region 16' has a thickness of 30 nm and is doped with Si at a doping concentration of 3×10 17 cm -3 ;

[0059] The second InGaAs contact layer 18' on the InP emitter region 17' has a thickness of 100 nm and is doped with Si at a doping concentration of 1×10 19 cm -3 .

[0060] According to the embodiment of the present invention, the buffer layer of the InP mHBT is made of an InAlAs buffer layer and an InGaP buffer layer, which can improve the material quality. InGaP has a higher thermal conductivity than InAlAs, which can reduce thermal resistance and improve device performance.

[0061] The terms "exemplary," "example," and the like used throughout this specification mean "serving as an example, instance, or illustration" and do not mean "preferred" or "advantageous" over other embodiments. The detailed description includes specific details for the purpose of providing an understanding of the described techniques. However, the techniques may be implemented without these specific details. In some instances, in order to avoid obscuring the concepts of the described embodiments, well-known structures and devices are shown in block diagram form.

[0062] The optional implementation modes of the embodiments of the present invention are described in detail above in conjunction with the accompanying drawings. However, the embodiments of the present invention are not limited to the specific details in the above implementation modes. Within the technical concept of the embodiments of the present invention, various simple modifications can be made to the technical solutions of the embodiments of the present invention, and these simple modifications all belong to the protection scope of the embodiments of the present invention.

Claims

1. A buffer layer structure, characterized in that: include: Gallium arsenide substrate; An InAlAs buffer layer and an InAlP or InGaP buffer layer sequentially stacked on the gallium arsenide substrate; The lattice parameter of the InAlAs cache layer is gradually increased from the lattice parameter of gallium arsenide to the predetermined lattice parameter by increasing the In component from 0% to the first predetermined content during the manufacturing process, and the lattice parameter of the InAlP or InGaP cache layer is gradually increased from the predetermined lattice parameter to the lattice parameter of indium phosphide by increasing the In component from the second predetermined content to 100% during the manufacturing process; The InAlAs buffer layer does not undergo phase separation when the In component thereof is the first predetermined content, and the InAlP or InGaP buffer layer does not undergo phase separation when the In component thereof is the second predetermined content.

2. The buffer layer structure according to claim 1, characterized in that: The first predetermined content is 25%, and the predetermined lattice parameter is 5.7615Å.

3. The buffer layer structure according to claim 1 or 2, characterized in that: The second predetermined content is 76%.

4. The buffer layer structure according to claim 1, characterized in that: The method of increasing the In component includes a continuous gradient method or a step gradient method.

5. An mHEMT device, characterized in that: include: The buffer layer structure according to any one of claims 1 to 4; An InAlAs barrier layer on the InAlP or InGaP buffer layer of the buffer layer structure; an InGaAs channel layer on the InAlAs barrier layer; An InAlAs spacer layer on the InGaAs channel layer; A Delta doped layer on the InAlAs spacer layer; An InAlAs Schottky layer on the Delta-doped layer; An InP stop layer on the InAlAs Schottky layer; An InGaAs contact layer is formed on the InP stop layer.

6. An mHBT device, characterized in that: include: The buffer layer structure according to any one of claims 1 to 4; An InP sub-collector region on the InAlP or InGaP buffer layer of the buffer layer structure; An InP collector region on the InP sub-collector region; An InGaAs collector region on the InP collector region; An InGaAs base region on the InGaAs collector region; An InP emitter region on the InGaAs base region; An InGaAs contact layer on the InP emitter region.

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