Semiconductor device and manufacturing method, power module, power conversion circuit and vehicle

Abstract

The present invention discloses a semiconductor device and a preparation method, a power module, a power conversion circuit and a vehicle, wherein the device comprises: a semiconductor body; the semiconductor body comprises a first surface and a second surface arranged opposite to each other, and the semiconductor body further comprises a well region and a first region; a gate structure, the gate structure extends from the first surface into the semiconductor body; the gate structure comprises a first insulating layer and a gate; a second insulating layer, the vertical projection of the second insulating layer on the first surface coincides with the vertical projection of the gate on the first surface; a third insulating layer, the vertical projection of the first insulating layer on both sides of the gate on the first surface is within the vertical projection of the third insulating layer on the first surface; a source electrode located on the first surface; and a drain electrode located on the second surface. The technical solution of the present invention solves the problem of gate-source leakage current failure and improves the reliability of MOSFET semiconductor devices.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a preparation method thereof, a power module, a power conversion circuit and a vehicle. Background Art

[0002] Trench-type silicon carbide (SiC) or gallium nitride (GaN) metal oxide semiconductor field effect transistor (MOSFET) semiconductor devices have the advantages of high current density and small cell size. In order to further reduce the device's specific on-resistance, the size of the cell needs to be reduced to the extreme. Therefore, the size of each part in the cell is small, which places higher requirements on the device design and the accuracy of the exposure machine.

[0003] For trench SiC MOSFET or GaN MOSFET devices, due to the reduction in cell size, the distance between the contact (CT) hole and the gate in the gate trench is small. The CT hole is a hole formed by photolithography and etching of the interlayer dielectric (ILD) layer, which is used to form the source in the CT hole. When the CT hole is formed by photolithography of the ILD, it is easy to produce overlay offset, so that the CT hole is opened on the gate. After the source is formed in the CT hole, the source and the gate are short-circuited, resulting in the problem of gate-source leakage current failure. Summary of the invention

[0004] The present invention provides a semiconductor device and a preparation method thereof, a power module, a power conversion circuit and a vehicle to solve the problem of gate-source leakage current failure.

[0005] In a first aspect, the present invention provides a semiconductor device, wherein the device comprises:

[0006] The semiconductor body comprises a first surface and a second surface which are arranged opposite to each other, and the semiconductor body further comprises a well region and a first region, wherein the first region is arranged on the first surface, and the well region is arranged on a side of the first region away from the first surface;

[0007] A gate structure located on the first surface, the gate structure extending from the first surface into the semiconductor body; the gate structure comprises a first insulating layer and a gate, the first insulating layer is used to insulate the semiconductor body and the gate;

[0008] A second insulating layer is located on a side of the gate structure away from the semiconductor body, wherein a vertical projection of the second insulating layer on the first surface coincides with a vertical projection of the gate on the first surface;

[0009] A third insulating layer is located on the side wall of the second insulating layer, and a vertical projection of the first insulating layer located on both sides of the gate on the first surface is within a vertical projection of the third insulating layer on the first surface;

[0010] a source electrode located on the first surface;

[0011] A drain is located on the second surface.

[0012] Optionally, a gate trench is provided on the first surface, and the gate trench extends from the first surface into the semiconductor body;

[0013] The first insulating layer is located at the bottom and sidewalls of the gate trench;

[0014] The gate is located on a side of the first insulating layer in the gate trench away from the semiconductor body.

[0015] Optionally, a source trench is provided on the first surface, and the source trench extends from the first surface into the semiconductor body; the semiconductor body further includes a fourth insulating layer, and the fourth insulating layer is located at the bottom and sidewalls of the source trench; the semiconductor device further includes a source trench structure;

[0016] The source trench structure is located on a side of the fourth insulating layer away from the semiconductor body;

[0017] The source is located on a side of the source trench structure away from the semiconductor body, the source is electrically connected to the first region, and a vertical projection of the source on the first surface covers vertical projections of the second insulating layer and the third insulating layer on the first surface.

[0018] Optionally, the second insulating layer is recessed at a side away from the semiconductor body and at a side close to the semiconductor body.

[0019] Optionally, a height of the third insulating layer is consistent with a height of an edge of the second insulating layer close to the third insulating layer.

[0020] Optionally, the second insulating layer and the third insulating layer are made of different materials.

[0021] In a second aspect, the present invention provides a method for preparing a semiconductor device, wherein the method comprises:

[0022] A semiconductor body is provided; the semiconductor body comprises a first surface and a second surface arranged opposite to each other, the semiconductor body further comprises a well region and a first region, the first region is arranged on the first surface, and the well region is arranged on a side of the first region away from the first surface;

[0023] A gate structure is formed on the first surface, the gate structure extending from the first surface into the semiconductor body; the gate structure comprises a first insulating layer and a gate, the first insulating layer is used to insulate the semiconductor body and the gate;

[0024] forming a second insulating layer on a side of the gate structure away from the semiconductor body, wherein a vertical projection of the second insulating layer on the first surface coincides with a vertical projection of the gate on the first surface;

[0025] Forming a third insulating layer on the side wall of the second insulating layer, wherein the vertical projection of the first insulating layer on both sides of the gate on the first surface is within the vertical projection of the third insulating layer on the first surface;

[0026] forming a source electrode on the first surface;

[0027] A drain electrode is formed on the second surface.

[0028] Optionally, forming a gate structure on the first surface and forming a second insulating layer on a side of the gate structure away from the semiconductor body includes:

[0029] forming a mask layer on the first surface, wherein the mask layer is provided with a mask groove;

[0030] forming a gate trench on the first surface, the gate trench extending from the first surface into the semiconductor body; a vertical projection of the gate trench on the first surface coincides with a vertical projection of the mask trench on the first surface;

[0031] forming a first insulating layer in the gate trench and on the sidewalls of the mask trench;

[0032] forming a gate on a side of the first insulating layer in the gate trench away from the semiconductor body;

[0033] forming a second insulating layer on a side of the first insulating layer in the mask trench away from the mask layer;

[0034] The mask layer and the first insulating layer on the sidewalls of the mask trench are removed.

[0035] Optionally, forming a third insulating layer on a sidewall of the second insulating layer includes:

[0036] forming a third insulating layer on the first surface of the semiconductor body and on a side of the second insulating layer away from the semiconductor body;

[0037] The third insulating layer on the sidewall of the second insulating layer is retained by etching back.

[0038] Optionally, the semiconductor body further includes a fourth insulating layer, and the semiconductor device further includes a source trench structure; providing the semiconductor body and forming a source on the first surface includes:

[0039] Forming a source trench on the first surface; the source trench extends from the first surface into the semiconductor body;

[0040] forming a fourth insulating layer at the bottom and sidewalls of the source trench;

[0041] forming a source trench structure on a side of the fourth insulating layer in the source trench away from the semiconductor body;

[0042] A source is formed on a side of the source trench structure away from the semiconductor body. The source is electrically connected to the first region, and a vertical projection of the source on the first surface covers vertical projections of the second insulating layer and the third insulating layer on the first surface.

[0043] In a third aspect, the present invention provides a power module, which includes a substrate and at least one semiconductor device provided in the first aspect, wherein the substrate is used to carry the semiconductor device.

[0044] In a fourth aspect, the present invention provides a power conversion circuit, wherein the power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction;

[0045] The power conversion circuit includes a circuit board and at least one semiconductor device as provided in the first aspect above, and the semiconductor device is electrically connected to the circuit board.

[0046] In a fifth aspect, the present invention provides a vehicle, comprising a load and a power conversion circuit as provided in the fourth aspect above, the power conversion circuit being used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

[0047] In the technical solution of the present invention, the vertical projection of the second insulating layer on the first surface coincides with the vertical projection of the gate on the first surface, and a third insulating layer is arranged on the side wall of the second insulating layer, and the vertical projection of the first insulating layer on both sides of the gate on the first surface is within the vertical projection of the third insulating layer on the first surface. Therefore, there is a certain distance between the CT hole and the gate, and this distance can be determined by the width of the third insulating layer parallel to the first surface. By controlling the width of the third insulating layer parallel to the first surface, the distance between the CT hole and the gate can be accurately controlled. The formation of the CT hole does not depend on the etching process of the interlayer insulating layer composed of the second insulating layer and the third insulating layer, so there is no easy occurrence of overlay offset in the process of etching the CT hole, so that the CT hole is opened on the gate. After the source electrode is formed in the CT hole, the source electrode and the gate are insulated and isolated, so there is no leakage current failure problem between the gate structure and the source electrode. The technical solution of the present invention solves the problem of gate-source leakage current failure and improves the reliability of MOSFET semiconductor devices.

[0048] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0050] Figure 1 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present invention;

[0051] Figure 2 is a schematic structural diagram of another semiconductor device provided by an embodiment of the present invention;

[0052] Figure 3 is a flow chart of a method for preparing a semiconductor device provided by an embodiment of the present invention;

[0053] Figure 4-Figure 9 It is a structural diagram corresponding to each step of a method for preparing a semiconductor device provided by an embodiment of the present invention;

[0054] Fig.10 is a flow chart of another method for preparing a semiconductor device provided by an embodiment of the present invention;

[0055] Figure 11-Figure 15 It is a structural diagram corresponding to some steps of another method for preparing a semiconductor device provided by an embodiment of the present invention;

[0056] Fig.16 is a flow chart of another method for preparing a semiconductor device provided by an embodiment of the present invention;

[0057] Fig.17 It is a structural diagram corresponding to some steps of another method for preparing a semiconductor device provided by an embodiment of the present invention;

[0058] Fig.18 is a flow chart of another method for preparing a semiconductor device provided by an embodiment of the present invention;

[0059] Fig.19 is a flow chart of another method for preparing a semiconductor device provided by an embodiment of the present invention;

[0060] Figure 20-22 It is a structural diagram corresponding to some steps of another method for preparing a semiconductor device provided by an embodiment of the present invention;

[0061] Fig.23 It is a flow chart of another method for preparing a semiconductor device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0062] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0063] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0064] In order to solve the problem of gate-source leakage current failure of MOSFET semiconductor devices and improve the reliability of MOSFET semiconductor devices, the embodiment of the present invention provides the following technical solutions:

[0065] Figure 1 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present invention, Figure 2 is a schematic diagram of the structure of another semiconductor device provided by an embodiment of the present invention, such as Figure 1 and Figure 2As shown, the semiconductor device comprises: a semiconductor body 1; the semiconductor body 1 comprises a first surface 101 and a second surface 102 arranged opposite to each other, the semiconductor body 1 further comprises a well region 13 and a first region 14, the first region 14 is arranged on the first surface 101, and the well region 13 is arranged on a side of the first region 14 away from the first surface 101. A gate structure 2 is located on the first surface 101, and the gate structure 2 extends from the first surface 101 into the semiconductor body 1. The gate structure 2 comprises a first insulating layer 21 and a gate 22, and the first insulating layer 21 is used to insulate the semiconductor body 1 and the gate 22. A second insulating layer 3 is located on a side of the gate structure 2 away from the semiconductor body 1, and the vertical projection of the second insulating layer 3 on the first surface 101 coincides with the vertical projection of the gate 22 on the first surface 101. A third insulating layer 4 is located on the sidewall of the second insulating layer 3, and the vertical projection of the first insulating layer 21 on both sides of the gate 22 on the first surface 101 is within the vertical projection of the third insulating layer 4 on the first surface 101. A source 5 is located on the first surface 101, and a drain 6 is located on the second surface 102.

[0066] A semiconductor device according to an embodiment of the present invention comprises Figure 1 The single trench MOSFET semiconductor device shown and Figure 2 A double trench MOSFET semiconductor device is shown.

[0067] Alternatively, if Figure 1 As shown, the semiconductor body 1 also includes a second region 15, the doping concentration of the second region 15 is greater than the doping concentration of the well region 13, and a good ohmic contact can be formed with the source 5. It should be noted that the MOSFET semiconductor device may include an N-channel MOSFET semiconductor device or a P-channel MOSFET semiconductor device. Exemplarily, for an N-channel MOSFET semiconductor device, the semiconductor body 1 is an N-type semiconductor body, the well region 13 is a P-type well region, the first region 14 is an N++ doping region, and the second region 15 is a P++ doping region. For a P-channel MOSFET semiconductor device, the semiconductor body 1 is a P-type semiconductor body, the well region 13 is an N-type well region, the first region 14 is a P++ doping region, and the second region 15 is an N++ doping region.

[0068] For example, in Figure 1 and Figure 2In the embodiment, the semiconductor body 1 further includes a substrate 11 and an epitaxial layer 12. For an N-channel MOSFET semiconductor device, the substrate 11 includes an N+ substrate, and the epitaxial layer 12 includes an N-epitaxial layer. For a P-channel MOSFET semiconductor device, the substrate 11 includes a P+ substrate, and the epitaxial layer 12 includes a P-epitaxial layer. In some embodiments of the present invention, the semiconductor body 1 may also include only the epitaxial layer 12. In other embodiments of the present invention, the semiconductor body 1 may also include a substrate 11 and a semiconductor layer formed by other processes. Among them, the epitaxial layer 12 is a semiconductor layer formed by a single epitaxial process on the basis of the substrate 11, and the epitaxial process includes processes such as chemical vapor epitaxy (CVE), molecular beam epitaxy (MBD), and atomic layer epitaxy (ALE).

[0069] The second insulating layer 3 and the third insulating layer 4 in the embodiment of the present invention are used as interlayer insulating layers, and the second insulating layer 3 and the third insulating layer 4 are used together to insulate the gate structure 2 and the source 5. Exemplarily, the second insulating layer 3 can be a silicon nitride insulating layer, and the first insulating layer 21 and the third insulating layer 4 can be silicon oxide insulating layers, which are not specifically limited here. The source 5 is electrically connected to the first region 14.

[0070] According to the technical solution of the embodiment of the present invention, the vertical projection of the second insulating layer 3 on the first surface 101 coincides with the vertical projection of the gate 22 on the first surface 101, and the third insulating layer 4 is disposed on the side wall of the second insulating layer 3, and the vertical projection of the first insulating layer 21 on both sides of the gate 22 on the first surface 101 is within the vertical projection of the third insulating layer 4 on the first surface 101. Therefore, there is a certain distance between the CT hole and the gate 22, and this distance can be determined by the width of the third insulating layer 4 parallel to the first surface 101. By controlling the width of the third insulating layer 4 parallel to the first surface 101, the distance between the CT hole and the gate 22 can be accurately controlled. The formation of the CT hole does not rely on the etching process of the interlayer insulating layer formed by the second insulating layer 3 and the third insulating layer 4. Therefore, there is no easy occurrence of overlay offset in the process of etching the CT hole, so that the CT hole is opened on the gate 22. After the source 5 is formed in the CT hole, the source 5 and the gate 22 are insulated and isolated. Therefore, there is no leakage current failure problem between the gate structure 2 and the source 5. The technical solution of the embodiment of the present invention solves the problem of gate-source leakage current failure and improves the reliability of the MOSFET semiconductor device.

[0071] Optionally, based on the above embodiment, continue to refer to Figure 1 and Figure 2For the single trench MOSFET semiconductor device and the double trench MOSFET semiconductor device, the first surface 101 is provided with a gate trench, and the gate trench extends from the first surface 101 into the first semiconductor body 1. The first insulating layer 21 is located at the bottom and sidewalls of the gate trench, and the gate 22 is located on a side of the first insulating layer 21 in the gate trench away from the semiconductor body 1.

[0072] Specifically, for a single trench MOSFET semiconductor device and a double trench MOSFET semiconductor device, the gate structure 2 is a trench gate structure. The trench gate structure includes a first insulating layer 21 and a gate 22, wherein the first insulating layer 21 is disposed at the bottom and sidewalls of the gate trench, and the gate 22 is disposed on a side of the first insulating layer 21 away from the semiconductor body 1. Exemplarily, the gate 22 may be a polysilicon electrode. The trench gate structure may eliminate the JFET effect, thereby reducing the on-resistance of the MOSFET semiconductor device.

[0073] Optionally, based on the above embodiments, continue to refer to Figure 1 For a single trench MOSFET semiconductor device, the source 5 is located on the first surface 101 of the semiconductor body 1, the source 5 is electrically connected to the first region 14, and the vertical projection of the source 5 on the first surface 101 covers the vertical projections of the second insulating layer 3 and the third insulating layer 4 on the first surface 101.

[0074] Specifically, for a single trench MOSFET semiconductor device, the gate structure 2 is a trench gate structure, the source structure is a planar source structure, and there is no need to set a source trench. The source 5 can be a metal electrode, and the source 5 is electrically connected to the first region 14. The manufacturing process of the single trench MOSFET semiconductor device is simple, which can effectively simplify the manufacturing process of the MOSFET semiconductor device, thereby effectively reducing the time cost.

[0075] Optionally, based on the above embodiments, continue to refer to Figure 2 For a double trench MOSFET semiconductor device, a source trench is provided on the first surface 101, and the source trench extends from the first surface 101 into the semiconductor body 1. The semiconductor body 1 further includes a fourth insulating layer 17, and the semiconductor device further includes a source trench structure 8. The fourth insulating layer 17 is located at the bottom and sidewalls of the source trench, the source trench structure 8 is located at a side of the fourth insulating layer 17 away from the semiconductor body 1, the source 5 is located at a side of the source trench structure 8 away from the semiconductor body 1, the source 5 is electrically connected to the first region 14, and the vertical projection of the source 5 on the first surface 101 covers the vertical projections of the second insulating layer 3 and the third insulating layer 4 on the first surface 101.

[0076] Specifically, for a dual trench MOSFET semiconductor device, the gate structure 2 is a trench gate structure, and the source structure is a trench source structure. The fourth insulating layer 17 may be a silicon oxide insulating layer, the source trench structure 8 may be a polysilicon trench structure, the source 5 may be a metal electrode, and the source 5 is electrically connected to the first region 14. The provision of the trench source structure can effectively alleviate the high electric field distribution at the first insulating layer 21 on one side of the trench gate structure close to the semiconductor body 1. Exemplarily, the source trench is located inside the second region 15.

[0077] Optionally, based on the above embodiments, continue to refer to Figure 1 and Figure 2 The second insulating layer 3 is recessed toward a side close to the semiconductor body 1 on a side away from the semiconductor body 1 .

[0078] Specifically, the second insulating layer 3 is formed by deposition and etching processes, and the side of the second insulating layer 3 away from the semiconductor body 1 is recessed toward the side close to the semiconductor body 1 , which is determined by the etching process.

[0079] Optionally, based on the above embodiments, continue to refer to Figure 1 and Figure 2 , the height of the third insulating layer 4 is consistent with the height of the edge of the second insulating layer 3 close to the third insulating layer 4.

[0080] Specifically, due to the etching process, the second insulating layer 3 is recessed from the side away from the semiconductor body 1 to the side close to the semiconductor body 1, and the height of the edge close to the third insulating layer 4 can be consistent with the height of the third insulating layer 4. The second insulating layer 3 and the third insulating layer 4 can be used together as an interlayer dielectric layer to insulate the gate 21 and the source 5.

[0081] Optionally, based on the above embodiments, continue to refer to Figure 1 and Figure 2 , the materials of the second insulating layer 3 and the third insulating layer 4 are different.

[0082] Specifically, the removal rate selection ratio of the third insulating layer 4 and the second insulating layer 3 should be large enough, and the removal rate selection ratio of the first insulating layer 21 and the second insulating layer 3 should be large enough. Exemplarily, the second insulating layer 3 can be a silicon nitride insulating layer, and the first insulating layer 21 and the third insulating layer 4 can be silicon oxide insulating layers, so as to ensure that the second insulating layer 3 will not be affected when the first insulating layer 21 and the third insulating layer 4 are removed.

[0083] Optionally, based on the above embodiments, continue to refer to Figure 1 and Figure 2 , the semiconductor body 1 includes a silicon carbide semiconductor body or a gallium nitride semiconductor body.

[0084] Specifically, a MOSFET semiconductor device composed of a silicon carbide semiconductor body or a gallium nitride semiconductor body has the advantages of high withstand voltage, low on-resistance and high frequency, which can further improve the performance of the semiconductor device.

[0085] Figure 3 is a flow chart of a method for preparing a semiconductor device provided by an embodiment of the present invention, such as Figure 3 As shown, the method includes:

[0086] S100: Provide a semiconductor body; the semiconductor body includes a first surface and a second surface that are arranged opposite to each other, and the semiconductor body also includes a well region and a first region, the first region is arranged on the first surface, and the well region is arranged on a side of the first region away from the first surface.

[0087] Specifically, Figure 4 As shown, a semiconductor body 1 is first provided, and the semiconductor body 1 may include a substrate 11 and an epitaxial layer 12. In some embodiments of the present invention, the semiconductor body 1 may also include only the epitaxial layer 12. In other embodiments of the present invention, the semiconductor body 1 may also include a substrate 11 and a semiconductor layer formed by other processes. A semiconductor layer is formed on one side of the substrate 11 by a single epitaxial process, and the epitaxial process includes chemical vapor epitaxy (CVE), molecular beam epitaxy (MBD), and atomic layer epitaxy (ALE) to form the epitaxial layer 12.

[0088] The semiconductor body 1 may further include a well region 13, a first region 14 and a second region 15. The well region 13, the first region 14 and the second region 15 are formed on the side of the epitaxial layer 12 away from the substrate 11 by processes such as doping, and then the doped impurities are activated by an annealing process.

[0089] The MOSFET semiconductor device may include an N-channel MOSFET semiconductor device or a P-channel MOSFET semiconductor device. For an N-channel MOSFET semiconductor device, the substrate 11 includes an N+ substrate, the epitaxial layer 12 includes an N-epitaxial layer, the well region 13 is a P-type well region, the first region 14 is an N++ doped region, and the second region 15 is a P++ doped region. For a P-channel MOSFET semiconductor device, the substrate 11 includes a P+ substrate, the epitaxial layer 12 includes a P-epitaxial layer, the well region 13 is an N-type well region, the first region 14 is a P++ doped region, and the second region 15 is an N++ doped region.

[0090] S110: forming a gate structure on the first surface, wherein the gate structure extends from the first surface into the semiconductor; the gate structure comprises a first insulating layer and a gate, wherein the first insulating layer is used to insulate the semiconductor body and the gate.

[0091] Specifically, Figure 5As shown, a gate structure 2 is formed on the first surface 101, and the gate structure 2 extends into the semiconductor body 1. The gate structure 2 includes a first insulating layer 21 and a gate 22. Exemplarily, a gate trench can be provided on the first surface 101, the first insulating layer 21 can be formed by depositing silicon oxide at the bottom and sidewalls of the gate trench, and the gate 22 can be formed by depositing doped polysilicon on the side of the first insulating layer 21 away from the semiconductor body 1.

[0092] S120: forming a second insulating layer on a side of the gate structure away from the semiconductor body, wherein a vertical projection of the second insulating layer on the first surface coincides with a vertical projection of the gate on the first surface.

[0093] Specifically, Figure 6 As shown, a second insulating layer 3 is formed on a side of the gate structure 2 away from the semiconductor body 1. Exemplarily, the second insulating layer 3 is formed by depositing silicon nitride on a side of the gate structure 2 away from the semiconductor body 1. In the embodiment of the present invention, the vertical projection of the second insulating layer 3 on the first surface 101 coincides with the vertical projection of the gate 22 on the first surface 101.

[0094] S130: forming a third insulating layer on the sidewalls of the second insulating layer, wherein the vertical projections of the first insulating layer located at both sides of the gate on the first surface are within the vertical projections of the third insulating layer on the first surface.

[0095] Specifically, Figure 7 As shown, a third insulating layer 4 is formed on the sidewall of the second insulating layer 3. For example, the third insulating layer 4 can be formed by forming silicon oxide on the sidewall of the second insulating layer 3. The second insulating layer 3 and the third insulating layer 4 are used together as interlayer dielectric layers to insulate the gate structure 2 and the source 5.

[0096] S140: forming a source electrode on the first surface.

[0097] Specifically, Figure 8 As shown, for a single trench MOSFET semiconductor device, the source structure is a planar source structure, and no source trench is required. A source 5 is formed on the first surface 101. Exemplarily, metal is deposited on the first surface 101 to form the source 5. The source 5 is electrically connected to the first region 14, and the vertical projection of the source 5 on the first surface 101 covers the vertical projection of the second insulating layer 3 and the third insulating layer 4 on the first surface 101.

[0098] like Fig. 9As shown, for a double trench MOSFET semiconductor device, the source structure is a trench source structure. The semiconductor body 2 also includes a fourth insulating layer 17, and the semiconductor device may also include a source trench structure 8. Exemplarily, a source trench is provided inside the second region 15, and a fourth insulating layer 17 is formed by depositing silicon oxide at the bottom and sidewalls of the source trench, and a doped polysilicon, metal or non-metallic material is deposited on the side of the fourth insulating layer 17 away from the semiconductor body 1 to form a source trench structure 8, and a metal is deposited on the side of the source trench structure 8 away from the semiconductor body 1 to form a source 5. The source 5 is electrically connected to the first region 14, and the vertical projection of the source 5 on the first surface 101 covers the vertical projections of the second insulating layer 3 and the third insulating layer 4 on the first surface 101.

[0099] S150: forming a drain electrode on the second surface.

[0100] Specifically, Figure 1 and Figure 2 As shown, for the single trench MOSFET semiconductor device and the double trench MOSFET semiconductor device, the drain 6 is formed on the second surface 102 . Exemplarily, the drain 6 is formed by depositing metal on the second surface 102 .

[0101] According to the technical solution of the embodiment of the present invention, the vertical projection of the second insulating layer 3 on the first surface 101 coincides with the vertical projection of the gate 22 on the first surface 101, and the third insulating layer 4 is disposed on the side wall of the second insulating layer 3, and the vertical projection of the first insulating layer 21 on both sides of the gate 22 on the first surface 101 is within the vertical projection of the third insulating layer 4 on the first surface 101. Therefore, there is a certain distance between the CT hole and the gate 22, and this distance can be determined by the width of the third insulating layer 4 parallel to the first surface 101. By controlling the width of the third insulating layer 4 parallel to the first surface 101, the distance between the CT hole and the gate 22 can be accurately controlled. The formation of the CT hole does not rely on the etching process of the interlayer insulating layer formed by the second insulating layer 3 and the third insulating layer 4. Therefore, there is no easy occurrence of overlay offset in the process of etching the CT hole, so that the CT hole is opened on the gate 22. After the source 5 is formed in the CT hole, the source 5 and the gate 22 are insulated and isolated. Therefore, there is no leakage current failure problem between the gate structure 2 and the source 5. The technical solution of the embodiment of the present invention solves the problem of gate-source leakage current failure and improves the reliability of the MOSFET semiconductor device.

[0102] Optionally, based on the above embodiments, Fig.10 is a flow chart of another method for preparing a semiconductor device provided by an embodiment of the present invention, such as Fig.10 As shown, the method includes:

[0103] S200: Provide a semiconductor body; the semiconductor body includes a first surface and a second surface that are arranged opposite to each other, and the semiconductor body also includes a well region and a first region, the first region is arranged on the first surface, and the well region is arranged on a side of the first region away from the first surface.

[0104] S210: forming a mask layer on the first surface, wherein the mask layer is provided with a mask trench.

[0105] Specifically, Fig.11 As shown, a mask layer 7 is formed on the first surface 101 of the semiconductor body 1, and the mask layer 7 is provided with a mask groove 71. Exemplarily, the mask layer 7 can be first deposited on the first surface 101, and then the pattern of the mask layer 7 is defined by photolithography and etching. In the embodiment of the present invention, the pattern of the mask layer 7 is the mask groove 71.

[0106] S220: forming a gate trench on the first surface, wherein the gate trench extends from the first surface into the semiconductor body; a vertical projection of the gate trench on the first surface coincides with a vertical projection of the mask trench on the first surface.

[0107] Specifically, Fig.12 As shown, a gate trench 18 is formed on the first surface 101 by an etching process according to the width of the mask trench 71 . The gate trench 18 penetrates the well region 13 and the first region 14 and extends into the epitaxial layer 12 .

[0108] S230: forming a first insulating layer in the gate trench and on the sidewalls of the mask trench.

[0109] Specifically, Fig.13 As shown, a first insulating layer 21 is formed in the gate trench 18 and on the sidewalls of the mask trench 71. Exemplarily, silicon oxide is deposited on the side of the mask layer 7 away from the semiconductor body 1, in the gate trench 18 and on the sidewalls of the mask trench 71 to form the first insulating layer 21. Then, the first insulating layer 21 on the side of the mask layer 7 away from the semiconductor body 1 can be removed, or it can be removed in S260.

[0110] S240: forming a gate on a side of the first insulating layer in the gate trench away from the semiconductor body.

[0111] Specifically, Fig.14 As shown, a gate 22 is formed on a side of the first insulating layer 21 away from the semiconductor body 1, and the gate 22 is located in the gate trench, and in the thickness direction of the semiconductor body 1, the upper interface of the gate 22 is flush with the first surface of the semiconductor body 1. Exemplarily, doped polysilicon can be deposited on the entire surface of the device first, and then the gate 22 in the gate trench is retained by an etch-back process.

[0112] S250: forming a second insulating layer on a side of the first insulating layer in the mask trench away from the mask layer.

[0113] Specifically, Fig.15 As shown, a second insulating layer 3 is formed on a side of the first insulating layer 21 away from the mask layer 7, and the second insulating layer 3 is located in the mask groove. For example, silicon nitride can be deposited on the entire surface of the device first, and then the silicon nitride in the mask groove is retained by etching back to form the second insulating layer 3. Due to the existence of the mask layer 7, it is ensured that the vertical projection of the second insulating layer 3 on the first surface 101 coincides with the vertical projection of the gate 22 on the first surface 101.

[0114] S260: removing the mask layer and the first insulating layer on the sidewalls of the mask trench.

[0115] Specifically, Figure 6 As shown, the mask layer and the first insulating layer 21 on the sidewall of the mask trench are removed to form Figure 6 When removing the first insulating layer 21 on the sidewall of the mask trench, it is necessary to ensure that the second insulating layer 3 is not damaged, that is, the removal rate selection ratio of the first insulating layer 21 and the second insulating layer 3 is large enough. For example, the first insulating layer 21 can be silicon oxide, and the second insulating layer 3 can be silicon nitride.

[0116] S270: forming a third insulating layer on the sidewalls of the second insulating layer, wherein the vertical projections of the first insulating layer located at both sides of the gate on the first surface are within the vertical projections of the third insulating layer on the first surface.

[0117] S280: forming a source electrode on the first surface.

[0118] S290: forming a drain on the second surface.

[0119] According to the technical solution of the embodiment of the present invention, the mask layer 7 is retained after etching the gate trench 18, and the mask layer 7 is removed after forming the second insulating layer 3, so as to ensure that the vertical projection of the second insulating layer 3 on the first surface 101 and the vertical projection of the gate 22 on the first surface 101 coincide with each other, so that there is no overlapping part between the CT hole and the gate 22. Then, the third insulating layer 4 is formed on the side wall of the second insulating layer 3, and the vertical projection of the first insulating layer 21 on both sides of the gate 22 on the first surface 101 is within the vertical projection of the third insulating layer 4 on the first surface 101, so there is a certain distance between the CT hole and the gate 22, and this distance can be determined by the width of the third insulating layer 4 parallel to the first surface 101. By controlling the width of the third insulating layer 4 parallel to the first surface 101, the distance between the CT hole and the gate 22 can be accurately controlled. The formation of the CT hole does not rely on the etching process of the interlayer insulating layer formed by the second insulating layer 3 and the third insulating layer 4. Therefore, there is no easy occurrence of overlay offset in the process of etching the CT hole, which causes the CT hole to be opened on the gate 22. After the source 5 is formed in the CT hole, the source 5 and the gate 22 are insulated and isolated. Therefore, there is no leakage current failure problem between the gate structure 2 and the source 5.

[0120] Optionally, based on the above embodiments, Fig.16 is a flow chart of another method for preparing a semiconductor device provided by an embodiment of the present invention, such as Fig.16 As shown, the method includes:

[0121] S300: Provide a semiconductor body; the semiconductor body includes a first surface and a second surface that are arranged opposite to each other, and the semiconductor body also includes a well region and a first region, the first region is arranged on the first surface, and the well region is arranged on a side of the first region away from the first surface.

[0122] S310: forming a gate structure on the first surface, wherein the gate structure extends from the first surface into the semiconductor; the gate structure comprises a first insulating layer and a gate, wherein the first insulating layer is used to insulate the semiconductor body and the gate.

[0123] S320: forming a second insulating layer on a side of the gate structure away from the semiconductor body, wherein a vertical projection of the second insulating layer on the first surface coincides with a vertical projection of the gate on the first surface.

[0124] S330 : forming a third insulating layer on the first surface of the semiconductor body and on a side of the second insulating layer away from the semiconductor body.

[0125] Specifically, Fig.17 As shown, a third insulating layer 4 is formed on the entire surface of the device. Exemplarily, the third insulating layer 4 is formed by depositing silicon oxide on the entire surface of the device.

[0126] S340: retaining the third insulating layer on the sidewall of the second insulating layer by etching back.

[0127] Specifically, Figure 7 As shown, the redundant third insulating layer 4 is removed by an etch-back process, and the third insulating layer 4 on the side wall of the second insulating layer 3 is retained. It is necessary to ensure that the structure of the second insulating layer 3 is not damaged while the third insulating layer 4 is etched back, that is, the removal rate selection ratio of the third insulating layer 4 and the second insulating layer 3 is large enough. For example, the third insulating layer 4 can be silicon oxide, and the second insulating layer 3 can be silicon nitride.

[0128] S350: forming a source electrode on the first surface.

[0129] S360: forming a drain on the second surface.

[0130] Optionally, based on the above embodiments, for a single trench MOSFET semiconductor device, Fig.18 is a flow chart of another method for preparing a semiconductor device provided by an embodiment of the present invention, such as Fig.18 As shown, the method includes:

[0131] S400: Provide a semiconductor body; the semiconductor body includes a first surface and a second surface that are arranged opposite to each other, and the semiconductor body also includes a well region and a first region, the first region is arranged on the first surface, and the well region is arranged on a side of the first region away from the first surface.

[0132] S410: forming a gate structure on the first surface, wherein the gate structure extends from the first surface into the semiconductor; the gate structure comprises a first insulating layer and a gate, wherein the first insulating layer is used to insulate the semiconductor body and the gate.

[0133] S420: forming a second insulating layer on a side of the gate structure away from the semiconductor body, wherein a vertical projection of the second insulating layer on the first surface coincides with a vertical projection of the gate on the first surface.

[0134] S430: forming a third insulating layer on the sidewalls of the second insulating layer, wherein the vertical projections of the first insulating layer located at both sides of the gate on the first surface are within the vertical projections of the third insulating layer on the first surface.

[0135] S440: forming a source electrode on the first surface of the semiconductor body, the source electrode being electrically connected to the first region, and a vertical projection of the source electrode on the first surface covering vertical projections of the second insulating layer and the third insulating layer on the first surface.

[0136] Specifically, Figure 8As shown, for a single trench MOSFET semiconductor device, the source structure is a planar source structure, that is, no source trench is required. A source 5 is formed on the first surface 101. Exemplarily, a metal is deposited on the first surface 101 to form the source 5. The source 5 is electrically connected to the first region 14, and the vertical projection of the source 5 on the first surface 101 covers the vertical projection of the second insulating layer 3 and the third insulating layer 4 on the first surface 101. The manufacturing process of the single trench MOSFET semiconductor device is simple, which can effectively simplify the manufacturing process of the MOSFET semiconductor device, thereby effectively reducing the time cost.

[0137] S450: forming a drain electrode on the second surface.

[0138] Optionally, based on the above embodiments, for a double trench MOSFET semiconductor device, Fig.19 is a flow chart of another method for preparing a semiconductor device provided by an embodiment of the present invention, such as Fig.19 As shown, the method includes:

[0139] S500: Provide a semiconductor body; the semiconductor body includes a first surface and a second surface that are arranged opposite to each other, and the semiconductor body also includes a well region and a first region, the first region is arranged on the first surface, and the well region is arranged on a side of the first region away from the first surface.

[0140] S510: forming a gate structure on the first surface, wherein the gate structure extends from the first surface into the semiconductor; the gate structure comprises a first insulating layer and a gate, wherein the first insulating layer is used to insulate the semiconductor body and the gate.

[0141] S520: forming a second insulating layer on a side of the gate structure away from the semiconductor body, wherein a vertical projection of the second insulating layer on the first surface coincides with a vertical projection of the gate on the first surface.

[0142] S530: forming a third insulating layer on the sidewalls of the second insulating layer, wherein the vertical projections of the first insulating layer located at both sides of the gate on the first surface are within the vertical projections of the third insulating layer on the first surface.

[0143] S540: forming a source trench on the first surface; the source trench extends from the first surface into the semiconductor body.

[0144] Specifically, Fig. 20 As shown, for the double trench MOSFET semiconductor device, the source structure is a trench source structure, and a source trench 16 is formed on the first surface 101 by an etching process, and the source trench 16 is located inside the second region 15 .

[0145] S550: forming a fourth insulating layer on the bottom and sidewalls of the source trench.

[0146] Specifically, Fig.21 As shown, a fourth insulating layer 17 is formed at the bottom and sidewalls of the source trench 16 . Exemplarily, silicon oxide is deposited at the bottom and sidewalls of the source trench 16 to form the fourth insulating layer 17 .

[0147] S560: forming a source trench structure on a side of the fourth insulating layer in the source trench away from the semiconductor body.

[0148] Specifically, Fig. 22 As shown, a source trench structure 8 is formed on the side of the fourth insulating layer 17 away from the semiconductor body 1, and the source trench structure 8 is located in the source trench. Exemplarily, doped polysilicon, metal or non-metallic materials are deposited on the side of the fourth insulating layer 17 away from the semiconductor body 1 to form the source trench structure 8.

[0149] S570: forming a source electrode on a side of the source trench structure away from the semiconductor body, the source electrode being electrically connected to the first region, and a vertical projection of the source electrode on the first surface covering vertical projections of the second insulating layer and the third insulating layer on the first surface.

[0150] Specifically, Fig. 9 As shown, metal is deposited on the side of the source trench structure 8 away from the semiconductor body 1 to form a source 5. The source 5 is electrically connected to the first region 14, and the vertical projection of the source 5 on the first surface 101 covers the vertical projections of the second insulating layer 3 and the third insulating layer 4 on the first surface 101. The setting of the source trench can effectively alleviate the high electric field distribution at the first insulating layer 21 on the side of the trench gate structure close to the semiconductor body 1.

[0151] S580: forming a drain on the second surface.

[0152] Optionally, based on the above embodiments, Fig.23 is a flow chart of another method for preparing a semiconductor device provided by an embodiment of the present invention, such as Fig.23 As shown, the method includes:

[0153] S600: Provide a silicon carbide semiconductor body or a gallium nitride semiconductor body. The semiconductor body includes a first surface and a second surface arranged opposite to each other, and the semiconductor body also includes a well region and a first region, the first region is arranged on the first surface, and the well region is arranged on a side of the first region away from the first surface.

[0154] Specifically, a MOSFET semiconductor device composed of a silicon carbide semiconductor body or a gallium nitride semiconductor body has the advantages of high withstand voltage, low on-resistance and high frequency, which can further improve the performance of the semiconductor device.

[0155] S610: forming a gate structure on the first surface, wherein the gate structure extends from the first surface into the semiconductor; the gate structure comprises a first insulating layer and a gate, wherein the first insulating layer is used to insulate the semiconductor body and the gate.

[0156] S620: forming a second insulating layer on a side of the gate structure away from the semiconductor body, wherein a vertical projection of the second insulating layer on the first surface coincides with a vertical projection of the gate on the first surface.

[0157] S630: forming a third insulating layer on the sidewalls of the second insulating layer, wherein the vertical projections of the first insulating layer on both sides of the gate on the first surface are within the vertical projections of the third insulating layer on the first surface.

[0158] S640: forming a source electrode on the first surface.

[0159] S650: forming a drain on the second surface.

[0160] An embodiment of the present invention provides a power module, wherein the power module includes a substrate and at least one semiconductor device provided by any of the above embodiments of the present invention, and the substrate is used to carry at least one semiconductor device provided by any of the above embodiments of the present invention.

[0161] The power module provided in any of the above embodiments of the present invention includes the semiconductor device provided in any of the above embodiments of the present invention, and has the beneficial effects of the semiconductor device provided in any of the above embodiments of the present invention.

[0162] An embodiment of the present invention provides a power conversion circuit, wherein the power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction.

[0163] The power conversion circuit includes a circuit board and at least one semiconductor device provided by any one of the above embodiments of the present invention, and the semiconductor device is electrically connected to the circuit board.

[0164] The power conversion circuit provided in any of the above embodiments of the present invention includes the semiconductor device provided in any of the above embodiments of the present invention, and has the beneficial effects of the semiconductor device provided in any of the above embodiments of the present invention.

[0165] An embodiment of the present invention provides a vehicle, wherein the vehicle includes a load and a power conversion circuit provided by any one of the above embodiments of the present invention, and the power conversion circuit is used to convert alternating current into direct current, convert alternating current into alternating current, convert direct current into direct current, or convert direct current into alternating current and then input it into the load.

[0166] The vehicle provided in any of the above embodiments of the present invention includes the power conversion circuit provided in any of the above embodiments of the present invention, and the power conversion circuit provided in any of the above embodiments of the present invention includes the semiconductor device provided in any of the above embodiments of the present invention, so the vehicle provided in any of the above embodiments of the present invention has the beneficial effects of the semiconductor device provided in any of the above embodiments of the present invention.

[0167] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0168] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A semiconductor device, characterized in that: include: A semiconductor body; the semiconductor body comprises a first surface and a second surface arranged opposite to each other, the semiconductor body further comprises a well region and a first region, the first region is arranged on the first surface, and the well region is arranged on a side of the first region away from the first surface; a gate structure located on the first surface, the gate structure extending from the first surface into the semiconductor body; the gate structure comprising a first insulating layer and a gate, the first insulating layer being used to insulate the semiconductor body from the gate; a second insulating layer located on a side of the gate structure away from the semiconductor body, wherein a vertical projection of the second insulating layer on the first surface coincides with a vertical projection of the gate on the first surface; A third insulating layer located on the side wall of the second insulating layer, wherein the vertical projection of the first insulating layer located on both sides of the gate on the first surface is within the vertical projection of the third insulating layer on the first surface; a source electrode located on the first surface; a drain electrode located on the second surface; A contact hole located on the first surface and on a side of the third insulating layer away from the second insulating layer, wherein the source electrode is formed in the contact hole; the contact hole is formed without etching the second insulating layer.

2. The semiconductor device according to claim 1, wherein: The first surface is provided with a gate trench, and the gate trench extends from the first surface into the semiconductor body; The first insulating layer is located at the bottom and sidewalls of the gate trench; The gate is located on a side of the first insulating layer in the gate trench away from the semiconductor body.

3. The semiconductor device according to claim 1, wherein: The first surface is provided with a source trench, and the source trench extends from the first surface into the semiconductor body; the semiconductor body further includes a fourth insulating layer, and the fourth insulating layer is located at the bottom and sidewalls of the source trench; the semiconductor device further includes a source trench structure; The source trench structure is located on a side of the fourth insulating layer away from the semiconductor body; The source is located on a side of the source trench structure away from the semiconductor body, the source is electrically connected to the first region, and a vertical projection of the source on the first surface covers vertical projections of the second insulating layer and the third insulating layer on the first surface.

4. The semiconductor device according to claim 1, wherein: The second insulating layer is recessed toward a side closer to the semiconductor body from a side away from the semiconductor body.

5. The semiconductor device according to claim 1, wherein: The height of the third insulating layer is consistent with the height of the edge of the second insulating layer close to the third insulating layer.

6. The semiconductor device according to claim 1, wherein: The second insulating layer and the third insulating layer are made of different materials.

7. A method for preparing a semiconductor device, characterized in that: include: A semiconductor body is provided; the semiconductor body comprises a first surface and a second surface arranged opposite to each other, the semiconductor body further comprises a well region and a first region, the first region is arranged on the first surface, and the well region is arranged on a side of the first region away from the first surface; A gate structure is formed on the first surface, wherein the gate structure extends from the first surface into the semiconductor body; the gate structure comprises a first insulating layer and a gate, wherein the first insulating layer is used to insulate the semiconductor body from the gate; forming a second insulating layer on a side of the gate structure away from the semiconductor body, wherein a vertical projection of the second insulating layer on the first surface coincides with a vertical projection of the gate on the first surface; forming a third insulating layer on the sidewall of the second insulating layer, wherein the vertical projections of the first insulating layer on both sides of the gate on the first surface are within the vertical projections of the third insulating layer on the first surface; forming a source electrode on the first surface; forming a drain electrode on the second surface; Forming a gate structure on the first surface and forming a second insulating layer on a side of the gate structure away from the semiconductor body comprises: forming a mask layer on the first surface, wherein the mask layer is provided with a mask groove; forming a gate trench on the first surface, wherein the gate trench extends from the first surface into the semiconductor body; a vertical projection of the gate trench on the first surface coincides with a vertical projection of the mask trench on the first surface; forming the first insulating layer in the gate trench and on the sidewalls of the mask trench; forming the gate on a side of the first insulating layer in the gate trench away from the semiconductor body; forming the second insulating layer on a side of the first insulating layer in the mask trench away from the mask layer; The mask layer and the first insulating layer on the sidewalls of the mask trench are removed.

8. The method for preparing a semiconductor device according to claim 7, characterized in that: Forming a third insulating layer on a sidewall of the second insulating layer comprises: forming the third insulating layer on the first surface of the semiconductor body and on a side of the second insulating layer away from the semiconductor body; The third insulating layer on the sidewall of the second insulating layer is retained by etching back.

9. The method for preparing a semiconductor device according to claim 7, characterized in that: The semiconductor body further includes a fourth insulating layer, and the semiconductor device further includes a source trench structure; Providing a semiconductor body and forming a source electrode on the first surface includes: Forming a source trench on the first surface; the source trench extending from the first surface into the semiconductor body; forming the fourth insulating layer at the bottom and sidewalls of the source trench; forming the source trench structure on a side of the fourth insulating layer in the source trench away from the semiconductor body; A source is formed on a side of the source trench structure away from the semiconductor body, the source is electrically connected to the first region, and a vertical projection of the source on the first surface covers vertical projections of the second insulating layer and the third insulating layer on the first surface.

10. A power module, characterized in that: It comprises a substrate and at least one semiconductor device according to any one of claims 1 to 6, wherein the substrate is used for carrying the semiconductor device.

11. A power conversion circuit, characterized in that: The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit comprises a circuit board and at least one semiconductor device according to any one of claims 1 to 6, wherein the semiconductor device is electrically connected to the circuit board.

12. A vehicle, characterized in that: It comprises a load and a power conversion circuit as claimed in claim 11, wherein the power conversion circuit is used to convert alternating current and / or direct current into alternating current and / or direct current and then input the converted alternating current and / or direct current into the load.

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