Complementary field effect transistor and method of making the same

Abstract

The disclosure provides a complementary field effect transistor and a preparation method thereof, the complementary field effect transistor comprising: a substrate; a first field effect transistor in a vertical structure, disposed on the substrate; and a second field effect transistor in a vertical structure, disposed on the first field effect transistor; wherein the first field effect transistor comprises a first channel, the second field effect transistor comprises a second channel, one of the first channel and the second channel is an N-type channel, the other of the first channel and the second channel is a P-type channel, the N-type channel is made of a silicon material, and the P-type channel is made of a silicon germanium material, so that a source-drain current of the first field effect transistor is similar to a source-drain current of the second field effect transistor, and the first field effect transistor and the second field effect transistor share a drain and share a gate.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of vertical channel transistor technology, and in particular to a complementary field effect transistor and a method for manufacturing the same. BACKGROUND

[0002] Vertical channel transistor (VCT) technology is considered as a key technology to improve integration density and continue Moore's law in the future.

[0003] Vertical devices belong to three-dimensional devices, which are different from two-dimensional horizontal devices in terms of logic manufacturing. Especially in the process of vertical device stacking manufacturing, many new technical challenges will arise.

[0004] In the related art, since the electron mobility is nearly twice the hole mobility, when a complementary field effect transistor (CFET) is formed under the same gate width, the current mismatch caused by the difference in electron and hole mobility will result in a decrease in device function. Under the condition of current matching, the device cell area is often determined by the size of the P-type field effect transistor (PMOS), which is not conducive to further miniaturization of the device. SUMMARY

[0005] Therefore, the present disclosure provides a complementary field effect transistor and a method for manufacturing the same, which can make the source-drain current of the P-type field effect transistor close to the source-drain current of the N-type field effect transistor.

[0006] As one method of the embodiments of the present disclosure, a complementary field effect transistor is provided, which includes a substrate, a first field effect transistor of a vertical structure, and a second field effect transistor of a vertical structure. The first field effect transistor is disposed on the substrate, and the second field effect transistor is disposed on the first field effect transistor. The first field effect transistor includes a first channel, and the second field effect transistor includes a second channel. One of the first channel and the second channel is an N-type channel, and the other of the first channel and the second channel is a P-type channel. The N-type channel is made of silicon material, and the P-type channel is made of silicon germanium material. The source-drain current of the first field effect transistor is close to the source-drain current of the second field effect transistor. The first field effect transistor and the second field effect transistor share a drain and a gate.

[0007] As another aspect of the embodiments of the present disclosure, a method for manufacturing any of the above complementary field effect transistors is provided, which includes:

[0008] forming a first growth layer and a second growth layer on the substrate in sequence, wherein the first growth layer comprises two first doped layers stacked and a first silicon germanium layer between the two first doped layers, and the second growth layer comprises two second doped layers stacked and a second silicon germanium layer between the two second doped layers;

[0009] etching one of the first silicon germanium layer and the second silicon germanium layer inward along a first direction parallel to the substrate and depositing a silicon layer as an N-type channel;

[0010] etching from the second doped layer at the upper portion downward along a second direction perpendicular to the substrate to the first doped layer close to the substrate to form a cavity on the substrate, and etching the first silicon germanium layer and the second silicon germanium layer outward along the first direction from the cavity respectively to remove the silicon germanium material adjacent to the N-type channel and to reserve part of the silicon germanium material in the other of the first silicon germanium layer and the second silicon germanium layer as a P-type channel;

[0011] forming a gate dielectric layer and a gate electrode on the periphery of the N-type channel and the P-type channel respectively.

[0012] According to the complementary field effect transistor of the embodiment of the present disclosure, by using silicon germanium (SiGe) material to manufacture the P-type channel, the hole mobility of the P-type channel can be enhanced, so that the source-drain current of the P-type field effect transistor (PMOS) is close to that of the N-type field effect transistor (NMOS) pure silicon channel under the condition of equal gate width. Not only can the PMOS current be flexibly regulated by adjusting the SiGe component, so that the source-drain current of the PMOS is improved and is closer to that of the NMOS, but also the overall performance of the complementary field effect transistor can be improved by matching the electron and hole mobility. Due to the improvement of the matching of the source-drain current of the PMOS and the source-drain current of the NMOS, the device cell area can be more effectively controlled, which is helpful for further miniaturizing the device size and thus improving the integration density of the integrated circuit. BRIEF DESCRIPTION OF DRAWINGS

[0013] The above and other objects, features and advantages of the present disclosure will become more apparent from the following description of embodiments of the present disclosure taken in conjunction with the accompanying drawings, in which:

[0014] Figure 1 a cross-sectional view of a complementary field effect transistor according to an embodiment of the present disclosure is schematically shown;

[0015] Figure 2 a cross-sectional view of a complementary field effect transistor according to another embodiment of the present disclosure is schematically shown;

[0016] Figure 3 an equivalent circuit diagram of a complementary field effect transistor according to an embodiment of the present disclosure is schematically shown.

[0017] Figure 4 A flow chart of a method for fabricating a complementary field effect transistor is schematically shown according to an embodiment of the present disclosure;

[0018] Figures 5 to 28 A flow chart of a method for fabricating a complementary field effect transistor is schematically shown according to an embodiment of the present disclosure; and

[0019] Figures 29 to 42 A flow chart of a method for fabricating a complementary field effect transistor is schematically shown according to an embodiment of the present disclosure.

[0020] Reference signs are explained as follows:

[0021] 1 - substrate; 11 - well layer;

[0022] 2 - first field effect transistor;

[0023] 21 - first channel; 22 - first doped layer; 23 - first gate; 24 - first gate dielectric layer; 25 - first sidewall;

[0024] 3 - second field effect transistor;

[0025] 31 - second channel; 32 - second doped layer; 33 - second gate; 34 - second gate dielectric layer;

[0026] 4 - first growth layer; 41 - first silicon germanium layer;

[0027] 5 - second growth layer; 51 - second silicon germanium layer;

[0028] 6 - barrier layer; 7 - core layer; 8 - sacrificial layer; 9 - first protrusion; 10 - cover layer; 101 - third protrusion; 102 - fourth protrusion; 103 - first annular space; 104 - silicon layer; 105 - first annular groove; 106 - protection layer; 107 - second annular space; 108 - first filling layer; 109 - cavity; 110 - third annular space; 111 - fourth annular space; 112 - second filling layer; 113 - etching layer; 114 - gate dielectric layer; 115 - first source; 116 - second source; 117 - drain; 118 - gate electrode; 120 - third filling layer; 121 - second annular groove. DETAILED DESCRIPTION

[0029] In order to make the objectives, technical solutions and advantages of the present disclosure clearer, the present disclosure is further described in detail below with reference to specific embodiments and the accompanying drawings.

[0030] Figure 1 A cross-sectional view of a complementary field effect transistor is schematically shown according to an embodiment of the present disclosure,Figure 2 A cross-sectional view of a complementary field effect transistor according to another embodiment of the present disclosure is schematically shown.

[0031] As an aspect of an embodiment of the present disclosure, a complementary field effect transistor is provided, as shown in Figure 1 and Figure 2 The complementary field effect transistor includes a substrate 1, a first field effect transistor 2 of vertical structure and a second field effect transistor 3 of vertical structure. The first field effect transistor 2 is disposed on the substrate 1, and the second field effect transistor 3 is disposed on the first field effect transistor 2. The first field effect transistor 2 includes a first channel 21, and the second field effect transistor 3 includes a second channel 22. One of the first channel 21 and the second channel 22 is an N-type channel, and the other of the first channel 21 and the second channel 22 is a P-type channel. The N-type channel is made of silicon material, and the P-type channel is made of silicon germanium material. The source-drain current of the first field effect transistor 2 is similar to the source-drain current of the second field effect transistor 3. The first field effect transistor 2 and the second field effect transistor 3 share a drain 117 and share a gate.

[0032] According to the complementary field effect transistor of the embodiment of the present disclosure, the P-type channel is made of silicon germanium (SiGe) material, which can enhance the hole mobility of the P-type channel, so as to achieve the source-drain current close to that of the N-type field effect transistor (NMOS) with a pure silicon channel under the condition of equal gate width. The PMOS current can be flexibly adjusted by adjusting the SiGe component, so as to improve the source-drain current of the PMOS and make the source-drain current of the PMOS closer to that of the NMOS. The electron and hole mobility can be matched, so as to improve the overall performance of the complementary field effect transistor. Due to the improvement of the matching of the source-drain current of the PMOS and the source-drain current of the NMOS, the device cell area can be more effectively controlled, which is helpful to further miniaturize the device size and improve the integration density of the integrated circuit.

[0033] According to the embodiment of the present disclosure, the P-type channel made of silicon germanium material and the N-type channel made of silicon material can make the difference between the source-drain current of the N-type field effect transistor and the source-drain current of the P-type field effect transistor within one time of the source-drain current of the P-type field effect transistor.

[0034] In an illustrative embodiment, the difference between the source-drain current of the N-type field effect transistor and the source-drain current of the P-type field effect transistor can be 0.9 times, 0.5 times, 0.3 times or 0 times of the source-drain current of the P-type field effect transistor by adjusting the SiGe component.

[0035] In an illustrative embodiment, as shown in Figure 1As shown, the first field-effect transistor 2 is a P-type field-effect transistor with a P-type channel; the second field-effect transistor 3 is an N-type field-effect transistor with an N-type channel.

[0036] In another illustrative embodiment, such as Figure 2 As shown, the first field-effect transistor 2 is an N-type field-effect transistor with an N-type channel; the second field-effect transistor 3 is a P-type field-effect transistor with a P-type channel.

[0037] Figure 3 An equivalent circuit diagram of a complementary field-effect transistor according to an embodiment of the present disclosure is shown schematically.

[0038] like Figure 3 As shown, T1 represents a PMOS transistor, and T2 represents an NMOS transistor. The PMOS and NMOS transistors have a common-gate structure, with v1 representing the gate voltage Vin as the input; they also have a common-drain structure, with Vo representing the drain voltage Vout as the output; VDD represents the power supply, connected to the source of the PMOS transistor; Vss represents ground, connected to the source of the NMOS transistor. The PMOS and NMOS transistors together form an inverter structure.

[0039] According to embodiments of this disclosure, an N-type channel is a semiconductor region formed by doping with donor impurities (e.g., phosphorus or arsenic), wherein the primary charge carriers are electrons. A P-type channel is a semiconductor region formed by doping with acceptor impurities (e.g., boron or gallium), wherein the primary charge carriers are holes.

[0040] According to embodiments of this disclosure, such as Figure 1 and Figure 2 As shown, the first field-effect transistor 2 further includes two first doped layers 22, two electrically connected first gates 23, and a first gate dielectric layer 24. The two first doped layers 22 are stacked on the substrate 1, wherein a first channel 21 is disposed between the two first doped layers 22, and the bottom first doped layer 22 is led out through a first source 115. The two electrically connected first gates 23 are disposed between the two first doped layers 22 and are respectively located on both sides of the first channel 21 in a first direction parallel to the substrate 1. The first gate dielectric layer 24 is disposed between the first channel 21 and the first gates 23, suitable for electrically isolating the first channel 21 and the first gates 23.

[0041] like Figure 1 and Figure 2As shown, the second field effect transistor 3 further comprises two second doped layers 32, two electrically connected second gates 33 and a second gate dielectric layer 34. The two second doped layers 32 are stacked on the first field effect transistor 2, wherein the second channel 22 is disposed between the two second doped layers 32, wherein the adjacent first doped layer 22 and the second doped layer 32 are led out through the common drain 117, and the second doped layer 32 on the top is led out through the second source 116. The two electrically connected second gates 33 are disposed between the two second doped layers 32 and are respectively located on both sides of the first direction of the second channel 22, wherein the two second gates 33 are electrically connected with the two first gates 23. The second gate dielectric layer 34 is disposed between the second channel 22 and the second gate 33, and the second gate dielectric layer 34 is suitable for electrically isolating the second channel 22 and the second gate 33.

[0042] According to embodiments of the present disclosure, the first doped layer 22 forms the source and drain 117 regions of the first field effect transistor 2 by doping different types of impurities (for example, N-type or P-type).

[0043] According to embodiments of the present disclosure, the second doped layer 32 forms the source and drain 117 regions of the first field effect transistor 2 by doping different types of impurities (for example, N-type or P-type).

[0044] According to embodiments of the present disclosure, the doping type of the first doped layer 22 is the same as the type of the first channel 21, and the doping type of the second doped layer 32 is the same as the type of the second channel 22. For example, in the case of the N-type first channel 21, the doping type of the first doped layer 22 is also N-type.

[0045] According to embodiments of the present disclosure, as shown in Figure 1 and Figure 2 , the first distance of the N-type channel from the first side wall 25 of the first doped layer 22 is greater than the second distance of the P-type channel from the first side wall 25, which will be described in detail below in conjunction with Figure 15 and Figure 34 .

[0046] According to embodiments of the present disclosure, as shown in Figure 1 and Figure 2 , the substrate 1 comprises a substrate (not shown in the figure) and a well layer 11. The well layer 11 is located between the substrate and the first field effect transistor 2. In the case of the N-type first channel 21, the well layer is P-type; in the case of the P-type first channel 21, the well layer is N-type. In this way, the well layer 11 can be used to electrically isolate the substrate and the first field effect transistor 2.

[0047] According to embodiments of the present disclosure, as shown in Figure 1 and Figure 2As shown, the complementary field effect transistor further comprises a third filling layer 120 filled in the periphery of the first field effect transistor 2 and the second field effect transistor 3, for protecting the first field effect transistor 2 and the second field effect transistor 3 and electrically isolating the first field effect transistor 2 and the second field effect transistor 3 from the outside.

[0048] In an illustrative embodiment, the third filling layer 120 is made of insulating material.

[0049] Figure 4 An illustrative flow chart of a method for manufacturing a complementary field effect transistor according to an embodiment of the present disclosure is shown.

[0050] As another aspect of the embodiments of the present disclosure, a method for manufacturing a complementary field effect transistor is provided, as shown in Figure 4 As shown, the method comprises operations S410-S440.

[0051] In operation S410, a first growth layer and a second growth layer are sequentially epitaxially grown on a substrate, wherein the first growth layer comprises two stacked first doped layers and a first silicon germanium layer between the two first doped layers, and the second growth layer comprises two stacked second doped layers and a second silicon germanium layer between the two second doped layers.

[0052] In operation S420, one of the first silicon germanium layer and the second silicon germanium layer is etched inward along a first direction parallel to the substrate and a silicon layer is deposited as an N-type channel.

[0053] In operation S430, the second doped layer on the upper portion is etched downward along a second direction perpendicular to the substrate to the first doped layer close to the substrate, a cavity is formed on the substrate, and the first silicon germanium layer and the second silicon germanium layer are etched outward along the first direction from the cavity, respectively, to remove the silicon germanium material adjacent to the N-type channel and retain part of the silicon germanium material in the other of the first silicon germanium layer and the second silicon germanium layer as a P-type channel.

[0054] In operation S440, a gate dielectric layer and a gate electrode are formed in the periphery of the N-type channel and the P-type channel, respectively.

[0055] According to the method for fabricating complementary field-effect transistors (CFETs) according to embodiments of this disclosure, by retaining the silicon-germanium layer as the P-type channel, the performance of the P-type transistor can be optimized by utilizing the material properties of silicon-germanium, such as improving hole mobility. This allows for source-drain currents close to those of a pure silicon channel in an N-type field-effect transistor (NMOS) under equal gate width conditions. Furthermore, the PMOS current can be flexibly controlled by adjusting the SiGe composition, thereby increasing the PMOS source-drain current and bringing it closer to that of an NMOS. Additionally, matching electron and hole mobilities further enhances the overall performance of the CFET. The improved matching between the PMOS and NMOS source-drain currents allows for more effective control of the device cell area, facilitating further miniaturization of device dimensions and increasing the integration density of integrated circuits. The fabrication method provided in this disclosure is compatible with existing semiconductor manufacturing technologies and is easily integrated into existing production processes.

[0056] Prior to operating S410, well layer implantation is performed on the substrate.

[0057] Furthermore, the injection type of the well layer is opposite to that of the first field-effect transistor 2. Specifically, when the first field-effect transistor 2 is N-type, the well layer is P-type; when the first field-effect transistor 2 is P-type, the well layer is N-type.

[0058] Figures 5 to 28 This diagram schematically illustrates a variation of the fabrication process of a complementary field-effect transistor according to an embodiment of the present disclosure. Figures 29 to 42 A schematic diagram illustrating a variation in the fabrication process of a complementary field-effect transistor according to another embodiment of the present disclosure is provided.

[0059] like Figure 5 As shown, epitaxy is performed sequentially from bottom to top in the well layer to form a first growth layer 4 and a second growth layer 5. Specifically, a first doped layer 22, a first silicon-germanium layer 41, a first doped layer 22, a second doped layer 32, a second silicon-germanium layer 51, and a second doped layer 32 are sequentially deposited on the well layer.

[0060] In one illustrative embodiment, heavily doped P-type silicon, intrinsic germanium silicon, heavily doped P-type silicon, heavily doped N-type silicon, intrinsic germanium silicon, and heavily doped N-type silicon are sequentially epitaxially grown on the well layer. The thickness of each layer can be adjusted according to actual conditions, with heavy doping approximately 1e. 19 ~1e 20 cm -3 It can be adjusted according to the specific performance requirements of the device.

[0061] According to embodiments of this disclosure, a silicon layer 104 is etched and deposited inward along a first direction in the second silicon-germanium layer 51 as an N-type channel, including:

[0062] As shown in FIG. 1, a fourth bump 102 is formed on the substrate 1, and a first annular space 103 is formed between two second doped layers 32; Figures 6-10

[0063] As shown in FIG. 2, a silicon layer 104 is deposited in the first annular space 103, and the silicon layer 104 in the first annular space 103 is surrounded to form a first annular groove 105; Figure 11

[0064] As shown in FIG. 3, a protective layer 106 is filled in the first annular groove 105 to protect the first annular groove 105; Figure 13

[0065] As shown in FIG. 4, the fourth bump 102 is used as a mask to remove the silicon layer 104 on the sidewall of the fourth bump 102, and etching is performed downward along the second direction to the first doped layer 22 adjacent to the substrate 1, and the silicon layer 104 in the first annular space 103 is reserved as an N-type channel. Figure 14 In such an embodiment, the first annular space 103 and the surrounding epitaxial silicon layer 104 are self-aligned vertical channels.

[0066] According to an embodiment of the present disclosure, the fourth bump 102 is formed on the substrate 1, and the first annular space 103 is formed between two second doped layers 32, comprising:

[0067] As shown in FIG. 5, a barrier layer 6, a core mold layer 7 and a sacrificial layer 8 are sequentially deposited on the second growth layer 5;

[0068] Figure 6 As shown in FIG. 6, the sacrificial layer 8 and the core mold layer 7 are sequentially etched to form a patterned sacrificial layer 8 and a core mold layer 7, and the patterned sacrificial layer 8 and the core mold layer 7 form a first bump 9 on the barrier layer 6;

[0069] As shown in FIG. 7, a cover layer 10 is deposited on the surface and sidewall of the first bump 9 to form a second bump; Figure 7 As shown in FIG. 8, the barrier layer 6 is etched with the second bump as a mask to form a third bump 101;

[0070] As shown in FIG. 9, the third bump 101 is used as a mask to etch from the second growth layer 5 to between the second doped layer 32 adjacent to the first growth layer 4 and the first doped layer 22 adjacent to the second growth layer 5, that is, t1 to t2 in FIG. 10, to form a fourth bump 102;

[0071] Figure 8 As shown in FIG. 11, a silicon layer 104 is deposited in the first annular space 103, and the silicon layer 104 in the first annular space 103 is surrounded to form a first annular groove 105;

[0072] As shown in FIG. 12, a protective layer 106 is filled in the first annular groove 105 to protect the first annular groove 105; Figure 9 Figure 9 As shown in FIG. 13, the fourth bump 102 is used as a mask to remove the silicon layer 104 on the sidewall of the fourth bump 102, and etching is performed downward along the second direction to the first doped layer 22 adjacent to the substrate 1, and the silicon layer 104 in the first annular space 103 is reserved as an N-type channel.

[0073] As shown in FIG. 14, the first annular space 103 and the surrounding epitaxial silicon layer 104 are self-aligned vertical channels. Figure 10 ​​​​​​As shown, the second silicon-germanium layer 51 is etched along the first direction to the first etching depth, so that a first annular space 103 is formed between the two second doped layers 32.

[0074] According to embodiments of this disclosure, the protective layer 106 filling the first annular groove 105 includes:

[0075] like Figure 12 As shown, a material layer is applied to the surface of the substrate 1 on which the first annular groove 105 is formed.

[0076] like Figure 13 As shown, the material layer outside the first annular groove 105 is removed, and the material layer inside the first annular groove 105 is used as the protective layer 106.

[0077] In one illustrative embodiment, the protective layer 106 may be made of silicon nitride.

[0078] In one illustrative embodiment, the material of the barrier layer 6 has a certain selection ratio to the silicon material, for example, it can be silicon nitride or silicon oxide.

[0079] In one illustrative embodiment, the material of the sacrificial layer 8 has a certain selection ratio to the silicon material, for example, it can be silicon nitride or silicon oxide.

[0080] In one illustrative embodiment, the barrier layer 6 is made of silicon oxide, the core layer 7 is made of amorphous silicon (a-Si), and the sacrificial layer 8 may be made of silicon oxide.

[0081] In one illustrative embodiment, the sacrificial layer 8 and the core mold layer 7 are etched sequentially to form a patterned sacrificial layer 8 and a core mold layer 7. The patterned sacrificial layer 8 and the core mold layer 7 form a first boss 9 on the barrier layer 6. This includes: defining the size of the first boss 9 through a patterning process, etching away the area outside the pattern definition, and stopping the etching on the barrier layer 6.

[0082] Depositing a capping layer 10 on the surface and sidewalls of the first boss 9 to form a second boss includes: depositing a capping layer 10 (e.g., silicon oxide) and etching; forming a second boss with a capping layer 10 on the sidewalls of the first boss 9; the capping layer 10 on the sidewalls of the first boss 9 defines a source / drain region located below the capping layer 10 on the sidewalls of the first boss 9.

[0083] According to embodiments of this disclosure, the method for etching the second silicon-germanium layer 51 may include dry etching or wet etching.

[0084] According to an embodiment of this disclosure, the second doped layer 32 located at the top is etched downward along a second direction to the first doped layer 22 near the substrate 1, forming a cavity 109 on the substrate 1. Then, the first silicon-germanium layer 41 and the second silicon-germanium layer 51 are etched outward from the cavity 109 along a first direction to remove the silicon-germanium material adjacent to the N-type channel, while retaining a portion of the silicon-germanium material in the first silicon-germanium layer 41 as the N-type channel. This includes:

[0085] like Figure 15 As shown, the first silicon-germanium layer 41 is etched in the first direction to the second etching depth, so that a second annular space 107 is formed between the two first doped layers 22 adjacent to the first silicon-germanium layer 41, wherein the second etching depth c is less than the first etching depth b (c < b).

[0086] like Figure 16 As shown, an active region protruding from the surrounding area is formed on substrate 1 by photolithographic pattern transfer etching;

[0087] Remove sacrificial layer 8;

[0088] like Figure 17 As shown, a first filler layer 108 is filled on the substrate 1. The first filler layer 108 is flush with the core mold layer 7 and exposes the core mold layer 7.

[0089] Remove core mold layer 7;

[0090] like Figure 18 As shown, the first cavity formed after removing the core film layer 7 is used as the etching pattern, and the etching is carried out downward (for example, dry anisotropic etching can be used) to the first silicon-germanium layer 41 adjacent to the substrate 1, forming a cavity 109 on the substrate 1, so that the first silicon-germanium layer 41 and the second silicon-germanium layer 51 are exposed in the cavity 109.

[0091] like Figure 18 As shown, the first silicon-germanium layer 41 and the remaining second silicon-germanium layer 51 are etched outward from the cavity 109 in the first direction, forming a third annular space 110 between the two second doped layers 32, and retaining part of the silicon-germanium material of the first silicon-germanium layer 41 as the first channel 21, so that a fourth annular space 111 is formed between the two first doped layers 22.

[0092] In such an embodiment, such as Figure 15 As shown, the second etching depth c and the first etching depth b are both less than the thickness a of the cover layer 10 covering the sidewall of the first boss 9, i.e. a > b > c.

[0093] According to embodiments of this disclosure, the method for etching the first silicon-germanium layer 41 may include dry etching or wet etching.

[0094] According to embodiments of this disclosure, the core mold layer 7 can be removed using a wet process.

[0095] According to embodiments of this disclosure, a silicon layer 104 is etched and deposited inward along a first direction in the first silicon-germanium layer 41 as an N-type channel, including:

[0096] A fourth protrusion 102 is formed on the substrate 1, and a first annular space 103 is formed between the two second doped layers 32;

[0097] like Figure 29 As shown, a protective layer 106 is filled within the first annular space 103;

[0098] like Figure 30 As shown, the fourth protrusion 102 is used as a mask to etch downwards to the first doped layer 22 adjacent to the substrate 1;

[0099] like Figure 31 As shown, an active region protruding from the surrounding area is formed on substrate 1 by photolithographic pattern transfer etching;

[0100] like Figure 32 As shown, the first silicon-germanium layer 41 is etched along the first direction to the second etching depth, so that a second annular space 107 is formed between the two first doped layers 22, wherein the second etching depth e is greater than the first etching depth d;

[0101] like Figure 33 As shown, a silicon layer 104 is deposited at least on the second annular space 107, and the silicon layer 104 located in the second annular space 107 forms a second annular groove 121, with the silicon layer 104 located in the second annular space 107 serving as an N-type channel.

[0102] In such an embodiment, such as Figure 34 As shown, the second etching depth e and the first etching depth d are both less than the thickness a of the cover layer 10 covering the sidewall of the first boss 9, i.e., a > e > d.

[0103] According to embodiments of this disclosure, the second doped layer 32 located at the top is etched downwards to the first doped layer 22 located near the substrate 1 to form a cavity 109 on the substrate 1. The first silicon-germanium layer 41 and the second silicon-germanium layer 51 are then etched outwards from the cavity 109 to remove the silicon-germanium material adjacent to the N-type channel, while retaining a portion of the silicon-germanium material in the second silicon-germanium layer 51 as a P-type channel. This includes:

[0104] like Figure 34 As shown, the protective layer 106 within the first annular space 103 is removed;

[0105] Remove sacrificial layer 8;

[0106] like Figure 35 As shown, a first filler layer 108 is filled on the substrate 1, making the first filler layer 108 flush with the core mold layer 7 and exposing the core mold layer 7.

[0107] removing the core mold layer (for example, by using a wet method);

[0108] As shown in Figure 36 , the first cavity formed after removing the core mold layer 7 is used as an etching pattern, and the first silicon germanium layer 41 is etched downward to form a cavity 109 on the surface of the first silicon germanium layer 41 adjacent to the substrate 1, so that the first silicon germanium layer 41 and the second silicon germanium layer 51 are exposed in the cavity 109;

[0109] As shown in Figure 37 , the second silicon germanium layer 51 and the remaining first silicon germanium layer 41 are etched outward from the cavity 109 in the first direction to form a third annular space 110 between the two first doped layers 22, and to retain part of the silicon germanium material of the second silicon germanium layer 51 as a P-type channel, so that a fourth annular space 111 is formed between the two second doped layers 32.

[0110] According to an embodiment of the present disclosure, a gate dielectric layer and a gate electrode are formed on the periphery of the N-type channel and the P-type channel, respectively, including:

[0111] As shown in Figure 19 and Figure 38 , the second filling layer 112 is filled in the cavity 109, and the second filling layer 112, the first filling layer 108 and the cover layer 10 form an etching layer 113;

[0112] As shown in Figure 20 , Figure 21 and Figure 39 , the etching layer 113 is etched so that the height of the etching layer 113 is below the active area, and the annular structure located in the active area is exposed; wherein, Figure 21 is a top view of the annular structure, Figure 21 is Figure 20 a sectional view along A-A;

[0113] As shown in Figure 23 , in the case of removing the protective layer 106 filled in the first annular groove 105, the annular structure is etched using a fin cutting photo mask to have an opening, forming a first substrate; wherein, Figure 23 is a top view of the first substrate;

[0114] A gate dielectric layer 114 is deposited on the surface of the first substrate, forming a ring-shaped first groove in the first annular groove 105, a ring-shaped second groove in the second annular space 107, a ring-shaped third groove in the third annular space 110, and a ring-shaped fourth groove in the fourth annular space 111, as a second substrate;

[0115] A metal gate is deposited on the periphery of the second substrate;

[0116] etching the metal gate outside the first recess, the second recess, the third recess and the fourth recess, wherein the metal gate in the first recess and the third recess together as the second gate 33, the metal gate in the second recess and the fourth recess as the first gate 23, forming a third base;

[0117] As shown in Figure 24 , Figure 25 , Figure 40 and Figure 41 , the gate dielectric layer 114 at the opening is protected by the photo mask, and the gate dielectric layer outside the photo mask protection area on the surface of the third base is removed, wherein the gate dielectric layer 114 in the first annular recess 105 and the third annular space 110 as the second gate dielectric layer 34, and the gate dielectric layer 114 in the first annular space 103 and the fourth annular space 111 as the first gate dielectric layer 24; wherein, Figure 24 is a top view after removing the gate dielectric layer 114 outside the fin cut photo mask;

[0118] As shown in Figures 26 to 28 , Figure 42 , the remaining first doped layer 22 adjacent to the base 1 is led out through the first source 115 by the interconnection mode of the side wall interconnection, the second doped layer 32 above is led out through the second source 116, the adjacent second doped layer 32 and the first doped layer 22 are led out through the drain 117, and the first gate 23 and the second gate 33 are led out through the gate electrode 118. Wherein, Figure 26 is a B-B cross-sectional view of the complementary field effect transistor shown in Figure 24 , Figure 27 is a C-C cross-sectional view of the complementary field effect transistor shown in Figure 24 .

[0119] According to the embodiments of the present disclosure, in the case that the first field effect transistor 2 is a P-type field effect transistor, before etching the annular structure by the fin cut photo mask, it further includes: as shown in Figure 22 , removing the protection layer 106 filled in the first annular recess 105.

[0120] In an illustrative embodiment, the protection layer 106 filled in the first annular recess 105 can be removed by wet etching.

[0121] In an illustrative embodiment, the cross-sectional shape of the annular structure with an opening in the horizontal direction can be a long strip or a C shape.

[0122] In an illustrative embodiment, a method for manufacturing a complementary field effect transistor, comprising:

[0123] Performing N-type well layer implantation on the substrate to form a base 1;

[0124] like Figure 5 As shown, a first growth layer 4 and a second growth layer 5 are sequentially epitaxially grown on the substrate 1;

[0125] like Figure 6 As shown, a barrier layer 6, a core mold layer 7, and a sacrificial layer 8 are sequentially deposited on the second growth layer 5;

[0126] like Figure 7 As shown, through a patterning process, the sacrificial layer 8 is etched downwards to the barrier layer 6 to etch the areas of the sacrificial layer 8 and the core mold layer 7 outside the pattern definition area, and a first protrusion 9 is formed on the surface of the barrier layer 6.

[0127] like Figure 8 As shown, a capping layer 10 is deposited on the surface and sidewall of the first boss 9, and the barrier layer 6 is etched using the second boss as a mask to form the third boss 101.

[0128] like Figure 9 As shown, anisotropic etching is used, retaining the capping layer 10, and etching is performed from the second growth layer 5 to the area between the second doped layer 32 adjacent to the first growth layer 4 and the first doped layer 22 adjacent to the second growth layer 5, that is... Figure 9 Between t1 and t2, a fourth protrusion 102 is formed;

[0129] like Figure 10 As shown, the second silicon-germanium layer 51 of the second growth layer 5 is etched inward to the first etching depth by selective dry or wet etching, so that a first annular space 103 is formed between the second doped layers of the second growth layer 5.

[0130] like Figure 11 As shown, a silicon layer 104 is formed on the wall of the first annular space 103, and a first annular groove 105 is formed between the silicon layers 104 located in the first annular space 103.

[0131] like Figure 13 As shown, a protective layer 106 is filled within the first annular groove 105 to protect the silicon layer 104 located within the first annular space 103; and

[0132] like Figure 14 As shown, the fourth protrusion 102 is used as a mask to remove the silicon layer 104 on the sidewall of the fourth protrusion 102, and is etched downward along the second direction to the first doped layer 22 adjacent to the substrate 1, while retaining the silicon layer 104 located in the first annular space 103 as an N-type channel.

[0133] like Figure 15As shown, the first silicon germanium layer 41 in the first growth layer 4 is etched inwardly to a second etching depth c by selective dry or wet etching, so that a second annular space 107 is formed between the two first doped layers 22 adjacent to the first silicon germanium layer 41;

[0134] As shown, the outer periphery of the fourth boss 102 is etched by photolithographic pattern transfer to form an active region on the substrate 1; Figure 16

[0135] As shown, the fourth boss 102 is etched downwardly from the top surface to remove the sacrificial layer 8; the first filling layer 108 is filled on the substrate 1, and the first filling layer 108 is planarized with the core mold layer 7 by chemical mechanical polishing, and the core mold layer 7 is exposed; Figure 17 The core mold layer 7 is removed;

[0136] As shown, the first cavity formed after the core mold layer 7 is removed is used as an etching pattern, and wet or dry etching is used to etch downwardly (for example, dry anisotropic etching can be used) to the first silicon germanium layer 41 adjacent to the substrate 1 to form a cavity 109 on the substrate 1, so that the first silicon germanium layer 41 and the second silicon germanium layer 51 are exposed in the cavity 109;

[0137] Figure 18 The first silicon germanium layer 41 and the remaining second silicon germanium layer 51 are etched outwardly in the first direction from the cavity 109 by atomic layer etching to form a third annular space 110 between the two second doped layers 32, and part of the silicon germanium material of the first silicon germanium layer 41 is reserved as a first channel 21, so that a fourth annular space 111 is formed between the two first doped layers 22.

[0138] As shown, the second filling layer 112 is filled in the cavity 109, and the second filling layer 112 forms an etching layer 113 with the first filling layer 108 and the cover layer 10 and is planarized by chemical mechanical polishing to process the surface;

[0139] As shown, the etching layer 113 is etched by wet or dry etching to reduce the height of the etching layer 113 below the active region, so that the annular structure in the active region is exposed; Figure 19 As shown, the protective layer 106 filled in the first annular groove 105 is removed by wet etching;

[0140] Figure 20 As shown, the annular structure is etched by using a fin cutting photo mask to make the annular structure have an opening, and a first substrate is formed. Figure 21

[0141] As shown, the protective layer 106 filled in the first annular groove 105 is removed by wet etching; Figure 22 As shown, the annular structure is etched by using a fin cutting photo mask to make the annular structure have an opening, and a first substrate is formed.

[0142] Figures 23 to 28 As shown, the annular structure is etched by using a fin cutting photo mask to make the annular structure have an opening, and a first substrate is formed.

[0143] ​​​​​In this way, after the first base surface is deposited with the gate dielectric layer, the first annular groove 105 is formed into a first annular recess, the second annular space 107 is formed into a second annular recess, the third annular space 110 is formed into a third annular recess, and the fourth annular space 111 is formed into a fourth annular recess, serving as a second base;

[0144] Depositing a metal gate on the periphery of the second base;

[0145] Etching the metal gate outside the first recess, the second recess, the third recess, and the fourth recess, wherein the metal gate in the first recess and the third recess together serves as a gate of an N-type field effect transistor, and the metal gate in the second recess and the fourth recess serves as a gate of a P-type field effect transistor, forming a third base.

[0146] Protecting the gate dielectric layer at the opening by a photo mask, and removing the gate dielectric layer on other areas on the surface of the third base outside the photo mask protection area, wherein the gate dielectric layer in the first annular groove and the third annular space serves as a second gate dielectric layer, and the gate dielectric layer in the first annular space and the fourth annular space serves as a first gate dielectric layer;

[0147] By the interconnection mode of the sidewall interconnection and punching, the remaining doped layer is respectively introduced as a source-drain layer of an N-type field effect transistor and a P-type field effect transistor through a source-drain electrode, and the gate is introduced through a gate electrode 118.

[0148] The preparation method of the complementary field effect transistor provided by the embodiments of the present disclosure not only saves the amount of photo masks, but also does not need two layers of photo masks to respectively define the gate width of the N-type field effect transistor and the P-type field effect transistor, which is conducive to further reducing the size of the complementary field effect transistor, and can save costs.

[0149] The above describes the embodiments of the present disclosure. However, these embodiments are only for illustrative purposes, and are not intended to limit the scope of the present disclosure. Although each embodiment is described above, this does not mean that the measures in each embodiment cannot be used advantageously in combination. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art can make various substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims

1. A complementary field effect transistor, characterized by, Comprise: a substrate (1); a first field effect transistor (2) of vertical structure, disposed on the substrate (1); and a second field effect transistor (3) of vertical structure, disposed on the first field effect transistor (2); wherein the first field effect transistor (2) comprises a first channel (21), the second field effect transistor (3) comprises a second channel (31), one of the first channel (21) and the second channel (31) is an N-type channel, the other of the first channel (21) and the second channel (31) is a P-type channel, the N-type channel is made of silicon material, and the P-type channel is made of silicon germanium material, so that the source-drain current of the first field effect transistor is similar to the source-drain current of the second field effect transistor, wherein the first field effect transistor and the second field effect transistor share a drain and a gate.

2. The complementary field effect transistor of claim 1, wherein, The first field effect transistor (2) further comprises: two first doped layers (22) stacked on the substrate (1), wherein the first channel (21) is disposed between the two first doped layers (22), and the first doped layer at the bottom is led out by a first source; two electrically connected first gates (23) disposed between the two first doped layers (22) and located on both sides of the first channel (21) in a first direction parallel to the substrate (1); and a first gate dielectric layer (24) disposed between the first channel (21) and the first gate (23), adapted to electrically isolate the first channel (21) and the first gate (23); The second field effect transistor (3) further comprises: two second doped layers (32) stacked on the first field effect transistor (2), wherein the second channel (31) is disposed between the two second doped layers (32), wherein the adjacent first doped layer and the second doped layer are led out by a shared drain, and the second doped layer at the top is led out by a second source; two electrically connected second gates (33) disposed between the two second doped layers (32) and located on both sides of the second channel (31) in the first direction, wherein the two second gates are electrically connected to the two first gates; a second gate dielectric layer (34) disposed between the second channel (31) and the second gate (33), adapted to electrically isolate the second channel (31) and the second gate (33).

3. The complementary field effect transistor of claim 2, wherein, The first distance between the N-type channel and the first sidewall (25) of the first doped layer (22) is greater than the second distance between the P-type channel and the first sidewall.

4. The complementary field effect transistor of claim 1, wherein, The substrate (1) comprises: a substrate; a well layer (11) between the substrate and the first field effect transistor (2); wherein, in the case that the first channel (21) is N-type, the well layer (11) is P-type, and in the case that the first channel (21) is P-type, the well layer (11) is N-type, so as to electrically isolate the substrate and the first field effect transistor (2).

5. A method of manufacturing a complementary field effect transistor as claimed in any one of claims 1 to 4, characterized in that Comprise: The first growth layer (4) and the second growth layer (5) are sequentially epitaxied on the substrate (1), wherein the first growth layer (4) comprises two first doped layers (22) stacked and a first silicon germanium layer (41) between the two first doped layers (22), and the second growth layer (5) comprises two second doped layers (32) stacked and a second silicon germanium layer (51) between the two second doped layers (32); One of the first silicon germanium layer (41) and the second silicon germanium layer (51) is etched inward along a first direction parallel to the substrate (1) and a silicon layer (104) is deposited as an N-type channel; The second doped layer (32) located at the upper part is etched downward along a second direction perpendicular to the substrate (1) to the first doped layer (22) close to the substrate (1), a cavity (109) is formed on the substrate, and the first silicon germanium layer (41) and the second silicon germanium layer (51) are etched outward along the first direction from the cavity (109) respectively to remove the silicon germanium material adjacent to the N-type channel and retain part of the silicon germanium material in the other of the first silicon germanium layer (41) and the second silicon germanium layer (51) as a P-type channel; A gate dielectric layer and a gate electrode are formed on the periphery of the N-type channel and the P-type channel respectively.

6. The production method according to claim 5, wherein The second silicon germanium layer (51) is etched inward along a first direction and a silicon layer (104) is deposited as an N-type channel, comprising: A barrier layer (6), a core layer (7) and a sacrificial layer (8) are sequentially deposited on the second growth layer (5); The sacrificial layer (8) and the core layer (7) are sequentially etched to form a patterned sacrificial layer (8) and a core layer (7), and the patterned sacrificial layer (8) and the core layer (7) form a first boss (9) on the barrier layer (6); A cover layer (10) is deposited on the surface and the sidewall of the first boss (9) to form a second boss; The barrier layer (6) is etched with the second boss as a mask to form a third boss (101); The second growth layer (5) is etched to the second doped layer (32) adjacent to the first growth layer (4) and the first doped layer (22) adjacent to the second growth layer (5) with the third boss (101) as a mask to form a fourth boss (102); The second silicon germanium layer (51) is etched to a first etching depth along the first direction, so that a first annular space (103) is formed between the two second doped layers (32); The silicon layer (104) is deposited in the first annular space (103), and the silicon layer (104) located in the first annular space (103) forms a first annular groove (105); A protective layer (106) is filled in the first annular groove (105); The silicon layer (104) on the sidewall of the fourth boss (102) is removed with the fourth boss (102) as a mask, and the silicon layer (104) located in the first annular space (103) is retained as the N-type channel by etching downward along the second direction to the first doped layer (22) adjacent to the substrate (1).

7. The preparation method according to claim 6, characterized in that, etching the first silicon germanium layer (41) and the remaining second silicon germanium layer (51) from the cavity (109) outward in the first direction, forming a third annular space (110) between the two second doped layers (32), and retaining part of the silicon germanium material of the first silicon germanium layer (41) as the first channel (21), so that the fourth annular space (111) is formed between the two first doped layers (22). etching the first silicon germanium layer (41) to a second etching depth in the first direction, forming a second annular space (107) between the two first doped layers (22) adjacent to the first silicon germanium layer (41), wherein the second etching depth is less than the first etching depth; forming an active region protruding from the surrounding area on the substrate (1) by photolithographic pattern transfer etching; removing the sacrificial layer (8); filling a first filling layer (108) on the substrate (1), the first filling layer (108) being flush with the core mold layer (7) and exposing the core mold layer (7); using the first cavity formed after removing the core mold layer (7) as an etching pattern, etching down to the first silicon germanium layer (41) adjacent to the substrate (1) to form the cavity (109) on the substrate (1), so that the first silicon germanium layer (41) and the second silicon germanium layer (51) are exposed in the cavity (109); etching the first silicon germanium layer (41) and the remaining second silicon germanium layer (51) from the cavity (109) outward in the first direction, forming a third annular space (110) between the two second doped layers (32), and retaining part of the silicon germanium material of the first silicon germanium layer (41) as the first channel (21), so that the fourth annular space (111) is formed between the two first doped layers (22).

8. The preparation method according to claim 5, characterized in that, etching the first silicon germanium layer (41) in the first direction and depositing a silicon layer (104) as an N-type channel, comprising: depositing a barrier layer (6), a core mold layer (7) and a sacrificial layer (8) on the second growth layer (5) in turn; etching the sacrificial layer (8) and the core mold layer (7) in turn to form a patterned sacrificial layer (8) and core mold layer (7), which form a first boss (9) on the barrier layer (6); depositing a cover layer (10) on the surface and sidewall of the first boss (9) to form a second boss; using the second boss as a mask, etching the barrier layer (6) to form a third boss (101); using the third boss (101) as a mask, etching the second growth layer (5), the first growth layer (4), the second doped layer (32) adjacent to the first growth layer (4), and the first doped layer (22) adjacent to the second growth layer (5) to form a fourth boss (102); etching the second silicon germanium layer (51) to a first etching depth in the first direction, so that a first annular space (103) is formed between the two second doped layers (32). Filling a protective layer (106) in the first annular space (103); Etching down to the first doped layer (22) adjacent to the substrate (1) with the fourth boss (102) as a mask; Forming an active region protruding from the surrounding area on the substrate (1) by photoetching pattern transfer etching; Etching the first silicon germanium layer (41) to a second etching depth along the first direction, forming a second annular space (107) between the two first doped layers (22), wherein the second etching depth is greater than the first etching depth; Depositing a silicon layer (104) on at least the second annular space (107), and making the silicon layer (104) located in the second annular space (107) form a second annular groove (121), and taking the silicon layer (104) located in the second annular space (107) as the N-type channel.

9. The production method according to claim 8, characterized by, Etching down from the second doped layer (32) located at the upper part to the first doped layer (22) located close to the substrate (1) to form a cavity (109) on the substrate (1), and etching the first silicon germanium layer (41) and the second silicon germanium layer (51) outward from the cavity (109) respectively to remove the silicon germanium material adjacent to the N-type channel and retain part of the silicon germanium material in the second silicon germanium layer (51) as a P-type channel, including: Removing the protective layer (106) in the first annular space (103); Removing the sacrificial layer (8); Filling a first filling layer (108) on the substrate (1) to make the first filling layer (108) flush with the core mold layer (7) and expose the core mold layer (7); Etching down to the first silicon germanium layer (41) with the first cavity formed after removing the core mold layer (7) as an etching pattern to form a cavity (109) on the surface of the first silicon germanium layer (41) adjacent to the substrate (1), and expose the first silicon germanium layer (41) and the second silicon germanium layer (51) in the cavity (109); Etching the second silicon germanium layer (51) and the remaining first silicon germanium layer (41) outward from the cavity (109) along the first direction to form a third annular space (110) between the two first doped layers (22) and retain part of the silicon germanium material of the second silicon germanium layer (51) as a P-type channel, and form a fourth annular space (111) between the two second doped layers (32).

10. The production method according to claim 7 or 9, characterized by, Forming a gate dielectric layer and a gate on the periphery of the N-type channel and the P-type channel, including: Filling a second filling layer (112) in the cavity (109), and the second filling layer (112) and the first filling layer (108) and the cover layer (10) form an etching layer (113); Etching the etching layer (113) to make the height of the etching layer (113) below the active region, exposing the annular structure in the active region; Etching the annular structure with a fin cut photo mask to make the annular structure have an opening and form a first substrate under the condition of removing the protective layer (106) filled in the first annular groove (105). Depositing a gate dielectric layer (114) on the surface of the first substrate, forming a first annular recess in the first annular space (105), a second annular recess in the second annular space (107), a third annular recess in the third annular space (110) and a fourth annular recess in the fourth annular space (111) as a second substrate; Depositing a metal gate on the periphery of the second substrate; Etching the metal gate outside the first recess, the second recess, the third recess and the fourth recess, wherein the metal gate in the first recess and the third recess together serves as a second gate (33), and the metal gate in the second recess and the fourth recess serves as a first gate (23), forming a third substrate; Protecting the gate dielectric layer (114) at the opening by a photo mask, removing the gate dielectric layer on the surface of the third substrate outside the photo mask protection area, wherein the gate dielectric layer (114) in the first annular recess (105) and the third annular space (110) serves as a second gate dielectric layer (34), and the gate dielectric layer in the first annular space (103) and the fourth annular space (111) serves as a first gate dielectric layer (24); Connecting the remaining first doped layer (22) adjacent to the substrate (1) through a first source (115), the second doped layer (32) above through a second source (116), the adjacent second doped layer (32) and the first doped layer (22) through a drain (117), and the first gate (23) and the second gate (33) through a gate electrode (118) by a sidewall interconnection.

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