Method for manufacturing optoelectronic synapse device and optoelectronic synapse device

Abstract

The application discloses a preparation method of a photoelectric synapse device and the photoelectric synapse device, and belongs to the technical field of semiconductors. The preparation method of the photoelectric synapse device comprises the following steps: providing a gate electrode and a gate oxide layer located on one side of the gate electrode; forming a channel layer on the side of the gate oxide layer away from the gate electrode; forming a source-drain electrode on the side of the channel layer away from the gate oxide layer, and the source-drain electrode is connected with the channel layer; and in a high-temperature environment, the channel layer is subjected to Lewis acid doping for a preset time length, so as to introduce a trap center into the energy band structure of the channel layer. The application can realize simulation of the photoelectric synapse function, and the simulation has an extremely low operating voltage, a weak light pulse intensity and an extremely low power consumption.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor technology, and particularly relates to a preparation method of an optoelectronic synapse device and the optoelectronic synapse device. BACKGROUND

[0002] In the era of big data, traditional computers are facing great challenges in quickly and efficiently processing huge and complex information, mainly due to the inherent separation between processors and memories. In contrast, the human brain uses a huge network of synaptic connections to exhibit excellent ability to process and store data simultaneously with minimal energy consumption. Therefore, artificial neural networks inspired by the brain have become one of the most promising information processing technologies, which is expected to overcome the performance bottleneck caused by the mismatch between the data transmission speed between the memory and the processor. This has triggered renewed interest in the development of artificial synapse devices to build neuromorphic systems. Early efforts have focused on using silicon-based complementary metal-oxide-semiconductor (CMOS) analog circuits to simulate synaptic functions, such as simulating 1 million neurons and 256 million configurable synapses using 5.4 billion transistors. With the development of artificial neural networks, it has been found that simulating visual perception functions is a key step to achieve artificial intelligence. Optoelectronic synapses have been proposed as the basic unit of neuromorphic vision systems, which need to integrate light detection and synaptic functions to process light signals and extract relevant information such as color, intensity and frequency.

[0003] Among transition metal dichalcogenides (TMDs), WSe2 has received extensive attention due to its easily adjustable bandgap structure and excellent optoelectronic response. However, WSe2-based optoelectronic synapse devices are affected by high readout voltage and significant energy consumption during operation, which may hinder their further development in the field of neuromorphic computing architecture. SUMMARY

[0004] The present application aims to at least solve one of the technical problems existing in the prior art. To this end, the present application provides a preparation method of an optoelectronic synapse device and the optoelectronic synapse device, which can simulate optoelectronic synaptic functions with extremely low operating voltage, weak light pulse intensity and extremely low power consumption.

[0005] In a first aspect, the present application provides a preparation method of an optoelectronic synapse device, comprising:

[0006] providing a gate electrode and a gate oxide layer located on one side of the gate electrode;

[0007] forming a channel layer on the side of the gate oxide layer away from the gate electrode;

[0008] forming a source-drain electrode on the side of the channel layer away from the gate oxide layer, and the source-drain electrode is connected to the channel layer;

[0009] performing Lewis acid doping on the channel layer for a preset time length under a high-temperature environment to introduce trap centers in the energy band structure of the channel layer.

[0010] According to the preparation method of the optoelectronic synaptic device, the trap centers are introduced in the energy band structure of the channel layer by performing Lewis acid doping on the channel layer for a preset time length under a high-temperature environment, the photo-generated charges are captured, the persistent photoconductivity effect is generated, the simulation of the optoelectronic synaptic function is realized, and the simulation has extremely low operating voltage, weak light pulse intensity, and extremely low power consumption.

[0011] According to an embodiment of the present application, the source-drain electrode is formed on the side of the channel layer away from the gate oxide layer, comprising:

[0012] forming a cover layer on the side of the channel layer away from the gate oxide layer;

[0013] forming an opening in the cover layer to expose the channel layer;

[0014] forming a source-drain electrode connected to the exposed channel layer in the opening;

[0015] removing the cover layer.

[0016] According to an embodiment of the present application, the Lewis acid doping on the channel layer for a preset time length under a high-temperature environment comprises:

[0017] dissolving the liquid Lewis acid into an alcohol polar protic solvent;

[0018] transferring the Lewis acid-dissolved solvent to a polytetrafluoroethylene reaction kettle and heating;

[0019] immersing the channel layer in the reaction kettle under a high-temperature environment to perform Lewis acid doping on the channel layer for a preset time length.

[0020] According to an embodiment of the present application, the high-temperature is 70-160°C.

[0021] According to an embodiment of the present application, the preset time length is 10 minutes to 1 hour.

[0022] According to an embodiment of the present application, the doping concentration of the Lewis acid is 0.01-1 mol%.

[0023] According to an embodiment of the present application, the Lewis acid comprises SnCl4.

[0024] According to an embodiment of the present application, the channel layer comprises a two-dimensional material layer.

[0025] According to one embodiment of the present application, the two-dimensional material layer comprises WSe2.

[0026] In a second aspect, the present application provides a photoelectric synapse device, which is formed by the preparation method of the photoelectric synapse device of the first aspect described above, and comprises:

[0027] a gate electrode;

[0028] a gate oxide layer located on one side of the gate electrode;

[0029] a channel layer located on the side of the gate oxide layer away from the gate electrode; the channel layer is doped with a Lewis acid to introduce a trap center in the energy band structure of the channel layer;

[0030] a source-drain electrode located on the side of the channel layer away from the gate oxide layer and connected with the channel layer.

[0031] The one or more technical solutions described above in the embodiments of the present application have at least one of the following technical effects:

[0032] By doping the channel layer with a Lewis acid for a preset time duration under a high-temperature environment, a trap center is introduced in the energy band structure of the channel layer to capture photo-generated charges, thereby producing a persistent photoconductivity effect and realizing the simulation of photoelectric synapse functions such as excitatory postsynaptic current (EPSC), paired-pulse facilitation (PPF), long-term memory (STM), short-term memory (LTM), etc. At the same time, the conductivity can be regulated in a light and electrical dual-mode, and the simulation has an extremely low operating voltage, a weak light pulse intensity, and an extremely low power consumption. The electrical pulse has an extremely fast and sensitive response, and can be applied to high-pass filtering for image preprocessing, or can be used to simulate Boolean logic commands.

[0033] Additional aspects and advantages of the present application will be in part apparent and in part pointed out hereinafter. BRIEF DESCRIPTION OF DRAWINGS

[0034] The above and / or additional aspects and advantages of the present application will become apparent and be readily appreciated from the following description, including the appended drawings, wherein:

[0035] Figure 1 is a flowchart of the preparation method of the photoelectric synapse device provided by the embodiments of the present application;

[0036] Figure 2 is a structural schematic diagram of the photoelectric synapse device provided by the embodiments of the present application;

[0037] Figure 3 is an optical microscope image of the photoelectric synapse device provided by the embodiments of the present application;

[0038] Figure 4 is a Raman spectrum of the optoelectronic synapse device provided by an embodiment of the present application;

[0039] Figure 5 is a PL (photoluminescence) spectrum of the optoelectronic synapse device provided by an embodiment of the present application;

[0040] Figure 6 is an AFM (atomic force microscope) image of the optoelectronic synapse device provided by an embodiment of the present application;

[0041] Figure 7 is a high-angle annular dark-field scanning transmission electron microscopy (HAADF-STEM) image of the optoelectronic synapse device provided by an embodiment of the present application;

[0042] Figure 8 is an I-t curve graph of a channel layer in the optoelectronic synapse device provided by an embodiment of the present application before the channel layer is not doped with a Lewis acid at a high temperature;

[0043] Figure 9 is an optoelectronic synapse function simulation test graph of the optoelectronic synapse device provided by an embodiment of the present application;

[0044] Figure 10 is an I-t curve graph of the optoelectronic synapse device provided by an embodiment of the present application;

[0045] Figure 11 is a high-pass filtering application graph of the optoelectronic synapse device provided by an embodiment of the present application;

[0046] Figure 12 is a Boolean logic command application graph of the optoelectronic synapse device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0047] Embodiments of the present application are described in detail below with reference to the accompanying drawings, in which the same or similar elements or elements having the same or similar functions are denoted by the same or similar reference numerals throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application and cannot be understood as a limitation of the present application.

[0048] The preparation method of the optoelectronic synapse device and the optoelectronic synapse device provided by an embodiment of the present application are described below with reference to the accompanying drawings.

[0049] Figure 1 is a flowchart of the preparation method of the optoelectronic synapse device provided by an embodiment of the present application.

[0050] As shown in Figure 1 , the preparation method of the optoelectronic synapse device provided by an embodiment of the present application includes steps 110 to 140.

[0051] Step 110, providing a gate electrode and a gate oxide layer on one side of the gate electrode.

[0052] In combination Figure 2 As shown, a gate electrode 1 is provided first. The gate electrode 1 can be a semiconductor layer including silicon, or a semiconductor layer including other elements. The gate electrode 1 is a highly doped semiconductor layer, and the doping type of the gate electrode 1 can be N-type or P-type. For example, a dopant with reducing ability is used to dope a pentavalent element such as phosphorus, antimony, arsenic, etc. in the gate electrode 1 to form an N-type gate electrode. Alternatively, a dopant with oxidizing ability is used to dope a trivalent element such as boron, indium, gallium, aluminum, etc. in the gate electrode 1 to form a P-type gate electrode.

[0053] Then, a thin film deposition process is used to form a gate oxide layer 2 on one side of the gate electrode 1. The thin film deposition process includes physical vapor deposition, chemical vapor deposition, atomic layer deposition, laser-assisted deposition, etc. The gate oxide layer 2 can include one or a combination of silicon oxide, silicon nitride, etc.

[0054] In some embodiments, the overall thickness of the gate electrode 1 and the gate oxide layer 2 is 300 nm.

[0055] Step 120, forming a channel layer on the side of the gate oxide layer away from the gate electrode.

[0056] In combination Figure 2 As shown, a thin film deposition process is used to form a channel layer 3 on the side of the gate oxide layer 2 away from the gate electrode 1. The channel layer 3 is a semiconductor layer. The channel layer 3 covers part of the gate oxide layer 2. In some embodiments, the channel layer 3 is formed by a thin film deposition process in combination with a lithography process. Figure 3 As shown, the lateral cross-section of the channel layer 3 is triangular, where the lateral direction is parallel to the upper surface of the gate oxide layer 2 (i.e. the surface of the gate oxide layer 2 away from the gate electrode 1).

[0057] In some embodiments, the channel layer 3 includes a two-dimensional material layer. Two-dimensional material refers to a material in which electrons are free to move in two dimensions on a non-nanoscale, i.e. two-dimensional atomic crystal material. Two-dimensional material has a nanoscale thickness, which effectively suppresses the short channel effect of the device, reduces the size of the device, and reduces power consumption.

[0058] In some embodiments, the two-dimensional material layer includes WSe2. The two-dimensional material layer can also include other types of two-dimensional materials such as MoS2, WS2, and MoSe2, etc. without specific limitation here.

[0059] In some embodiments, the thickness of the channel layer 3 is thin, for example, the thickness of the channel layer 3 is 5 nm.

[0060] For example, a thin layer of channel layer 3 (e.g., WSe2) is grown on the side of gate oxide layer 2 facing away from gate 1 by a chemical vapor deposition process. In this process, the precursor for chemical vapor deposition is 0.3 g of sodium tungstate and 0.8 g of selenium powder, the temperature is 945℃, the flow rate is 65:7 (Ar:H2), and the holding time is 3 min.

[0061] Step 130: Forming source and drain on the side of the channel layer facing away from the gate oxide layer, and the source and drain are connected to the channel layer.

[0062] In combination Figure 2 As shown, source 4 and drain 5 are formed on the side of channel layer 3 facing away from gate oxide layer 2, and source 4 and drain 5 are laterally spaced apart. Source 4 is connected to channel layer 3 and extends onto gate oxide layer 2, and drain 5 is connected to channel layer 3 and extends onto gate oxide layer 2. In this embodiment, source 4 can include one or more combinations of copper, titanium, aluminum, nickel, gold, etc. Drain 5 can include one or more combinations of copper, titanium, aluminum, nickel, gold, etc.

[0063] In some embodiments, the step 130 of forming source and drain on the side of the channel layer facing away from the gate oxide layer includes:

[0064] Forming a cover layer on the side of the channel layer facing away from the gate oxide layer;

[0065] Forming an opening in the cover layer to expose the channel layer;

[0066] Forming source and drain in the opening and connected to the exposed channel layer;

[0067] Removing the cover layer.

[0068] Using a spin coater, a cover layer is spin-coated on the side of channel layer 3 facing away from gate oxide layer 2, and the cover layer covers channel layer 3 and gate oxide layer 2. The cover layer is heated by a heating table to solidify the cover layer. In this embodiment, the cover layer can include PMMA (Polymethyl Methacrylate). The spin-coating parameters of the cover layer are 600 rpm for 6 seconds and 4000 rpm for 60 seconds. The heating temperature of the heating table is 150℃, and the heating time is 5 min.

[0069] Then, an exposure pattern is designed on the channel layer 3 using an electron beam exposure system. The exposure system controls the light source and electron beam to achieve pattern processing exposure on the specific area of the cover layer with the assistance of a mask or a pattern template. After development and fixing, the exposure pattern is exposed to form an opening in the specific area of the cover layer.

[0070] The openings of the cover layer include a first sub-opening and a second sub-opening arranged transversely. The first sub-opening exposes part of the channel layer 3 and part of the gate oxide layer 2, and the second sub-opening exposes part of the channel layer 3 and part of the gate oxide layer 2.

[0071] The source and drain electrodes are deposited in the openings by using a vacuum thermal evaporation system. The source electrode 4 is deposited in the first sub-opening so that the source electrode 4 is connected to the channel layer 3 and extends onto the gate oxide layer 2. The drain electrode 5 is deposited in the second sub-opening so that the drain electrode 5 is connected to the channel layer 3 and extends onto the gate oxide layer 2.

[0072] After the source and drain electrodes are formed, the remaining cover layer is removed.

[0073] In step 140, the channel layer is subjected to Lewis acid doping for a preset time length in a high-temperature environment, so as to introduce trap centers into the energy band structure of the channel layer.

[0074] The energy band structure of the channel layer 3 can be adjusted by adjusting the doping temperature, doping time length, and / or doping concentration of the Lewis acid. In this embodiment, the channel layer 3 is subjected to Lewis acid doping for a preset time length in a high-temperature environment, so as to introduce trap centers into the energy band structure of the channel layer 3, capture photo-generated charges, produce a persistent photoconductive effect, and realize simulation of the function of a phototransistor.

[0075] In some embodiments, the high-temperature temperature is 70-160°C. For example, the high-temperature temperature is 160°C, i.e., the channel layer 3 is subjected to Lewis acid doping in an environment at 160°C.

[0076] In some embodiments, the preset time length is 10 min-1 h. For example, the preset time length is 1 h, i.e., the channel layer 3 is subjected to Lewis acid doping for 1 h in a high-temperature environment.

[0077] In some embodiments, the doping concentration of the Lewis acid is 0.01-1 mol%.

[0078] In some embodiments, the Lewis acid includes SnCl4. The Lewis acid refers to any molecule, ion, or atomic group that can accept an external electron pair. The Lewis acid can also include other liquid electrophilic reagents such as BF3, AlCl3, and SO3, which are not specifically limited here.

[0079] In some embodiments, the Lewis acid doping of the channel layer for a preset time length in a high-temperature environment in step 140 includes:

[0080] The liquid Lewis acid is dissolved in an alcohol polar protic solvent;

[0081] The solvent in which the Lewis acid is dissolved is transferred to a polytetrafluoroethylene reaction kettle and heated;

[0082] The channel layer is immersed in a reaction kettle at a high temperature environment for a preset time length to perform Lewis acid doping on the channel layer.

[0083] A liquid Lewis acid (e.g., SnCl4) is measured into an alcohol polar protic solvent (e.g., ethanol), and a magnetic stirrer is added to stir until the Lewis acid is completely dissolved in the alcohol polar protic solvent. The volume of the Lewis acid (e.g., liquid SnCl4) can be 1.6 ml, and the volume of the alcohol polar protic solvent (e.g., anhydrous ethanol) can be 10 ml.

[0084] Then, the alcohol polar protic solution (e.g., ethanol) in which the Lewis acid (e.g., SnCl4) is dissolved is transferred into a polytetrafluoroethylene reaction kettle and placed on a heating table for heating. The substrate is placed in the polytetrafluoroethylene reaction kettle, so that the channel layer 3 (e.g., a thin layer of WSe2) is immersed in the polytetrafluoroethylene reaction kettle to perform Lewis acid doping on the channel layer 3 at a high temperature environment. The temperature required for heating (i.e., the high temperature) can be 160°C, and the time length of immersion in the polytetrafluoroethylene reaction kettle (i.e., the preset time length) can be 1 h. The substrate refers to a structure after the source and drain electrodes are formed, i.e., the substrate includes a gate electrode 1, a gate oxide layer 2 located on one side of the gate electrode 1, a channel layer 3 located on a side of the gate oxide layer 2 away from the gate electrode 1, and source and drain electrodes located on a side of the channel layer 3 away from the gate oxide layer 2 and connected to the channel layer 3.

[0085] Then, the substrate is rinsed with the alcohol polar protic solution (e.g., anhydrous ethanol), and the surface is blown dry with high-purity nitrogen.

[0086] The channel layer 3 changes in performance after being doped with the Lewis acid at a high temperature environment. As shown in FIG. 2B, compared with the channel layer (e.g., WSe2) before doping, the WSe2 characteristic peak position of the channel layer (e.g., Sn-WSe2) after high-temperature Lewis acid doping is slightly blue-shifted, which affects the electrical performance of the channel layer. Figure 4 As shown in FIG. 2C, compared with the channel layer (e.g., WSe2) before doping, the WSe2 characteristic peak position of the channel layer (e.g., Sn-WSe2) after high-temperature Lewis acid doping is slightly red-shifted, which affects the energy band structure of the channel layer. Figure 5 The thickness of the channel layer 3 does not change after being doped with the Lewis acid at a high temperature environment. For example, the thickness of the channel layer before doping is 5 nm. The AFM (atomic force microscope) image of the channel layer (e.g., Sn-WSe2) after high-temperature Lewis acid doping is shown in FIG. 3A. The thickness (i.e., height) of the edge and surrounding position of the channel layer (e.g., Sn-WSe2) after high-temperature Lewis acid doping is measured, and the measurement result is shown in FIG. 3B.

[0087] Figure 6 Figure 6 ​​As shown in (b), it can be seen that the thickness of the channel layer after high-temperature Lewis acid doping (such as Sn-WSe2) is 5 nm, while the thickness of the channel layer before doping (such as WSe2) is also 5 nm, that is, there is no difference in the thickness of the channel layer before and after doping.

[0088] The high-angle annular dark field-scanning transmission electron microscopy (HAADF-STEM) image of the channel layer (such as Sn-WSe2) after high-temperature Lewis acid doping is as follows: Figure 7 (a) shows. Read three columns of atoms and detect the intensities of the three columns of atomic peaks, respectively as Figure 7 (b), 7(c) and 7(d). The intensities of the peaks of different atoms are different. Figure 7 (b) The intensities of the two atomic peaks were detected. Figure 7 (c) Detect the intensities of the two atomic peaks, Figure 7 (d) The intensity of one atomic peak was detected, and the intensities of three atomic peaks were detected in total, indicating that Sn atoms were doped into the channel layer. The high-temperature Lewis acid doping process causes Sn to enter the WSe2 lattice and replace the W site.

[0089] The It (source-drain current-time) curve of the channel layer (such as WSe2) without high-temperature Lewis acid doping treatment is as follows: Figure 8 As shown, when the light pulse frequency is 1 Hz and the source-drain voltage is applied at 0.1 V, the change in source-drain current shows the light response characteristics of fast switching, which cannot simulate the performance of the photoelectric synapse.

[0090] In this embodiment, after the channel layer is doped with high-temperature Lewis acid, by changing the gate voltage and the number, width and frequency of light pulses, synaptic behavior can be simulated, including excitatory postsynaptic current (EPSC), paired pulse facilitation (PPF), long-term memory (STM), short-term memory (LTM) and other functions. Figure 9 As shown in (a), the source-drain current changes were detected at 50, 100, 200, and 400 light pulses, and the transition from short-term memory (STM) to long-term memory (LTM) was observed, which is consistent with the performance of the optoelectronic synaptic device. Figure 9 As shown in (b), the source-drain current changes were detected at light pulse widths of 0.05, 0.2, 0.4, and 1 s, and the transition from short-term memory (STM) to long-term memory (LTM) was observed, which is consistent with the performance of optoelectronic synaptic devices. Figure 9 As shown in (c), the changes in source-drain current were detected at light pulse frequencies of 1, 1.67, 3.33, and 20 Hz, respectively, and the transition from short-term memory (STM) to long-term memory (LTM) was observed, which is consistent with the performance of optoelectronic synaptic devices.

[0091] The EPSC (excitatory post synaptic current) of the Sn-WSe2-based optoelectronic synapse device under the lowest power consumption condition is shown in Figure 10 The power consumption calculation formula is: E erasing = V d × I d × T duration . Wherein, E erasing is the power consumption, V d is the operating voltage, I d is the current peak value, T duration is the light pulse width. The lowest power consumption condition is: operating voltage 0.004V, light pulse intensity 0.6mWcm 2 , light pulse width 50ms, and the minimum power consumption is 0.1fJ.

[0092] The optoelectronic synapse device in this embodiment has extremely fast and sensitive response to light pulses, and can be applied to high-pass filtering for image preprocessing. As shown in Figure 11 (a), the change of source-drain current under light pulse frequencies of 0.2, 1, 2, 3, 3.5, 4, 4.5 and 5Hz was detected respectively. Figure 11 (b) shows that the source-drain current of the 30th light pulse is divided by the source-drain current of the 1st light pulse, and the ratio is named gain. The gain is taken as the vertical coordinate, and the light pulse frequency is taken as the horizontal coordinate to draw a curve, and the cutoff frequency f c is determined according to the fitting curve, which is 0.95Hz. Figure 11 (c) is the image before high-pass filtering, Figure 11 (d) is the high-pass filtered image under the cutoff frequency f c , Figure 11 (e) is the high-pass filtered image under 5Hz. It can be seen that under the condition of greater than or equal to the cutoff frequency f c , the image edge is more obvious.

[0093] The optoelectronic synapse device in this embodiment can be applied to Boolean logic commands. As shown in Figure 12 (a), under the dual-mode synergistic modulation of light and electricity, input A is a light pulse, and the light state is defined as logic "1" and the no-light state is defined as logic "0"; input B is a gate voltage, and the no-gate voltage is defined as logic "1" and the gate voltage is defined as logic "0". The threshold current is set to 100pA, and the source-drain current after AND Boolean logic command is detected. It can be seen that the AND Boolean logic command is successfully simulated. As shown in Figure 12(b) As shown, under the dual-mode synergistic modulation of light and electricity, input A is a light pulse, defining the light state as logic "1" and the no-light state as logic "0"; input B is a gate voltage, defining the no-gate voltage as logic "1" and the gate voltage as logic "0". The threshold current is set to 100 pA, and the source-drain current after the OR (or) Boolean logic command is detected. It can be seen that the OR (or) Boolean logic command is successfully simulated.

[0094] As shown above, according to the preparation method of the optoelectronic synapse device provided in the embodiments of the present application, the channel layer is doped with a Lewis acid for a preset time length in a high-temperature environment, so as to introduce a trap center in the energy band structure of the channel layer, capture photo-generated charges, produce a sustained photoconductivity effect, realize simulation of the optoelectronic synapse function, and the optoelectronic synapse function includes functions such as excitatory postsynaptic current (EPSC), paired pulse facilitation (PPF), long-term memory (STM), short-term memory (LTM), etc. At the same time, the conductivity is adjusted in the light and electricity dual-mode, and the simulation has an extremely low operating voltage (0.004 V), a weak light pulse intensity (0.6 mWcm 2 ), and an extremely low power consumption (0.1 fJ). The response to the electrical pulse is extremely fast and sensitive, which can be applied to high-pass filtering for image preprocessing, and can also simulate the Boolean logic command.

[0095] Correspondingly, the embodiments of the present application also provide an optoelectronic synapse device, which can be prepared by using the preparation method of the optoelectronic synapse device in the above embodiments.

[0096] As shown in Figure 2 , the optoelectronic synapse device provided in the embodiments of the present application includes a gate 1, a gate oxide layer 2, a channel layer 3, and a source-drain electrode.

[0097] The gate 1 can be a semiconductor layer including silicon, or a semiconductor layer including other elements. The gate 1 is a highly doped semiconductor layer, and the doping type of the gate 1 can be N-type or P-type.

[0098] The gate oxide layer 2 is located on one side of the gate 1. The gate oxide layer 2 can include one or more combinations of silicon oxide, silicon nitride, etc.

[0099] The channel layer 3 is located on the side of the gate oxide layer 2 away from the gate 1. The channel layer 3 covers part of the gate oxide layer 2. The channel layer 3 is a semiconductor layer. In some embodiments, in combination with Figure 3 As shown, the lateral cross section of the channel layer 3 is triangular.

[0100] The channel layer 3 is doped with a Lewis acid to introduce trap centers in the energy band structure of the channel layer 3. By adjusting the doping temperature (e.g., 70-160°C), the doping time (10 min-1 h), and / or the doping concentration (0.01-1 mol%) of the Lewis acid, the energy band structure of the channel layer 3 can be adjusted to introduce trap centers in the energy band structure of the channel layer 3 to capture photo-generated charges, produce a persistent photoconductivity effect, and realize the simulation of the optoelectronic synapse function.

[0101] The source-drain electrode is located on the side of the channel layer 3 away from the gate oxide layer 2 and is connected to the channel layer 3. The source-drain electrode includes a source electrode 4 and a drain electrode 5, which are laterally spaced apart. The source electrode 4 is located on the side of the channel layer 3 away from the gate oxide layer 2 and is connected to the channel layer 3. The source electrode 4 can also extend onto the gate oxide layer 2. The drain electrode 5 is located on the side of the channel layer 3 away from the gate oxide layer 2 and is connected to the channel layer 3. The drain electrode 5 can also extend onto the gate oxide layer 2. The source electrode 4 can include one or more combinations of copper, titanium, aluminum, nickel, gold, etc. The drain electrode 5 can include one or more combinations of copper, titanium, aluminum, nickel, gold, etc.

[0102] In some embodiments, the channel layer 3 includes a two-dimensional material layer.

[0103] In some embodiments, the two-dimensional material layer includes WSe2. The two-dimensional material layer can also include other types of two-dimensional materials, such as MoS2, WS2, and MoSe2, etc., which are not specifically limited here.

[0104] In some embodiments, the channel layer 3 has a relatively thin thickness, for example, the thickness of the channel layer 3 is 5 nm.

[0105] In some embodiments, the Lewis acid includes SnCl4. The Lewis acid refers to any molecule, ion, or atomic group that can accept an external electron pair. The Lewis acid can also include other liquid electrophilic reagents, such as BF3, AlCl3, and SO3, etc., which are not specifically limited here.

[0106] In summary, the optoelectronic synapse device provided by the embodiments of the present application introduces trap centers in the energy band structure of the channel layer by doping the channel layer with a Lewis acid for a preset time at a high temperature environment, captures photo-generated charges, produces a persistent photoconductivity effect, realizes the simulation of the optoelectronic synapse function, including excitatory postsynaptic current (EPSC), paired pulse facilitation (PPF), long-term memory (STM), short-term memory (LTM), etc., and simultaneously realizes the light and electrical dual-mode regulation of conductivity, with an extremely low operating voltage (0.004 V), a weak light pulse intensity (0.6 mWcm-2), and a high signal-to-noise ratio (SNR) of 10-20 dB, etc. during simulation. 2) and extremely low power consumption (0.1fJ). It has an extremely fast and sensitive response to electrical pulses and can be applied to high-pass filtering for image preprocessing and to simulate Boolean logic commands.

[0107] The terms "first," "second," and the like in the specification and claims of this application are used to distinguish similar objects, and are not used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate, so that the embodiments of this application can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "first," "second," and the like generally distinguish objects of a class and do not limit the number of objects. For example, the first object may be one or more.

[0108] In the description of this application, “plurality” means two or more.

[0109] Throughout this specification, reference to terms such as "one embodiment," "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0110] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions, and variations may be made to the embodiments without departing from the principles and intent of the present application, and that the scope of the present application is defined by the claims and their equivalents.

Claims

1. A method for preparing a photoelectric synaptic device, characterized in that: include: Providing a gate and a gate oxide layer located on one side of the gate; forming a channel layer on a side of the gate oxide layer facing away from the gate; The channel layer includes a two-dimensional material layer, and the two-dimensional material layer includes WSe2, MoS2, WS2 or MoSe2; forming a source and a drain on a side of the channel layer away from the gate oxide layer, wherein the source and the drain are connected to the channel layer; In a high temperature environment, the channel layer is doped with a Lewis acid for a preset time to introduce trap centers into the energy band structure of the channel layer; The Lewis acid includes SnCl4; The step of performing Lewis acid doping on the channel layer for a preset time under a high temperature environment includes: Dissolving a liquid Lewis acid in an alcoholic polar protic solvent; The solvent containing the Lewis acid is transferred into a polytetrafluoroethylene reactor and heated; In a high-temperature environment, the channel layer is immersed in the reactor to perform Lewis acid doping on the channel layer for a preset time.

2. The method for preparing a photoelectric synapse device according to claim 1, wherein: The forming of a source and a drain on a side of the channel layer away from the gate oxide layer comprises: forming a capping layer on a side of the channel layer facing away from the gate oxide layer; forming an opening in the cover layer to expose the channel layer; forming a source and a drain in the opening connected to the exposed channel layer; The covering layer is removed.

3. The method for preparing a photoelectric synapse device according to claim 1, wherein: The high temperature is 70°C-160°C.

4. The method for preparing a photoelectric synapse device according to claim 1, wherein: The preset duration is 10 minutes to 1 hour.

5. The method for preparing a photoelectric synapse device according to claim 1, wherein: The doping concentration of the Lewis acid is 0.01 mol % to 1 mol %.

6. A photoelectric synaptic device, characterized in that: The photoelectric synapse device is prepared by the method for preparing the photoelectric synapse device according to any one of claims 1 to 5, wherein the photoelectric synapse device comprises: gate; a gate oxide layer, located on one side of the gate; a channel layer located on a side of the gate oxide layer facing away from the gate; the channel layer is doped with Lewis acid to introduce trap centers into the energy band structure of the channel layer; The source and drain electrodes are located on a side of the channel layer away from the gate oxide layer and are connected to the channel layer.

Images