Solar cell and preparation method thereof

Abstract

The invention provides a solar cell and a preparation method thereof, and relates to the technical field of solar cells. The method for preparing the solar cell comprises the following steps: forming a tunneling oxide layer on one side of the back surface of a silicon substrate; forming a first intrinsic amorphous silicon layer, a first doped amorphous silicon layer and a second doped amorphous silicon layer; forming a second intrinsic amorphous silicon layer, a third doped amorphous silicon layer and a fourth doped amorphous silicon layer; performing annealing treatment on the silicon substrate to enable the first intrinsic amorphous silicon layer, the first doped amorphous silicon layer and the second doped amorphous silicon layer to form a first doped layer, enable the second intrinsic amorphous silicon layer, the third doped amorphous silicon layer and the fourth doped amorphous silicon layer to form a second doped layer, and enabling the first doped layer to point to the direction of the silicon substrate along the first doped layer, the concentration of the gallium element in the first doping layer is reduced; and the concentration of the boron element in the second doped layer is reduced. Therefore, the formed p-type doped polycrystalline silicon can achieve a good passivation effect, the concentration of the doping element B on the outer side is high, and the contact resistance can be reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of solar cells, and in particular to a solar cell and a method for preparing the same. Background Art

[0002] n-TOPCon (Tunnel Oxide Passivating Contact) solar cells are n-type tunnel oxide passivated contact solar cells. This type of solar cell has made significant progress in improving efficiency and reducing costs. It uses n-poly (n-type doped polycrystalline silicon) as a high-efficiency electron passivation transport layer. Several photovoltaic companies in the industry have achieved mass production conversion efficiencies of 26%. At present, the Auger recombination of the boron-expanded emitter (hole transport end) and the further improvement of the high metal contact recombination restriction efficiency make it very important to develop high-performance p-poly (p-type doped polycrystalline silicon) technology. In addition, p-poly, as an efficient hole transport layer, is applied to BC (Back Contact) cells, etc., which can further improve the device efficiency by more than 0.4%. Since 2020, many battery manufacturers and research institutions have carried out p-poly technology development.

[0003] However, current p-type polysilicon has difficulty in simultaneously meeting the requirements of high passivation efficiency and low contact resistivity. Summary of the invention

[0004] The present invention aims to alleviate or solve at least one of the above-mentioned problems to at least some extent.

[0005] In one aspect of the present invention, the present invention proposes a method for preparing a solar cell. In some embodiments of the present invention, the method for preparing a solar cell includes: forming a tunneling oxide layer on the back side of a silicon substrate; forming a first intrinsic amorphous silicon layer on the side of the tunneling oxide layer away from the silicon substrate, and the reaction gas for forming the first intrinsic amorphous silicon layer includes a first silicon source and hydrogen; forming a first doped amorphous silicon layer on the side of the first intrinsic amorphous silicon layer away from the silicon substrate, and the reaction gas for forming the first doped amorphous silicon layer includes the first silicon source, the first doping source and hydrogen, wherein the first doping source contains gallium, and the flow rate of the first doping source is a; forming a second doped amorphous silicon layer on the side of the first doped amorphous silicon layer away from the silicon substrate, and the reaction gas for forming the second doped amorphous silicon layer includes the first silicon source, the first doping source and hydrogen, wherein the flow rate of the first doping source is b, b>a; forming a second intrinsic amorphous silicon layer on the side of the second doped amorphous silicon layer away from the silicon substrate, and the reaction gas for forming the second intrinsic amorphous silicon layer includes a second silicon source and hydrogen; A third doped amorphous silicon layer is formed on a side of the second intrinsic amorphous silicon layer away from the silicon substrate, and the reaction gas for forming the third doped amorphous silicon layer includes the second silicon source, the second doping source and hydrogen, wherein the second doping source contains boron element, and the flow rate of the second doping source is c; a fourth doped amorphous silicon layer is formed on a side of the third doped amorphous silicon layer away from the silicon substrate, and the reaction gas for forming the fourth doped amorphous silicon layer includes the second silicon source, the second doping source and hydrogen, wherein the flow rate of the second doping source is d, d>c; the silicon substrate is annealed so that the first intrinsic amorphous silicon layer, the first doped amorphous silicon layer and the second doped amorphous silicon layer form a first doped layer, and the second intrinsic amorphous silicon layer, the third doped amorphous silicon layer and the fourth doped amorphous silicon layer form a second doped layer, and in a direction from the first doped layer to the silicon substrate, the concentration of gallium element in the first doped layer shows a decreasing trend; the concentration of boron element in the second doped layer shows a decreasing trend. Therefore, the above method can be used to adjust and control the diffusion of gallium and boron elements, and the formed p-type doped polysilicon can have a good passivation effect. The concentration of the doping element B on the outside is higher, which can reduce the contact resistance.

[0006] In some embodiments of the present invention, 50 sccm≤a≤300 sccm, 100 sccm≤b≤800 sccm; and / or, 50 sccm≤c≤300 sccm, 100 sccm≤d≤800 sccm. This is beneficial to regulating and controlling the diffusion of doping elements, thereby being more conducive to achieving a higher passivation effect and a lower contact resistivity.

[0007] In some embodiments of the present invention, the method for preparing a solar cell satisfies at least one of the following conditions: the first doping source includes trimethylgallium; the second doping source includes trimethylboron; the first silicon source includes silane; and the second silicon source includes silane.

[0008] In some embodiments of the present invention, the method for preparing a solar cell satisfies at least one of the following conditions: the temperature for forming the first intrinsic amorphous silicon layer, the temperature for forming the first doped amorphous silicon layer, and the temperature for forming the second doped amorphous silicon layer are each independently 200°C to 500°C; in the process of forming the first intrinsic amorphous silicon layer, the flow rate of the first silicon source is 2000sccm to 4000sccm, and the flow rate of hydrogen is 8000sccm to 12000sccm; in the process of forming the first doped amorphous silicon layer, the flow rate of the first silicon source is 2000sccm to 4000sccm, and the flow rate of hydrogen is 8000sccm to 12000sccm; in the process of forming the second doped amorphous silicon layer, the flow rate of the first silicon source is 2000sccm to 4000sccm, and the flow rate of hydrogen is 8000sccm to 12000sccm. 000sccm~12000sccm; the temperature for forming the second intrinsic amorphous silicon layer, the temperature for forming the third doped amorphous silicon layer and the temperature for forming the fourth doped amorphous silicon layer are each independently 200℃~500℃; in the process of forming the second intrinsic amorphous silicon layer, the flow rate of the second silicon source is 2000sccm~4000sccm, and the flow rate of hydrogen is 8000sccm~12000sccm; in the process of forming the third doped amorphous silicon layer, the flow rate of the second silicon source is 2000sccm~4000sccm, and the flow rate of hydrogen is 8000sccm~12000sccm; in the process of forming the fourth doped amorphous silicon, the flow rate of the second silicon source is 2000sccm~4000sccm, and the flow rate of hydrogen is 8000sccm~12000sccm.

[0009] In some embodiments of the present invention, the method for preparing a solar cell satisfies at least one of the following conditions: the ratio of the thickness of the first intrinsic amorphous silicon layer, the thickness of the first doped amorphous silicon layer, and the thickness of the second doped amorphous silicon layer is 1:(1-4):(2-5); the thickness of the first doped layer is 5nm-150nm; the ratio of the thickness of the second intrinsic amorphous silicon layer, the thickness of the third doped amorphous silicon layer, and the thickness of the fourth doped amorphous silicon layer is 1:(1-4):(2-5); the thickness of the second doped layer is 5nm-150nm.

[0010] In some embodiments of the present invention, the concentration of gallium in the first doping layer is 1×10 16 cm -3 ~1×1021 cm -3 ; and / or, the concentration of boron in the second doping layer is 1×10 16 cm -3 ~1×10 21 cm -3 .

[0011] In some embodiments of the present invention, before forming the second intrinsic amorphous silicon layer, an interface barrier layer is formed on the side of the second doped amorphous silicon layer away from the silicon substrate, and the material of the interface barrier layer includes at least one of silicon oxide, aluminum oxide and nitrogen-doped silicon oxide. This is more conducive to regulating and controlling the doping of the B element, thereby better blocking the B element from entering the tunneling oxide layer, thereby helping to improve the passivation effect and improve the performance of the solar cell.

[0012] In some embodiments of the present invention, the thickness of the interface barrier layer is 0.5 nm-3 nm. The thickness of the interface barrier layer within the above range is conducive to further improving the passivation effect and improving the performance of the solar cell.

[0013] In some embodiments of the present invention, the method for preparing a solar cell satisfies at least one of the following conditions: the material of the tunneling oxide layer includes at least one of silicon oxide, aluminum oxide and nitrogen-doped silicon oxide; the thickness of the tunneling oxide layer is 0.5nm-3nm; the temperature of the annealing treatment is 880℃~1050℃.

[0014] In another aspect of the present invention, the present invention provides a solar cell. In some embodiments of the present invention, the solar cell is prepared by the method described above. Thus, the solar cell has a good back passivation effect and a low back contact resistivity. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0016] Figure 1 A flow chart of a method for preparing a solar cell according to an embodiment of the present invention is shown;

[0017] Figure 2 A flow chart of a method for preparing a solar cell according to another embodiment of the present invention is shown;

[0018] Figure 3 A schematic diagram of the structure of a solar cell according to an embodiment of the present invention is shown;

[0019] Figure 4 A schematic structural diagram of a solar cell according to another embodiment of the present invention is shown;

[0020] Figure 5 A schematic structural diagram of a solar cell according to yet another embodiment of the present invention is shown.

[0021] Description of reference numerals:

[0022] 10: silicon substrate; 11: back side; 12: front side; 20: tunneling oxide layer; 30: first doping layer; 40: second doping layer; 50: interface barrier layer; 1: first n-type passivation polysilicon layer; 2: second n-type passivation polysilicon layer; 3: first passivation anti-reflection layer; 4: second passivation anti-reflection layer; 5: front side gate line; 6: third passivation anti-reflection layer; 7: fourth passivation anti-reflection layer; 8: back side gate line. DETAILED DESCRIPTION

[0023] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.

[0024] The present invention is based on the inventor's discovery and understanding of the following facts and problems:

[0025] The passivation contact quality of p-type poly (polycrystalline silicon) film layer still has a lot of room for improvement compared with n-type poly (polycrystalline silicon). The main problems at this stage are: (1) B atoms in SiO x The separation coefficient in Ga is lower than that in P (phosphorus), that is, B atoms are more likely to accumulate in the oxide layer, and the influence (aggregation, distortion) of B atoms on the interface oxide layer (tunneling oxide layer) is reduced, which will reduce the passivation performance. (2) Ga in SiO x The separation coefficient in the silicon is high, which can achieve a higher passivation effect, but the diffusion coefficient of Ga is smaller than that of B, making it more difficult to obtain uniformly doped polysilicon. In addition, the solid solubility of Ga in silicon is one order of magnitude lower than that of B, and the effective doping concentration activated by annealing is low, making it difficult to obtain a low contact resistivity.

[0026] In view of the problem that it is difficult to achieve high passivation effect and low contact resistivity simultaneously in current p-type polysilicon, the present invention proposes a method for preparing a multilayer film system structure, in which a Ga-doped polysilicon film layer is prepared on the side close to the silicon wafer and the interface oxide layer, and a B-doped polysilicon film layer is prepared on the side away from the silicon wafer. The doping and diffusion of the doping elements Ga and B are regulated by controlling the flow rate of the doping gas to obtain a better passivation effect and a lower contact resistivity. Furthermore, an interface barrier layer can be set between the two polysilicon film layers to better regulate the diffusion of the doping elements and reduce the diffusion of the B element into the tunneling oxide layer, so as to achieve both an excellent passivation effect and a low contact resistivity, thereby facilitating the improvement of the device's V oc (open circuit voltage) and FF (impact factor).

[0027] In order to at least alleviate or even solve at least one of the above problems to a certain extent, in one aspect of the present invention, the present invention provides a method for preparing a solar cell. Figure 1 and Figure 2 , the method for preparing a solar cell may include the following steps:

[0028] S10: forming a tunnel oxide layer on the back side of the silicon substrate.

[0029] In the present invention, the silicon substrate may be an n-type silicon substrate or a p-type silicon substrate.

[0030] The surface morphology of the silicon substrate is not particularly limited in the present invention, and may be a polished structure or a textured structure.

[0031] refer to Figures 3 to 5 The silicon substrate 10 has a front side 12 and a back side 11. In a solar cell, the front side 12 of the silicon substrate 10 refers to the surface facing the light source (sun), and the back side 11 refers to the surface facing away from the light source. In some embodiments, the front side 12 and / or the back side 11 may be a planar structure. In other embodiments, the front side 12 and / or the back side 11 may be a velvet structure.

[0032] In some embodiments, reference Figures 1 to 5 A tunnel oxide layer 20 is formed on the back side 11 of the silicon substrate 10. The tunnel oxide layer can selectively transmit carriers, which helps to reduce the surface recombination of carriers, thereby helping to improve the open circuit voltage and fill factor of the solar cell.

[0033] In some embodiments of the present invention, the material of the tunnel oxide layer 20 may include at least one of silicon oxide, aluminum oxide and nitrogen-doped silicon oxide. In some specific embodiments, the material of the tunnel oxide layer 20 may include silicon oxide, aluminum oxide or nitrogen-doped silicon oxide.

[0034] In some embodiments of the present invention, the material of the tunnel oxide layer 20 may be silicon oxide. In some specific embodiments, the tunnel oxide layer may be prepared in a PECVD (plasma enhanced chemical vapor deposition) device, the silicon substrate 10 is placed in the PECVD device, N2O is used as a reaction gas, Ar is used as a dilution gas, and the tunnel oxide layer 20 is deposited on the back side 11 of the silicon substrate 10. This helps to control the reaction process and obtain a film of better quality.

[0035] In some embodiments of the present invention, the thickness of the tunnel oxide layer 20 may be 0.5 nm-3 nm, for example, the thickness of the tunnel oxide layer 20 may be 0.5 nm, 1 nm, 1.5 nm, 2 nm, 2.5 nm, 3 nm, etc. The thin thickness of the tunnel oxide layer can play a good role in interface passivation and reduce surface recombination; it helps the majority carriers to pass through the tunnel oxide layer and prevents the transmission of minority carriers, thereby facilitating the improvement of the photoelectric conversion efficiency of the battery; it helps to reduce the absorption loss of light, thereby facilitating the improvement of the short-circuit current density of the battery.

[0036] In some embodiments of the present invention, before forming the tunneling oxide layer on the back side of the silicon substrate, the cutting damage layer on the surface of the silicon substrate may be removed by an alkali polishing process.

[0037] S20: forming a first intrinsic amorphous silicon layer.

[0038] In some embodiments of the present invention, a first intrinsic amorphous silicon layer may be formed on a side of the tunnel oxide layer away from the silicon substrate using a first silicon source and hydrogen as reaction gases. The silicon source may provide silicon elements to form amorphous silicon by plasma enhanced chemical vapor deposition.

[0039] In some embodiments of the present invention, the first intrinsic amorphous silicon layer may be formed using the first silicon source, hydrogen and argon as reaction gases. Argon can be dissociated to form plasma, which is beneficial to improving the generation rate and film quality of the thin film.

[0040] In some embodiments of the present invention, the first silicon source may include silane, whereby the silane may be decomposed to form an intrinsic amorphous silicon layer.

[0041] In some embodiments of the present invention, the temperature for forming the first intrinsic amorphous silicon layer may be 200° C. to 500° C. For example, the temperature for forming the first intrinsic amorphous silicon layer may be 200° C., 250° C., 300° C., 350° C., 400° C., 450° C., 500° C., etc. The above temperatures are conducive to the reaction of the silicon source and the hydrogen gas and form a flat film layer.

[0042] In some embodiments of the present invention, during the formation of the first intrinsic amorphous silicon layer, the flow rate of the first silicon source may be 2000sccm to 4000sccm, and the flow rate of the hydrogen may be 8000sccm to 12000sccm. For example, the flow rate of the first silicon source may be 2000sccm, 2500sccm, 3000sccm, 3300sccm, 3500sccm, 3700sccm, 4000sccm, etc., and the flow rate of the hydrogen may be 8000sccm, 8300sccm, 8600sccm, 8900sccm, 9200sccm, 9600sccm, 10000sccm, 12000sccm, etc. This is conducive to adjusting and controlling the film formation speed of the amorphous silicon layer and obtaining an amorphous silicon film layer of better quality.

[0043] S30: forming a first doped amorphous silicon layer.

[0044] In some embodiments of the present invention, a first doped amorphous silicon layer is formed on a side of the first intrinsic amorphous silicon layer away from the silicon substrate, and the reaction gas for forming the first doped amorphous silicon layer may include a first silicon source, a first doping source, and hydrogen, wherein the first doping source contains gallium, and the flow rate of the first doping source is a. Thus, an amorphous silicon layer doped with gallium can be formed.

[0045] In some embodiments of the present invention, the reaction gas for forming the first doped amorphous silicon layer may further include argon gas, so that the argon gas can be dissociated, which can help control the growth rate of the thin film and improve the quality of the thin film.

[0046] In some embodiments of the present invention, the first doping source may include trimethylgallium. Ga has a high separation coefficient in silicon oxide, which can achieve a high passivation effect, but the diffusion coefficient of Ga is smaller than that of B, and it is difficult to obtain uniformly doped polysilicon. Trimethylgallium is used as the doping source. Trimethylgallium contains carbon, which can be added during the deposition process to avoid film explosion and improve the passivation level.

[0047] In some embodiments of the present invention, during the process of forming the first doped amorphous silicon layer, the flow rate a of the first doping source may be 50 sccm to 300 sccm, for example, a may be 50 sccm, 100 sccm, 150 sccm, 200 sccm, 250 sccm, 300 sccm, etc. Thus, the doping concentration of the gallium element in the first doped amorphous silicon layer may be adjusted and controlled to obtain a film layer with a lower gallium doping concentration.

[0048] In some embodiments of the present invention, during the formation of the first doped amorphous silicon layer, the flow rate of the first silicon source may be 2000sccm to 4000sccm, and the flow rate of the hydrogen may be 8000sccm to 12000sccm. For example, the flow rate of the first silicon source may be 2000sccm, 2500sccm, 2800sccm, 3000sccm, 3200sccm, 3500sccm, 4000sccm, etc., and the flow rate of the hydrogen may be 8000sccm, 8500sccm, 9000sccm, 9500sccm, 10000sccm, 12000sccm, etc. The flow rates of the first silicon source and the hydrogen are within the above ranges, which is conducive to regulating and controlling the formation speed and film quality of the doped amorphous silicon layer.

[0049] In some embodiments of the present invention, the temperature for forming the first doped amorphous silicon layer may be 200° C. to 500° C. For example, the temperature for forming the first doped amorphous silicon layer may be 200° C., 250° C., 300° C., 350° C., 400° C., 450° C., 500° C., etc. The above temperature is not only conducive to the formation of the amorphous silicon layer, but also conducive to the doping of gallium, thereby obtaining a doped amorphous silicon layer with good film quality.

[0050] S40: forming a second doped amorphous silicon layer.

[0051] In some embodiments of the present invention, a second doped amorphous silicon layer is formed on a side of the first doped amorphous silicon layer away from the silicon substrate, and the reaction gas for forming the second doped amorphous silicon layer may include a first silicon source, a first doping source, and hydrogen, wherein the flow rate of the first doping source is b, b>a. Thus, the concentration of the doping element in the second doped amorphous silicon layer is higher than the concentration of the doping element in the first doped amorphous silicon layer, and after subsequent annealing, the concentration of the first doping element in the formed first doping layer presents a certain change trend, which is conducive to improving the passivation effect.

[0052] In some embodiments of the present invention, the reaction gas for forming the second doped amorphous silicon layer may further include argon gas, so that the argon gas can be dissociated, which can help control the growth rate of the thin film and improve the quality of the thin film.

[0053] In some embodiments of the present invention, 100sccm≤b≤800sccm, for example, in the process of forming the second doped amorphous silicon layer, the flow rate b of the first doping source can be 100sccm, 300sccm, 400sccm, 500sccm, 600sccm, 700sccm, 800sccm, etc. This is conducive to controlling the concentration of the doping element in the second doped amorphous silicon layer, thereby being more conducive to improving the quality of the film layer.

[0054] In some embodiments of the present invention, the temperature for forming the second doped amorphous silicon layer may be 200° C. to 500° C. For example, the temperature for forming the second doped amorphous silicon layer may be 200° C., 300° C., 350° C., 400° C., 450° C., 500° C., etc. The above temperature is conducive to the formation of the amorphous silicon layer and the doping of gallium element, thereby facilitating the formation of a doped amorphous silicon layer with better quality.

[0055] In some embodiments of the present invention, during the process of forming the first intrinsic amorphous silicon layer, the doping source may not be introduced. After a period of time, the first doping source is introduced with a small flow rate to prepare the first doped amorphous silicon layer. After a period of time, the flow rate of the first doping source is increased to form the second doped amorphous silicon layer. By adjusting the flow rate of the doping source to adjust and control the doping amount of the amorphous silicon layer, a film layer with a gradient distribution of doping elements can be obtained after subsequent annealing treatment, which is conducive to improving the passivation effect.

[0056] In some embodiments of the present invention, the ratio of the thickness of the first intrinsic amorphous silicon layer, the thickness of the first doped amorphous silicon layer, and the thickness of the second doped amorphous silicon layer may be 1:(1-4):(2-5), for example, the ratio of the thickness of the first intrinsic amorphous silicon layer, the thickness of the first doped amorphous silicon layer, and the thickness of the second doped amorphous silicon layer may be 1:1:2, 1:2:3, 1:2:4, 1:2:5, 1:3:3, 1:3:5, 1:4:3, 1:4:4, 1:4:5, etc. The thickness ratio of the above film layers is within the above range, which is conducive to adjusting and controlling the distribution of the doping elements, and after the subsequent annealing treatment, a film layer with excellent performance is obtained, thereby improving the passivation effect.

[0057] In the present invention, when the reaction gas includes argon, there is no specific limitation on the flow rate of argon in the process of forming the first intrinsic amorphous silicon layer, the first doped amorphous silicon layer and the second doped amorphous silicon layer, and those skilled in the art can select and set it according to actual needs.

[0058] S50: forming a second intrinsic amorphous silicon layer.

[0059] In some embodiments of the present invention, a second intrinsic amorphous silicon layer is formed on a side of the second doped amorphous silicon layer away from the silicon substrate, and the reaction gas for forming the second intrinsic amorphous silicon layer may include a second silicon source and hydrogen. Thus, the amorphous silicon layer may be formed by a plasma enhanced chemical vapor deposition method under certain conditions.

[0060] In some embodiments of the present invention, the second silicon source may include silane, whereby the silane may be decomposed to form an amorphous silicon layer.

[0061] In some embodiments of the present invention, the reaction gas for forming the second intrinsic amorphous silicon layer may further include argon gas, which can be dissociated to adjust the reaction process and film formation quality.

[0062] In some embodiments of the present invention, the temperature for forming the second intrinsic amorphous silicon layer may be 200° C. to 500° C. For example, the temperature for forming the second intrinsic amorphous silicon layer may be 200° C., 250° C., 300° C., 400° C., 500° C., etc. The above temperature is conducive to the reaction between the second silicon source and hydrogen, thereby promoting the formation of the second intrinsic amorphous silicon layer.

[0063] In some embodiments of the present invention, during the formation of the second intrinsic amorphous silicon layer, the flow rate of the second silicon source may be 2000sccm to 4000sccm, and the flow rate of the hydrogen gas may be 8000sccm to 12000sccm. For example, the flow rate of the second silicon source may be 2000sccm, 2500sccm, 2700sccm, 3000sccm, 3300sccm, 3600sccm, 4000sccm, etc., and the flow rate of the hydrogen gas may be 8000sccm, 8500sccm, 9000sccm, 9600sccm, 10000sccm, 12000sccm, etc. Therefore, the flow rates of the second silicon source and the hydrogen gas are within the above ranges, which is conducive to forming an intrinsic amorphous silicon layer with good film quality in a shorter time.

[0064] In some embodiments of the present invention, reference Figure 2 Before forming the second intrinsic amorphous silicon layer, an interface barrier layer may be formed on the side of the second doped amorphous silicon layer away from the silicon substrate, wherein the material of the interface barrier layer may include at least one of silicon oxide, aluminum oxide and nitrogen-doped silicon oxide. Thus, it can at least to some extent prevent the B element from diffusing into the tunnel oxide layer.

[0065] In some specific embodiments of the present invention, the material of the interface barrier layer may be silicon oxide, aluminum oxide or nitrogen-doped silicon oxide.

[0066] In some specific embodiments of the present invention, the silicon oxide interface barrier layer may be formed by a plasma enhanced chemical vapor deposition method using N2O as a reaction gas and argon as a diluent gas.

[0067] In some embodiments of the present invention, the thickness of the interface barrier layer may be 0.5 nm-3 nm, for example, the thickness of the interface barrier layer may be 0.5 nm, 1 nm, 1.5 nm, 2 nm, 2.5 nm, 3 nm, etc. When the thickness of the interface barrier layer is within the above range, it can play a good role in blocking the diffusion of the B element into the tunneling oxide layer, thereby further improving the passivation effect and reducing the contact resistivity.

[0068] S60: forming a third doped amorphous silicon layer.

[0069] In some embodiments of the present invention, a third doped amorphous silicon layer is formed on a side of the second intrinsic amorphous silicon layer away from the silicon substrate, and the reaction gas for forming the third doped amorphous silicon layer may include a second silicon source, a second doping source, and hydrogen, wherein the second doping source contains a boron element, and the flow rate of the second doping source is c. Thus, a boron-doped amorphous silicon layer may be formed.

[0070] In some embodiments of the present invention, the reaction gas for forming the third doped amorphous silicon layer may further include argon gas.

[0071] In some embodiments of the present invention, the second doping source may include trimethyl boron. Using trimethyl boron as a doping source can reduce the defect density in the film, which is beneficial to improving the film quality of the doped amorphous silicon layer; trimethyl boron has low toxicity and low pollution, and using it as a doping source can reduce environmental pollution.

[0072] In some embodiments of the present invention, the temperature for forming the third doped amorphous silicon layer may be 200° C. to 500° C. For example, the temperature for forming the third doped amorphous silicon layer may be 200° C., 300° C., 400° C., 500° C., etc. Preparing the third doped amorphous silicon layer within the above range is beneficial to the reaction of the second silicon source and the hydrogen and the doping of the amorphous silicon layer.

[0073] In some embodiments of the present invention, during the formation of the third doped amorphous silicon layer, the flow rate of the second silicon source may be 2000sccm to 4000sccm, and the flow rate of hydrogen may be 8000sccm to 12000sccm. For example, the flow rate of the second silicon source may be 2000sccm, 2500sccm, 3000sccm, 3500sccm, 3700sccm, 4000sccm, etc., and the flow rate of hydrogen may be 8000sccm, 8500sccm, 9000sccm, 9500sccm, 10000sccm, 12000sccm, etc. This is beneficial to regulating and controlling the formation of amorphous silicon and improving the film quality.

[0074] In some embodiments of the present invention, during the formation of the third doped amorphous silicon layer, the flow rate c of the second doping source may be 50 sccm to 300 sccm, for example, c may be 50 sccm, 100 sccm, 150 sccm, 200 sccm, 250 sccm, 300 sccm, etc. Thus, the B doping amount of the third doped amorphous silicon layer is relatively low, which is conducive to forming a gradient doped B doped layer through subsequent annealing.

[0075] S70: forming a fourth doped amorphous silicon layer.

[0076] In some embodiments of the present invention, a fourth doped amorphous silicon layer is formed on a side of the third doped amorphous silicon layer away from the silicon substrate, and the reaction gas for forming the fourth doped amorphous silicon layer may include a second silicon source, a second doping source, and hydrogen, wherein the flow rate of the second doping source is d, d>c. Thus, the doping concentration of the B element in the fourth doped amorphous silicon layer is higher than the doping concentration of B in the third doped amorphous silicon layer, thereby facilitating the formation of a gradient doped film layer, the doping concentration of B is higher on the side away from the silicon substrate, and the region with a higher doping concentration of B is in direct contact with the metal gate line, which is conducive to reducing the contact resistivity.

[0077] In some embodiments of the present invention, during the formation of the fourth doped amorphous silicon layer, the flow rate d of the second doping source may be 100 sccm to 800 sccm, for example, d may be 100 sccm, 300 sccm, 400 sccm, 500 sccm, 600 sccm, 800 sccm, etc. Thus, the flow rate of the second doping source is relatively large, and the doping concentration of the B element in the formed fourth doped amorphous silicon layer is relatively high. After subsequent annealing, the side of the second doping layer away from the silicon substrate can still maintain a relatively high doping concentration of the B element, which is conducive to further reducing the contact resistivity.

[0078] In some embodiments of the present invention, the reaction gas for forming the fourth doped amorphous silicon layer may further include argon gas.

[0079] In the present invention, when the reaction gas includes argon, there is no specific limitation on the flow rate of argon during the formation of the second intrinsic amorphous silicon layer, the third doped amorphous silicon layer and the fourth doped amorphous silicon layer, and those skilled in the art can select and set it according to actual needs.

[0080] In some embodiments of the present invention, during the formation of the fourth doped amorphous silicon, the flow rate of the second silicon source may be 2000 sccm to 4000 sccm, and the flow rate of hydrogen may be 8000 sccm to 12000 sccm. For example, the flow rate of the second silicon source may be 2000 sccm, 2500 sccm, 2700 sccm, 3000 sccm, 3200 sccm, 3500 sccm, 4000 sccm, and the flow rate of hydrogen may be 8000 sccm, 8500 sccm, 9000 sccm, 9500 sccm, 10000 sccm, 12000 sccm. This is conducive to regulating and controlling the formation rate of the doped amorphous silicon layer and improving the film quality.

[0081] In some embodiments of the present invention, the temperature for forming the fourth doped amorphous silicon layer may be 200° C. to 500° C. For example, the temperature for forming the fourth doped amorphous silicon layer may be 200° C., 300° C., 400° C., 450° C., 500° C., etc. The above temperature conditions are conducive to improving the film quality, thereby improving the overall performance of the solar cell.

[0082] In some embodiments of the present invention, during the formation of the second intrinsic amorphous silicon layer, the second doping source may not be introduced. After a period of time, the second doping source is introduced with a small flow rate to prepare a third doped amorphous silicon layer. After a period of time, the flow rate of the second doping source is increased to form a fourth doped amorphous silicon layer. Thus, the doping concentration of the amorphous silicon layer is regulated by adjusting the flow rate of the doping source. After subsequent annealing, a film layer with a gradient distribution of doping elements can be formed, thereby further improving the passivation effect and reducing the contact resistivity.

[0083] In some embodiments of the present invention, the thickness of the second intrinsic amorphous silicon layer, the thickness of the third doped amorphous silicon layer, and the thickness of the fourth doped amorphous silicon layer may be in a ratio of 1:(1-4):(2-5), for example, the thickness of the second intrinsic amorphous silicon layer, the thickness of the third doped amorphous silicon layer, and the thickness of the fourth doped amorphous silicon layer may be in a ratio of 1:1:2, 1:2:3, 1:2:4, 1:2:5, 1:3:3, 1:3:5, 1:4:3, 1:4:4, 1:4:5, etc. Thus, it is beneficial to control the distribution of doping elements, and after the subsequent annealing treatment, a film layer with good film quality can be obtained, which is beneficial to improve the passivation effect and reduce the contact resistivity.

[0084] In the present invention, the tunneling oxide layer, the first intrinsic amorphous silicon layer, the first doped amorphous silicon layer, the second doped amorphous silicon layer, the interface barrier layer, the second intrinsic amorphous silicon layer, the third doped amorphous silicon layer and the fourth doped amorphous silicon layer can all be prepared in a PECVD device, and the preparation of multiple film layers in the same device can be achieved by only replacing the gas or adjusting the gas flow rate.

[0085] S80: performing annealing treatment on the silicon substrate.

[0086] In some embodiments of the present application, after forming the fourth doped amorphous silicon layer, the silicon substrate may be annealed so that the first intrinsic amorphous silicon layer, the first doped amorphous silicon layer and the second doped amorphous silicon layer form a first doped layer, and the second intrinsic amorphous silicon layer, the third doped amorphous silicon layer and the fourth doped amorphous silicon layer form a second doped layer. Figures 3 to 5 , along the direction of the first doping layer 30 pointing to the silicon substrate 10 (such as Figures 3 to 5In the X direction shown in FIG, the concentration of gallium in the first doping layer 30 shows a decreasing trend, and the concentration of boron in the second doping layer 40 shows a decreasing trend. Therefore, after annealing, the concentration of the doped elements in the first doping layer and the second doping layer is higher on the side away from the silicon substrate, and lower on the side close to the silicon substrate. The side of the second doping layer away from the silicon substrate contacts the back gate line, which is beneficial to reducing the contact resistivity. In addition, the B element is not easy to diffuse into the tunneling oxide layer, which is beneficial to improving the passivation effect.

[0087] In some embodiments of the present invention, the temperature of the annealing treatment may be 880°C to 1050°C, and the temperature of the annealing treatment may be 880°C, 900°C, 950°C, 1000°C, 1050°C, etc. Annealing treatment at the above temperature is beneficial to activate the doping elements and improve the conductivity of the doping layer; it is beneficial to reduce defects in the film layer, release stress in the amorphous silicon material, and extend the life of minority carriers, thereby further improving the performance of the solar cell.

[0088] In some embodiments of the present invention, reference Figures 3 to 5 The thickness of the first doping layer 30 may be 5 nm to 150 nm, for example, the thickness of the first doping layer 30 may be 5 nm, 15 nm, 30 nm, 50 nm, 100 nm, 150 nm, etc. Therefore, the thickness of the first doping layer within the above range is helpful to reduce the recombination of carriers on the surface of the silicon substrate, thereby facilitating further improvement of the passivation effect.

[0089] In some embodiments of the present invention, the concentration of gallium in the first doping layer 30 may be 1×10 16 cm -3 ~1×10 21 cm -3 For example, the concentration of gallium in the first doping layer 30 may be 1×10 16 cm -3 , 1×10 17 cm -3 , 1×10 18 cm -3 , 1×10 19 cm -3 , 1×10 20 cm -3 , 1×10 21 cm -3 Etc., thus, the gallium element in the first doping layer has a suitable doping concentration, which is beneficial to further improve the passivation effect and reduce the contact resistivity.

[0090] In some embodiments of the present invention, reference Figures 3 to 5The thickness of the second doping layer 40 may be 5 nm to 150 nm, for example, the thickness of the second doping layer 40 may be 5 nm, 15 nm, 30 nm, 50 nm, 100 nm, 150 nm, etc. This is beneficial to further reduce the contact resistivity, thereby improving the open circuit voltage and fill factor of the solar cell.

[0091] In some embodiments of the present invention, the concentration of boron in the second doping layer may be 1×10 16 cm -3 ~1×10 21 cm -3 For example, the concentration of boron in the second doping layer 40 may be 1×10 16 cm -3 , 1×10 17 cm -3 , 1×10 18 cm -3 , 1×10 19 cm -3 , 1×10 20 cm -3 , 1×10 21 cm -3 Etc., thus, the boron element in the second doping layer has a suitable doping concentration, which is beneficial to further improve the passivation effect and reduce the contact resistivity.

[0092] In some embodiments of the present invention, multiple first doping layers and second doping layers can be formed. That is, after forming a group of first doping layers and second doping layers, one or more groups of first doping layers and second doping layers can be formed on the side of the first second doping layer away from the silicon substrate. Furthermore, an interface barrier layer can be formed between adjacent first doping layers and second doping layers to prevent the doping elements from diffusing across the interface barrier layer to the tunneling oxide layer.

[0093] In some embodiments of the present invention, the method for preparing a solar cell may further include the steps of forming a back passivation layer, a back grid line, a front n-type polysilicon layer, a front passivation layer, and a front grid line. The method for forming the above-mentioned film layer is not specifically limited in the present invention, and those skilled in the art may set and adjust it according to actual needs.

[0094] In general, the method proposed in the present invention has the following advantages for preparing solar cells: first, a first intrinsic amorphous silicon layer is formed on the side of the tunneling oxide layer away from the silicon substrate, and then a gallium-doped amorphous silicon layer is formed by adjusting the flow rate of the doping source, and then a second intrinsic amorphous silicon layer is formed, and then a boron-doped amorphous silicon layer is formed by adjusting the flow rate of the doping source, and a first doping layer and a second doping layer are formed by annealing, and the concentration of the doping elements in the first doping layer and the second doping layer along the direction of the first doping layer pointing to the silicon substrate shows a decreasing trend, so that both a better passivation effect and a lower contact resistivity can be obtained; multiple film layers can be prepared in the same PECVD device, and only the type and flow rate of the gas need to be adjusted; further, an interface barrier layer can be formed between the first doping layer and the second doping layer, at least to a certain extent, to prevent the B element from diffusing into the tunneling oxide layer, thereby further improving the passivation effect, reducing the contact resistivity, and preventing corrosion to the metal.

[0095] In another aspect of the present invention, the present invention provides a solar cell. In some embodiments of the present invention, the solar cell is prepared by the method described above. As a result, the solar cell has a good passivation effect and a low contact resistivity, which is beneficial to improving the open circuit voltage and fill factor of the battery.

[0096] In some embodiments of the present invention, the solar cell may be a TOPCon (Tunnel Oxide Passivating Contact) solar cell, that is, a tunnel oxide passivating contact solar cell.

[0097] In some other embodiments of the present invention, the solar cell may be a tBC cell (a cell formed by combining TOPCon and IBC technologies).

[0098] Of course, the solar cell in the present invention may also be other types of cells, and is not limited to TOPCon solar cells and tBC cells.

[0099] In some embodiments, reference Figure 3 and Figure 4 The solar cell includes a silicon substrate 10, a tunneling oxide layer 20, a first doping layer 30 and a second doping layer 40. The type, material and thickness of the silicon substrate 10, the tunneling oxide layer 20, the first doping layer 30 and the second doping layer 40 have been described in detail above and will not be repeated here.

[0100] In some embodiments, reference Figure 4 and Figure 5The solar cell includes a silicon substrate 10, a tunneling oxide layer 20, a first doping layer 30, an interface barrier layer 50, and a second doping layer 40. The material, thickness and other characteristics of the interface barrier layer have been described in detail above and will not be repeated here.

[0101] In some embodiments of the present invention, reference Figure 5 The solar cell may further include a first n-type passivation polysilicon layer 1, a second n-type passivation polysilicon layer 2, a first passivation anti-reflection layer 3, a second passivation anti-reflection layer 4, a front grid line 5, a third passivation anti-reflection layer 6, a fourth passivation anti-reflection layer 7 and a back grid line 8.

[0102] In some embodiments, the first n-type passivation polysilicon layer 1 is located on the front side 12 of the silicon substrate 10, the second n-type passivation polysilicon layer 2 is located on the side of the first n-type passivation polysilicon layer 1 away from the silicon substrate 10, and the front gate line 5 is located on the side of the second n-type passivation polysilicon layer 2 away from the silicon substrate 10. The first passivation anti-reflection layer 3 is located on the front side 12 of the silicon substrate 10, and the surface of the silicon substrate 10 in contact with the first passivation anti-reflection layer 3 may be a suede surface, and the second passivation anti-reflection layer 4 is located on the side of the first passivation anti-reflection layer 3 away from the silicon substrate 10. In some embodiments, the material of the first passivation anti-reflection layer 3 may be aluminum oxide, and the material of the second passivation anti-reflection layer 4 may be silicon nitride.

[0103] In some embodiments, the first n-type passivation polysilicon layer 1 and the second n-type passivation polysilicon layer 2 can be prepared by LPCVD (plasma enhanced chemical vapor deposition) process and annealed at 880-950° C. in a tubular annealing furnace. Afterwards, the PSG (phosphosilicate glass) outside the gate line area is removed by laser etching process, and the n-type polysilicon is etched by alkaline solution. Afterwards, the front side of the silicon substrate is textured to form a textured surface, and then an aluminum oxide passivation anti-reflection layer and a silicon nitride passivation anti-reflection layer are deposited.

[0104] In some embodiments of the present invention, reference Figure 5 The third passivation anti-reflection layer 6 is located on the side of the second doped layer 40 away from the silicon substrate 10, the fourth passivation anti-reflection layer 7 is located on the side of the third passivation anti-reflection layer 6 away from the silicon substrate 10, the back gate line 8 is in contact with the second doped layer 40, the third passivation anti-reflection layer 6 may be made of aluminum oxide, and the fourth passivation anti-reflection layer 7 may be made of silicon nitride. In some embodiments of the present invention, the third passivation anti-reflection layer and the fourth passivation anti-reflection layer are formed by a deposition process.

[0105] The material of the front grid line 5 and the back grid line 8 is not specifically limited in the present invention, and those skilled in the art can select and set it according to actual conditions. In some embodiments of the present invention, the front grid line 5 and the back grid line 8 can be metal electrodes, prepared by screen printing process, and then further improved by sintering annealing process.

[0106] The present invention will be described below by specific examples, and it will be appreciated by those skilled in the art that the following specific examples are only for illustrative purposes, and do not limit the scope of the present invention in any way. In addition, in the following examples, unless otherwise specified, the materials and equipment used are all commercially available. If in the following examples, specific processing conditions and processing methods are not clearly described, then conditions and methods known in the art can be used to process.

[0107] Example 1

[0108] (1) An n-type silicon wafer with a thickness of 130 μm was selected as the substrate, and the surface cutting damage layer was removed by an alkaline polishing process.

[0109] (2) Place the silicon wafer into a PECVD device to deposit a tunneling oxide layer, an intrinsic amorphous silicon layer, a doped amorphous silicon layer, and an interface barrier layer.

[0110] N2O is used as a reaction gas and Ar is used as a diluent gas to prepare an interface tunneling oxide layer 20. In an argon atmosphere, silane, trimethyl gallium and hydrogen are used as reaction gases. The initial 10 nm is the first intrinsic amorphous silicon layer, the flow rate of trimethyl gallium is 0 sccm, the flow rate of silane is 3200 sccm, and the flow rate of H2 is 9000 sccm; about 10-30 nm is the first doped amorphous silicon layer, the flow rate of silane is 3200 sccm, the flow rate of H2 is 9000 sccm, and the flow rate of trimethyl gallium is 150 sccm; 30-80 nm is the second doped amorphous silicon layer, the flow rate of silane is 3200 sccm, the flow rate of H2 is 9000 sccm, and the flow rate of trimethyl gallium is 600 sccm.

[0111] Continue to use N2O as the reaction gas and Ar as the dilution gas to prepare a 1nm interface silicon oxide barrier layer in an argon atmosphere, using silane, trimethyl boron and hydrogen as reaction gases. The initial 10nm based on the interface silicon oxide barrier layer is the second intrinsic amorphous silicon layer, the silane flow rate is 3200sccm, the H2 flow rate is 9000sccm, and the trimethyl boron flow rate is 0sccm; 10-50nm is the third doped amorphous silicon layer, the silane flow rate is 3200sccm, the H2 flow rate is 9000sccm, and the trimethyl boron flow rate is 150sccm; 50-80nm is the fourth doped amorphous silicon layer, the silane flow rate is 3200sccm, the H2 flow rate is 9000sccm, and the trimethyl boron flow rate is 600sccm.

[0112] (3) Then, the tube is placed in a tubular annealing furnace for annealing at 880-1050°C and subsequent H passivation treatment.

[0113] After annealing, the first intrinsic amorphous silicon layer, the first doped amorphous silicon layer and the second doped amorphous silicon layer form a first doped layer, the second intrinsic amorphous silicon layer, the third doped amorphous silicon layer and the fourth doped amorphous silicon layer form a second doped layer, and in the direction from the first doped layer to the silicon wafer, the concentration of gallium in the first doped layer shows a decreasing trend, and the concentration of boron in the second doped layer shows a decreasing trend, that is, the doping concentration of the activated B element is the highest at the surface of the second doped layer, and the doping concentration on the side close to the silicon wafer is relatively small, the interface silicon oxide barrier layer can block the boron element from diffusing to the tunneling oxide layer, and the boron element basically does not diffuse to the tunneling oxide layer, while the gallium element diffuses to the tunneling oxide layer and then enters the silicon body region.

[0114] In the first doping layer, the maximum gallium doping concentration is about 8×10 19 cm -3 -12×10 19 cm -3 , the doping concentration of gallium gradually decreases along the direction close to the silicon wafer, and part of the gallium element can diffuse into the tunnel oxide layer. The doping concentration of gallium at the interface of the tunnel oxide layer is about 1×10 19 cm -3 -5×10 19 cm -3 .

[0115] In the second doping layer, the maximum boron doping concentration is about 5×10 19 cm -3 -11×10 19 cm -3 , the boron doping concentration gradually decreases along the direction close to the silicon wafer, and after passing through the interface barrier layer, the boron doping concentration is reduced to 2×10 19 cm -3 -4×10 19 cm -3 , but avoid diffusing to the interface of the tunnel oxide layer, where the doping concentration of boron is less than 1×10 17 cm -3 Too much B element will destroy the passivation effect of the tunneling oxide layer.

[0116] It should be noted that, in Example 1, the doping concentration of the boron element in the tunnel oxide layer is much lower than the doping concentration of the boron element in the second doping layer.

[0117] (4) A back gate line is formed, wherein the back gate line is in contact with the second doped layer.

[0118] Comparative Example 1

[0119] The difference between Comparative Example 1 and Example 1 is that after the second doped amorphous silicon layer is formed, subsequent annealing treatment and other steps are directly performed.

[0120] Comparative Example 2

[0121] The difference between Comparative Example 2 and Example 1 is that after the tunneling oxide layer is formed, the second intrinsic amorphous silicon layer, the third doped amorphous silicon layer and the fourth doped amorphous silicon layer are directly prepared, and then subsequent annealing treatment and other steps are performed.

[0122] The products prepared in Example 1, Comparative Example 1 and Comparative Example 2 were tested, including a passivation test and a contact resistivity test. The test results are recorded in Table 1.

[0123] Table 1

[0124] Passivation(μs) <![CDATA[Contact resistivity (mΩ·cm 2 )]]> Example 1 1200 1.8 Comparative Example 1 1200 30 Comparative Example 2 1000 1.5

[0125] In Comparative Example 1, only a gallium-doped doped layer is formed, and the contact resistivity is relatively high; in Comparative Example 2, only a boron-doped doped layer is formed, and after annealing, boron diffuses into the tunneling oxide layer, significantly reducing the passivation effect of the tunneling oxide layer; in Example 1, a solar cell is prepared according to the method proposed in the present invention, and the interface barrier layer, the first intrinsic amorphous silicon layer, and the gallium-doped amorphous silicon layer can prevent the boron element from diffusing into the tunneling oxide layer, and the passivation effect is better, and the doping concentration of the boron element in the area in contact with the back gate line is higher, and the contact resistivity is lower.

[0126] In the description of the present invention, the orientation or position relationship indicated by the terms "front" and "back" is based on the orientation or position relationship shown in the drawings and is only for the convenience of describing the present invention rather than requiring the present invention to be constructed and operated in a specific orientation. Therefore, it should not be understood as a limitation on the present invention.

[0127] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "some specific embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment are included in at least one embodiment of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples, unless they are contradictory. In addition, it should be noted that in this specification, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated.

[0128] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present invention.

Claims

1. A method for preparing a solar cell, characterized in that: include: forming a tunneling oxide layer on a back side of the silicon substrate; Forming a first intrinsic amorphous silicon layer on a side of the tunnel oxide layer away from the silicon substrate, wherein the reaction gas for forming the first intrinsic amorphous silicon layer includes a first silicon source and hydrogen; forming a first doped amorphous silicon layer on a side of the first intrinsic amorphous silicon layer away from the silicon substrate, wherein the reaction gas for forming the first doped amorphous silicon layer comprises the first silicon source, a first doping source and hydrogen, wherein the first doping source contains gallium element, and the flow rate of the first doping source is a; forming a second doped amorphous silicon layer on a side of the first doped amorphous silicon layer away from the silicon substrate, wherein the reaction gas for forming the second doped amorphous silicon layer includes the first silicon source, the first doping source and hydrogen, wherein the flow rate of the first doping source is b, b>a; forming a second intrinsic amorphous silicon layer on a side of the second doped amorphous silicon layer away from the silicon substrate, wherein the reaction gas for forming the second intrinsic amorphous silicon layer includes a second silicon source and hydrogen; forming a third doped amorphous silicon layer on a side of the second intrinsic amorphous silicon layer away from the silicon substrate, wherein the reaction gas for forming the third doped amorphous silicon layer comprises the second silicon source, a second doping source and hydrogen, wherein the second doping source contains boron element, and the flow rate of the second doping source is c; forming a fourth doped amorphous silicon layer on a side of the third doped amorphous silicon layer away from the silicon substrate, wherein the reaction gas for forming the fourth doped amorphous silicon layer includes the second silicon source, the second doping source and hydrogen, wherein the flow rate of the second doping source is d, d>c; The silicon substrate is annealed so that the first intrinsic amorphous silicon layer, the first doped amorphous silicon layer and the second doped amorphous silicon layer form a first doped layer, and the second intrinsic amorphous silicon layer, the third doped amorphous silicon layer and the fourth doped amorphous silicon layer form a second doped layer, and in a direction from the first doped layer to the silicon substrate, the concentration of gallium in the first doped layer shows a decreasing trend; and the concentration of boron in the second doped layer shows a decreasing trend.

2. The method according to claim 1, characterized in that: 50sccm≤a≤300sccm, 100sccm≤b≤800sccm; And / or, 50 sccm≤c≤300 sccm, 100 sccm≤d≤800 sccm.

3. The method according to claim 1, characterized in that At least one of the following conditions is met: The first doping source includes trimethylgallium; The second doping source includes trimethyl boron; The first silicon source includes silane; The second silicon source includes silane.

4. The method according to claim 1, characterized in that At least one of the following conditions is met: The temperature for forming the first intrinsic amorphous silicon layer, the temperature for forming the first doped amorphous silicon layer, and the temperature for forming the second doped amorphous silicon layer are each independently 200° C. to 500° C.; In the process of forming the first intrinsic amorphous silicon layer, the flow rate of the first silicon source is 2000 sccm to 4000 sccm, and the flow rate of hydrogen is 8000 sccm to 12000 sccm; In the process of forming the first doped amorphous silicon layer, the flow rate of the first silicon source is 2000 sccm to 4000 sccm, and the flow rate of hydrogen is 8000 sccm to 12000 sccm; In the process of forming the second doped amorphous silicon, the flow rate of the first silicon source is 2000 sccm to 4000 sccm, and the flow rate of hydrogen is 8000 sccm to 12000 sccm; The temperature for forming the second intrinsic amorphous silicon layer, the temperature for forming the third doped amorphous silicon layer and the temperature for forming the fourth doped amorphous silicon layer are each independently 200° C. to 500° C.; During the formation of the second intrinsic amorphous silicon layer, the flow rate of the second silicon source is 2000 sccm to 4000 sccm, and the flow rate of hydrogen is 8000 sccm to 12000 sccm; In the process of forming the third doped amorphous silicon layer, the flow rate of the second silicon source is 2000 sccm to 4000 sccm, and the flow rate of hydrogen is 8000 sccm to 12000 sccm; In the process of forming the fourth doped amorphous silicon, the flow rate of the second silicon source is 2000 sccm to 4000 sccm, and the flow rate of hydrogen is 8000 sccm to 12000 sccm.

5. The method according to claim 1, characterized in that At least one of the following conditions is met: The ratio of the thickness of the first intrinsic amorphous silicon layer, the thickness of the first doped amorphous silicon layer, and the thickness of the second doped amorphous silicon layer is 1:(1-4):(2-5); The thickness of the first doping layer is 5nm to 150nm; The ratio of the thickness of the second intrinsic amorphous silicon layer, the thickness of the third doped amorphous silicon layer, and the thickness of the fourth doped amorphous silicon layer is 1:(1-4):(2-5); The thickness of the second doping layer is 5 nm to 150 nm.

6. The method according to claim 1, characterized in that The concentration of gallium in the first doping layer is 1×10 16 cm -3 ~1×10 21 cm -3 ; And / or, the concentration of boron in the second doping layer is 1×10 16 cm -3 ~1×10 21 cm -3 .

7. The method according to claim 1, characterized in that Before forming the second intrinsic amorphous silicon layer, an interface barrier layer is formed on a side of the second doped amorphous silicon layer away from the silicon substrate, wherein the material of the interface barrier layer includes at least one of silicon oxide, aluminum oxide and nitrogen-doped silicon oxide.

8. The method according to claim 7, characterized in that The thickness of the interface barrier layer is 0.5nm-3nm.

9. The method according to any one of claims 1 to 8, characterized in that: At least one of the following conditions is met: The material of the tunnel oxide layer includes at least one of silicon oxide, aluminum oxide and nitrogen-doped silicon oxide; The thickness of the tunnel oxide layer is 0.5nm-3nm; The temperature of the annealing treatment is 880°C to 1050°C.

10. A solar cell, characterized in that: The solar cell is prepared by the method according to any one of claims 1 to 9.

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