Back contact battery, photovoltaic module and manufacturing method of back contact battery

Abstract

The invention discloses a back contact battery, a photovoltaic module and a manufacturing method of the back contact battery, relates to the technical field of back contact batteries, and aims to solve the problems of relatively large defect hidden danger and relatively high electric leakage risk between an N-type doping layer and a P-type doping layer. According to the back contact battery, a first surface of a semiconductor substrate comprises a first area, a second area and a third area located between the first area and the second area. The first doped semiconductor layer is arranged in the first region, and the second doped semiconductor layer opposite to the first doped semiconductor layer in conductive type is arranged in the second region. The resistivity of the surface layer of at least part of the surface of the semiconductor substrate in the third region is greater than 20ohm. Cm; h1 + H2 + W is greater than or equal to 4 [mu] m and less than or equal to 300 [mu] m; h1 is the height difference between the bottom surface of the third region and the surface of the first region, H2 is the height difference between the bottom surface of the third region and the surface of the second region, and W is the width of the third region.

Description

Technical Field

[0001] The present invention relates to the technical field of back-contact cells, and in particular to a back-contact cell, a photovoltaic module and a method for manufacturing the back-contact cell. Background Art

[0002] Back-contact cells refer to solar cells with emitter and metal contact on the back of the cell, and no metal electrode blocking the front. Compared with solar cells with blocking on the front, back-contact cells have higher short-circuit current and photoelectric conversion efficiency, and are one of the current technical directions for achieving high-efficiency crystalline silicon cells.

[0003] In the prior art, the back contact battery has an N-type doping layer and a P-type doping layer, and there are great hidden dangers of defects between the N-type doping layer and the P-type doping layer, and the risk of leakage is high. Summary of the invention

[0004] The object of the present invention is to provide a back-contact cell, a photovoltaic module and a method for manufacturing a back-contact cell, so as to reduce the risk of electric leakage and reduce safety hazards.

[0005] In order to achieve the above-mentioned objectives, in a first aspect, the present invention provides a back-contact battery. The back-contact battery comprises: a semiconductor substrate. The semiconductor substrate comprises a first surface and a second surface opposite to each other, the first surface comprising a first region, a second region and a third region located between the first region and the second region. The first doped semiconductor layer is disposed in the first region, the second doped semiconductor layer is disposed in the second region, and the first doped semiconductor layer and the second doped semiconductor layer have opposite conductivity types. The resistivity of the surface layer of at least part of the surface of the semiconductor substrate located in the third region is greater than 20 ohm·cm; and H1+H2+W is greater than or equal to 4μm and less than or equal to 300μm; wherein H1 is the height difference between the bottom surface of the third region and the surface of the first region, H2 is the height difference between the bottom surface of the third region and the surface of the second region, and W is the width of the third region.

[0006] Compared with the prior art, in the back contact cell provided by the present invention, the resistivity of the surface layer of at least part of the surface of the semiconductor substrate located in the third region is greater than 20 ohm·cm, and the shortest surface distance L (i.e., H1+H2+W) between the first region and the second region is greater than or equal to 4 μm and less than or equal to 300 μm, which can reduce the risk of leakage between the first doped semiconductor layer on the first region and the second doped semiconductor layer in the second region, reduce safety hazards and improve the photoelectric conversion efficiency of the back contact cell. The resistivity of the surface layer of the third region is set in a larger range, which can inhibit the lateral movement of carriers at the surface of the third region and reduce the carrier concentration at the surface, thereby ensuring the risk of leakage between the first doped semiconductor layer and the second doped semiconductor layer. On this basis, the shortest surface distance L between the first region and the second region is greater than or equal to 4 μm and less than or equal to 300 μm, which can increase the proportion of the first region and the second region, thereby increasing the proportion of the first doped semiconductor layer located in the first region and the second doped semiconductor layer located in the second region, and further improving the photoelectric conversion efficiency of the back contact cell. Furthermore, since the resistivity of the surface layer in the semiconductor substrate corresponding to the third region is high, it is greatly affected by the electric field of the first doped semiconductor layer or the second doped semiconductor layer, and the relative electric field strength is high, the photogenerated carriers generated near the surface of the third region can be effectively separated. Therefore, although the high resistivity of the surface of the third region affects the transmission of carriers, its additional advantage enables the battery efficiency to be improved, especially when the overall width of the third region is small. The carriers generated by the semiconductor substrate in the third region are basically transmitted in the first doped semiconductor layer and the second doped semiconductor layer. Based on this, in the present invention, the shortest surface distance L between the first region and the second region is less than or equal to 300μm, so as to ensure that the carriers generated by the semiconductor substrate in the third region can be effectively collected by the first doped semiconductor layer and the second doped semiconductor layer, thereby ensuring the conversion efficiency of the back contact battery. On the other hand, although the surface layer of the third region has a high resistivity, if the surface distance L between the first region and the second region is set too small, there will be a large risk of leakage and unpredictable risks caused by process fluctuations, so the matching shortest surface distance L is greater than or equal to 4μm.

[0007] In one implementation, along the direction from the first region to the second region, the surface of the first region, the surface of the second region and the surface of the third region are approximately located in the same plane; H1 is approximately 0, H2 is approximately 0, and 4μm≤W≤300μm.

[0008] In one implementation, along a direction from the second surface to the first surface, a surface of the first region is higher than a bottom surface of the third region.

[0009] In the case of adopting the above technical solution, compared with the surface of the first region, the surface of the second region and the surface of the third region being located in the same plane, since the surface of the first region is higher than the bottom surface of the third region, there is a height difference H1 between the surface of the first region and the bottom surface of the third region. At this time, the shortest surface distance L between the first region and the second region (i.e., H1+H2+W) is greater than the width W of the third region. Therefore, while ensuring that the shortest surface distance L between the first region and the second region is constant, the width W of the third region can be reduced. At this time, on the basis of ensuring the isolation of the first doped semiconductor layer and the second doped semiconductor layer, the proportion of the first region and the second region can be further increased, thereby further increasing the proportion of the first doped semiconductor layer located in the first region and the second doped semiconductor layer located in the second region, and further improving the photoelectric conversion efficiency of the back contact battery.

[0010] In one implementation, 0 μm

[0011] In one implementation, along the direction from the second surface to the first surface, the surface of the second region is higher than the bottom surface of the third region.

[0012] In the case of adopting the above technical solution, compared with the surface of the first region, the surface of the second region and the surface of the third region being located in the same plane, when the shortest surface distance L between the first region and the second region is constant, the width W of the third region can be further reduced. At this time, on the basis of ensuring the isolation of the first doped semiconductor layer and the second doped semiconductor layer, the proportion of the first region and the second region can be further increased, thereby further increasing the proportion of the first doped semiconductor layer located in the first region and the second doped semiconductor layer located in the second region, thereby further improving the photoelectric conversion efficiency of the back contact cell.

[0013] In one implementation, 0 μm<H2≤20 μm.

[0014] In one implementation, the semiconductor substrate in the third region further includes: a first sidewall, the first sidewall is connected to the bottom surface and the surface of the first region respectively. The first sidewall includes a surface inclined relative to the first surface; or the first sidewall is perpendicular to the first surface.

[0015] In one implementation, the semiconductor substrate in the third region further includes: a second sidewall, the second sidewall is connected to the bottom surface and the surface of the second region respectively. The second sidewall includes a surface inclined relative to the first surface; or the second sidewall is perpendicular to the first surface.

[0016] In one implementation, when both the first side wall and the second side wall include surfaces inclined relative to the first surface, a horizontal distance between the first side wall and the second side wall gradually decreases along a direction from the first surface to the second surface.​

[0017] Combined with the previous description, it is beneficial for the film layer to be better coated on the first side wall and the second side wall when a film layer is formed on the surface of the third region later, thereby preventing unfilled gaps in the film layer at the boundary between the first region and the third region or the second region and the third region, reducing the number of defects on the first side of the back-contact battery, and improving the formation quality of the film layer at the above-mentioned boundary.

[0018] In one implementation, when the back contact battery includes the first region, the third region, the second region and the third region in sequence, the width of the back contact battery is greater than or equal to 500 μm and less than or equal to 2000 μm; the ratio of the width of all third regions to the width of the back contact battery is less than or equal to 0.2%; the width direction of the back contact battery and the width direction of the third region are consistent with the direction from the first region to the second region.

[0019] In the case of adopting the above technical solution, since the ratio of the width of the third region to the width of the back contact battery is less than or equal to 0.2%, the ratio of the sum of the width of the first region and the width of the second region to the width of the back contact battery is greater than or equal to 99.8%. It can be seen that the total proportion of the first region and the second region is larger than that of the third region, so the total proportion of the first doped semiconductor layer located in the first region and the second doped semiconductor layer located in the second region is large. At this time, the amount of carriers collected by the back contact battery can be increased, thereby improving the photoelectric conversion efficiency of the back contact battery.

[0020] In one implementation, the back contact battery further includes a first electrode and a second electrode, the first electrode is electrically connected to the first doped semiconductor layer, and the second electrode is electrically connected to the second doped semiconductor layer. The first electrode includes a contact portion that is in direct contact with the first doped semiconductor layer and a main portion that is away from the first doped semiconductor layer, and the second electrode includes a contact portion that is in direct contact with the second doped semiconductor layer and a main portion that is away from the second doped semiconductor layer. The spacing L1 between the contact portion of the first electrode and the third region is greater than or equal to 80 μm and less than or equal to 500 μm, and the direction of the spacing L1 is consistent with the direction from the first region to the second region. And / or, the spacing L2 between the contact portion of the second electrode and the third region is greater than or equal to 80 μm and less than or equal to 500 μm, and the direction of the spacing L2 is consistent with the direction from the first region to the second region.

[0021] When the above technical solution is adopted, the above L1 and L2 are within the above value range, which can not only ensure the firmness of the connection between the first electrode and the first doped semiconductor layer (or the second electrode and the second doped semiconductor layer), but also improve the bonding force between the electrode and the doped semiconductor layer. At the same time, compared with the case where the spacing is less than 80 μm, the current transmission efficiency can be improved, thereby improving the conversion efficiency of the back contact battery.

[0022] In one implementation, the ratio of the width of the first doped semiconductor layer to the spacing L1 is greater than or equal to 2, and the direction of the width of the first doped semiconductor layer is consistent with the direction from the first region to the second region; and / or the ratio of the width of the second doped semiconductor layer to the spacing L2 is greater than or equal to 2, and the direction of the width of the second doped semiconductor layer is consistent with the direction from the first region to the second region.

[0023] In one implementation, the spacing between the main portion of the first electrode and the third region is L3, L3≤L1; the direction of the spacing L3 is consistent with the direction from the first region to the second region; and / or, the spacing between the main portion of the second electrode and the third region is L4, L4≤L2; the direction of the spacing L4 is consistent with the direction from the first region to the second region.

[0024] In one implementation, a ratio of a width W of the third region to a width of the first doped semiconductor layer is less than or equal to 35%; and / or a ratio of a width W of the third region to a width of the second doped semiconductor layer is less than or equal to 35%.

[0025] When the above technical solution is adopted, on the basis of ensuring the isolation of the first doped semiconductor layer and the second doped semiconductor layer, the proportion of the first region and the second region can be increased, thereby increasing the proportion of the first doped semiconductor layer located in the first region and the second doped semiconductor layer located in the second region, thereby improving the photoelectric conversion efficiency of the back contact battery.

[0026] In an implementation manner, a ratio of an area of ​​the semiconductor substrate located in the third region to an area of ​​the first surface is less than or equal to 20%.

[0027] When the above technical solution is adopted, on the basis of ensuring the isolation of the first doped semiconductor layer and the second doped semiconductor layer, the proportion of the first region and the second region can be increased, thereby increasing the proportion of the first doped semiconductor layer located in the first region and the second doped semiconductor layer located in the second region, thereby improving the photoelectric conversion efficiency of the back contact battery.

[0028] In one implementation, the resistivity of the surface layer of at least a portion of the surface of the semiconductor substrate located in the third region is greater than 80 ohm·cm; and / or the doping concentration of the IIIA group doping element and the doping concentration of the VA group doping element in the semiconductor substrate located in the third region are both less than 1E14 / cm -3 .

[0029] In one implementation, within a depth range of 20 nm, the doping concentration of the doping element in the semiconductor substrate located in the third region is A; within a depth range of 2000 nm, the doping concentration of the doping element in the semiconductor substrate located in the third region is B;

[0030] In one implementation, the back contact cell further includes a first interface passivation layer; the first interface passivation layer is disposed between the semiconductor substrate and the first doped semiconductor layer.

[0031] When the above technical solution is adopted, the passivation contact structure composed of the first interface passivation layer and the first doped semiconductor layer has an excellent interface passivation effect, and can realize the selective collection of carriers, at least reduce the carrier recombination rate in the first area of ​​the first surface, and further improve the photoelectric conversion efficiency of the back contact battery.

[0032] In one implementation, the back contact cell further includes a second interface passivation layer, and the second interface passivation layer is disposed between the second doped semiconductor layer and the semiconductor substrate.

[0033] When the above technical solution is adopted, the passivation contact structure composed of the second interface passivation layer and the second doped semiconductor layer has an excellent interface passivation effect, and can realize the selective collection of carriers, at least reduce the carrier recombination rate in the second area of ​​the first surface, and further improve the photoelectric conversion efficiency of the back contact battery.

[0034] In a second aspect, the present invention further provides a photovoltaic module. The photovoltaic module comprises a battery string and an encapsulation layer. The battery string is formed by connecting a plurality of back-contact batteries as described in the above technical solution, and the encapsulation layer is used to cover the surface of the battery string.

[0035] The beneficial effects of the second aspect of the present invention and its various implementations can be analyzed by referring to the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0036] In a third aspect, the present invention further provides a method for manufacturing a back-contact battery. The method for manufacturing a back-contact battery comprises:

[0037] A semiconductor substrate is provided; the semiconductor substrate comprises a first surface and a second surface opposite to each other; the first surface comprises a first region, a second region and a third region located between the first region and the second region;

[0038] forming a first doped semiconductor layer disposed in the first region;

[0039] forming a second doped semiconductor layer disposed in the second region; the first doped semiconductor layer and the second doped semiconductor layer have opposite conductivity types;

[0040] The resistivity of the surface layer of at least a portion of the surface of the semiconductor substrate located in the third region is greater than 20 ohm·cm;

[0041] Furthermore, H1+H2+W is greater than or equal to 4 μm and less than or equal to 300 μm; wherein H1 is the height difference between the bottom surface of the third region and the surface of the first region, H2 is the height difference between the bottom surface of the third region and the surface of the second region, and W is the width of the third region.

[0042] The beneficial effects of the third aspect of the present invention and its various implementations can be analyzed by referring to the beneficial effects of the first aspect and its various implementations, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0044] Figure 1 This is a schematic structural diagram of a first back-contact battery in an embodiment of the present invention;

[0045] Figure 2 Schematic diagram of the structure of a second back contact battery in an embodiment of the present invention;

[0046] Figure 3 Schematic diagram of the structure of a third back contact battery in an embodiment of the present invention;

[0047] Figure 4 Schematic diagram of the structure of a fourth back-contact battery in an embodiment of the present invention;

[0048] Figure 5 Schematic diagram of the distribution of the first electrode and the second electrode in the back contact battery in an embodiment of the present invention;

[0049] Figure 6 Schematic diagram of the structure of the fifth back contact battery in an embodiment of the present invention;

[0050] Figure 7 In the embodiment of the present invention Figure 6 A schematic diagram of the structure of a partial area;

[0051] Figure 8 Schematic diagram of the structure of the sixth back contact battery in an embodiment of the present invention.

[0052] Reference numerals:

[0053] 1-semiconductor substrate, 10-first region, 11-second region, 12-third region, 13-bottom surface, 14-first side wall, 15-second side wall; 2-first doped semiconductor layer, 3-second doped semiconductor layer, 4-first interface passivation layer, 5-second interface passivation layer, 6-first electrode, 60-contact portion of the first electrode, 61-main body of the first electrode; 7-second electrode, 70-contact portion of the second electrode, 71-main body of the second electrode; 8-surface passivation layer. DETAILED DESCRIPTION

[0054] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0055] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0056] In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined. The meaning of "several" is one or more, unless otherwise clearly and specifically defined. In the description of the present invention, it should be understood that the orientation or positional relationship indicated by the terms "upper", "lower", "front", "back", "left", "right", etc. is based on the orientation or positional relationship shown in the accompanying drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0057] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0058] In current silicon solar cells, the substrate usually uses a silicon wafer with an N-type or P-type doped substrate. P-type and N-type doped layers are formed at different positions of the silicon wafer, and then electrodes are formed on the regions of the P-type and N-type doped layers.

[0059] When light enters the substrate, electron-hole pairs are generated. The free electron-hole pairs are separated by carriers, so that electrons gather near the N pole and holes gather near the P pole. When the electrodes are connected to an external circuit, current can be output.

[0060] BC cells, also known as back-contact cells, have positive and negative electrodes on one side of the cell, which can effectively reduce the shading area of ​​the main incident surface and improve the light utilization rate of solar cells. In the prior art, back-contact cells have N-type doping layers and P-type doping layers, and there are large defects and hidden dangers between the N-type doping layers and the P-type doping layers, resulting in a high risk of leakage.

[0061] In order to solve the above technical problems, in the first aspect, an embodiment of the present invention provides a back contact battery. Figures 1 to 4 The back contact cell comprises: a semiconductor substrate 1. The semiconductor substrate 1 comprises a first surface and a second surface opposite to each other, the first surface comprises a first region 10, a second region 11 and a third region 12 located between the first region 10 and the second region 11. A first doped semiconductor layer 2 is arranged in the first region 10, and a second doped semiconductor layer 3 is arranged in the second region 11, and the first doped semiconductor layer 2 and the second doped semiconductor layer 3 have opposite conductivity types.

[0062] The resistivity of the surface layer of at least a portion of the surface of the semiconductor substrate located in the third region is greater than 20 ohm·cm; illustratively, the resistivity of the surface layer of at least a portion of the surface of the semiconductor substrate located in the third region may be 20 ohm·cm, 21 ohm·cm, 25 ohm·cm, 30 ohm·cm, 32 ohm·cm, 35 ohm·cm, 40 ohm·cm, 45 ohm·cm, 50 ohm·cm, 55 ohm·cm, 60 ohm·cm, 65 ohm·cm, 70 ohm·cm, 75 ohm·cm, 80 ohm·cm, 85 ohm·cm, 90 ohm·cm, 95 ohm·cm, 100 ohm·cm, 105 ohm·cm, 110 ohm·cm, 115 ohm·cm, 120 19 0ohm·cm, 200ohm·cm, 250ohm·cm, 300ohm·cm, 350ohm·cm, 400ohm·cm, 450ohm·cm, 500ohm·cm, 550ohm·cm, 600ohm·cm, 700ohm·cm, 800ohm·cm, 900ohm·cm, 1000ohm·cm, etc. Preferably, the resistivity of the surface layer of at least a portion of the surface of the semiconductor substrate located in the third region is greater than 80 ohm·cm. More preferably, the resistivity of the surface layer of at least a portion of the surface of the semiconductor substrate located in the third region is greater than 200 ohm·cm. The resistivity of the surface layer in the present invention refers to the body resistivity within a certain thickness range of the surface, such as a thickness range of 1 micron, a thickness range of 1 millimeter, a thickness range of 1 centimeter, etc.

[0063] See also Figures 1 to 4, the semiconductor substrate 1 located in the third region 12 is located between the first doped semiconductor layer 2 in the first region 10 and the second doped semiconductor layer 3 in the second region 11. The shortest surface distance L between the first region 10 and the second region 11 can be regarded as the shortest distance from the first region 10 along the surface of the third region 12 to the second region 11. In the present application, the shortest surface distance L between the first region 10 and the second region 11 is greater than or equal to 4μm and less than or equal to 300μm. Exemplarily, the shortest surface distance L between the first region 10 and the second region 11 can be 4μm, 10μm, 50μm, 100μm, 120μm, 150μm, 180μm, 200μm, 230μm, 250μm, 280μm or 300μm, etc. Preferably, the shortest surface distance L between the first region 10 and the second region 11 is greater than or equal to 30 μm and less than or equal to 200 μm. For example, the shortest surface distance L between the first region 10 and the second region 11 may be 30 μm, 40 μm, 50 μm, 100 μm, 120 μm, 150 μm, 180 μm or 200 μm, etc. In the embodiment of the present invention, the shortest surface distance L between the first region 10 and the second region 11 is 150 μm. At the same time, in the back-contact battery provided by the embodiment of the present invention, the resistivity of the surface layer of at least part of the surface of the semiconductor substrate 1 located in the third region 12 is greater than 20 ohm·cm. The resistivity of the surface layer of at least part of the surface of the third region 12 of the semiconductor substrate 1 in the embodiment of the present invention is greater than 20 ohm·cm. Combined with the shortest surface distance L between the first region 10 and the second region 11 being greater than or equal to 4 μm and less than or equal to 300 μm, the leakage risk between the first doped semiconductor layer 2 on the first region 10 and the second doped semiconductor layer 3 in the second region 11 can be reduced, thereby reducing safety hazards and improving the photoelectric conversion efficiency of the back-contact battery. The resistivity of the surface layer of the third region is set in a larger range, which can suppress the lateral movement of carriers at the surface of the third region and reduce the carrier concentration at the surface, thereby ensuring the leakage risk between the first doped semiconductor layer and the second doped semiconductor layer. On this basis, the shortest surface distance L between the first region 10 and the second region 11 is greater than or equal to 4μm and less than or equal to 300μm, which can increase the proportion of the first region 10 and the second region 11, thereby increasing the proportion of the first doped semiconductor layer 2 located in the first region 10 and the second doped semiconductor layer 3 located in the second region 11, thereby improving the photoelectric conversion efficiency of the back contact battery.Furthermore, since the resistivity of the surface layer in the semiconductor substrate 1 corresponding to the third region 12 is high, it is greatly affected by the electric field of the first doped semiconductor layer or the second doped semiconductor layer, and the relative electric field strength is high, the photogenerated carriers generated near the surface of the third region can be effectively separated. Therefore, although the high resistivity of the surface of the third region affects the transmission of carriers, its additional advantage enables the battery efficiency to be improved, especially when the overall width of the third region is small. The carriers generated by the semiconductor substrate 1 in the third region 12 are basically transmitted in the first doped semiconductor layer 2 and the second doped semiconductor layer 3. Based on this, in the present invention, the shortest surface distance L between the first region 10 and the second region 11 is less than or equal to 300 μm, so as to ensure that the carriers generated by the semiconductor substrate 1 in the third region 12 can be effectively collected by the first doped semiconductor layer 2 and the second doped semiconductor layer 3, thereby ensuring the conversion efficiency of the back contact battery. On the other hand, although the surface of the third region has a high resistivity, if the surface distance L between the first region 10 and the second region 11 is set too small, there will be a large risk of leakage and unpredictable risks caused by process fluctuations, so the matching shortest surface distance L is greater than or equal to 4 μm.

[0064] In the actual application process, the embodiment of the present invention does not specifically limit the structure and material of the semiconductor substrate, as long as it can be applied to the back contact battery provided by the embodiment of the present invention. Exemplarily, the above-mentioned semiconductor substrate can be a P-type doped semiconductor substrate or an N-type doped semiconductor substrate or a semiconductor substrate close to the intrinsic conductivity type. The crystal type of the semiconductor substrate can be single crystal or polycrystalline, etc.

[0065] Specifically, the semiconductor substrate may be a semiconductor substrate on which no structure is formed. Alternatively, the semiconductor substrate may also be a semiconductor substrate on which some structures are formed; in this case, the structure formed on the semiconductor substrate may be arranged according to actual needs, and is not specifically limited here. For example: the semiconductor substrate may include a semiconductor substrate, and a passivation anti-reflection layer arranged on the side of the semiconductor substrate away from the first doped semiconductor layer and the second doped semiconductor layer, so as to passivate the side of the semiconductor substrate away from the first doped semiconductor layer and the second doped semiconductor layer, reduce the carrier recombination rate on this side, and facilitate more light to be refracted into the semiconductor substrate through this side, thereby further improving the working efficiency of the back contact battery. Among them, the material of the semiconductor substrate may include any semiconductor material such as silicon, silicon germanium, germanium or gallium arsenide. The material of the passivation anti-reflection layer may include silicon oxide, silicon nitride or aluminum oxide, etc.

[0066] In addition, the first surface of the semiconductor substrate corresponds to the backlight surface of the back contact battery, and the second surface of the semiconductor substrate corresponds to the light-receiving surface of the back contact battery. The distribution of the first region, the second region, and the third region of the semiconductor substrate on the first surface can be determined based on the distribution of the first doped semiconductor layer and the second doped semiconductor layer on the first surface. Specifically, since the first doped semiconductor layer included in the back contact battery is arranged on the first region, the distribution range of the first region on the first surface can be determined based on the distribution requirements of the first doped semiconductor layer in the actual application scenario. Since the second doped semiconductor layer included in the back contact battery is arranged on the second region of the first surface, the distribution range of the second region on the first surface can be determined based on the distribution requirements of the second doped semiconductor layer on the semiconductor substrate in the actual application scenario.

[0067] Furthermore, the light-receiving surface of the semiconductor substrate can be a plane, or the light-receiving surface of the semiconductor substrate can also be a velvet surface. Among them, because the velvet surface has a light-trapping effect, when the light-receiving surface of the semiconductor substrate is a velvet surface, the reflectivity of the light-receiving surface can be reduced, which is conducive to more light being refracted from the light-receiving surface into the semiconductor substrate and absorbed and utilized by the semiconductor substrate, which is conducive to improving the photoelectric conversion efficiency of the back-contact battery. When the backlight surface is a polished surface, the light incident from the light-receiving surface to the surface of the solar cell and passing through the solar cell can be better re-reflected, so that the light has the opportunity to be reused by the solar cell, thereby improving the conversion efficiency of the solar cell. In addition, since the polished surface has better flatness, when preparing other film layers on the semiconductor substrate, the coating effect will be better, which is conducive to reducing the generation of interface defects and improving the passivation performance of the battery, thereby improving the photoelectric conversion efficiency of the back-contact battery.

[0068] Furthermore, the first region and / or the second region is a polished surface or a structure similar to a polished surface. The surface of the third region can be a polished surface or a structure similar to a polished surface, and of course, it can also be a velvet surface. When the surface of the third region is a polished surface or a structure similar to a polished surface, it is beneficial to the formation of the later film layer, thereby facilitating surface passivation and deposition. When the surface of the third region is a velvet surface, it is beneficial to further reduce the generation of leakage current, and the proportion of the third region can be further reduced. Exemplarily, the velvet surface can be a pyramid velvet surface structure.

[0069] It can be understood that one of the first region and the second region corresponds to the P region, and the other corresponds to the N region.

[0070] The morphology of the first region and the second region in the first surface can be determined according to the morphology of the electrode structure of the back contact battery and the actual application scenario. For example, the first region and the second region can be arranged alternately in strips or in interdigitated shapes.

[0071] For the above-mentioned first doped semiconductor layer and the second doped semiconductor layer, in terms of doping type, the doping type of the first doped semiconductor layer can be N-type, in which case the doping type of the second doped semiconductor layer is P-type; or, the doping type of the first doped semiconductor layer can also be P-type, in which case the doping type of the second doped semiconductor layer is N-type. The embodiment of the present invention does not specifically limit the doping type of the first doped semiconductor layer and the second doped semiconductor layer, as long as the doping types of the two are opposite. When the doping type is P-type, it is generally doped with group III elements. When the doping type is N-type, it is generally doped with group V elements or group VI elements.

[0072] In terms of materials, the material of the first doped semiconductor layer and / or the second doped semiconductor layer may include any semiconductor material such as silicon, silicon germanium or germanium. In terms of the arrangement of the material, the crystal phase of the first doped semiconductor layer and / or the second doped semiconductor layer may be amorphous, microcrystalline, nanocrystalline, single crystal or polycrystalline. Exemplarily, the first doped semiconductor layer and / or the second doped semiconductor layer may be composed of one or more of polycrystalline silicon, amorphous silicon and microcrystalline silicon.

[0073] In terms of thickness, as the thickness of the first doped semiconductor layer and / or the thickness of the second doped semiconductor layer increases, the conductivity of the first doped semiconductor layer and / or the second doped semiconductor layer increases, and leakage problems are likely to occur between the first doped semiconductor layer and the second doped semiconductor layer. Therefore, the width of the third region needs to be wider. However, in order to take into account the conductivity of the first doped semiconductor layer and the second doped semiconductor layer, the proportion of the first doped semiconductor layer and the second doped semiconductor layer, and the width of the third region, the thickness of the first doped semiconductor layer and / or the thickness of the second doped semiconductor layer is greater than or equal to 50nm and less than or equal to 500nm. The thickness direction of the first doped semiconductor layer and the thickness direction of the second doped semiconductor layer are consistent with the direction from the first surface to the second surface. Exemplarily, the thickness of the first doped semiconductor layer and / or the thickness of the second doped semiconductor layer may be 50 nm, 80 nm, 100 nm, 120 nm, 150 nm, 180 nm, 200 nm, 220 nm, 250 nm, 280 nm, 300 nm, 320 nm, 350 nm, 380 nm, 400 nm, 420 nm, 450 nm, 480 nm or 500 nm, etc. The thickness of the first doped semiconductor layer and the thickness of the second doped semiconductor layer may be equal or unequal.

[0074] In terms of the location, the first doped semiconductor layer can be directly formed on the semiconductor substrate. Figures 1 to 4As shown, the back contact battery may also include a first interface passivation layer 4. The first interface passivation layer 4 is arranged between the semiconductor substrate 1 and the first doped semiconductor layer 2. The material and thickness of the first interface passivation layer 4 can be set according to the material of the first doped semiconductor layer 2 and the actual needs, and are not specifically limited here. The first interface passivation layer 4 can be a single-layer structure or a multi-layer structure. The first interface passivation layer 4 can be composed of different materials in different regions. It should be noted that the "regions" here are divided into detailed divisions based on the first interface passivation layer 4 as the main body, and do not refer to the first region 10, the second region 11, and the third region 12 in the above text. The material of the first interface passivation layer 4 can be one or more of silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, silicon carbide, and amorphous silicon. For example: when the first doped semiconductor layer 2 is a doped polycrystalline silicon layer, the first interface passivation layer 4 is a tunneling oxide layer. For another example: when the first doped semiconductor layer 2 is a doped amorphous silicon layer, the first interface passivation layer 4 can be an intrinsic amorphous silicon layer. The thickness of the first interface passivation layer 4 is greater than or equal to 0.5 nm and less than or equal to 5 nm. For example, the thickness of the first interface passivation layer 4 can be 0.5 nm, 1 nm, 1.5 nm, 2 nm, 2.5 nm, 3 nm, 3.5 nm, 4 nm, 4.5 nm or 5 nm. The passivation contact structure composed of the first interface passivation layer 4 and the first doped semiconductor layer 2 has an excellent interface passivation effect, and can realize the selective collection of carriers, at least reduce the carrier recombination rate of the first region 10 of the first surface, and further improve the photoelectric conversion efficiency of the back contact battery.

[0075] As for the second doped semiconductor layer, the second doped semiconductor layer can be directly formed on the semiconductor substrate. Figure 1 and Figure 2As shown, the back contact battery may further include a second interface passivation layer 5, wherein the second interface passivation layer 5 is disposed between the second doped semiconductor layer 3 and the semiconductor substrate 1. The material and thickness of the second interface passivation layer 5 may be set according to the material of the second doped semiconductor layer 3 and actual needs, and are not specifically limited here. The second interface passivation layer 5 may be a single-layer structure or a multi-layer structure, and the second interface passivation layer 5 may be composed of different materials in different regions. It should be noted that the "regions" here are divided into detailed divisions based on the second interface passivation layer 5 as the main body, and do not refer to the first region 10, the second region 11, and the third region 12 in the foregoing text. The material of the second interface passivation layer 5 may be one or more of silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, silicon carbide, and amorphous silicon. For example: when the second doped semiconductor layer 3 is a doped polycrystalline silicon layer, the second interface passivation layer 5 is a tunneling oxide layer. For another example: when the second doped semiconductor layer 3 is a doped amorphous silicon layer, the second interface passivation layer 5 may be an intrinsic amorphous silicon layer. The thickness of the second interface passivation layer 5 is greater than or equal to 0.5 nm and less than or equal to 5 nm. For example, the thickness of the second interface passivation layer 5 can be 0.5 nm, 1 nm, 1.5 nm, 2 nm, 2.5 nm, 3 nm, 3.5 nm, 4 nm, 4.5 nm or 5 nm. The passivation contact structure composed of the second interface passivation layer 5 and the second doped semiconductor layer 3 has an excellent interface passivation effect, and can realize the selective collection of carriers, at least reduce the carrier recombination rate of the second region 11 of the first surface, and further improve the photoelectric conversion efficiency of the back contact battery.

[0076] Some specific usage scenarios of the present invention are described below with several possible embodiments. It should be understood that the following description is only for understanding and is not intended to be a specific limitation.

[0077] The first one: see Figure 1 and Figure 2 , along the direction from the first region 10 to the second region 11, the surface of the first region 10, the surface of the second region 11 and the surface of the third region 12 are located in approximately the same plane.

[0078] At this time, H1 is approximately 0, H2 is approximately 0, and the width of the third region is W, 4μm≤W≤300μm. That is, the shortest surface distance L between the first region 10 and the second region 11 is approximately the width W of the third region, where W can be 4μm, 10μm, 50μm, 100μm, 120μm, 150μm, 180μm, 200μm, 230μm, 250μm, 280μm or 300μm, etc.

[0079] Combined with the above description, the resistivity of the surface layer of the semiconductor substrate in the third region is greater than 20 ohm·cm. Since the surface of the third region is located on substantially the same plane as the surfaces of the first region and the second region, the risk of leakage between the first doped semiconductor layer 2 and the second doped semiconductor layer 3 is relatively large, and the resistivity of the surface layer of the third region may be preferably greater than 50 ohm·cm.

[0080] See attached Figure 1 A first interface passivation layer 4 and a first doped semiconductor layer 2 on the first interface passivation layer are formed on the first region. A second interface passivation layer 3 and a second doped semiconductor layer 3 on the second interface passivation layer are formed on the second region. Figure 2 The second doped semiconductor layer 3 is located within a certain depth of the surface of the semiconductor substrate in the second region, for example, it can be an aluminum doped region.

[0081] Second: See Figure 3 and Figure 4 , along the direction from the second surface to the first surface, the surface of the first region 10 is higher than the bottom surface 13 of the third region 12.

[0082] In the case of adopting the above technical solution, compared with the surface of the first region 10, the surface of the second region 11 and the surface of the third region 12 being located in the same plane, since the surface of the first region 10 is higher than the bottom surface 13 of the third region 12, there is a height difference H1 between the surface of the first region 10 and the bottom surface 13 of the third region 12. At this time, the shortest surface distance L between the first region 10 and the second region 11 is greater than the width W of the third region. Therefore, while ensuring that the shortest surface distance L between the first region 10 and the second region 11 is constant, the width W of the third region 12 can be reduced. At this time, on the basis of ensuring the isolation of the first doped semiconductor layer 2 and the second doped semiconductor layer 3, the proportion of the first region 10 and the second doped semiconductor layer 3 can be further increased, thereby further increasing the proportion of the first doped semiconductor layer 2 located in the first region 10 and the second doped semiconductor layer 3 located in the second region 11, and further improving the photoelectric conversion efficiency of the back contact battery.

[0083] In this embodiment, 0μm

[0084] See also Figure 3 ​, a first interface passivation layer 4 and a first doped semiconductor layer 2 are arranged on the first region, and a second interface passivation layer 5 and a second doped semiconductor layer 3 are arranged on the second region. Along the direction from the second surface to the first surface, the surface of the second region is higher than the bottom surface located in the third region, and at this time, the surface of the second region 11 and the bottom surface of the third region also have a height difference H2. In this case, the semiconductor substrate 1 located in the third region 12 also includes a first side wall 14 and a second side wall 15. The first side wall 14 is connected to the bottom surface 13 and the surface of the first region 10 respectively, and the second side wall 15 is connected to the bottom surface 13 and the surface of the second region 11 respectively. The shortest surface distance L between the first region 10 and the second region 11 is the sum of the bottom width of the third region and the length of the first side wall 14 and the length of the second side wall 15. The length of the first side wall 14 here is the shortest distance from the surface of the first region 10 along the surface of the first side wall 14 to the bottom surface of the third region. The length of the second side wall 15 here is the shortest distance from the surface of the second region 11 along the surface of the second side wall 15 to the bottom surface of the third region. As Figure 3 When the first side wall 14 and the second side wall 15 are both vertical side walls, the shortest surface distance L between the first region 10 and the second region 11 is H1+W+H2. Wherein, W is preferably greater than 4 μm and less than or equal to 300 μm.

[0085] In an optional manner, 0μm<H2≤20μm. Exemplarily, H2 can be 1μm, 3μm, 5μm, 7μm, 10μm, 12μm, 15μm, 18μm or 20μm, etc. Preferably, 1μm≤H2≤7μm. Exemplarily, H2 can be 1μm, 1.3μm, 1.5μm, 2μm, 2.3μm, 2.5μm, 3μm, 3.5μm, 4μm, 4.3μm, 4.5μm, 5μm, 5.5μm, 6μm, 6.3μm, 6.5μm or 7μm, etc.

[0086] When one or both of the first side wall 14 and the second side wall 15 include a surface inclined relative to the first surface, the shortest surface distance L between the first region 10 and the second region 11 will be slightly smaller than H1+W+H2, but the difference is not large. Figure 6 and Figure 7 As shown. At this time, when a film layer is formed on the surface of the third region 12 later, the film layer can be better coated on the first side wall 14 and the second side wall 15, preventing the film layer from having unfilled gaps at the boundary between the first region 10 and the third region 12 or the second region 11 and the third region 12, thereby reducing the number of defects on the first side of the back contact battery and improving the formation quality of the film layer at the above boundary. It should be noted that the width W of the third region is the maximum distance between the first side wall and the second side wall. See the attached Figure 4, the surface of the second region and the bottom surface of the third region may be located in approximately the same plane. At this time, when the first side wall 14 is a vertical side wall, the surface distance L between the first region 10 and the second region 11 is H1+W. Of course, when the first side wall 14 includes a surface inclined relative to the first surface, the shortest surface distance L between the first region 10 and the second region 11 is slightly less than H1+W. Among them, 4μm≤W≤250μm, 0μm

[0087] In the case of adopting the above technical solution, compared with the surface of the first region 10, the surface of the second region 11 and the surface of the third region 12 being located in the same plane, when the shortest surface distance L between the first region 10 and the second region 11 is constant, the width W of the third region 12 can be further reduced. At this time, on the basis of ensuring the isolation of the first doped semiconductor layer 2 and the second doped semiconductor layer 3, the proportion of the first region 10 and the second region 11 can be further increased, thereby further increasing the proportion of the first doped semiconductor layer 2 located in the first region 10 and the second doped semiconductor layer 3 located in the second region 11, thereby further improving the photoelectric conversion efficiency of the back contact cell.

[0088] Further, when the third region has a sidewall structure (i.e., a first sidewall and / or a second sidewall including a surface inclined relative to the first surface), the first sidewall and / or the second sidewall surface close to the first doped semiconductor layer and / or the second semiconductor layer may be affected by the doping of the first doped semiconductor layer and / or the second doped semiconductor layer and have a local high-doping region. At this time, it is preferred that the surface layer of the bottom surface of the third region has a resistivity greater than 20 ohm·cm, and more preferably a resistivity greater than 50 ohm·cm to offset the high-doping region of part of the sidewall surface. The high-doping region here should be understood as having an impurity concentration greater than that inside the substrate.

[0089] As a possible implementation manner, when the first side wall and the second side wall both include surfaces inclined relative to the first surface, a horizontal distance between the first side wall and the second side wall gradually decreases along a direction from the first surface to the second surface.

[0090] ​Furthermore, the surface of the first side wall and / or the surface of the second side wall may be a polished surface or a similar polished surface, and may also be a velvet surface. When the surface of the first side wall and / or the surface of the second side wall is a polished surface or a similar polished surface, it is beneficial to the formation of the subsequent film layer, thereby facilitating surface passivation and deposition. When the surface of the first side wall and / or the surface of the second side wall is a velvet surface, it is beneficial to further reduce the generation of leakage current. Exemplarily, the velvet surface may be a pyramid velvet surface structure.

[0091] In the present invention, as a possible implementation, the minimum value of the width of the third region preferably conforms to W min =k / ρ+C; wherein ρ represents resistivity, k=400μm·ohm·cm, 0μm≤C≤40μm.

[0092] For example, when ρ=5, W min =80; when ρ = 20, W min =20; when ρ = 50, W min =8; when ρ = 100, W min =4.

[0093] As a possible implementation, when the back contact battery includes the first region, the third region, the second region and the third region in sequence, the width of the back contact battery is greater than or equal to 500μm and less than or equal to 2000μm; the ratio of the width of all third regions to the width of the back contact battery is less than or equal to 0.2%; the width direction of the back contact battery and the width direction of the third region are consistent with the direction from the first region to the second region. Exemplarily, the width of the back contact battery can be 500μm, 800μm, 1000μm, 1200μm, 1500μm, 1800μm, 1900μm or 2000μm, etc. The ratio of the width of all third regions to the width of the back contact battery can be 0.2%, 0.18%, 0.15%, 0.1% or 0.05%, etc.

[0094] In the case of adopting the above technical solution, since the ratio of the width of the third region to the width of the back contact battery is less than or equal to 0.2%, the ratio of the sum of the width of the first region and the width of the second region to the width of the back contact battery is greater than or equal to 99.8%. It can be seen that the total proportion of the first region and the second region is larger than that of the third region, so the total proportion of the first doped semiconductor layer located in the first region and the second doped semiconductor layer located in the second region is large. At this time, the amount of carriers collected by the back contact battery can be increased, thereby improving the photoelectric conversion efficiency of the back contact battery.

[0095] As a possible implementation, see Figures 1 to 5The above-mentioned back contact battery further includes a first electrode 6 and a second electrode 7 , the first electrode 6 is electrically connected to the first doped semiconductor layer 2 , and the second electrode 7 is electrically connected to the second doped semiconductor layer 3 .

[0096] See also Figure 1 , the first electrode 6 includes a contact portion directly in contact with the first doped semiconductor layer 2 and a main portion away from the first doped semiconductor layer 2, and the second electrode 7 includes a contact portion directly in contact with the second doped semiconductor layer 3 and a main portion away from the second doped semiconductor layer 3. The spacing L1 between the contact portion 60 of the first electrode and the third region 12 is greater than or equal to 80 μm and less than or equal to 500 μm, and the direction of the spacing L1 is consistent with the direction from the first region 10 to the second region 11. And / or, the spacing L2 between the contact portion 70 of the second electrode and the third region 12 is greater than or equal to 80 μm and less than or equal to 500 μm, and the direction of the spacing L2 is consistent with the direction from the first region 10 to the second region 11. Exemplarily, the spacing L1 can be 80 μm, 100 μm, 150 μm, 200 μm, 250 μm, 300 μm, 350 μm, 400 μm, 450 μm or 500 μm, etc. The spacing L2 may be 80 μm, 100 μm, 150 μm, 200 μm, 250 μm, 300 μm, 350 μm, 400 μm, 450 μm or 500 μm, etc. Preferably, the spacing L1 and the spacing L2 are greater than or equal to 150 μm and less than or equal to 300 μm. Exemplarily, the spacing L1 and the spacing L2 may be 150 μm, 160 μm, 180 μm, 200 μm, 220 μm, 250 μm, 280 μm or 300 μm, etc. The values ​​of the above spacings L1 and L2 may be equal or unequal.

[0097] When the above technical solution is adopted, the above L1 and L2 are within the above value range, which can not only ensure the firmness of the connection between the first electrode 6 and the first doped semiconductor layer 2 (or the second electrode 7 and the second doped semiconductor layer 3), but also improve the bonding force between the electrode and the doped semiconductor layer. At the same time, compared with the case where the spacing is less than 80 μm, the current transmission efficiency can be improved, thereby improving the conversion efficiency of the back contact battery.

[0098] In an alternative approach, see Figure 1, the ratio of the width W1 of the first doped semiconductor layer 2 to the spacing L1 is greater than or equal to 2, and the direction of the width of the first doped semiconductor layer 2 is consistent with the direction from the first region 10 to the second region 11; and / or, the ratio of the width W2 of the second doped semiconductor layer 3 to the spacing L2 is greater than or equal to 2, and the direction of the width of the second doped semiconductor layer 3 is consistent with the direction from the first region 10 to the second region 11. Exemplarily, the above ratios may be 2, 2.1, 2.3, 2.5, 2.7 or 3, etc. It should be noted that the ratio of the width of the first doped semiconductor layer 2 to the spacing L1 and the ratio of the width of the second doped semiconductor layer 3 to the spacing L2 may be equal or unequal.

[0099] In an alternative approach, see Figure 1 , the spacing between the main portion 61 of the first electrode and the third region 12 is L3, L3≤L1; the direction of the spacing L3 is consistent with the direction from the first region 10 to the second region 11; and / or, the spacing between the main portion 71 of the second electrode and the third region 12 is L4, L4≤L2; the direction of the spacing L4 is consistent with the direction from the first region 10 to the second region 11. Under the optimized metallization conditions, L3 and / or L4 are equal to 0.

[0100] As a possible implementation, the electrode slurry for forming the first electrode and the electrode slurry for forming the second electrode may be the same or different. Exemplarily, the electrode slurry for forming the first electrode and the electrode slurry for forming the second electrode may include metals (e.g., Ag, Cu, Al, Ni, Au, Zn, Sn, Pb, etc.), metal oxides (e.g., ITO, AZO, IWO, etc.), metal nitrides (e.g., TiN, etc.), metal carbides (e.g., TiC, etc.), or metal sulfides, etc., as well as other conductive connecting materials (e.g., graphene, etc.), or various combinations of the above materials.

[0101] As a possible implementation, the width of the first electrode and the width of the second electrode may be the same or different. Exemplarily, the width of the first electrode and the width of the second electrode are both greater than or equal to 5 μm and less than or equal to 600 μm. For example, the width may be 5 μm, 10 μm, 50 μm, 100 μm, 150 μm, 200 μm, 250 μm, 300 μm, 350 μm, 400 μm, 450 μm, 500 μm, 550 μm or 600 μm, etc.

[0102] As a possible implementation, see Figures 1 to 4The back contact cell further includes a surface passivation layer 8 formed on the first doped semiconductor layer 2, the second doped semiconductor layer 3 and the semiconductor substrate 1 located in the third region 12. The material of the surface passivation layer 8 can be one or more of silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, silicon carbide, and amorphous silicon. The surface passivation layer 8 can be a single-layer structure or a multi-layer structure.

[0103] The above-mentioned first electrode and second electrode can be in continuous contact. At this time, in the actual process of manufacturing a back-contact battery, the electrode slurry used to form the first electrode and the second electrode is coated on the surface passivation layer, and then sintered so that the electrode slurry passes through the surface passivation layer and is electrically connected to the corresponding first doped semiconductor layer and second doped semiconductor layer respectively.

[0104] The first electrode and the second electrode may also be in partial contact, for example, the first electrode and / or the second electrode include a fine gate and a main gate line, wherein the fine gate line is in contact with the first doped semiconductor layer and the second doped semiconductor layer, and the main gate is not in contact with the first doped semiconductor layer or the second doped semiconductor layer. For another example, the first electrode and / or the second electrode only includes a fine gate, and the fine gate may be in contact with the first doped semiconductor layer or the second doped semiconductor layer at a selective position.

[0105] As a possible implementation, see Figure 1 , the ratio of the width W of the third region 12 to the width W1 of the first doped semiconductor layer 2 is less than or equal to 35%; illustratively, the ratio may be 35%, 33%, 31%, 30%, 29%, 26%, 20%, etc. Preferably, the ratio of the width W of the third region 12 to the width W1 of the first doped semiconductor layer 2 is less than or equal to 30%. And / or, the ratio of the width W of the third region 12 to the width W2 of the second doped semiconductor layer 3 is less than or equal to 35%. illustratively, the ratio may be 35%, 33%, 31%, 30%, 29%, 26%, 20%, etc. Preferably, the ratio of the width W of the third region 12 to the width W2 of the second doped semiconductor layer 3 is less than or equal to 30%. It should be noted that the above two types of ratios may be equal or unequal.

[0106] As another possible implementation, the ratio of the area of ​​the semiconductor substrate located in the third region to the area of ​​the first surface is less than or equal to 20%. Exemplarily, the ratio may be 20%, 19%, 18%, 17%, 16%, 15%, 14%, 13%, 12%, 11% or 10%, etc.

[0107] In both of the above cases, on the basis of ensuring isolation between the first doped semiconductor layer and the second doped semiconductor layer, the proportion of the first region and the second region can be increased, thereby increasing the proportion of the first doped semiconductor layer located in the first region and the second doped semiconductor layer located in the second region, thereby improving the photoelectric conversion efficiency of the back contact battery.

[0108] As a possible implementation, the doping concentration of the IIIA group doping element and the doping concentration of the VA group doping element in the semiconductor substrate located in the third region are both less than 1E14 / cm -3 For example, the doping concentration may be 9.9E13 / cm -3 、9E13 / cm -3 、8E13 / cm -3 、7E13 / cm -3 、6E13 / cm -3 wait.

[0109] As another possible implementation, within a depth range of 20 nm, the doping concentration of the doping element in the semiconductor substrate located in the third region is A; within a depth range of 2000 nm, the doping concentration of the doping element in the semiconductor substrate located in the third region is B; For example, It can be 9.9%, 9%, 8.5%, 8%, etc. It can be seen from the above that within the above two depth ranges, the doping concentrations of the doping elements in the semiconductor substrate located in the third region are the same or close.

[0110] As a possible implementation, Figure 3-4 In the case where the third region includes the first sidewall 14, the first doped semiconductor layer in the first region and the first sidewall 14 in the third region have a lateral spacing, for example Figure 8 and / or, in the case where the third region includes the second sidewall 15, the second doped semiconductor layer located in the second region has a lateral spacing with the second sidewall 15 of the third region.

[0111] At this time, not only can the first doped semiconductor layer and the second doped semiconductor layer be further isolated, the leakage risk between the first doped semiconductor layer and the second doped semiconductor layer be further reduced, and potential safety hazards be reduced, but parasitic absorption can also be reduced to improve battery efficiency.

[0112] In a second aspect, an embodiment of the present invention further provides a photovoltaic module. The photovoltaic module includes a battery string and an encapsulation layer. The battery string is formed by connecting a plurality of back-contact batteries as described in the above technical solution, and the encapsulation layer is used to cover the surface of the battery string.

[0113] The beneficial effects of the second aspect of the present invention and its various implementations can be analyzed by referring to the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0114] In a third aspect, an embodiment of the present invention further provides a method for manufacturing a back-contact battery. The method for manufacturing a back-contact battery comprises:

[0115] First, a semiconductor substrate is provided; the semiconductor substrate comprises a first surface and a second surface opposite to each other; the first surface comprises a first region, a second region and a third region located between the first region and the second region;

[0116] It should be noted that before actually manufacturing the back contact cell, the semiconductor substrate needs to be surface treated, such as damage removal, stain removal, polishing or texturing, to obtain a semiconductor substrate that meets the requirements. As for the specific treatment process, reference can be made to the prior art and no specific limitation is made here.

[0117] Next, forming a first doped semiconductor layer disposed in the first region;

[0118] Exemplarily, a process such as chemical vapor deposition can be used to form a first doped semiconductor material layer that is disposed in an entire layer on the first surface of the semiconductor substrate. Then, a first mask material layer that is disposed in an entire layer is formed on the first doped semiconductor material layer. Then, the first mask material layer is patterned (for example, the first mask material layer is patterned using a laser) to obtain a first mask layer corresponding to the first region. Then, under the action of the first mask layer, the first doped semiconductor material layer is processed (for example, the first doped semiconductor material layer is patterned using KOH or NaOH) to obtain a first doped semiconductor layer corresponding to the first region. The material of the above-mentioned first mask material layer can be silicon oxide.

[0119] In one example, the specific steps of forming a first doped semiconductor material layer arranged in an entire layer on the first surface of the semiconductor substrate may be: forming an intrinsic amorphous silicon layer in an entire layer on the first surface of the semiconductor substrate, and then performing boron diffusion on the intrinsic amorphous silicon layer to form a P-type doped polycrystalline silicon layer. The thickness of the above-mentioned P-type doped polycrystalline silicon layer is greater than or equal to 50nm and less than or equal to 500nm. For example, the thickness of the P-type doped polycrystalline silicon layer may be 50nm, 100nm, 150nm, 200nm, 250nm, 300nm, 350nm, 400nm, 450nm or 500nm, etc. It should be understood that the above-mentioned intrinsic amorphous silicon layer may be replaced by other semiconductor layers, for example, microcrystalline silicon, polycrystalline silicon, nano silicon or a mixture of any two or more thereof.

[0120] In another example, the specific steps of forming the first doped semiconductor layer disposed in the first region may be: forming an intrinsic semiconductor layer on the first surface of the semiconductor substrate in an entire layer, and then completing the P-type doping of the intrinsic semiconductor layer in a step under a high temperature, BCl3 and oxygen environment to obtain a first doped semiconductor material layer. At the same time, a borosilicate glass layer (Borosilicate Glass, abbreviated as BSG) is formed on the first doped semiconductor material layer, and the borosilicate glass layer is used as a first mask material layer. Then, the first mask material layer is patterned to obtain a first mask layer corresponding to the first region. Then, under the action of the first mask layer, the first doped semiconductor material layer is processed to obtain a first doped semiconductor layer corresponding to the first region.

[0121] As a possible implementation method, in the case where the back contact battery also includes a first interface passivation layer, after providing a semiconductor substrate and before forming a first doped semiconductor layer arranged in the first region, the manufacturing method of the above-mentioned back contact battery also includes: forming a first interface passivation material layer in an entire layer on the first surface of the semiconductor substrate, and then processing the first interface passivation material layer under the action of the mask layer to form a first interface passivation layer located in the first region. For the description of the material and thickness of the first interface passivation layer, please refer to the description in the first aspect and will not be repeated here. It should be noted that the method for forming the above-mentioned first interface passivation layer includes one or more of plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, catalytic chemical vapor deposition (Cat-CVD) or atomic layer deposition (ALD).

[0122] Next, a second doped semiconductor layer is formed in the second region; the first doped semiconductor layer and the second doped semiconductor layer have opposite conductivity types;

[0123] Exemplarily, a second doped semiconductor material layer can be formed on the first surface of the semiconductor substrate and on the first mask layer by using processes such as chemical vapor deposition. Then, a second mask material layer is formed on the entire second doped semiconductor material layer. Then, the second mask material layer is patterned (for example, the second mask material layer is patterned by using a laser) to obtain a second mask layer corresponding to the second region. Then, under the action of the second mask layer, the second doped semiconductor material layer is processed (for example, the second doped semiconductor material layer is patterned by using KOH or NaOH) to obtain a second doped semiconductor layer corresponding to the second region. The above-mentioned second mask material layer can be a silicon oxide layer or a phosphoric acid glass layer. Then, the first mask layer and the second mask layer are removed.

[0124] As a possible implementation, in the case where the back contact battery also includes a second interface passivation layer, after providing a semiconductor substrate and before forming a second doped semiconductor layer disposed in the second region, the manufacturing method of the above-mentioned back contact battery also includes: forming a second interface passivation material layer on the first surface of the semiconductor substrate and on the first mask layer, and then processing the second interface passivation material layer under the action of the mask layer to form a second interface passivation layer located in the second region. For descriptions of the material and thickness of the second interface passivation layer, reference can be made to the description in the first aspect and will not be repeated here. It should be noted that the method for forming the above-mentioned second interface passivation layer includes one or more of plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, catalytic chemical vapor deposition (Cat-CVD) or atomic layer deposition (ALD).

[0125] The resistivity of the surface layer of at least part of the surface of the semiconductor substrate located in the third region is greater than 20 ohm·cm; and H1+H2+W is greater than or equal to 4 μm and less than or equal to 300 μm; wherein H1 is the height difference between the bottom surface of the third region and the surface of the first region, H2 is the height difference between the bottom surface of the third region and the surface of the second region, and W is the width of the third region.

[0126] Next, a surface passivation layer is formed on the first doped semiconductor layer, the second doped semiconductor layer and the semiconductor substrate located in the third region. The material of the surface passivation layer can be one or more of silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, silicon carbide, and amorphous silicon. The surface passivation layer can be a single-layer structure or a multi-layer structure. The method for forming the surface passivation layer can be one or more of plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), atmospheric pressure chemical vapor deposition (APCVD), metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD) or physical vapor deposition (PVD). Exemplarily, an aluminum oxide layer is prepared by atomic layer deposition, and then one or more silicon nitride layers are prepared on the aluminum oxide layer by plasma enhanced chemical vapor deposition.

[0127] As a possible implementation, when the back contact cell further includes a passivation layer and / or an anti-reflection layer located on the second surface of the semiconductor substrate, the material of the passivation layer and / or the anti-reflection layer may be one or more of silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, silicon carbide, and amorphous silicon. The formation process of the passivation layer and / or the anti-reflection layer may refer to the formation process of the surface passivation layer, which will not be described in detail here.

[0128] Next, an electrode paste is printed on the first doped semiconductor layer located in the first region and the second doped semiconductor layer located in the second region to form a first electrode electrically connected to the first doped semiconductor layer and a second electrode electrically connected to the second doped semiconductor layer. As for the selection of the electrode paste, please refer to the description of the first aspect, which will not be repeated here.

[0129] The beneficial effects of the third aspect and its various implementations in the embodiments of the present invention can be analyzed with reference to the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0130] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in any one or more embodiments or examples in a suitable manner. The above description is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be based on the protection scope of the claims.

Claims

1. A back contact battery, characterized in that: include: A semiconductor substrate, comprising a first surface and a second surface opposite to each other; the first surface comprises a first region, a second region and a third region located between the first region and the second region; A first doped semiconductor layer, disposed in the first region; A second doped semiconductor layer is disposed in the second region; the first doped semiconductor layer and the second doped semiconductor layer have opposite conductivity types; The resistivity of the surface layer of at least a portion of the surface of the semiconductor substrate located in the third region is greater than 20 ohm·cm; Furthermore, H1+H2+W is greater than or equal to 4 μm and less than or equal to 300 μm; wherein H1 is the height difference between the bottom surface of the third region and the surface of the first region, H2 is the height difference between the bottom surface of the third region and the surface of the second region, and W is the width of the third region.

2. The back contact cell according to claim 1, characterized in that: Along the direction from the first region to the second region, the surface of the first region, the surface of the second region and the surface of the third region are approximately located in the same plane; H1 is approximately 0, H2 is approximately 0, and 4μm≤W≤300μm.

3. The back contact battery according to claim 1, characterized in that: Along a direction from the second surface to the first surface, a surface of the first region is higher than a bottom surface of the third region.

4. The back contact cell according to claim 3, characterized in that: 0μm<H1≤20μm.

5. The back contact cell according to claim 3 or 4, characterized in that: Along a direction from the second surface to the first surface, a surface of the second region is higher than a bottom surface of the third region.

6. The back contact cell according to claim 5, characterized in that: 0μm<H2≤20μm.

7. The back contact cell according to claim 3, characterized in that: The semiconductor substrate located in the third region further includes: a first side wall, the first side wall being connected to the bottom surface and the surface of the first region respectively; The first side wall includes a surface inclined relative to the first surface; or the first side wall is perpendicular to the first surface.

8. The back contact battery according to claim 7, characterized in that: The semiconductor substrate located in the third region further includes: a second side wall, the second side wall being connected to the bottom surface and the surface of the second region respectively; The second side wall includes a surface inclined relative to the first surface; or the second side wall is perpendicular to the first surface.

9. The back contact cell according to claim 8, characterized in that: When both the first side wall and the second side wall include surfaces inclined relative to the first surface, a horizontal distance between the first side wall and the second side wall gradually decreases along a direction from the first surface to the second surface.

10. The back contact cell according to claim 1, characterized in that: The width of the back contact battery is greater than or equal to 500μm and less than or equal to 2000μm; the ratio of the width of all the third regions to the width of the back contact battery is less than or equal to 0.2%; the width direction of the back contact battery and the width direction of the third region are consistent with the direction from the first region to the second region.

11. The back contact cell according to claim 1, characterized in that: The back contact cell further comprises a first electrode and a second electrode, the first electrode is electrically connected to the first doped semiconductor layer; the second electrode is electrically connected to the second doped semiconductor layer; The first electrode comprises a contact portion directly contacting the first doped semiconductor layer and a main portion away from the first doped semiconductor layer; The second electrode comprises a contact portion directly contacting the second doped semiconductor layer and a main portion away from the second doped semiconductor layer; A distance L1 between the contact portion of the first electrode and the third region is greater than or equal to 80 μm and less than or equal to 500 μm; a direction of the distance L1 is consistent with a direction from the first region to the second region; and / or, a distance L2 between the contact portion of the second electrode and the third region is greater than or equal to 80 μm and less than or equal to 500 μm; The direction of the interval L2 is consistent with the direction from the first region to the second region.

12. The back contact cell according to claim 11, characterized in that: The ratio of the width of the first doped semiconductor layer to the distance L1 is greater than or equal to 2, and the direction of the width of the first doped semiconductor layer is consistent with the direction from the first region to the second region; And / or, a ratio of a width of the second doped semiconductor layer to the interval L2 is greater than or equal to 2, and a direction of the width of the second doped semiconductor layer is consistent with a direction from the first region to the second region.

13. The back contact cell according to claim 11, characterized in that: The distance between the main part of the first electrode and the third region is L3, L3≤L1; the direction of the distance L3 is consistent with the direction from the first region to the second region; And / or, a distance between the main portion of the second electrode and the third region is L4, L4≤L2; and a direction of the distance L4 is consistent with a direction from the first region to the second region.

14. The back contact cell according to claim 1, characterized in that The ratio of the width W of the third region to the width of the first doped semiconductor layer is less than or equal to 35%; And / or, a ratio of a width W of the third region to a width of the second doped semiconductor layer is less than or equal to 35%.

15. The back contact cell according to claim 1, characterized in that: A ratio of an area of ​​the semiconductor substrate located in the third region to an area of ​​the first surface is less than or equal to 20%.

16. The back contact cell according to claim 1, characterized in that The resistivity of the surface layer of at least a portion of the surface of the semiconductor substrate located in the third region is greater than 80 ohm·cm; and / or, the doping concentration of the IIIA group doping element and the doping concentration of the VA group doping element in the semiconductor substrate located in the third region are both less than 1E14 / cm -3 .

17. The back contact cell according to claim 1, characterized in that: Within a depth range of 20 nm, the doping concentration of the doping element in the semiconductor substrate located in the third region is A; within a depth range of 2000 nm, the doping concentration of the doping element in the semiconductor substrate located in the third region is B; 18. The back contact cell according to any one of claims 1 to 17, characterized in that: The back contact cell further comprises a first interface passivation layer; the first interface passivation layer is arranged between the semiconductor substrate and the first doped semiconductor layer; And / or, the back contact cell further includes a second interface passivation layer, and the second interface passivation layer is arranged between the second doped semiconductor layer and the semiconductor substrate.

19. A photovoltaic module, characterized in that: The photovoltaic module comprises: A battery string, wherein the battery string is formed by connecting a plurality of back-contact batteries according to any one of claims 1 to 18; The encapsulation layer is used to cover the surface of the battery string.

20. A method for manufacturing a back contact battery, characterized in that: include: Providing a semiconductor substrate; The semiconductor substrate comprises a first surface and a second surface opposite to each other; the first surface comprises a first region, a second region and a third region located between the first region and the second region; forming a first doped semiconductor layer disposed in the first region; forming a second doped semiconductor layer disposed in the second region; the first doped semiconductor layer and the second doped semiconductor layer have opposite conductivity types; The resistivity of the surface layer of at least a portion of the surface of the semiconductor substrate located in the third region is greater than 20 ohm·cm; Furthermore, H1+H2+W is greater than or equal to 4 μm and less than or equal to 300 μm; wherein H1 is the height difference between the bottom surface of the third region and the surface of the first region, H2 is the height difference between the bottom surface of the third region and the surface of the second region, and W is the width of the third region.

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