Solar cell and photovoltaic module comprising same

Abstract

The invention provides a solar cell and a photovoltaic module comprising the same, and belongs to the technical field of photovoltaics. The solar cell includes: a semiconductor substrate; the first carrier selection layer is located on the first surface of the semiconductor substrate, and the material of the first carrier selection layer comprises transition metal oxide; the first middle conductive layer is located on the surface, away from the semiconductor substrate, of the first carrier selection layer, the material of the first middle conductive layer comprises metal nitride or metal sulfide, and the thickness of the first middle conductive layer ranges from 0.2 nm to 10 nm; the second carrier selection layer is located on the surface, away from the semiconductor substrate, of the first intermediate conductive layer, and the material of the second carrier selection layer comprises transition metal oxide with the same conduction type as the first carrier selection layer; the electrode is in contact with the surface, far away from the semiconductor substrate, of the second carrier selection layer; the sum of the thickness of the first carrier selection layer and the thickness of the second carrier transmission layer is 4 nm to 10 nm. And / or the doping concentration of the first carrier selection layer and the doping concentration of the second carrier transmission layer are respectively smaller than or equal to 1 * 10 < 21 > atom / cm < 3 >.

Description

Technical Field

[0001] The present application relates to the technical field of solar cells, and in particular, to a solar cell and a photovoltaic module comprising the same. Background Art

[0002] The front structure of solar cells, such as Tunnel Oxide Passivated Contact (TOPCon) cells or Passivated Emitter and Rear Cell (PERC) cells, usually adopts direct contact between the metal electrode and the silicon layer, which leads to a relatively high surface recombination rate on the front side of the cell, limiting the further improvement of the cell efficiency.

[0003] With the development of passivation technology in crystalline silicon cells, conventional passivation structures such as tunneling oxide passivation contact structures have played a good role in suppressing carrier recombination on the back of the cell. However, if they are applied to the front of the cell, they will cause strong parasitic absorption due to the relatively narrow band gap of the silicon film, limiting the improvement of cell efficiency.

[0004] If wide bandgap materials are used as passivation contact layers, although optical parasitic absorption can be reduced to a certain extent, these wide bandgap materials have poor electrical transmission performance, which also limits their application. Therefore, it is still necessary to study how to further improve the passivation contact effect of solar cells and reduce the photoelectric loss of solar cells, thereby improving the cell efficiency of solar cells. Summary of the invention

[0005] In view of this, in order to at least partially solve at least one of the above-mentioned technical problems, the present application provides a solar cell and a photovoltaic module including the same.

[0006] In order to achieve the above purpose, the technical solution of this application is as follows:

[0007] According to an embodiment of one aspect of the present application, a solar cell is provided, comprising: a semiconductor substrate, comprising a first surface and a second surface opposite to each other; a first carrier selection layer, located on the first surface of the semiconductor substrate, the material of the first carrier selection layer comprising a transition metal oxide; a first intermediate conductive layer, located on the surface of the first carrier selection layer away from the semiconductor substrate, the material of the first intermediate conductive layer comprising a metal nitride or a metal sulfide, and the thickness of the first intermediate conductive layer is 0.2 nm to 10 nm; a second carrier selection layer, located on the surface of the first intermediate conductive layer away from the semiconductor substrate, the material of the second carrier selection layer comprising a transition metal oxide of the same conductivity type as the first carrier selection layer; and an electrode, located on the surface of the second carrier selection layer away from the semiconductor substrate; wherein the sum of the thicknesses of the first carrier selection layer and the second carrier transport layer is less than 70 nm, preferably 4 nm to 10 nm; and / or the doping concentrations of the first carrier selection layer and the second carrier transport layer are respectively less than or equal to 1×10 21 atom / cm 3 .

[0008] According to another embodiment of the present application, a photovoltaic assembly is provided, comprising: a plurality of solar cells as described above, connected into a solar cell string; and a packaging structure, disposed around the periphery of the solar cell string.

[0009] According to the embodiments of the present application, the solar cell provided by the present application uses a sandwich laminate structure formed by a first carrier selection layer, a first intermediate conductive layer and a second carrier selection layer between a semiconductor substrate and an electrode. By selecting a wide bandgap transition metal oxide as the first and second carrier selection layers and adjusting the thickness of the first intermediate conductive layer, the optical parasitic absorption can be reduced and the electrical transmission performance can be improved when the first and second carrier selection layers have a thin thickness or a small doping concentration, and the passivation and contact effects are good. Therefore, based on the above sandwich laminate structure, the electrical performance of solar cells and photovoltaic modules, such as battery efficiency, is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other objects, features and advantages of the present application will become more apparent through the following description of the embodiments of the present application with reference to the accompanying drawings, in which:

[0011] Figure 1 A schematic diagram of a partial structure of a solar cell according to an embodiment of the present application;

[0012] Figure 2 A schematic diagram of a partial structure of a solar cell according to another embodiment of the present application;

[0013] Figure 3A schematic diagram of the complete structure of a solar cell according to an embodiment of the present application;

[0014] Figure 4 A schematic diagram of the complete structure of a solar cell according to another embodiment of the present application;

[0015] Figure 5 This is a schematic diagram of the complete structure of a solar cell according to another embodiment of the present application. DETAILED DESCRIPTION

[0016] In order to make the objectives, technical solutions and advantages of the present application more clearly understood, the present application is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0017] In the detailed description below, for ease of explanation, many specific details are set forth to provide a comprehensive understanding of the embodiments of the present application. However, it is apparent that one or more embodiments may be implemented without these specific details. In addition, in the following description, the description of known structures and technologies is omitted to avoid unnecessary confusion of the concepts of the present application.

[0018] The terms used herein are only for describing specific embodiments and are not intended to limit the present application. The term "comprising" used herein indicates the existence of features, steps, operations, but does not exclude the existence or addition of one or more other features.

[0019] In the case of using expressions such as "at least one of A, B, and C, etc.", it should generally be interpreted in accordance with the meaning of the expression generally understood by those skilled in the art (for example, "a system having at least one of A, B, and C" should include but is not limited to a system having A alone, B alone, C alone, A and B, A and C, B and C, and / or A, B, C, etc.). In the case of using expressions such as "at least one of A, B, or C, etc.", it should generally be interpreted in accordance with the meaning of the expression generally understood by those skilled in the art (for example, "a system having at least one of A, B, or C" should include but is not limited to a system having A alone, B alone, C alone, A and B, A and C, B and C, and / or A, B, C, etc.).

[0020] The relative position between two components (such as film layers or regions) mentioned in this application, such as "above", "upper" or "above", may refer to the direct contact between the two components, or may refer to the indirect contact between the two components. Similarly, the relative position between two components mentioned in this application, such as "below", "lower" or "below", may refer to the direct contact between the two components, or may refer to the indirect contact between the two components. For example, when one of the components (such as film layers or regions) is referred to as "on another component", it can be directly on the other component, or there may be other components between the two. On the other hand, when a component is referred to as "directly on another component", there is no component between the two. In addition, when one of the components is referred to as "on another component", the two have an up-and-down relationship in the top-view direction, and this component can be above or below the other component, so this up-and-down relationship depends on the orientation of the device.

[0021] In the selective passivation contact technology of solar cells, the use of wide bandgap oxides as passivation contact materials is beneficial to reducing optical parasitic absorption and optimizing interface recombination losses caused by direct contact between metal and semiconductor substrates. However, according to the applicant's research, compared with passivation contact materials such as doped silicon, although the optical parasitic absorption of wide bandgap oxides is weaker, the electrical properties such as charge mobility are lower and the contact resistance is higher, which is not conducive to charge extraction, thereby causing charge interface accumulation and reducing battery efficiency.

[0022] In the process of realizing the concept of this application, it was found that using transition metal oxides as wide-bandgap oxides and adding metal nitrides or metal sulfides between two layers of wide-bandgap oxides to form a selective passivation contact structure can optimize the charge extraction and transfer process between the semiconductor substrate and the electrode, help reduce the contact resistance and battery series resistance, and improve the battery conversion efficiency.

[0023] Specifically, according to an embodiment of one aspect of the present application, a solar cell is provided. Figure 1 FIG. 1 is a schematic diagram of a partial structure of a solar cell according to an embodiment of the present application. Figure 1As shown, the solar cell of the present application includes a semiconductor substrate 101 , a first carrier selection layer 103 , a first intermediate conductive layer 104 , a second carrier selection layer 105 and an electrode 106 . The semiconductor substrate 101 includes a first surface 101a and a second surface 101b opposite to each other; the first carrier selection layer 103 is located on the first surface 101a of the semiconductor substrate 101, and the material of the first carrier selection layer 103 includes a transition metal oxide; the first intermediate conductive layer 104 is located on the surface of the first carrier selection layer 103 away from the semiconductor substrate 101, and the material of the first intermediate conductive layer 104 includes a metal nitride or a metal sulfide, and the thickness of the first intermediate conductive layer 104 is 0.2 nm to 10 nm; the second carrier selection layer 105 is located on the surface of the first intermediate conductive layer 104 away from the semiconductor substrate 101, and the material of the second carrier selection layer 105 includes a transition metal oxide of the same conductivity type as the first carrier selection layer 103; and the electrode 106 is located on the surface of the second carrier selection layer 105 away from the semiconductor substrate 101; wherein the sum of the thicknesses of the first carrier selection layer 103 and the second carrier transport layer 105 is less than 70 nm, preferably 4 nm to 10 nm. nm; and / or, the doping concentrations of the first carrier selection layer 103 and the second carrier transport layer 105 are less than or equal to 1×10 21 atom / cm 3 .

[0024] According to an embodiment of the present application, the material of the semiconductor substrate 101 may be an N-type or P-type crystalline silicon substrate, for example, it may be a semiconductor material selected from monocrystalline silicon, polycrystalline silicon, and microcrystalline silicon, preferably an N-type or P-type monocrystalline silicon substrate, and the conversion efficiency of the battery based on the monocrystalline silicon substrate is higher than that of other types such as polycrystalline silicon batteries. By introducing donor impurities such as phosphorus (P), arsenic (As) or antimony (Sb) into these semiconductor materials, an N-type crystalline silicon substrate is obtained, or by introducing acceptor impurities such as boron (B), aluminum (Al) or gallium (Ga) into these semiconductor materials, a P-type crystalline silicon substrate is obtained.

[0025] According to the embodiment of the present application, the first surface of the semiconductor substrate 101 can be the front or back of the battery, without limitation. Generally speaking, the front of the battery is used as the light-receiving surface, and the back is used as the backlight surface, or it can also be double-sided, then both the front and back are used as the light-receiving surface, and it is more preferred that the first surface is the light-receiving surface, because compared with the backlight surface, the optical parasitic absorption problem of the light-receiving surface is more significant, so that when the first surface is the light-receiving surface, it is more conducive to giving play to the advantages of the selective passivation contact structure of the present application that can take into account the improvement of optical performance and electrical performance, so that the improvement of battery conversion efficiency is more significant.

[0026] According to an embodiment of the present application, the thickness of the first intermediate conductive layer 104 may be 0.2 nm to 10 nm, for example, 0.2 nm, 0.6 nm, 1 nm, 2 nm, 2.3 nm, 2.5 nm, 2.8 nm, 3 nm, 4 nm, 6 nm, 8 nm, 10 nm, etc., and further, may be preferably 2 to 3 nm. Under the aforementioned suitable thickness of the first intermediate conductive layer, not only the selective passivation contact structure has good electrical transmission performance, but also it is beneficial to reduce optical parasitic absorption.

[0027] According to an embodiment of the present application, the sum of the thicknesses of the first carrier selection layer 103 and the second carrier transport layer 105 may be less than 70 nm, for example, 5 nm, 10 nm, 20 nm, 40 nm, 60 nm, 65 nm, etc., preferably 4 nm to 10 nm, for example, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, etc. Alternatively, the doping concentrations of the first carrier selection layer 103 and the second carrier transport layer 105 are less than or equal to 1×10 21 atom / cm 3 , preferably 1×10 16 ~1×10 20 atom / cm 3 , for example, it can be 1×10 16 atom / cm 3 , 5×10 16 atom / cm 3 , 1×10 17 atom / cm 3 , 5×10 17 atom / cm 3 , 1×10 18 atom / cm 3 , 5×10 18 atom / cm 3 , 1×10 19 atom / cm 3 , 5×10 19 atom / cm 3 , 1×10 20 atom / cm 3 wait.

[0028] According to the embodiments of the present application, in order to improve the electrical transmission performance of the transition metal oxide when it is used as a carrier selection layer, it is usually necessary to thicken it or dope it with a high concentration. However, its selective contact effect is still difficult to improve to a significant extent, and thickening or high-concentration doping also has process difficulties.

[0029] Based on the passivation contact structure of the present application, specifically by adding a first intermediate conductive layer 104 between the first carrier selection layer 103 and the second carrier transport layer 105, the electrical transmission performance and the carrier mobility can be improved, so that even with the aforementioned thinner carrier transport layer thickness or lower doping concentration, a good passivation contact effect can be achieved.

[0030] According to an embodiment of the present application, further optionally, the thickness of the second carrier transport layer 105 is greater than or equal to the thickness of the first carrier transport layer 103 to avoid the second carrier transport layer 105 being too thin, resulting in unstable work function. By controlling the thickness of the second carrier transport layer 105, energy band matching with the semiconductor substrate 101 and the electrode 106 can be achieved, thereby promoting charge transfer.

[0031] According to the embodiment of the present application, the materials of the first carrier selection layer 103 and the second carrier selection layer 105 may be the same or different, but the conductivity type needs to be the same, for example, they may be both N-type or P-type, mainly playing the role of field passivation and selective contact. The first carrier selection layer 103 and the second carrier selection layer 105 may be conductive by doping or oxygen vacancies (in the case of undoping).

[0032] Exemplarily, in order to meet the requirements of conductivity and work function, thereby achieving field passivation and selective contact effects, the first carrier selection layer 103 and the second carrier selection layer 105 are independently selected from at least one of doped or undoped zinc oxide, tin oxide, molybdenum oxide, titanium oxide, nickel oxide, gallium oxide, indium oxide, copper oxide, magnesium oxide, aluminum oxide, tungsten oxide, cerium oxide, manganese oxide, vanadium oxide, chromium oxide, cobalt oxide, germanium oxide, cadmium oxide, and rhenium oxide. It is understandable that the aforementioned materials such as copper oxide, manganese oxide, etc. can also be doped to widen their band gaps to meet the requirements of reducing optical parasitic absorption.

[0033] Furthermore, doping can be adding third or fifth group elements such as aluminum, gallium, indium, etc., or trace amounts of transition metal elements or rare earth elements such as nickel, copper, lanthanum, iridium, actinium, etc., to the first carrier selection layer. The electrical properties of the material can be regulated by controlling the ratio of oxygen elements to doping elements; oxygen vacancies can be achieved by regulating process parameters, such as the source ratio and time of atomic layer deposition. For ease of understanding, for example, the electrical properties of zinc oxide can be regulated by doping aluminum, and the electrical properties of molybdenum oxide can be regulated by forming oxygen vacancies. Specifically, appropriate implementation methods can be selected according to different materials and conductivity types, and are not listed here one by one.

[0034] According to an embodiment of the present application, further optionally, at least one of the first carrier selection layer 103 and the second carrier selection layer 105 has a nanocrystalline or microcrystalline structure penetrating along the thickness direction. Such a configuration can promote the transmission of charges along the thickness direction, and further improve the electrical transmission performance of the first carrier selection layer 103 and the second carrier selection layer 105. The nanocrystalline or microcrystalline structure can be detected by a microscopic morphology detection method such as a transmission electron microscope.

[0035] Further optionally, the resistivity of the first carrier transport layer 103 and the second carrier transport layer 105 is 10 -1 ~10 -3 More specifically, the resistivity of transition metal oxides is generally in the range of 10 -1 ~10 -2 Ω·m order of magnitude, and its resistivity can be reduced to 10 by doping or oxygen vacancy regulation. -3 However, as a selective contact material, the work function of transition metal oxides needs to match that of the semiconductor substrate. Considering the optical properties of the material, excessive doping concentration will increase the number of free carriers and cause light parasitic absorption loss. Therefore, the resistivity value should not be too low.

[0036] According to an embodiment of the present application, when the first carrier selection layer 103 and the second carrier selection layer 105 are N-type materials, the work function of the material of the second carrier selection layer 105 is less than or equal to the work function of the material of the first carrier selection layer 103; or, when the first carrier selection layer 103 and the second carrier selection layer 105 are P-type materials, the work function of the material of the second carrier selection layer 105 is greater than or equal to the work function of the material of the first carrier selection layer 103. Thus, the charge transfer to the electrode can be promoted to achieve charge collection.

[0037] Further optionally, in the case where the semiconductor substrate is a crystalline silicon substrate, the second carrier selection layer 105 is an N-type material with a low work function, and its work function is preferably an N-type material less than or equal to 4.5 eV; or, the second carrier selection layer is a P-type material with a high work function, and its work function is preferably greater than or equal to 4.8 eV.

[0038] The work function setting of the first carrier selection layer 103 and the second carrier selection layer 105 can facilitate energy band matching with the semiconductor substrate 101 and the electrode 106, thereby promoting charge transfer.

[0039] According to an embodiment of the present application, the first intermediate conductive layer 104 can be selected from at least one of doped or undoped titanium nitride, molybdenum nitride, zirconium nitride, gallium nitride, nickel nitride, and tungsten nitride. The resistivity of these materials is generally between 10 -5In the case where the resistivity can be regulated only by transition metal oxides, the first intermediate conductive layer 104 has good conductivity, thereby optimizing the electrical performance of the selective passivation contact structure.

[0040] Furthermore, the mobility of the first intermediate conductive layer 104 is preferably not less than 800 cm 2 V −1 s −1 , which is higher than the mobility of conventional selective contact materials in related technologies, generally not exceeding 100 cm 2 V −1 s −1 For example, the mobility of ITO is about 50 cm 2 V −1 s −1 .

[0041] Exemplarily, the first intermediate conductive layer 104 may be deposited and doped by atomic layer deposition (ALD for short), vacuum evaporation, electron beam deposition or chemical vapor deposition (CVD for short).

[0042] According to the embodiment of the present application, the work function of the material of the first intermediate conductive layer 104 is not particularly limited, and further, its work function is preferably located between the first carrier selection layer 103 and the second carrier selection layer 105. This allows the energy band of the selective passivation contact structure to bend, promotes the transfer of charges to the electrode, reduces the contact resistance, and is conducive to the collection of charges at the electrode.

[0043] According to an embodiment of the present application, further optionally, the solar cell may further include at least one group of stacked structures (not shown in the figure), located between the first carrier selection layer 103 and the first intermediate conductive layer 104, and along the direction away from the first surface 101a, the group of stacked structures sequentially includes a second intermediate conductive layer and a third carrier selection layer.

[0044] Among them, the material of the second intermediate conductive layer is similar to that of the first intermediate conductive layer, which plays a role in optimizing electrical performance. The material of the third carrier selection layer is similar to that of the first carrier selection layer 103 or the second carrier selection layer 105, which plays a role in field passivation and selective contact, which will not be elaborated here.

[0045] According to the embodiment of the present application, at least one of the first carrier selection layer 103, the first intermediate conductive layer 104, and the second carrier selection layer 105 is a non-doped material. Thus, the characteristics of the material itself are utilized to achieve selective passivation contact and electrical transmission effects, while reducing process optimization and electrical parameter adjustment in film preparation, thereby expanding the process window as much as possible.

[0046] In other embodiments, not limited thereto, the first carrier selection layer 103, the first intermediate conductive layer 104, and the second carrier selection layer 105 may all be doped materials. For example, the same metal element may be doped, such as aluminum doped into zinc oxide or oxygen content in molybdenum oxide increasing in a direction away from the first surface 101a.

[0047] According to the embodiments of the present application, Figure 1 As shown, the solar cell of the present application further includes a first passivation layer 102, which is located between the semiconductor substrate 101 and the first carrier selection layer 103. The first passivation layer 102 is suitable for passivating the dangling bonds on the surface of the crystalline silicon to reduce the contact recombination loss. Of course, the first passivation layer 102 may not be provided, and the oxygen in the first carrier selection layer may be directly used to passivate the dangling bonds on the surface of the crystalline silicon to reduce the contact recombination loss.

[0048] According to an embodiment of the present application, further optionally, the material of the first passivation layer 102 may include silicon oxide, aluminum oxide, amorphous silicon, etc., but is not limited thereto. It may be prepared by atomic layer deposition (ALD for short), vacuum evaporation, electron beam deposition or chemical vapor deposition (CVD for short).

[0049] According to an embodiment of the present application, the projection of the first intermediate conductive layer 104 and / or the second carrier selection layer 105 on the semiconductor substrate 101 is located within the projection of the first carrier selection layer 103 on the semiconductor substrate 101. As a result, the first intermediate conductive layer 104 is not in direct contact with the semiconductor substrate 101, which is beneficial for the first carrier selection layer 103 and the second carrier selection layer 105 to play a role of selective contact.

[0050] Further optionally, the first carrier selection layer 103 covers the first surface 101a of the semiconductor substrate 101, and the first intermediate conductive layer 104 and / or the second carrier selection layer 105 can be located on a local surface of the first carrier selection layer 103 away from the semiconductor substrate 101, which is beneficial to improving the electrical transmission performance.

[0051] By way of example, the locally disposed first intermediate conductive layer 104 or second carrier selection layer 105 is further described. Figure 2 FIG. 1 is a schematic diagram of a partial structure of a solar cell according to another embodiment of the present application. Figure 2 As shown, Figure 1 The main difference of the solar cell with the structure shown is that the first surface 101a of the semiconductor substrate 101 includes an electrode region A and a non-electrode region B; the projection of the first carrier selection layer 103 on the semiconductor substrate 101 covers the first surface 101a; and the projections of the first intermediate conductive layer 104 and the second carrier selection layer 105 on the semiconductor substrate 101 are located within the electrode region A.

[0052] The first carrier selection layer 103 is disposed on the entire first surface 101a of the semiconductor substrate 101 to play a selective contact role, and the first intermediate conductive layer 104 and the second carrier selection layer 105 are disposed in the electrode region to improve the electrical transmission performance.

[0053] The above-mentioned "electrode region" refers to a region that can be used to form an electrode, so that the electrode can contact the second carrier selection layer 105 in the region. This is in consideration of the accuracy of the electrode manufacturing process, so the electrode region includes a region where the electrode position can be reasonably adjusted.

[0054] According to an embodiment of the present application, the contact position of the electrode 106 is preferably on the surface of the second carrier selection layer 105 away from the semiconductor substrate 101 or stays in the second carrier selection layer 1.5, but is not limited to this. The electrode 106 can contact any one of the first carrier selection layer 103, the first intermediate layer 104 or the second carrier selection layer 105.

[0055] According to the embodiments of the present application, the above-mentioned selective passivation contact structure of the present application can be more widely suitable for various types of solar cells, and can be used alone to form a double-sided contact or back-contact solar cell; or, it can also be used in combination with a tunneling oxidation passivation contact structure, a direct doping in a silicon substrate, or a heterojunction passivation contact structure to form a double-sided contact or back-contact solar cell.

[0056] For example, taking a double-sided contact solar cell as an example, Figure 3 is a schematic diagram of the complete structure of a solar cell according to an embodiment of the present application, Figure 4 FIG. 1 is a schematic diagram of the complete structure of a solar cell according to another embodiment of the present application. Figure 3 and Figure 4 As shown, on the basis of the aforementioned selective passivation contact structure, the solar cell of the present application further includes a second passivation layer 107 and a third carrier selection layer 108, wherein the second passivation layer 107 is located on the second surface 101b of the semiconductor substrate 101; the third carrier selection layer 108 is located on the surface of the second passivation layer 107 away from the semiconductor substrate 101, wherein the conductivity type of the third carrier selection layer 108 is different from the conductivity type of the first carrier selection layer 103. The passivation contact structure formed by the second passivation layer 107 and the third carrier selection layer 108 can be a tunneling oxidation passivation contact structure, a structure directly doped in a silicon substrate, or a heterojunction passivation contact structure, and can be used for the front or back of the battery.

[0057] Further optionally, the material of the second passivation layer 107 is the same as or different from that of the first passivation layer 102, and the material of the second passivation layer 107 may include silicon oxide, aluminum oxide, amorphous silicon, etc., but is not limited thereto. The material of the third carrier selection layer 108 may include at least one of amorphous silicon, polycrystalline silicon, microcrystalline silicon, and nanocrystalline silicon, but is not limited thereto.

[0058] For ease of understanding, taking the case where the material of the second passivation layer 107 includes silicon oxide or aluminum oxide and the material of the third carrier selection layer 108 includes polysilicon as an example, the second passivation layer 107 and the third carrier selection layer 108 can form a tunneling oxide passivation contact structure.

[0059] At this time, the solar cell may further include a first passivation anti-reflection layer 109a located on the surface of the third carrier selection layer 108 away from the semiconductor substrate 101; the electrode 106 located on the second surface 101b contacts the third carrier selection layer 108 through the first passivation anti-reflection layer 109a.

[0060] For another example, taking the case where the material of the second passivation layer 107 includes intrinsic amorphous silicon and the material of the third carrier selection layer 108 includes doped amorphous silicon or microcrystalline silicon, the second passivation layer 107 and the third carrier selection layer 108 form a heterojunction passivation contact structure. Figure 4 As shown, the solar cell may further include a transparent conductive layer 109 b located on a surface of the third carrier selection layer 108 away from the semiconductor substrate 101 .

[0061] Further optionally, according to the material selected for the second passivation layer 107, a suitable thickness can be set to achieve a passivation effect. Specifically, taking the second passivation layer 107 as a silicon oxide layer as an example, its thickness can be 1~2.5 nm, for example, 1nm, 1.5 nm, 2 nm, 2.5 nm, etc.; taking the second passivation layer 107 as an intrinsic amorphous silicon layer as an example, its thickness can be 5~30 nm, for example, 5 nm, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, etc., which are not listed one by one here.

[0062] Similarly, the material selected for the third carrier selection layer 108 can be set to a suitable thickness to achieve selective contact. Specifically, taking the third carrier selection layer 108 as a doped amorphous silicon layer as an example, its thickness can be 10~50nm, for example, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, etc., which are not listed one by one here.

[0063] For example, taking a back-contact solar cell as an example, Figure 5FIG. 1 is a schematic diagram of the complete structure of a solar cell according to another embodiment of the present application. Figure 5 As shown, based on the aforementioned selective passivation contact structure, the first surface 101a of the semiconductor substrate 101 includes a first region and a second region arranged at intervals, and the first carrier selection layer 103 is located on the first region of the semiconductor substrate. One of the first region and the second region is a minority region, and the other is a majority region.

[0064] The solar cell of the present application may also include a second passivation layer 107 and a third carrier selection layer 108, wherein: the second passivation layer 107 is located on the second region of the semiconductor substrate 101; the third carrier selection layer 108 is located on the surface of the second passivation layer 107 away from the semiconductor substrate 101, wherein the conductivity type of the third carrier selection layer 108 is different from the conductivity type of the first carrier selection layer 103.

[0065] The materials and thicknesses of the second passivation layer 107 and the third carrier selection layer 108 in this example are similar to those described above and will not be described in detail herein. Figure 5 As shown, the second passivation layer 107 and the first passivation layer 102 may be the same film layer, covering the first surface 101a of the semiconductor substrate 101.

[0066] Further optionally, if Figure 5 As shown, the solar cell of the present application may further include a second passivation anti-reflection layer 110 formed on the second surface 101b of the semiconductor substrate 101. The first passivation anti-reflection layer 109a and the second passivation anti-reflection layer 110 may include silicon nitride (SiNx) or aluminum oxide / SiNx stacked films.

[0067] For example, Figure 3 , 4 The second passivation layer 107 and the third carrier selection layer 108 of the solar cell shown in Figure 5 can also be replaced as a whole by the selective passivation contact structure of this application, or the second passivation layer 107, the third carrier selection layer 108 and the transparent conductive layer 109b can be replaced as a whole by the selective passivation contact structure of this application. In this way, by using the selective passivation contact structure of the present application alone, a double-sided contact or back-contact solar cell is formed. For example, with one end as the N region and the other end as the P region, a high oxygen content MoOx-InAlN-low oxygen content MoOx-silicon oxide-crystalline silicon-silicon oxide-AZO (low doping)-InAlN-AZO (high doping) structure is formed, wherein x is 2.85, the high oxygen content molybdenum oxide is not less than 2.85, and the low oxygen content molybdenum oxide is not more than 2.85.

[0068] According to another embodiment of the present application, a photovoltaic assembly is provided, comprising a plurality of the above-mentioned solar cells and a packaging structure, wherein the plurality of solar cells are connected into a solar cell string, and the packaging structure is disposed around the periphery of the solar cell string.

[0069] According to an embodiment of the present application, the packaging structure may include, for example, a glass panel, an adhesive film and a back panel, wherein the glass panel is located on one side of the solar cell string, and the back panel is located on the other side of the solar cell string, both of which play a protective role, wherein at least one of the two surfaces is a light-receiving surface; the adhesive film is an adhesive film between the solar cell string and the glass panel and the back panel, which plays a role of bonding and fixing, and a transparent material must be used.

[0070] According to the embodiments of the present application, the solar cells and photovoltaic modules of the present application, when using the selective passivation contact structure provided by the present application, help to improve the passivation contact effect and the electrical transmission effect, thereby improving the photoelectric conversion efficiency of the solar cells and photovoltaic modules.

[0071] The following lists a number of specific embodiments to illustrate the technical solution of the present invention in detail. It should be noted that the specific embodiments below are only used for illustration and are not used to limit the present invention.

[0072] Example 1

[0073] like Figure 4 As shown, the method for preparing a solar cell provided in this embodiment includes:

[0074] 1. Silicon wafer cleaning

[0075] The semiconductor substrate 101 is a single crystal silicon wafer (N type) with a front surface. The substrate is cleaned using a standard RCA (Radio Corporation of America) cleaning process, then repeatedly rinsed with deionized water, and dried with nitrogen for later use.

[0076] 2. Preparation of intrinsic amorphous silicon passivation layer

[0077] PECVD (chemical vapor deposition) is used to deposit an intrinsic amorphous silicon layer with a thickness of 5 nm on the front and back sides of the N-type silicon substrate, covering the entire structure, serving as the first passivation layer 102 and the second passivation layer 107 respectively. The specific preparation process is prior art and will not be repeated here.

[0078] 3. Preparation of electron selective passivation contact structure (front):

[0079] An N-type aluminum-doped zinc oxide layer as a first carrier selection layer 103, titanium nitride as an intermediate conductive layer 104, and an N-type aluminum-doped zinc oxide layer as a second carrier selection layer 105 are sequentially prepared on the intrinsic amorphous silicon layer on the front side. Specifically:

[0080] 3.1. The first carrier selection layer 103 is prepared by ALD method with a deposition thickness of 5 nm. The preparation conditions are:

[0081] The deposition temperature was 200°C, and the precursors were diethyl zinc, trimethyl aluminum, and deionized water. The diethyl zinc pulse was 0.2 seconds, nitrogen purge was 10 seconds, deionized water pulse was 0.2 seconds, and nitrogen purge was 10 seconds. The trimethyl aluminum pulse was 0.2 seconds, and nitrogen purge was 10 seconds. The deionized water pulse was 0.2 seconds, and nitrogen purge was 10 seconds. The cycle ratio of diethyl zinc to trimethyl aluminum was 24:1.

[0082] 3.2. The intermediate conductive layer 104 is prepared by ALD with a deposition thickness of 1.3 nm. The preparation conditions are:

[0083] The deposition temperature is 80°C, and the precursors are tetrakis(dimethylamino)titanium (TDMAT) and ammonia (NH3). Tetrakis(dimethylamino)titanium needs to be heated to 50°C in advance and carried into the ALD chamber by argon gas. Tetrakis(dimethylamino)titanium (TDMAT) pulse is 2s, vacuum cleaning is 9s, ammonia plasma action (500W) is 6s, and vacuum cleaning is 9s.

[0084] 3.3. The second carrier selection layer 105 is prepared by ALD method with a deposition thickness of 5 nm. The preparation conditions are:

[0085] The deposition temperature was 200°C, and the precursors were diethyl zinc, trimethyl aluminum, and deionized water. The diethyl zinc pulse was 0.2 seconds, nitrogen purge was 10 seconds, deionized water pulse was 0.2 seconds, and nitrogen purge was 10 seconds. The trimethyl aluminum pulse was 0.2 seconds, and nitrogen purge was 10 seconds. The deionized water pulse was 0.2 seconds, and nitrogen purge was 10 seconds. The cycle ratio of diethyl zinc to trimethyl aluminum was 24:1.

[0086] 4. Preparation of hole selective contact layer (back side):

[0087] A P-type doped silicon layer, such as a P-type amorphous silicon, nanocrystalline silicon or microcrystalline silicon layer, is deposited on the intrinsic amorphous silicon layer on the back side by PECVD as the third carrier selection layer 108 with a thickness of 10 nm. The doping element boron in the P-type doped silicon layer has a specific preparation process that is prior art and will not be described in detail here.

[0088] 5. TCO preparation (back side):

[0089] A transparent conductive (TCO) layer 109b is prepared on the P-type doped silicon layer by PVD. The thickness of the transparent conductive layer 109b is 80nm, and the target material used for the transparent conductive layer includes but is not limited to indium tin oxide (ITO), aluminum-doped zinc oxide (AZO), and tungsten-doped indium oxide (IWO). The specific preparation process is existing technology and will not be repeated here.

[0090] 6. Electrode Preparation

[0091] The front / back silver electrodes were screen printed and dried at 180 degrees Celsius to complete the electrode 106 preparation.

[0092] Example 2

[0093] like Figure 3 As shown, the method for preparing a solar cell provided in this embodiment includes:

[0094] 1. Silicon wafer cleaning

[0095] The sample substrate is a single crystal silicon wafer (N type) with a front plane. The substrate is cleaned using a standard RCA (Radio Corporation of America) cleaning process, then rinsed repeatedly with deionized water, and dried with nitrogen gas for later use.

[0096] 2. Silicon oxide layer preparation

[0097] A silicon oxide layer with a thickness of 1.6 nm is prepared on the front and back sides of the N-type silicon substrate by thermal oxidation, covering the entire structure, respectively serving as the first passivation layer 102 and the second passivation layer 107. The specific preparation process is prior art and will not be described in detail here.

[0098] 3. Preparation of electron selective contact structure (back side):

[0099] An N-type doped polysilicon layer is deposited on the silicon oxide layer on the back side by PECVD as the third carrier selection layer 108. The thickness of the deposited N-type doped polysilicon layer is 70 nm and is doped with phosphorus. The specific preparation process is prior art and will not be described in detail here. An aluminum oxide / silicon nitride passivation anti-reflection layer is then formed on the N-type doped polysilicon layer as the first passivation anti-reflection layer 109a.

[0100] 4. Preparation of hole selective passivation contact structure (front):

[0101] A nickel oxide layer as the first carrier selection layer 103, a molybdenum nitride layer as the intermediate conductive layer 104, and a molybdenum oxide layer as the second carrier selection layer 105 are sequentially prepared on the front silicon oxide layer. Specifically:

[0102] 4.1. The first carrier selection layer is prepared by ALD method with a deposition thickness of 3 nm. The preparation conditions are:

[0103] The deposition temperature was 170 °C, the precursors were nickel chloride and deionized water, the nickel oxide pulse was 1 s, the nitrogen purge was 10 s, the deionized water pulse was 0.5 s, and the nitrogen purge was 10 s.

[0104] 4.2. The intermediate conductive layer 104 is prepared by ALD with a deposition thickness of 1.3 nm. The preparation conditions are:

[0105] The deposition temperature was 200°C, and the precursors were molybdenum isopropoxide and nitrogen (N2). Molybdenum isopropoxide pulse was 0.7s, nitrogen purge was 2s, ammonia pulse was 5s, and nitrogen purge was 20s.

[0106] 4.3. The second carrier selection layer 105 is deposited by ALD with a thickness of 7 nm. The preparation conditions are:

[0107] The evaporation temperature was 110°C, and molybdenum pentachloride (MoCl5) and deionized water were used as precursors. The cycle was: 0.1s of molybdenum chloride, followed by nitrogen purge for 20s, 0.05s of deionized water, followed by nitrogen purge for 20s.

[0108] 5. Electrode Preparation

[0109] The front / back silver electrodes are screen printed and dried to complete the preparation of electrode 106.

[0110] Example 3

[0111] like Figure 5 As shown, the method for preparing a solar cell provided in this embodiment includes:

[0112] 1. Silicon wafer cleaning

[0113] The sample substrate is a single crystal silicon wafer (N type) 5 with a flat front surface. The substrate is cleaned using a standard RCA (Radio Corporation of America) cleaning process, then rinsed repeatedly with deionized water, and dried with nitrogen for later use.

[0114] 2. Preparation of intrinsic amorphous silicon passivation layer

[0115] An intrinsic amorphous silicon layer with a thickness of 5 nm is deposited on an N-type silicon substrate by PECVD (chemical vapor deposition), covering the entire structure and serving as the first passivation layer 102 and the second passivation layer 107. The specific preparation process is prior art and will not be described in detail here.

[0116] 3. Preparation of electron selective contact layer (back side):

[0117] An N-type doped silicon layer, such as an N-type amorphous silicon layer, nanocrystalline silicon layer or microcrystalline silicon layer, is deposited on a portion of the intrinsic amorphous silicon layer by PECVD as the third carrier transport layer 108. The thickness of the deposited N-type doped silicon layer is 10 nm, wherein the doping element phosphorus in the N-type doped silicon layer, and the specific preparation process is prior art and will not be repeated here.

[0118] 4. TCO preparation:

[0119] A transparent conductive layer 109b is prepared on the N-type doped silicon layer by magnetron sputtering. The thickness of the transparent conductive layer 109b is 80nm. The target material used for the transparent conductive film layer includes but is not limited to ITO, AZO, and IWO. The specific preparation process is prior art and will not be repeated here.

[0120] 5. Preparation of hole selective passivation contact structure (back side):

[0121] A molybdenum oxide layer (MoO 2.78 ) as the first carrier selection layer 103, a molybdenum nitride layer as the intermediate conductive layer 104, and a molybdenum oxide layer (MoO 2.95 ) as the second carrier selection layer 105, specifically:

[0122] 5.1. The first carrier selection layer 103 is prepared by vacuum evaporation method with a deposition thickness of 5 nm. The preparation conditions are:

[0123] The preparation conditions are as follows: dry molybdenum oxide is placed in a graphite crucible. The MoO3 target sample is heated by an electron beam collimated by a tungsten filament DC heating cathode. Under the conditions of an acceleration voltage of 5 kV and a power density of about 1.5 kW / cm2, the molybdenum oxide evaporates and is deposited on the substrate in the form of a thin film.

[0124] 5.2. The intermediate conductive layer 104 is prepared by ALD with a deposition thickness of 2 nm. The preparation conditions are:

[0125] The preparation was carried out at 225°C, using molybdenum hexacarbonyl and ammonia as precursors. The molybdenum hexacarbonyl was heated to 45°C before entering the chamber, with a molybdenum hexacarbonyl pulse of 10 seconds, an argon purge of 10 seconds, an ammonia pulse of 10 seconds, and an argon pulse of 10 seconds.

[0126] 5.3. The second carrier selection layer 105 is prepared by vacuum evaporation with a thickness of 8 nm. The preparation conditions are:

[0127] The preparation is carried out by vacuum evaporation method, and the preparation method is consistent with the preparation conditions of the first carrier selection layer 103 .

[0128] 6. Anti-reflection layer preparation (front):

[0129] A silicon nitride anti-reflection layer with a thickness of about 100 nm is prepared on the front side by PECVD. This technology is prior art and will not be described in detail.

[0130] 7. Electrode Preparation

[0131] The front / back silver electrodes were screen printed and dried at 180 degrees Celsius to complete the preparation of electrode 106.

[0132] Comparative Example 1

[0133] Similar to Example 1, the only difference is that the electron selective passivation contact structure (front side) is replaced by an N-type doped silicon layer and a TCO layer. Specifically:

[0134] An N-type doped silicon layer, such as an N-type amorphous silicon layer, a nanocrystalline silicon layer or a microcrystalline silicon layer, is sequentially prepared on the front intrinsic amorphous silicon layer, with a thickness of 70 nm, wherein the doping element in the N-type doped silicon layer is phosphorus. The specific preparation process is prior art and will not be repeated here.

[0135] The preparation conditions of the front TCO layer and the back TCO layer are the same, which will not be described in detail here.

[0136] Comparative Example 2

[0137] Similar to Example 3, the only difference is that the hole selective passivation contact structure (back side) is replaced by a P-type doped silicon layer and a TCO layer. Specifically:

[0138] A P-type doped silicon layer, such as a P-type amorphous silicon, nanocrystalline silicon or microcrystalline silicon layer, is deposited on the intrinsic amorphous silicon layer on the back side by PECVD, with a thickness of 50 nm, wherein the doping element in the P-type doped silicon layer is boron. The specific preparation process is prior art and will not be repeated here.

[0139] The preparation conditions of the TCO layer located on the P-type doped silicon layer are the same as those of the TCO layer located on the N-type doped silicon layer, which will not be described in detail here.

[0140] In AM1.5 standard spectrum, 25℃, 1000W / m 2 The battery is tested for current and voltage under light intensity.

[0141] The battery performance of Examples 1 to 3 and Comparative Examples 1 to 2, such as open circuit voltage (Voc), short circuit current (Isc), fill factor (FF), series resistance (Rsr), parallel resistance (Rsh) and battery conversion efficiency (Eta) were tested under standard test conditions, wherein battery conversion efficiency = (open circuit voltage*short circuit current*fill factor) / (battery area*light amplitude)*100%. The test method is briefly described as follows, and the results are shown in Table 1 below.

[0142] Table 1

[0143]

[0144] As can be seen from Table 1 above, the selective passivation contact structure of the present application can improve the electrical and optical performance of the battery. By comparing the results of Examples 1 and 2 with Comparative Example 1, the current of the battery has been significantly improved, indicating that the structure can reduce light parasitic absorption, increase the proportion of light entering crystalline silicon, and increase its current. By comparing the results of Example 3 with Comparative Example 2, the selective passivation contact structure of the present application can effectively improve the passivation effect and selective contact performance, reduce the internal resistance of the battery, and improve the battery performance.

[0145] The specific embodiments described above further illustrate the purpose, technical solutions and beneficial effects of the present application. It should be understood that the above description is only a specific embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should be included in the scope of protection of the present application.

Claims

1. A solar cell comprising: A semiconductor substrate including a first surface and a second surface opposite to each other; A first carrier selection layer, located on the first surface of the semiconductor substrate, wherein the material of the first carrier selection layer comprises a transition metal oxide; A first intermediate conductive layer, located on a surface of the first carrier selection layer away from the semiconductor substrate, wherein the material of the first intermediate conductive layer comprises metal nitride or metal sulfide, and the thickness of the first intermediate conductive layer is 0.2 nm to 10 nm; A second carrier selection layer is located on a surface of the first intermediate conductive layer away from the semiconductor substrate, wherein the material of the second carrier selection layer comprises a transition metal oxide of the same conductivity type as that of the first carrier selection layer; as well as an electrode, located on a surface of the second carrier selection layer away from the semiconductor substrate; The sum of the thicknesses of the first carrier selection layer and the second carrier transport layer is less than 70 nm, preferably 4 nm to 10 nm; and / or the doping concentrations of the first carrier selection layer and the second carrier transport layer are less than or equal to 1×10 21 atom / cm 3 .

2. The solar cell according to claim 1, wherein: The thickness of the second carrier transport layer is greater than or equal to the thickness of the first carrier transport layer; and / or, The thickness of the first intermediate conductive layer is 2-3 nm.

3. The solar cell according to claim 1, wherein: The first carrier selection layer and the second carrier selection layer are each independently selected from at least one of doped or undoped zinc oxide, tin oxide, molybdenum oxide, titanium oxide, nickel oxide, gallium oxide, indium oxide, copper oxide, magnesium oxide, aluminum oxide, tungsten oxide, cerium oxide, manganese oxide, vanadium oxide, chromium oxide, cobalt oxide, germanium oxide, cadmium oxide, and rhenium oxide; The first intermediate conductive layer is selected from at least one of doped or undoped titanium nitride, molybdenum nitride, zirconium nitride, gallium nitride, nickel nitride, and tungsten nitride.

4. The solar cell according to any one of claims 1 to 3, wherein: The first carrier selection layer and the second carrier selection layer are N-type materials, and the work function of the material of the second carrier selection layer is less than or equal to the work function of the material of the first carrier selection layer; or The first carrier selection layer and the second carrier selection layer are P-type materials, and the work function of the material of the second carrier selection layer is greater than or equal to the work function of the material of the first carrier selection layer.

5. The solar cell according to claim 4, wherein: The work function of the material of the first intermediate conductive layer is between the first carrier selection layer and the second carrier selection layer.

6. The solar cell according to claim 4, wherein: The semiconductor substrate is a crystalline silicon substrate, and the second carrier transport layer is an N-type material with a work function less than or equal to 4.5 eV, or a P-type material with a work function greater than or equal to 4.8 eV.

7. The solar cell according to claim 1, wherein: The resistivity of the first intermediate conductive layer is 10 -5 Ω·m order of magnitude, the resistivity of the first carrier transport layer and the second carrier transport layer is 10 -1 ~10 -3 Ω·m order of magnitude.

8. The solar cell according to claim 1, further comprising: The first passivation layer is located between the semiconductor substrate and the first carrier selection layer.

9. The solar cell according to claim 1, wherein: The projection of the first intermediate conductive layer and / or the second carrier selection layer on the semiconductor substrate is located within the projection of the first carrier selection layer on the semiconductor substrate.

10. The solar cell according to claim 9, wherein: The first surface of the semiconductor substrate includes an electrode area and a non-electrode area; The projection of the first carrier selection layer on the semiconductor substrate covers the first surface; Projections of the first intermediate conductive layer and the second carrier selection layer on the semiconductor substrate are located within the electrode region.

11. The solar cell according to claim 1, wherein: At least one of the first carrier selection layer, the first intermediate conductive layer and the second carrier selection layer is made of non-doped material.

12. The solar cell according to claim 1, wherein: At least one of the first carrier selection layer and the second carrier selection layer has a nanocrystalline or microcrystalline structure penetrating along a thickness direction.

13. The solar cell according to claim 1, further comprising: A second passivation layer is located on the second surface of the semiconductor substrate; A third carrier selection layer is located on a surface of the second passivation layer away from the semiconductor substrate, wherein the conductivity type of the third carrier selection layer is different from the conductivity type of the first carrier selection layer.

14. The solar cell according to claim 1, wherein: The first surface of the semiconductor substrate comprises a first region and a second region which are spaced apart from each other, and the first carrier selection layer is located on the first region of the semiconductor substrate; The solar cell further comprises: A second passivation layer, located on the second region of the semiconductor substrate; A third carrier selection layer is located on a surface of the second passivation layer away from the semiconductor substrate, wherein the conductivity type of the third carrier selection layer is different from the conductivity type of the first carrier selection layer.

15. A photovoltaic module, comprising: A plurality of solar cells according to any one of claims 1 to 14, connected into a solar cell string; as well as The packaging structure is arranged around the outer periphery of the solar cell string.

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