A topcon cell structure and a method of fabricating the same

Abstract

The application provides a Topcon battery structure and a preparation method thereof, and relates to the technical field of solar cells, and comprises a semiconductor substrate, a second conductive type semiconductor region is arranged on one side of the semiconductor substrate, a second passivation layer A is arranged on the side, away from the second conductive type semiconductor region, of the second conductive type semiconductor region, a second passivation layer B is arranged on the side, away from the second conductive type semiconductor region, of the second passivation layer A, an ultrathin amorphous silicon layer is arranged on the side, away from the second conductive type semiconductor region, of the semiconductor substrate, a tunneling layer is arranged on the side, away from the semiconductor substrate, of the ultrathin amorphous silicon layer, a first conductive type semiconductor region is arranged on the side, away from the tunneling layer, of the first conductive type semiconductor region, and a first passivation layer is arranged on the side, away from the tunneling layer, of the first conductive type semiconductor region. In the application, the ultrathin amorphous silicon layer is arranged, so that the lattice mismatch problem between the semiconductor substrate and the tunneling layer can be relieved, the generation of interface defects can be reduced, and the performance and reliability of the Topcon battery are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of solar cells, in particular to a Topcon cell structure and a preparation method thereof. BACKGROUND

[0002] The back structure of the Topcon cell mainly consists of an ultrathin silicon oxide layer and a doped polysilicon layer, which together form a passivation contact structure.

[0003] A TOPCon solar cell is disclosed in a Chinese patent with the authorization announcement number CN117542915B, which comprises a cell sheet composed of, from top to bottom, a front anti-reflection layer, a front passivation layer, an emitter, a silicon substrate layer, an ultrathin tunneling silicon dioxide layer, a polysilicon layer back passivation layer, and a back anti-reflection layer. The TOPCon solar cell device designed by the present application can quickly transfer heat to the heat conduction sheet using the insulating heat conduction layer and the heat conduction support layer, and then use the heat conduction sheet and the heat exchange sheet to exchange heat with the external water flow for rapid heat dissipation and cooling. At the same time, it can also take advantage of the light-transmitting plate and the water flow sprayed on the light-transmitting plate to cool down, so as to quickly stabilize the temperature of the cell sheet within the ideal temperature range, effectively ensuring the conversion efficiency of the cell sheet.

[0004] Among them, the silicon substrate layer deposits a silicon dioxide layer on the back, but the above structure has the following defects: during the deposition of silicon oxide, stress may be generated between the silicon oxide and the silicon substrate layer due to the difference in thermal expansion coefficient and lattice mismatch, etc. This stress may cause the silicon substrate to deform, bend, and even cracks may occur in the silicon oxide layer, affecting the performance and reliability of the device. SUMMARY

[0005] The present application provides a Topcon cell structure and a preparation method thereof to solve at least one technical problem raised in the background art.

[0006] To solve the above technical problems, the present application discloses a Topcon cell structure, comprising: a semiconductor substrate, one side of the semiconductor substrate is provided with a second conductive type semiconductor region, the second conductive type semiconductor region is provided with a second passivation layer A away from one side of the semiconductor substrate, the second passivation layer A is provided with a second passivation layer B away from one side of the second conductive type semiconductor region, the semiconductor substrate is provided with an ultrathin amorphous silicon layer away from one side of the second conductive type semiconductor region, the ultrathin amorphous silicon layer is provided with a tunneling layer away from one side of the semiconductor substrate, the tunneling layer is provided with a first conductive type semiconductor region away from one side of the ultrathin amorphous silicon layer, and the first conductive type semiconductor region is provided with a first passivation layer away from one side of the tunneling layer.

[0007] Preferably, the thickness of the ultrathin amorphous silicon layer is 0.1-5nm, more preferably 0.1-3nm.

[0008] Preferably, the thickness of the tunneling layer is 0.1-5nm, more preferably 0.1-2.5nm.

[0009] The application also discloses a preparation method of the Topcon battery structure.

[0010] Step 1: preparing a single-side polished wafer after texturing, boron diffusion and etching as a semiconductor substrate;

[0011] Step 2: placing the semiconductor substrate into a reaction chamber;

[0012] Step 3: introducing a silicon source gas and a carrier gas into the reaction chamber to prepare an ultrathin amorphous silicon layer;

[0013] Step 4: preparing a tunneling layer on the side of the ultrathin amorphous silicon layer away from the semiconductor substrate;

[0014] Step 5: preparing a first conductive type semiconductor region on the side of the tunneling layer away from the ultrathin amorphous silicon layer;

[0015] Step 6: preparing a first passivation layer on the side of the first conductive type semiconductor region away from the tunneling layer, and then preparing a first electrode, which passes through the first passivation layer and contacts the first conductive type semiconductor region;

[0016] Step 7: preparing a second conductive type semiconductor region on the side of the semiconductor substrate away from the first conductive type semiconductor region;

[0017] Step 8: preparing a second passivation layer A on the side of the second conductive type semiconductor region away from the semiconductor substrate;

[0018] Step 9: preparing a second passivation layer B and a second electrode, which passes through the second passivation layer B, the second passivation layer A and contacts the second conductive type semiconductor region.

[0019] Preferably, in Step 2, nitrogen is introduced into the reaction chamber first, so that the pressure in the reaction chamber is consistent with the outside, and the temperature of the reaction chamber is set in a preset temperature range, then the semiconductor substrate is placed into the reaction chamber, the nitrogen introduction is stopped, and the reaction chamber is subjected to vacuum treatment.

[0020] Preferably, after the vacuum treatment, the reaction chamber is subjected to airtightness inspection, and the leakage of the reaction chamber is not more than 120mTorr per minute.

[0021] Preferably, after the airtightness inspection, the reaction chamber is subjected to temperature rising, so that the temperature in the reaction chamber reaches a deposition target temperature.

[0022] Preferably, the preparation of the first conductive type semiconductor region comprises:

[0023] The mixture gas containing the silicon source gas, the doping gas and the carrier gas is introduced into the reaction chamber to prepare the amorphous silicon layer A;

[0024] The mixture gas containing the silicon source gas, the doping gas and the carrier gas is introduced into the reaction chamber to prepare the amorphous silicon layer B;

[0025] Finally, the doped amorphous silicon is prepared, and the doped amorphous silicon is crystallized into doped polysilicon to prepare the first conductive type semiconductor region.

[0026] Preferably, the sum of the thicknesses of the amorphous silicon layer A and the amorphous silicon layer B is 30-170nm.

[0027] Preferably, the preparation of the first conductive type semiconductor region comprises: depositing polysilicon on the surface of the tunneling layer, and performing a doping process on the polysilicon to become doped polysilicon to prepare the first conductive type semiconductor region.

[0028] The technical scheme of the present application has the following advantages: the present application provides a Topcon battery structure and a preparation method thereof, and relates to the technical field of solar cells, comprising a semiconductor substrate, a second conductive type semiconductor region is arranged on one side of the semiconductor substrate, a second passivation layer A is arranged on the side of the second conductive type semiconductor region away from the semiconductor substrate, a second passivation layer B is arranged on the side of the second passivation layer A away from the second conductive type semiconductor region, an ultrathin amorphous silicon layer is arranged on the side of the semiconductor substrate away from the second conductive type semiconductor region, a tunneling layer is arranged on the side of the ultrathin amorphous silicon layer away from the semiconductor substrate, a first conductive type semiconductor region is arranged on the side of the tunneling layer away from the ultrathin amorphous silicon layer, and a first passivation layer is arranged on the side of the first conductive type semiconductor region away from the tunneling layer. In the present application, by arranging the ultrathin amorphous silicon layer, the lattice mismatch problem between the semiconductor substrate and the tunneling layer can be relieved, and the generation of interface defects can be reduced, so that the performance and reliability of the Topcon battery are improved.

[0029] Other features and advantages of the present application will be set forth in the following description, and in part will become apparent to those skilled in the art from the description, or can be learned by practice of the present application. The objects and other advantages of the present application can be achieved and obtained by means of the instrumentalities particularly pointed out in the written description and the appended drawings.

[0030] The technical scheme of the present application will be further described in detail below with the aid of the drawings and examples. BRIEF DESCRIPTION OF DRAWINGS

[0031] The accompanying drawings are included to provide a further understanding of the present application, and constitute a part of the specification, illustrate embodiments of the present application and explain the present application together with the written description, and do not constitute a limitation on the present application. In the drawings:

[0032] Figure 1 It is a schematic diagram of a Topcon battery structure of the present application;

[0033] Figure 2 The structure schematic diagram of the air supply device in the application;

[0034] Figure 3 The structure schematic diagram of the air inlet box in the application;

[0035] Figure 4 The structure schematic diagram of the air injection pipe in the application;

[0036] Figure 5 The structure schematic diagram of the rotating cylinder in the application.

[0037] In the figure: 1, semiconductor substrate; 2, second conductive type semiconductor region; 3, second passivation layer A; 4, second passivation layer B; 5, ultra-thin amorphous silicon layer; 6, tunneling layer; 7, first conductive type semiconductor region; 8, first passivation layer; 9, air inlet box; 10, air injection pipe; 11, injection pipe; 12, reaction chamber; 13, rotating disc; 14, sliding frame; 15, sliding column; 16, driving rod; 17, piston block; 18, air inlet cavity; 19, first air inlet pipe; 20, second air inlet pipe; 21, air outlet pipe; 22, rotating shaft; 23, blade; 24, rotating column; 25, helical guide groove; 26, rotating cylinder; 27, communication hole; 28, driving piece; 29, sliding block; 30, reciprocating screw rod; 31, filter screen. DETAILED DESCRIPTION

[0038] The preferred embodiments of the present application will be described herein below with reference to the drawings; it is to be noted that the preferred embodiments described herein are intended to explain and illustrate the present application, and are not intended to limit the present application.

[0039] In addition, the description such as "first", "second" and the like in the present application is only for the purpose of description, and does not mean to particularly indicate the order or sequence, nor to limit the present application, which is merely to distinguish the components or operations described by the same technical terms, and cannot be understood as indicating or implying the relative importance of the indicated technical features or implying the number of the indicated technical features. Therefore, the features defined as "first", "second" can explicitly or implicitly include at least one of the features. In addition, the technical solutions and technical features of various embodiments can be combined with each other, but it must be based on the realization of a person skilled in the art, when the combination of technical solutions appears to be contradictory or unachievable, it should be considered that the combination of technical solutions does not exist, nor within the protection scope required by the present application.

[0040] The embodiment of the present application provides a Topcon battery structure, such as Figure 1As shown, including: semiconductor substrate 1, one side of semiconductor substrate 1 is provided with a second conductive type semiconductor region 2, the second conductive type semiconductor region 2 is provided with a second passivation layer A3 away from the side of the semiconductor substrate 1, the second passivation layer A3 is provided with a second passivation layer B4 away from the side of the second conductive type semiconductor region 2, the semiconductor substrate 1 is provided with an ultrathin amorphous silicon layer 5 away from the side of the second conductive type semiconductor region 2, the ultrathin amorphous silicon layer 5 is provided with a tunneling layer 6 away from the side of the semiconductor substrate 1, the tunneling layer 6 is provided with a first conductive type semiconductor region 7 away from the side of the ultrathin amorphous silicon layer 5, the first conductive type semiconductor region 7 is provided with a first passivation layer 8 away from the side of the tunneling layer 6;

[0041] The thickness of the ultrathin amorphous silicon layer 5 is 0.1-5nm, more preferably, the thickness of the ultrathin amorphous silicon layer 5 is 0.1-3nm; the thickness of the tunneling layer 6 is 0.1-5nm, more preferably, the thickness of the tunneling layer 6 is 0.1-2.5nm;

[0042] The second passivation layer A3, the second passivation layer B4 and the first passivation layer 8 can have a single film selected from the group consisting of silicon nitride film, silicon nitride film containing hydrogen, silicon oxide film, silicon oxynitride; the film can be an aluminum oxide film, magnesium fluoride MgF2, zinc sulfide ZnS, titanium dioxide TiO2 and cerium oxide CeO2, or can have a multilayer structure in which two or more films selected from the group are combined;

[0043] The semiconductor substrate 1 can adopt a silicon substrate;

[0044] The fifth main group elements such as phosphorus (P), arsenic (As), antimony (Sb) and bismuth (Bi) are doped in the first conductive type semiconductor region 7;

[0045] The third main group elements such as boron (B), aluminum (Al), gallium (Ga) and indium (In) are doped in the second conductive type semiconductor region 2;

[0046] The tunneling layer 6 can be any one of oxide, nitride, semiconductor and conductive polymer.

[0047] The existing Topcon cell structure deposits silicon oxide on the back of the silicon substrate, which has the following defects:

[0048] 1) During the deposition of silicon oxide, stress may occur between silicon oxide and silicon substrate due to the difference in thermal expansion coefficient and lattice mismatch, etc. This stress may cause the silicon substrate to deform, bend, and even cause cracks in the tunneling layer, affecting the performance and reliability of the device;

[0049] 2) The interface between the silicon substrate and the tunneling layer has some interface states that can trap carriers, increase the recombination probability of carriers, and reduce the electrical performance of the device. For example, the interface states can cause the lifetime of the carriers to be shortened, thereby affecting the photoelectric conversion efficiency of the solar cell, etc.

[0050] 3) Silicon oxide itself is an insulator, and the tunneling of electrons therein requires overcoming a high potential barrier. Although in the case of an ultra-thin layer, the transmission of electrons can be achieved by utilizing the quantum tunneling effect, the thickness control of the tunneling layer is extremely strict. If the thickness is too thick, the probability of electron tunneling will decrease sharply, affecting the collection of current and thereby reducing the photoelectric conversion efficiency of the cell; and if the thickness is too thin, too many pinholes and other defects can be generated, reducing the passivation effect and increasing the recombination of carriers.

[0051] The Topcon cell structure of the present application sets an ultra-thin amorphous silicon layer 5 between the tunneling layer 6 and the semiconductor substrate 1, the ultra-thin amorphous silicon layer 5 has a band gap, and the difference between the band gap of the tunneling layer 6 and the band gap of the semiconductor substrate 1 is less than the difference between the band gap of the tunneling layer 6 and the band gap of the semiconductor substrate 1. When the thickness of the ultra-thin amorphous silicon layer 5 is extremely thin, the tunneling layer formed by the combination of the ultra-thin amorphous silicon layer 5 and the tunneling layer 6 can utilize the quantum tunneling effect to enable electrons to pass through the potential barrier with a high probability;

[0052] And the ultra-thin amorphous silicon layer 5 can to some extent alleviate the lattice mismatch problem between the semiconductor substrate 1 and the tunneling layer 6, reduce the generation of interface defects, and improve the performance and reliability of the Topcon cell. The structure of the ultra-thin amorphous silicon layer 5 is relatively flexible, and can to some extent adapt to the lattice structure of the semiconductor substrate 1 and the tunneling layer 6, thereby reducing the stress and defect density at the interface.

[0053] The present application also discloses a Topcon cell structure preparation method for preparing the above-mentioned Topcon cell structure, comprising the following steps:

[0054] Step 1: Prepare a single-side polished wafer that has undergone texturing, boron diffusion, and etching processes as the semiconductor substrate 1;

[0055] Step 2: Put the semiconductor substrate 1 into the reaction chamber 12;

[0056] Step 3: Introduce a silicon source gas and a carrier gas into the reaction chamber 12 to prepare the ultra-thin amorphous silicon layer 5;

[0057] Step 4: Prepare the tunneling layer 6 on the side of the ultra-thin amorphous silicon layer 5 away from the semiconductor substrate 1;

[0058] Step 5: Prepare the first conductive type semiconductor region 7 on the side of the tunneling layer 6 away from the ultra-thin amorphous silicon layer 5;

[0059] Step 6: a first passivation layer 8 is prepared on the side of the first conductive type semiconductor region 7 away from the tunneling layer 6, and then a first electrode is made, which passes through the first passivation layer and contacts the first conductive type semiconductor region;

[0060] Step 7: a second conductive type semiconductor region 2 is prepared on the side of the semiconductor substrate 1 away from the first conductive type semiconductor region;

[0061] Step 8: a second passivation layer A3 is prepared on the side of the second conductive type semiconductor region 2 away from the semiconductor substrate 1;

[0062] Step 9: a second passivation layer B and a second electrode are prepared, which passes through the second passivation layer B, the second passivation layer A and contacts the second conductive type semiconductor region.

[0063] The working principle and beneficial effects of the above technical solution are as follows: first, a semiconductor substrate 1 is prepared, which is a single-side polished wafer 1 after going through the processes of texturing, boron diffusion and etching, and the semiconductor substrate 1 can be a silicon substrate; the semiconductor substrate 1 is placed in a reaction chamber 12; a silicon source gas and a carrier gas (the carrier gas can be hydrogen) are introduced into the reaction chamber 12 to prepare an ultrathin amorphous silicon layer 5; a tunneling layer 6 is prepared on the side of the ultrathin amorphous silicon layer 5 away from the semiconductor substrate 1; a first conductive type semiconductor region 7 is prepared on the side of the tunneling layer 6 away from the ultrathin amorphous silicon layer 5; a first passivation layer 8 is prepared on the side of the first conductive type semiconductor region 7 away from the tunneling layer 6, and then a first electrode is made, which passes through the first passivation layer and contacts the first conductive type semiconductor region; a second conductive type semiconductor region 2 is prepared on the side of the semiconductor substrate 1 away from the first conductive type semiconductor region; a second passivation layer A3 is prepared on the side of the second conductive type semiconductor region 2 away from the semiconductor substrate 1; finally, a second passivation layer B4 and a second electrode are prepared according to the existing preparation process, which passes through the second passivation layer B, the second passivation layer A and contacts the second conductive type semiconductor region.

[0064] The above scheme has the following advantages:

[0065] (1) By setting an ultrathin amorphous silicon layer 5 between the tunneling layer 6 and the semiconductor substrate 1, the ultrathin amorphous silicon layer 5 has a band gap, and the difference between the band gap of the ultrathin amorphous silicon layer 5 and the tunneling layer 6 is less than the difference between the band gap of the semiconductor substrate 1 and the tunneling layer 6. When the thickness of the ultrathin amorphous silicon layer 5 is extremely thin, the tunneling layer formed by the combination of the ultrathin amorphous silicon layer 5 and the tunneling layer 6 can utilize the quantum tunneling effect to enable electrons to pass through the potential barrier with a higher probability;

[0066] (2) The ultrathin amorphous silicon layer 5 can alleviate the lattice mismatch problem between the semiconductor substrate 1 and the tunneling layer 6 to a certain extent, reducing the generation of interface defects. The structure of the ultrathin amorphous silicon layer 5 is relatively flexible and can adapt to the lattice structure of the semiconductor substrate 1 and the tunneling layer 6 to a certain extent, thereby reducing the stress and defect density at the interface; specifically,

[0067] A. The lattice constant of silicon is approximately 5.43 angstroms, while the structure of silicon oxide is more complex, and there is no single value that directly corresponds to the lattice constant of silicon. This mismatch in lattice constants is more pronounced between silicon substrates and silicon oxide because the structure and properties of silicon oxide differ significantly from those of silicon substrates.

[0068] B. Although ultrathin amorphous silicon does not have a definite single lattice constant, the disordered arrangement of its atoms suggests that its average lattice constant differs from that of the silicon substrate. However, due to the structural characteristics of amorphous silicon, it can mitigate the effects of lattice constant mismatch to some extent through structural adjustments.

[0069] C. Lattice Matching of Ultrathin Amorphous Silicon: Although amorphous silicon lacks long-range order, it still possesses a certain degree of short-range order. Within a short distance, the atomic arrangement of amorphous silicon exhibits a certain regularity, similar to the local structure of crystalline silicon. This short-range order allows amorphous silicon to achieve a certain degree of lattice matching with the silicon substrate in localized regions when in contact with it.

[0070] (3) By adjusting parameters such as the thickness and doping concentration of the ultrathin amorphous silicon layer 5 and the fabrication process of the tunneling layer 6, the performance of the tunneling layer can be precisely controlled. This allows engineers to customize the optimal tunneling layer structure according to different application requirements to meet the performance requirements of various electronic devices.

[0071] Furthermore, such as Figures 1-5 As shown, in step 3, a gas containing silicon source gas and carrier gas is introduced into the reaction chamber 12 through a ventilation device. The ventilation device includes an inlet box 9 and an injection pipe 10. The inlet box 9 is connected to the injection pipe 10 through an outlet pipe 21. An injection pipe 11 is provided at the output end of the injection pipe 10, and one end of the injection pipe 11 extends into the reaction chamber 12.

[0072] The air intake assembly is arranged in the air intake box 9, and the air intake assembly comprises a driving motor. The driving motor is arranged at the center position of the air intake box 9 and is connected with the inner wall of the air intake box 9. The output end of the driving motor is provided with a rotating disc 13. The sliding frame 14 is arranged in front of the rotating disc 13. The left and right sides of the sliding frame 14 are slidably connected with the upper and lower inner walls of the air intake box 9. The sliding column 15 is arranged in the sliding frame 14 and is slidably connected with the inner wall of the sliding frame 14. One end of the sliding column 15 is rotatably connected with the eccentric position of the rotating disc 13. The driving rods 16 are symmetrically arranged on the upper and lower sides of the sliding frame 14. The piston block 17 is arranged at the end of the driving rod 16 away from the sliding frame 14. The air intake cavity 18 is arranged at the side of the piston block 17 away from the driving motor. The first air intake pipe 19 and the second air intake pipe 20 which are in communication with the air intake cavity 18 are arranged outside the air intake box 9. The first one-way valve and the flow control valve are arranged in the first air intake pipe 19 and the second air intake pipe 20. One end of the air outlet pipe 21 is in communication with the air intake cavity 18. The second one-way valve is arranged in the air outlet pipe 21. The rotating shaft 22 is arranged at the side of the piston block 17 away from the driving motor and is rotatably connected with the piston block 17. The blades 23 are arranged on the rotating shaft 22. The rotating column 24 is rotatably arranged on the side wall of the rotating shaft 22 and is perpendicular to the rotating shaft 22. The rotating column 24 is rotatably connected with the side wall of the rotating shaft 22. The spiral guide groove 25 is arranged on the inner wall of the air intake box 9. One end of the rotating column 24 away from the rotating shaft 22 extends into the spiral guide groove 25 and is slidably connected with the inner wall of the spiral guide groove 25.

[0073] The working principle and beneficial effects of the above technical solution are as follows: the first gas inlet pipe 19 is used to deliver the silicon source gas to the gas inlet box 9, and the second gas inlet pipe 20 is used to deliver the carrier gas to the gas inlet box 9. When the gas is introduced into the reaction chamber 12, the driving motor is started to drive the rotating disc 13 to rotate, and the rotating disc 13 drives the sliding column 15 to move, and the sliding column 15 drives the sliding frame 14 to move up and down in the gas inlet box 9. When the piston block 17 moves towards the driving motor, the gas in the first gas inlet pipe 19 and the second gas inlet pipe 20 enters the gas inlet cavity 18, and the silicon source gas and the carrier gas are mixed in the gas inlet cavity 18 to form a mixed gas. When the piston block 17 moves away from the driving motor, the piston block 17 compresses the mixed gas into the gas outlet pipe 21, and the mixed gas enters the gas injection pipe 10 through the gas outlet pipe 21, and then is injected into the reaction chamber 12 through the injection pipe 11. The piston block 17 can compress the mixed gas to realize precise gas injection through the injection pipe 11, improve the gas injection efficiency, and avoid interruption of the gas injection process to ensure the gas injection effect of the reaction chamber 12. During the sliding process of the piston block 17, the piston block 17 drives the rotating shaft 22 to move, the rotating column 24 on the side wall of the rotating shaft 22 slides along the spiral guide groove 25 and drives the rotating shaft 22 to rotate, the rotating shaft 22 drives the blade 23 to rotate, and the blade 23 rotates to stir the mixed gas, improve the mixing efficiency of the silicon source gas and the carrier gas, and enhance the mixing effect of the silicon source gas and the carrier gas, thereby improving the preparation quality of the ultra-thin amorphous silicon layer 5.

[0074] Further, as shown in Figure 4 、 Figure 5 , the gas injection pipe 10 is provided with a gas injection assembly, which includes a rotating cylinder 26. The central axis of the rotating cylinder 26 is on the same straight line as the central axis of the gas injection pipe 10. The two ends of the rotating cylinder 26 are rotatably connected with the inner wall of the gas injection pipe 10. A plurality of communication holes 27 are arranged on the side wall of the rotating cylinder 26. A driving piece 28 is arranged on the outer wall of the rotating cylinder 26. The driving piece 28 is in the shape of W. The side of the driving piece 28 away from the rotating cylinder 26 is attached to the inner wall of the gas injection pipe 10. A sliding block 29 is arranged in the rotating cylinder 26. The sliding block 29 is slidably connected with the inner wall of the rotating cylinder 26. A connecting hole is arranged in the center of the sliding block 29. The sliding block 29 is drivingly connected with the outer wall of a reciprocating screw rod 30 through the connecting hole. The reciprocating screw rod 30 is arranged in the rotating cylinder 26. One end of the reciprocating screw rod 30 is fixedly connected with the inner wall of the gas injection pipe 10. A filter screen 31 and a third one-way valve are arranged in the injection pipe 11.

[0075] The working principle and beneficial effects of the above technical solution are as follows: after the mixed gas enters the gas injection pipe 10 through the gas outlet pipe 21, part of the mixed gas can push the driving piece 28 to move, the driving piece 28 drives the rotating cylinder 26 to rotate in the gas injection pipe 10, the mixed gas is stirred by rotating the driving piece 28, and the mixing effect of the mixed gas is further improved. The sliding block 29 can rotate synchronously with the rotating cylinder 26. During the rotating process, the sliding block 29 reciprocates left and right along the reciprocating wire rod 30. Part of the mixed gas enters the inside of the rotating cylinder 26 through the communication hole 27. The reciprocating sliding block 29 can push the mixed gas in the rotating cylinder 26, so that the mixed gas further collides and mixes, and the mixing effect is enhanced. Finally, the uniformly mixed gas enters the reaction chamber 12 through the filter screen 31, ensuring the smooth preparation of the ultra-thin amorphous silicon layer 5.

[0076] Embodiment 1

[0077] A method for preparing a Topcon battery structure includes:

[0078] (I) Preparation

[0079] The single-side polished wafer which has undergone texturing, boron expansion and etching processes in sequence is used as the semiconductor substrate 1.

[0080] (II) Deposition Process

[0081] 1. Nitrogen gas is introduced into the LPCVD / PECVD reaction chamber 12 at a flow rate of 5000-10000sccm, so that the pressure in the reaction chamber 12 is consistent with the outside, and the temperature of the reaction chamber 12 is set to 300-500℃;

[0082] 2. The carrier with the polished wafer is grabbed into the reaction chamber 12 by the mechanical hand, the gas flow is set to 0, and the reaction chamber 12 is vacuumized for 80-200S;

[0083] 3. The reaction chamber 12 is heated to 300-380℃;

[0084] 4. The pressure is set to 0 at the process temperature, and the airtightness of the reaction chamber 12 is checked, which requires that the air leakage per minute does not exceed 120mTorr;

[0085] 5. The reaction chamber 12 is heated to the deposition target temperature, which is preferably 350-380℃;

[0086] 6. Silicon source gas 1000-3000sccm (such as silane) and carrier gas 5000-15000sccm (such as hydrogen) are introduced into the reaction chamber 12, the reaction time is 5-50S, and an ultra-thin amorphous silicon layer 5 with a thickness of 0.1-5nm, more preferably 0.1-3nm, is prepared;

[0087] 7. Introduce oxygen source gas 8000-20000 seem (e.g. laughing gas) and silicon source gas 800-5000 seem (e.g. silane) into the reaction chamber 12 for 50-300 seconds to form the tunneling layer 6 with a thickness of 0.1-5 nm, more preferably 0.1-2.5 nm;

[0088] 8. Heat the reaction chamber 12 to 420-500°C;

[0089] 9. Introduce a mixture of silicon source gas 1000-5000 seem (e.g. silane), dopant gas 100-1000 seem (the dopant gas is a first conductive type impurity gas containing a group 5 element, such as phosphine, etc., used to control the conductive type and doping concentration of the first conductive type semiconductor region) and hydrogen 5000-20000 seem into the reaction chamber 12 to form the amorphous silicon layer A, wherein the ratio of silane to phosphine is 3-8, the reaction time is 300-800 seconds and the thickness is 10-80 nm, more preferably 20-30 nm;

[0090] 10. Introduce a mixture of silicon source gas 1000-5000 seem (e.g. silane), dopant gas 1500-5000 seem (the dopant gas is a first conductive type impurity gas containing a group 5 element, such as phosphine, etc., used to control the conductive type and doping concentration of the first conductive type semiconductor region) and hydrogen 3000-15000 seem into the reaction chamber 12 to form the amorphous silicon layer B, wherein the ratio of silane to phosphine is 0.8-5, the reaction time is 500-2000 seconds and the thickness is 20-90 nm, more preferably 60-80 nm;

[0091] 11. The sum of the thicknesses of the amorphous silicon layer A and the amorphous silicon layer B is 30-170 nm;

[0092] 12. Introduce oxygen source gas 5000-10000 seem (e.g. laughing gas) and silicon source gas 800-5000 seem (e.g. silane) into the reaction chamber 12 for 50-200 seconds to form the tunneling layer 6 to protect the inner first conductive type semiconductor region (which will be washed away in a subsequent cleaning process);

[0093] 13. Annealing process: use a quartz tube as the reaction chamber 12 to crystallize the poly-doped amorphous silicon into doped polysilicon; introduce nitrogen 5000-10000 seem into the reaction chamber 12 to make the pressure inside the reaction chamber 12 consistent with the outside pressure, and set the temperature of the reaction chamber 12 to 600-1200°C;

[0094] 14. The carrier with the poly semiconductor substrate 1 is grabbed into the reaction chamber 12 by the mechanical hand, the gas flow is set to 0, and the reaction chamber 12 is vacuumized for 80-200 seconds;

[0095] 15. The reaction chamber 12 is heated to 800-2000°C;

[0096] 16. Nitrogen gas is introduced into the reaction chamber 12 at 6000-20000 sccm, and the temperature is kept constant for 500-1500 seconds;

[0097] 17. The reaction chamber 12 is heated by 15-50°C based on the previous step;

[0098] 18. Nitrogen gas is introduced into the reaction chamber 12 at 6000-20000 sccm, and the temperature is kept constant for 2000-5000 seconds;

[0099] 19. The total temperature keeping time is 2500-8000 seconds to ensure complete crystallization;

[0100] (Three) Post-processing

[0101] According to the existing Topcon preparation process, the preparation of the first passivation layer 8, the first electrode, the second passivation layer A3, the second passivation layer B4, and the second electrode is completed respectively, and finally a Topcon battery structure is formed.

[0102] Example 2

[0103] Another method for preparing a Topcon battery structure includes:

[0104] (I) Preparation

[0105] The single-side polished wafer which has undergone texturing, boron diffusion, and etching processes is used as the semiconductor substrate 1.

[0106] (II) Deposition process

[0107] 1. Nitrogen gas is introduced into the LPCVD / PECVD reaction chamber 12 at 1000-10000 sccm to make the pressure in the reaction chamber 12 consistent with the outside, and the temperature of the reaction chamber 12 is set to 400-800°C;

[0108] 2. The carrier with the polished wafer is grabbed into the reaction chamber 12 by the mechanical hand, the gas flow is set to 0, and the reaction chamber 12 is vacuumized for 120-300 seconds;

[0109] 3. The pressure is set to 0 at the process temperature, and the airtightness of the reaction chamber 12 is checked, requiring that the air leakage per minute does not exceed 120 mTorr;

[0110] 4. The reaction chamber 12 is heated to a deposition target temperature, preferably 400-1000°C;

[0111] 5. The temperature is maintained for 200-800 seconds;

[0112] 6. The reaction chamber 12 is supplied with a silicon source gas 1000-3000 seem (e.g. silane) and a carrier gas 500-2000 seem (e.g. hydrogen) for 5-50 seconds to form a super-thin amorphous silicon layer 5 having a thickness of 0.1-5 nm, more preferably 0.1-3 nm;

[0113] 7. The reaction chamber 12 is supplied with an oxygen source gas 10000-50000 seem (e.g. oxygen) for 200-800 seconds to form a tunneling layer 6 having a thickness of 0.1-5 nm, more preferably 0.1-2.5 nm;

[0114] 8. The temperature and pressure are maintained for 200-600 seconds;

[0115] 9. The pressure is gradually reduced to a limit by vacuum pumping;

[0116] 10. The reaction chamber 12 is purged by supplying silane 200-2000 seem for 30-200 seconds;

[0117] 11. The temperature is maintained by supplying silane 2000-20000 seem for 30-300 seconds;

[0118] 12. The reaction chamber 12 is checked for tightness by setting the pressure to 0 at the process temperature, requiring no more than 120 mTorr of leakage per minute;

[0119] 13. The pressure is controlled to 100-2000 by supplying silane 1000-10000 seem and nitrogen 100-1000 seem for 10-60 seconds;

[0120] 14. The conditions are maintained for 800-3000 seconds to deposit a poly layer by pyrolysis of the silane to form SiH2 and hydrogen;

[0121] 15. The pressure is reduced to a limit by vacuum pumping, and then nitrogen 300-3000 seem is supplied to clean the furnace tube;

[0122] 16. The pressure is reduced to a limit by vacuum pumping to empty the reaction chamber 12 and reduce the temperature to 500-800°C;

[0123] 17. The pressure is equalized by supplying nitrogen 800-8000 seem to break the vacuum and the boat is removed.

[0124] 18. Phosphorus diffusion process (doping) : using quartz tube as reaction chamber 12 to dope the poly layer of polysilicon, becoming doped polysilicon; nitrogen gas is introduced into the reaction chamber 12 at 2000-10000sccm, so that the pressure in the reaction chamber 12 is consistent with the external pressure, and the temperature of the reaction chamber 12 is set at 600-1200℃;

[0125] 19. The carrier carrying the poly semiconductor substrate 1 is grabbed into the reaction chamber 12 by the mechanical hand, the gas flow is set to 0, and the reaction chamber 12 is vacuumized, the pressure is controlled at 50-500, and the time is 60-200S;

[0126] 20. The reaction chamber 12 is heated to 700-1500℃;

[0127] 21. Source gas (which can be phosphorus oxychloride) (which can be nitrogen) 800-3000sccm, oxygen 200-2000sccm, nitrogen 300-3000sccm are introduced into the reaction chamber 12, the pressure is controlled at 50-500, and the time is 400-2000S;

[0128] 22. The reaction chamber 12 is heated to 800-2000℃;

[0129] 23. Source gas (which can be phosphorus oxychloride) (which can be nitrogen) 500-2500sccm, nitrogen 800-5000sccm are introduced into the reaction chamber 12, the pressure is controlled at 50-500, and the time is 600-2000S;

[0130] 24. Source gas (which can be phosphorus oxychloride) (which can be nitrogen) 500-2500sccm, oxygen 500-5000sccm, nitrogen 800-5000sccm are introduced into the reaction chamber 12, the pressure is controlled at 100-800, and the time is 300-1000S;

[0131] 25. Source gas (which can be phosphorus oxychloride) (which can be nitrogen) 200-5000sccm, oxygen 500-5000sccm, nitrogen 500-5000sccm are introduced into the reaction chamber 12, the pressure is controlled at 300-2000, the temperature is gradually reduced to 600-1200℃, and the time is 500-5000S;

[0132] 26. Source gas (which can be phosphorus oxychloride) (which can be nitrogen) 1000-5000sccm, nitrogen 800-5000sccm are introduced into the reaction chamber 12, the pressure is controlled at 50-500, and the time is 30-600S;

[0133] 27. nitrogen is introduced into the reaction chamber 12 at 2000-10000sccm, so that the pressure in the reaction chamber 12 is consistent with the outside, while setting the temperature of the reaction chamber 12 at 600-1200℃, so that the pressure in the reaction chamber 12 is balanced after the boat is taken out;

[0134] (III) Post-processing

[0135] According to the existing Topcon preparation process, the preparation of the first passivation layer 8, the first electrode, the second passivation layer A3, the second passivation layer B4, and the second electrode is completed respectively, and finally a Topcon battery structure is formed.

[0136] In the above scheme, by arranging the ultra-thin amorphous silicon layer 5 between the tunneling layer 6 and the semiconductor substrate 1, the ultra-thin amorphous silicon layer 5 has a band gap, and the difference between the band gap of the tunneling layer 6 and the band gap of the semiconductor substrate 1 is less than the difference between the band gap of the tunneling layer 6 and the band gap of the semiconductor substrate 1. When the thickness of the ultra-thin amorphous silicon layer 5 is very thin, the tunneling layer formed by the combination of the ultra-thin amorphous silicon layer 5 and the tunneling layer 6 can utilize the quantum tunneling effect, so that electrons can pass through the potential barrier with a higher probability;

[0137] And the ultra-thin amorphous silicon layer 5 can to some extent alleviate the lattice mismatch problem between the semiconductor substrate 1 and the tunneling layer 6, reduce the generation of interface defects, and the structure of the ultra-thin amorphous silicon layer 5 is relatively flexible, which can to some extent adapt to the lattice structure of the semiconductor substrate 1 and the tunneling layer 6, thereby reducing the stress and defect density at the interface.

[0138] In the description of the present application, it should be understood that the orientation or positional relationship indicated by the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and therefore cannot be understood as indicating or implying that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application.

[0139] In the present application, unless otherwise explicitly specified and limited, the terms "mounting", "connecting", "connecting", "fixing" and the like should be understood in a broad sense, for example, it can be fixedly connected, or it can be detachably connected, or it can be integrated; it can be mechanically connected, or it can be electrically connected or in communication with each other; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the internal communication of two elements or the interaction relationship between two elements, unless otherwise explicitly limited. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0140] While embodiments of the application have been disclosed in connection with the above specification and drawings this description is not intended to limit the scope of the application and many modifications, enhancements, alternatives, and variations will become apparent to those skilled in the art from this disclosure. Accordingly, it is intended that the application not be limited to the described embodiments, but that it include all variations falling within the scope of the claims, and their equivalents.

Claims

1. A method for fabricating a Topcon battery structure, characterized in that, Includes the following steps: Step 1: Prepare a single-sided polished wafer that has undergone texturing, boron diffusion, and etching processes as a semiconductor substrate; Step 2: Place the semiconductor substrate into the reaction chamber; Step 3: Introduce a silicon source gas and a carrier gas into the reaction chamber to prepare an ultrathin amorphous silicon layer; Step 4: Prepare a tunneling layer on the side of the ultrathin amorphous silicon layer away from the semiconductor substrate; Step 5: Fabricate a semiconductor region of the first conductivity type on the side of the tunneling layer away from the ultrathin amorphous silicon layer; Step 6: Prepare a first passivation layer on the side of the first conductivity type semiconductor region away from the tunneling layer, and then fabricate a first electrode. The first electrode passes through the first passivation layer and contacts the first conductivity type semiconductor region. Step 7: Fabricate a second conductivity type semiconductor region on the side of the semiconductor substrate away from the first conductivity type semiconductor region; Step 8: Prepare a second passivation layer A on the side of the second conductivity type semiconductor region away from the semiconductor substrate; Step 9: Prepare the second passivation layer B and the second electrode, with the second electrode passing through the second passivation layer B and the second passivation layer A to contact the semiconductor region of the second conductivity type; In step 3, a gas containing silicon source gas and carrier gas is introduced into the reaction chamber through a ventilation device. The ventilation device includes an inlet box and an injection pipe. The inlet box is connected to the injection pipe through an outlet pipe. An injection pipe is provided at the output end of the injection pipe, and one end of the injection pipe extends into the reaction chamber. An intake assembly, including a drive motor, is installed inside the intake box. The drive motor is located at the center of the intake box and connected to the inner wall of the intake box. A rotating disk is installed at the output end of the drive motor, and a sliding frame is installed in front of the rotating disk. The left and right sides of the sliding frame are slidably connected to the inner wall of the intake box. A sliding column is installed inside the sliding frame and is slidably connected to the inner wall of the sliding frame. One end of the sliding column is rotatably connected to the rotating disk at an eccentric position. Drive rods are symmetrically arranged on the upper and lower sides of the sliding frame. A piston block is installed at the end of the drive rod away from the sliding frame. An intake chamber is located on the side of the piston block away from the drive motor. Outside the intake box... The unit is equipped with a first intake pipe and a second intake pipe that are connected to the intake chamber. A first one-way valve and a flow control valve are installed in both the first and second intake pipes. One end of the exhaust pipe is connected to the intake chamber. A second one-way valve is installed in the exhaust pipe. A rotating shaft is installed on the side of the piston block away from the drive motor. The rotating shaft is rotatably connected to the piston block. A blade is installed on the rotating shaft. A rotating column is rotatably installed on the side wall of the rotating shaft. The rotating column is perpendicular to the rotating shaft and is rotatably connected to the side wall of the rotating shaft. A spiral guide groove is provided on the inner wall of the intake box. The end of the rotating column away from the rotating shaft extends into the spiral guide groove and is slidably connected to the inner wall of the spiral guide groove. The Topcon battery structure includes: a semiconductor substrate, a second conductivity type semiconductor region disposed on one side of the semiconductor substrate, a second passivation layer A disposed on the side of the second conductivity type semiconductor region away from the semiconductor substrate, a second passivation layer B disposed on the side of the second passivation layer A away from the second conductivity type semiconductor region, an ultrathin amorphous silicon layer disposed on the side of the semiconductor substrate away from the second conductivity type semiconductor region, a tunneling layer disposed on the side of the ultrathin amorphous silicon layer away from the semiconductor substrate, a first conductivity type semiconductor region disposed on the side of the tunneling layer away from the ultrathin amorphous silicon layer, and a first passivation layer disposed on the side of the first conductivity type semiconductor region away from the tunneling layer.

2. The method for fabricating a Topcon battery structure according to claim 1, characterized in that, The thickness of the ultrathin amorphous silicon layer is 0.1-5nm.

3. The method for fabricating a Topcon battery structure according to claim 1, characterized in that, The thickness of the tunneling layer is 0.1-5 nm.

4. The method for fabricating a Topcon battery structure according to claim 1, characterized in that, In step 2, nitrogen gas is first introduced into the reaction chamber to make the pressure inside the reaction chamber the same as that outside. At the same time, the temperature of the reaction chamber is set within a preset temperature range. Then, the semiconductor substrate is placed into the reaction chamber, the nitrogen gas is stopped, and the reaction chamber is evacuated.

5. The method for fabricating a Topcon battery structure according to claim 4, characterized in that, After vacuuming, the reaction chamber is checked for airtightness, and the leakage rate is no more than 120 mTorr per minute.

6. The method for fabricating a Topcon battery structure according to claim 5, characterized in that, After the airtightness test is completed, the reaction chamber is heated until the temperature inside the reaction chamber reaches the target deposition temperature.

7. The method for fabricating a Topcon battery structure according to claim 1, characterized in that, Fabricating the semiconductor region of the first conductivity type includes: A mixed gas containing silicon source gas, dopant gas, and carrier gas is introduced into the reaction chamber to prepare amorphous silicon layer A; A mixed gas containing silicon source gas, dopant gas, and carrier gas is introduced into the reaction chamber to prepare amorphous silicon layer B; Finally, doped amorphous silicon was obtained, and the doped amorphous silicon was crystallized to become doped polycrystalline silicon, thus obtaining a semiconductor region of the first conductivity type.

8. The method for fabricating a Topcon battery structure according to claim 7, characterized in that, The combined thickness of amorphous silicon layer A and amorphous silicon layer B is 30-170 nm.

9. The method for fabricating a Topcon battery structure according to claim 1, characterized in that, The preparation of the first type of conductivity semiconductor region includes: depositing polycrystalline silicon on the surface of the tunneling layer, performing a doping process on the polycrystalline silicon to become doped polycrystalline silicon, and thus obtaining the first type of conductivity semiconductor region.

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