Solar cell and preparation method thereof

Abstract

The solar cell comprises a silicon substrate and a first tunneling silicon oxide layer, the first tunneling silicon oxide layer is located on one side of the silicon substrate, and in the first tunneling silicon oxide layer, Si < 1 + > / (Si < 2 + > + Si < 3 + >) is larger than 0 and smaller than or equal to 3; and the N-type polycrystalline silicon layer is positioned on one side, far away from the silicon substrate, of the first tunneling silicon oxide layer. Therefore, the compactness of the first tunneling silicon oxide layer is high, and diffusion of doped elements in the N-type polycrystalline silicon layer to the silicon substrate can be effectively relieved.

Description

Technical Field

[0001] The present application relates to the field of photovoltaics, and in particular, to solar cells and methods for preparing the same. Background Art

[0002] The tunneling oxide passivated contact (TOPCON) cell can significantly reduce the recombination of electrons and holes due to its unique tunneling characteristics of the tunneling layer, greatly increasing the cell's opening voltage and current density. In particular, the double-sided poly structure TOPCON cell has a limit efficiency of about 28.5%, which is closest to the limit efficiency of silicon at 29%. At present, there are a large number of technologies to optimize the TOPCON cell process technology. How to design an efficient double-sided poly TOPCON cell while reducing the cost brought by the process is an urgent problem to be solved.

[0003] It should be noted that the above statements are only used to provide background technical information related to the present application and do not necessarily constitute prior art. Summary of the invention

[0004] In a first aspect of the present application, the present application proposes a solar cell, comprising: a silicon substrate, a first tunneling silicon oxide layer, wherein the first tunneling silicon oxide layer is located on one side of the silicon substrate, and in the first tunneling silicon oxide layer, 0<Si 1 + / (Si 2+ +Si 3+ )≤3; N-type polysilicon layer, the N-type polysilicon layer is located on the side of the first tunneling silicon oxide layer away from the silicon substrate. Thus, the first tunneling silicon oxide layer has a high density, which can effectively alleviate the diffusion of doping elements in the N-type polysilicon layer into the silicon substrate.

[0005] In some embodiments, the solar cell further comprises: a second tunneling silicon oxide layer, the second tunneling silicon oxide layer is located on a side of the silicon substrate away from the first tunneling silicon oxide layer; and a P-type polysilicon layer, the P-type polysilicon layer is located on a side of the second tunneling silicon oxide layer away from the silicon substrate. Thus, sunlight can be absorbed from both sides of the solar cell and converted into electrical energy, thereby increasing the power generation of the battery.

[0006] In some embodiments, it further comprises: an aluminum oxide layer, the aluminum oxide layer is located on the side of the P-type polysilicon layer away from the second tunneling silicon oxide layer; and / or, a stacked passivation layer, the stacked passivation layer is located on the side of the aluminum oxide layer away from the P-type polysilicon layer, the stacked passivation layer comprises a first sub-silicon oxide layer, a sub-silicon nitride layer and a second sub-silicon oxide layer stacked; and / or, a silicon nitride layer; the silicon nitride layer is located on the side of the N-type polysilicon layer away from the first tunneling silicon oxide layer. In this way, reflection can be reduced and the passivation effect can be improved.

[0007] In some embodiments, the thickness of the first tunneling silicon oxide layer is 1nm-1.5nm, and the thickness of the N-type polysilicon layer is 110nm-250nm. Thus, the first tunneling silicon oxide layer has a good tunneling effect of carriers, and the N-type polysilicon layer can reduce the recombination during the carrier transmission process while achieving good carrier collection.

[0008] In the second aspect of the present application, the present application proposes a method for preparing the aforementioned solar cell, comprising: forming a first tunneling silicon oxide layer on one side of a silicon substrate by a first deposition process, wherein the deposition gas of the first deposition process comprises nitrous oxide and an auxiliary gas, wherein the auxiliary gas comprises at least one of hydrogen and argon, and the flow rate ratio of the auxiliary gas to the nitrous oxide is (1-4):5; forming an N-type polysilicon layer on the side of the first tunneling silicon oxide layer away from the silicon substrate by a second deposition process; and annealing the silicon substrate after the second deposition process, wherein the temperature of the annealing process is greater than or equal to 900°C. Thus, the annealing temperature of the N-type polysilicon layer can be increased to be consistent with the annealing temperature of the P-type polysilicon layer, so that the two-step annealing process can be combined into one step, which reduces both the total process time and the machine investment cost.

[0009] In some embodiments, the flow rate ratio of the auxiliary gas to the nitrous oxide is (2-3): 5. Thus, the number ratio of silicon and oxygen atoms in the first tunneling silicon oxide layer can be increased.

[0010] In some embodiments, the gas flow rate of the nitrous oxide is 8000 sccm-15000 sccm, and the gas flow rate of the auxiliary gas is 3000 sccm-6000 sccm. This helps to form a first tunneling silicon oxide layer with a high silicon-oxygen atomic ratio and reduces loss.

[0011] In some embodiments, the power of the first deposition process is 9000W-12000W; and / or the pressure of the first deposition process is 800mtorr-1500mtorr; and / or the time of the first deposition process is 60s-120s, and the temperature of the first deposition process is 430° C.-500° C. This helps to further increase the number ratio of silicon-oxygen atoms in the first tunneling silicon oxide layer.

[0012] In some embodiments, after the second deposition process, the method further includes: forming a second tunneling silicon oxide layer on the side of the silicon substrate away from the first tunneling silicon oxide layer through a third deposition process; forming a P-type polysilicon layer on the side of the second tunneling silicon oxide layer away from the silicon substrate through a fourth deposition process; and annealing the silicon substrate after the fourth deposition process. Thus, after the preparation of the P-type polysilicon layer and the N-type polysilicon layer is completed, annealing and crystallization can be completed simultaneously, which simplifies the preparation process and reduces process energy consumption.

[0013] In some embodiments, the annealing temperature is 940° C.-980° C., and the annealing time is 15 min-25 min. This helps the doping atoms migrate from the lattice gaps or substitution positions to the appropriate lattice positions, thereby activating electrical activity and improving the crystal quality of the polysilicon layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0015] Figure 1 A schematic diagram of the structure of a solar cell according to an embodiment of the present application.

[0016] Figure 2 A schematic diagram of a process for preparing a solar cell according to an embodiment of the present application.

[0017] Figure 3 This is a schematic diagram of a process for preparing a solar cell according to another embodiment of the present application.

[0018] Description of reference numerals:

[0019] Silicon substrate 100 , first tunneling silicon oxide layer 210 , second tunneling silicon oxide layer 220 , N-type polysilicon layer 310 , P-type polysilicon layer 320 , silicon nitride layer 410 , aluminum oxide layer 421 , stacked passivation layer 422 , first metal electrode 510 , second metal electrode 520 . DETAILED DESCRIPTION

[0020] The embodiments of the present application are described in detail below. Examples of the embodiments are shown in the drawings, but unnecessary detailed descriptions may be omitted. For example, detailed descriptions of well-known matters and repeated descriptions of actually identical structures may be omitted. This is to avoid the following description from becoming unnecessarily lengthy and to facilitate understanding by those skilled in the art. In addition, the drawings and the following description are provided for those skilled in the art to fully understand the present application and are not intended to limit the subject matter described in the claims.

[0021] Unless otherwise defined, all technical and scientific terms used in this application have the same meanings as those commonly understood by technicians in the technical field to which this application belongs; the terms used in this application are only for the purpose of describing specific embodiments and are not intended to limit this application; unless otherwise specified, the numerical values ​​of the parameters mentioned in this application can be measured using various measurement methods commonly used in the art (for example, they can be tested according to the methods given in the embodiments of this application).

[0022] The terms "including" and "having" in the specification and claims of the present application and any modifications thereof are open expressions, that is, including the contents specified in the present application but not excluding other contents.

[0023] In the description of this application, regardless of whether the words "about" or "approximately" are used, all the numbers disclosed herein are approximate values. The value of each number may differ by less than 10% or a reasonable difference considered by those skilled in the art, such as 1%, 2%, 3%, 4% or 5%.

[0024] "Scope" disclosed in the present application is limited in the form of lower limit and upper limit, and a given range is limited by selecting a lower limit and an upper limit, and the selected lower limit and upper limit define the boundary of a special range. The scope limited in this way can be including end values ​​or not including end values, and can be arbitrarily combined, that is, any lower limit can be combined with any upper limit to form a scope. For example, if the scope of 60-120 and 80-110 is listed for a specific parameter, it is understood that the scope of 60-110 and 80-120 is also expected. In addition, if the minimum range values ​​1 and 2 are listed, and if the maximum range values ​​3, 4 and 5 are listed, the following scope can be all expected: 1-3, 1-4, 1-5, 2-3, 2-4 and 2-5. In the present application, unless otherwise specified, the numerical range "ab" represents the abbreviation of any real number combination between a and b, wherein a and b are real numbers. For example, the numerical range "0-5" means that all real numbers between "0-5" are listed in this document, and "0-5" is just an abbreviation of these numerical combinations. In addition, when a parameter is expressed as an integer ≥ 2, it is equivalent to disclosing that the parameter is, for example, an integer of 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, etc.

[0025] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. "First feature" and "second feature" may include one or more of the features.

[0026] In the description of the present application, "A and / or B" may include the case of A alone, the case of B alone, or any of the cases of A and B, where A and B are only used for examples and may be any technical feature connected by "and / or" in the present application.

[0027] In the present application, the writing order of each step does not mean a strict execution order and does not constitute any limitation on the implementation process. The specific execution order of each step should be determined by its function and possible internal logic. If there is no special explanation, all steps of the present application can be performed sequentially or randomly, preferably sequentially. For example, the method includes steps (a) and (b), indicating that the method may include steps (a) and (b) performed sequentially, or may include steps (b) and (a) performed sequentially. For example, the method may also include step (c), indicating that step (c) can be added to the method in any order, for example, the method may include steps (a), (b) and (c), or may include steps (a), (c) and (b), or may include steps (c), (a) and (b), etc.

[0028] Unless otherwise specified, all embodiments and optional embodiments of the present application can be combined with each other to form a new technical solution.

[0029] Unless otherwise specified, all technical features and optional technical features of this application can be combined with each other to form a new technical solution.

[0030] The double-sided TOPcon cell has a theoretical conversion efficiency of 28.5%. Compared with the traditional pn junction cell, the TOPCon cell can achieve a higher open circuit voltage (Voc) and fill factor (FF). In the process of preparing the polysilicon layer of the double-sided TOPcon cell, whether PECVD (plasma enhanced chemical vapor deposition) combined with annealing process or low-pressure chemical vapor deposition combined with diffusion process is used for preparation, two annealing processes are required, and the process is relatively cumbersome. In terms of mass production, the two-step high-temperature process requires both two machines and two process times, which greatly increases the manufacturing cost.

[0031] Specifically, the phosphorus element doped in the N-type polysilicon layer has a strong diffusion ability. For example, the phosphorus element can be fully diffused in the polysilicon layer at about 880°C, thereby achieving sufficient doping of the polysilicon layer. The diffusion ability of the boron element is relatively weak, and the annealing temperature of the P-type polysilicon layer is slightly higher than that of the N-type polysilicon. For example, the annealing temperature of N-type polysilicon can be 840°C-910°C, and the annealing temperature of P-type polysilicon can be 940°C-980°C. When the annealing temperature is 940°C, both the N-type polysilicon layer and the P-type polysilicon layer have higher crystal quality, and the passivation performance of the N-type polysilicon layer can be further improved, and the minority carrier lifetime and open circuit voltage of the battery can be improved. However, as the annealing temperature continues to increase, for example, when the annealing temperature is 900°C, the phosphorus element in the N-type polysilicon layer will penetrate the adjacent tunneling silicon oxide layer and enter the silicon substrate. As a large number of phosphorus atoms are lost from the N-type polysilicon layer and accumulate in the silicon substrate, a poor N- / N+ high-low junction will be formed, thereby affecting the output of charges and causing damage to the structure of the tunneling silicon oxide layer, thereby increasing the possibility of interface recombination.

[0032] In the present application, in the first tunneling silicon oxide layer 210, 0<Si 1+ / (Si 2+ +Si 3+ )≤3, where Si 1+ Si represents abundance, Si 2+ , Si 3+ represents O-rich, indicating that SiO x The composition of the first tunneling silicon oxide layer 210 is closer to SiO2, the first tunneling silicon oxide layer 210 has better compactness, and has better blocking effect on phosphorus. It is difficult for the phosphorus in the N-type polysilicon layer 310 to pass through the first tunneling silicon oxide layer 210 to reach the substrate. Therefore, the internal diffusion of phosphorus in the N-type polysilicon layer 310 caused by high-temperature annealing during the preparation process can be effectively reduced. In addition, during the preparation of the battery, due to the first tunneling silicon oxide layer 210 with better compactness, the annealing temperature of the annealing process for the N-type polysilicon layer 310 can be further increased to the same annealing temperature as the P-type polysilicon layer 320, and then the two-step annealing process can be combined into one step, which not only reduces the total process time but also reduces the machine investment cost.

[0033] In some embodiments, when SiO2 is prepared using PECVD equipment, nitrous oxide and auxiliary gas can be introduced at the same time, and the flow ratio of nitrous oxide and auxiliary gas can be adjusted to 5:(1-4), so that an oxygen-rich SiO2 tunneling layer can be formed. Compared with the traditional tunneling layer, the oxygen content is further improved and the tolerance to high temperature is higher, thereby suppressing the internal diffusion of phosphorus in the N-type polysilicon layer 310 caused by high-temperature annealing.

[0034] In a first aspect of the present application, the present application proposes a solar cell, referring to Figure 1 , comprising: a silicon substrate 100, a first tunneling silicon oxide layer 210, wherein the first tunneling silicon oxide layer 210 is located on one side of the silicon substrate 100, and in the first tunneling silicon oxide layer 210, 0<Si 1+ / (Si 2+ +Si 3+ )≤3; an N-type polysilicon layer 310, wherein the N-type polysilicon layer 310 is located on a side of the first tunneling silicon oxide layer 210 away from the silicon substrate 100. Thus, the first tunneling silicon oxide layer 210 has a high density, which can effectively alleviate the diffusion of doping elements in the N-type polysilicon layer 310 into the silicon substrate 100.

[0035] As an example, Si 1+ / (Si 2+ +Si 3+ ) can be 0.2, 0.4, 0.6, 0.8, 1, 1.2, 1.4, 1.6, 1.8, 2, 2.2, 2.4, 2.6, 2.8 or 3.

[0036] In some embodiments, reference Figure 1 The solar cell further comprises: a second tunneling silicon oxide layer 220, the second tunneling silicon oxide layer 220 is located on the side of the silicon substrate 100 away from the first tunneling silicon oxide layer 210; and a P-type polysilicon layer 320, the P-type polysilicon layer 320 is located on the side of the second tunneling silicon oxide layer 220 away from the silicon substrate 100. Thus, sunlight can be absorbed from both sides of the solar cell and converted into electrical energy, thereby increasing the power generation of the cell.

[0037] Bifacial TOPCon cells are able to absorb sunlight from both sides and convert it into electrical energy. This means that in addition to the direct light received on the front side, it is also possible to capture back reflected light, scattered light, and even indirect light from the ground or other reflective surfaces. The total power generation of the cell can be significantly increased. And, due to the ability to generate electricity on both sides, bifacial TOPCon cells are able to obtain more energy in the same area. Especially in places with high ground reflectivity and good surrounding reflective conditions, the energy harvest of bifacial TOPCon cells will be higher than that of single-sided TOPCon cells.

[0038] In some embodiments, reference Figure 1 The solar cell further comprises: an aluminum oxide layer 421, wherein the aluminum oxide layer 421 is located on a side of the P-type polysilicon layer 320 away from the second tunneling silicon oxide layer 220. x The layer can provide field passivation and hydrogen passivation.

[0039] In some embodiments, reference Figure 1 The solar cell further comprises: a laminated passivation layer 422, the laminated passivation layer 422 is located on the side of the aluminum oxide layer 421 away from the P-type polysilicon layer 320, and the laminated passivation layer 422 comprises a first sub-silicon oxide layer, a sub-silicon nitride layer and a second sub-silicon oxide layer which are laminated. Thus, the laminated passivation layer 422 can be used as an anti-reflection film to improve light trapping, increase photoelectric conversion efficiency, and improve passivation performance.

[0040] In some embodiments, reference Figure 1 The solar cell further includes: a silicon nitride layer 410; the silicon nitride layer 410 is located on a side of the N-type polysilicon layer 310 away from the first tunneling silicon oxide layer 210. Therefore, the silicon nitride layer 410 can be used as an anti-reflection film to improve light trapping, increase photoelectric conversion efficiency, and improve passivation performance.

[0041] In some embodiments, the first tunneling silicon oxide layer 210 has a thickness of 1 nm-1.5 nm, and the N-type polysilicon layer 310 has a thickness of 110 nm-250 nm.

[0042] As an example, the thickness of the first tunneling silicon oxide layer 210 may be 1 nm, 1.2 nm, 1.3 nm, 1.4 nm or 1.5 nm. Thus, the first tunneling silicon oxide layer 210 has a good tunneling effect of carriers.

[0043] As an example, the thickness of the N-type polysilicon layer 310 may be 110 nm, 120 nm, 130 nm, 140 nm, 15 nm, 160 nm, 170 nm, 180 nm, 190 nm, 200 nm, 210 nm, 220 nm, 230 nm, 240 nm or 250 nm. Thus, the N-type polysilicon layer 310 can achieve good carrier collection while reducing recombination during carrier transport.

[0044] In some embodiments, reference Figure 1 The solar cell further includes: a first metal electrode 510 and a second metal electrode 520, the first metal electrode 510 is connected to the N-type polysilicon layer 310, and the second metal electrode 520 is connected to the P-type polysilicon layer 320, so that the photocurrent of the solar cell can be output to an external circuit.

[0045] In some embodiments, the photovoltaic module may include at least one battery string, wherein the battery string includes at least two of the aforementioned solar cells. Thus, the photovoltaic module has all the features and advantages of the aforementioned solar cells, which will not be described in detail here.

[0046] In some embodiments, the solar cells may be connected together by serial welding, so that the electric energy generated by the individual solar cells can be collected for subsequent transmission.

[0047] In some embodiments, the solar cells may be arranged at intervals or stacked together in a shingled form.

[0048] For example, the photovoltaic module further includes an encapsulation layer and a cover plate, wherein the encapsulation layer is used to cover the surface of the battery string, and the cover plate is used to cover the surface of the encapsulation layer away from the battery string.

[0049] In some embodiments, the photovoltaic system may include the photovoltaic assembly described above. Therefore, the photovoltaic system has all the features and advantages of the photovoltaic assembly described above, which will not be described in detail here.

[0050] Photovoltaic systems can be used in photovoltaic power stations, such as ground power stations, rooftop power stations, water power stations, etc., and can also be used in equipment or devices that use solar energy to generate electricity, such as user solar power supplies, solar street lights, solar cars, solar buildings, etc. Of course, it is understandable that the application scenarios of photovoltaic systems are not limited to this, that is to say, photovoltaic systems can be used in all fields that require solar energy to generate electricity. Taking the photovoltaic power generation system network as an example, the photovoltaic system may include a photovoltaic array, a junction box and an inverter. The photovoltaic array may be an array combination of multiple photovoltaic components. For example, multiple photovoltaic components can form multiple photovoltaic arrays. The photovoltaic array is connected to the junction box. The junction box can converge the current generated by the photovoltaic array. The converged current flows through the inverter and is converted into the alternating current required by the mains power grid, and then connected to the mains network to realize solar power supply.

[0051] In the second aspect of the present application, the present application proposes a method for preparing a solar cell, by which the aforementioned solar cell can be obtained, referring to Figure 2 and Figure 3 ,include:

[0052] S100: Forming a first tunneling silicon oxide layer on one side of the silicon substrate through a first deposition process

[0053] In some embodiments, the deposition gas of the first deposition process includes nitrous oxide and an auxiliary gas, the auxiliary gas includes at least one of hydrogen and argon, wherein a flow rate ratio of the auxiliary gas to the nitrous oxide is (1-4):5.

[0054] As an example, the first deposition process may be performed by PECVD. Specifically, nitrous oxide is passed through the PECVD under high temperature ionization, and the nitrous oxide reacts with silicon to produce silicon oxide. The reaction equation is: 2N2O+Si→SiO2+2N2.

[0055] As an example, the auxiliary gas is argon.

[0056] As an example, the flow rate ratio of the auxiliary gas to the nitrous oxide is 1:5, 1.5:5, 2:5, 2.5:5, 3:5, 3.5:5 or 4:5.

[0057] In some embodiments, the flow rate ratio of the auxiliary gas to the nitrous oxide is (2-3):5.

[0058] When the flow rate ratio of the auxiliary gas to the nitrous oxide is within the aforementioned range, the auxiliary gas can effectively increase the gas pressure of the cavity, promote the full silicon oxide formation reaction of the nitrous oxide gas on the surface of the silicon substrate, and the oxygen content in the first tunneling silicon oxide layer is improved, approaching SiO2, and the flow rate of the nitrous oxide is relatively moderate, with a high deposition rate, a short reaction time, and less gas consumption, and the manufacturing cost is significantly reduced. Therefore, by adjusting the flow rate ratio of the auxiliary gas to the nitrous oxide, the oxygen content in the first tunneling silicon oxide layer can be adjusted, and then a first tunneling silicon oxide layer with good density and high temperature resistance can be obtained, and then in the subsequent process, the annealing temperature of the N-type polysilicon layer can be increased to be consistent with the annealing temperature of the P-type polysilicon layer, achieving the effect of reducing costs.

[0059] In some embodiments, the gas flow rate of the nitrous oxide is 8000 sccm-15000 sccm, and the gas flow rate of the auxiliary gas is 3000 sccm-6000 sccm. This helps to form a first tunneling silicon oxide layer with a high silicon-oxygen atomic ratio and reduces loss.

[0060] As an example, the gas flow rate of nitrous oxide may be 8000 sccm, 9000 sccm, 10000 sccm, 11000 sccm, 12000 sccm, 13000 sccm, 14000 sccm, or 15000 sccm.

[0061] As an example, the gas flow rate of the auxiliary gas may be 3000 sccm, 4000 sccm, 5000 sccm, or 6000 sccm.

[0062] In some embodiments, the power of the first deposition process is 9000 W-12000 W. This helps to obtain a first tunneling silicon oxide layer with a moderate thickness and a high oxygen content.

[0063] As an example, the power of the first deposition process may be 9000W, 9500W, 10000W, 10500W, 11000W, 11500W, or 12000W.

[0064] In some embodiments, the pressure of the first deposition process is 800 mtorr-1500 mtorr, which helps to obtain a first tunneling silicon oxide layer with moderate thickness and high oxygen content.

[0065] As an example, the pressure of the first deposition process may be 800 mtorr, 900 mtorr, 1000 mtorr, 1100 mtorr, 1200 mtorr, 1300 mtorr, 1400 mtorr, or 1500 mtorr.

[0066] In some embodiments, the temperature of the first deposition process is 430° C.-500° C., and the time of the first deposition process is 60s-120s. This helps to obtain a first tunneling silicon oxide layer with moderate thickness and high oxygen content.

[0067] As an example, the temperature of the first deposition process may be 430°C, 440°C, 450°C, 460°C, 470°C, 480°C, 490°C, or 500°C.

[0068] As an example, the time of the first deposition process may be 60 s, 70 s, 80 s, 90 s, 100 s, 110 s or 120 s.

[0069] S200: forming an N-type polysilicon layer on a side of the first tunneling silicon oxide layer away from the silicon substrate through a second deposition process

[0070] As an example, the second deposition process may be performed by PECVD. Specifically, phosphine may be used as a dopant, and phosphine may be introduced into a reaction chamber together with a pure silicon source gas (such as silane) and a carrier gas to react and generate phosphorus-doped polysilicon, wherein phosphorus atoms replace positions in part of the silicon lattice and become donor atoms, providing additional electrons, thereby making the polysilicon have n-type conductivity.

[0071] In some embodiments, the second deposition process further comprises:

[0072] S210: forming a second tunneling silicon oxide layer on a side of the silicon substrate away from the first tunneling silicon oxide layer through a third deposition process

[0073] As an example, the second deposition process may be performed by PECVD. Specifically, nitrous oxide is passed through the PECVD under high temperature ionization, and the nitrous oxide reacts with silicon to produce silicon oxide. The reaction equation is: 2N2O+Si→SiO2+2N2.

[0074] The boron element in the P-type polysilicon layer corresponding to the second tunneling oxide layer has weak internal expansion at high temperature, so the second deposition process can use only nitrous oxide to deposit silicon oxide, or use a mixture of nitrous oxide and auxiliary gas to deposit silicon oxide.

[0075] In some embodiments, before the third deposition process, the method further includes: forming a silicon oxide protective layer on the surface of the N-type polycrystalline layer by PECVD, thereby effectively reducing the entry of boron elements into the N-type polycrystalline silicon layer during the preparation of the P-type polycrystalline silicon layer, thereby reducing the quality of the film layer.

[0076] S220: Forming a P-type polysilicon layer on a side of the second tunneling silicon oxide layer away from the silicon substrate through a fourth deposition process

[0077] As an example, the fourth deposition process may be PECVD. Specifically, trimethylboron (TMB) or borane (B2H6) may be used as a dopant, and the dopant is introduced into the reaction chamber together with a silicon source gas (such as silane) and a carrier gas to react to obtain polysilicon doped with boron, wherein the boron atoms replace the positions in part of the silicon lattice, become acceptor atoms, accept electrons to form holes, and make the polysilicon exhibit p-type conductivity.

[0078] S300: performing annealing on the silicon substrate after the second deposition process

[0079] In some embodiments, the silicon substrate after the second deposition process is annealed in this step, so as to promote the diffusion and activation of phosphorus in the N-type polysilicon layer and improve the quality of the first tunneling silicon oxide layer.

[0080] In some embodiments, the silicon substrate after the fourth deposition process may be subjected to an annealing process. Thus, after the preparation of the P-type polysilicon layer and the N-type polysilicon layer, annealing and crystallization may be performed simultaneously, thereby promoting the diffusion and activation of phosphorus in the N-type polysilicon layer and boron in the P-type polysilicon layer, and jointly improving the quality of the first tunneling silicon oxide layer and the second tunneling silicon oxide layer, simplifying the preparation process, and reducing process energy consumption.

[0081] In some embodiments, the annealing temperature is greater than or equal to 900° C. Thus, the annealing temperature of the N-type polysilicon layer is consistent with the annealing temperature of the P-type polysilicon layer, so that the two-step annealing process can be combined into one step, which reduces the total process time and the equipment investment cost.

[0082] In some embodiments, the annealing temperature is 940° C.-980° C., and the annealing time is 15 min-25 min. This helps the doping atoms migrate from the lattice gaps or substitution positions to the appropriate lattice positions, thereby activating electrical activity and improving the crystal quality of the polysilicon layer.

[0083] As an example, the temperature of the annealing process is 940°C, 950°C, 960°C, 970°C or 980°C.

[0084] As an example, the annealing treatment time is 15 min, 17 min, 20 min, 22 min or 25 min.

[0085] It should be noted that the relevant parameters of the above-mentioned method for preparing solar cells can refer to part or all of the technical features in the aforementioned embodiments. The parts not described in the embodiments of the method for preparing solar cells can also refer to the aforementioned embodiments and related drawings, which will not be repeated here.

[0086] The above description of various embodiments tends to emphasize the differences between the various embodiments. The same or similar aspects can be referenced to each other, and for the sake of brevity, they will not be repeated herein.

[0087] The scheme of the present application is described below by specific examples. It should be noted that the following examples are only used to illustrate the present application and should not be considered as limiting the scope of the present application. If no specific technology or conditions are specified in the examples, the technology or conditions described in the literature in this area or the product instructions are used. The reagents or instruments used are not specified by the manufacturer, and are all conventional products that can be obtained commercially.

[0088] Example 1

[0089] (1) Polish the N-type silicon substrate to remove damage and perform RCA cleaning.

[0090] (2) Using PECVD to prepare a first tunneling silicon oxide layer, an N-type polysilicon layer and a silicon dioxide protective layer on the back side of the silicon substrate. The process conditions for preparing the first tunneling silicon oxide layer are as follows:

[0091] Argon gas flow rate: 4000 sccm, nitrous oxide gas flow rate: 10000 sccm, deposition power 11000 W, chamber pressure 1000 mtorr, deposition time 90 s, deposition temperature 480 °C.

[0092] (3) The front side of the silicon substrate is subjected to chain HF cleaning, texturing and RCA cleaning.

[0093] (4) Prepare the second tunneling silicon oxide layer and P-type polysilicon layer by PECVD.

[0094] (5) The silicon substrate is placed in an annealing furnace at a temperature of 960° C. for 20 minutes to crystallize the N-type polysilicon and P-type polysilicon layers.

[0095] (6) Use a chain machine to remove the BSG wrap-around plating on the back side, and use polishing liquid to remove the residual P-type polysilicon on the back side.

[0096] (7) Perform RCA cleaning on both sides of the battery.

[0097] (8) An aluminum oxide layer is formed on the front of the battery using an ALD device, and a laminated passivation layer (including 2 nm SiO2, SiN x , 100nm SiO2, wherein after the first layer of SiO2 is formed, the battery needs to be annealed at 700℃ for 20min).

[0098] (9) Prepare a back passivation layer (silicon nitride layer, 80 nm thick) using PECVD.

[0099] (10) The front and back metal silver electrodes are electroplated.

[0100] Example 2

[0101] Example 2 is consistent with Example 1, except that when preparing the first tunneling silicon oxide layer, the argon gas flow rate is 2000 sccm, and the nitrous oxide gas flow rate is 10000 sccm.

[0102] Example 3

[0103] Example 3 is consistent with Example 1, except that when preparing the first tunneling silicon oxide layer, the argon gas flow rate is 6000 sccm, and the nitrous oxide gas flow rate is 10000 sccm.

[0104] Example 4

[0105] Example 4 is consistent with Example 1, except that when preparing the first tunneling silicon oxide layer, argon gas is replaced by hydrogen gas.

[0106] Comparative Example 1

[0107] Comparative Example 1 is consistent with Example 1, except that when preparing the first tunneling silicon oxide layer, only nitrous oxide gas is introduced, and the flow rate of the nitrous oxide gas is 12000 sccm.

[0108] The batteries in the above-mentioned embodiments and comparative examples were tested as follows, using a Sinton FCT-650IV tester. The test results are shown in Table 1, where Jsc represents short-circuit current density, Voc represents open-circuit voltage, FF represents fill factor, and Eff represents photoelectric conversion efficiency, Eff = Jsc × Voc × FF / 100.

[0109] Table 1

[0110]

[0111] It should be noted that the present application is not limited to the above-mentioned embodiments. The above-mentioned embodiments are only examples, and the embodiments having the same structure as the technical idea and exerting the same effect within the scope of the technical solution of the present application are all included in the technical scope of the present application. In addition, without departing from the scope of the main purpose of the present application, various modifications that can be thought of by those skilled in the art to the embodiments and other methods of combining some of the constituent elements in the embodiments are also included in the scope of the present application.

Claims

1. A solar cell, characterized in that: include: Silicon substrate, A first tunneling silicon oxide layer, wherein the first tunneling silicon oxide layer is located on one side of the silicon substrate, and in the first tunneling silicon oxide layer, 0<Si 1+ / (Si 2+ +Si 3+ )≤3; An N-type polysilicon layer is located on a side of the first tunneling silicon oxide layer away from the silicon substrate.

2. The solar cell according to claim 1, characterized in that Further including; a second tunneling silicon oxide layer, wherein the second tunneling silicon oxide layer is located on a side of the silicon substrate away from the first tunneling silicon oxide layer; A P-type polysilicon layer is located on a side of the second tunneling silicon oxide layer away from the silicon substrate.

3. The solar cell according to claim 2, characterized in that: Further including: an aluminum oxide layer, the aluminum oxide layer being located on a side of the P-type polysilicon layer away from the second tunneling silicon oxide layer; and / or, a laminated passivation layer, the laminated passivation layer being located on a side of the aluminum oxide layer away from the P-type polysilicon layer, the laminated passivation layer comprising a first sub-silicon oxide layer, a sub-silicon nitride layer and a second sub-silicon oxide layer which are laminated; and / or, Silicon nitride layer; the silicon nitride layer is located on a side of the N-type polysilicon layer away from the first tunneling silicon oxide layer.

4. The solar cell according to any one of claims 1 to 3, characterized in that: The thickness of the first tunneling silicon oxide layer is 1 nm-1.5 nm, and the thickness of the N-type polysilicon layer is 110 nm-250 nm.

5. A method for preparing a solar cell, characterized in that: include: forming a first tunneling silicon oxide layer on one side of the silicon substrate by a first deposition process, wherein a deposition gas of the first deposition process includes nitrous oxide and an auxiliary gas, wherein the auxiliary gas includes at least one of hydrogen and argon, and a flow rate ratio of the auxiliary gas to the nitrous oxide is (1-4):5; forming an N-type polysilicon layer on a side of the first tunneling silicon oxide layer away from the silicon substrate through a second deposition process; The silicon substrate after the second deposition process is subjected to an annealing process, wherein the annealing process is performed at a temperature greater than or equal to 900° C.

6. The method according to claim 5, characterized in that: The flow rate ratio of the auxiliary gas to the nitrous oxide is (2-3):

5.

7. The method according to claim 5, characterized in that The gas flow rate of the nitrous oxide is 8000sccm-15000sccm, and the gas flow rate of the auxiliary gas is 3000sccm-6000sccm.

8. The method according to any one of claims 5 to 7, characterized in that: The power of the first deposition process is 9000W-12000W; and / or, The pressure of the first deposition process is 800mtorr-1500mtorr; and / or, The time of the first deposition process is 60s-120s, and the temperature of the first deposition process is 430°C-500°C.

9. The method according to any one of claims 5 to 7, characterized in that: The second deposition process further comprises: forming a second tunneling silicon oxide layer on a side of the silicon substrate away from the first tunneling silicon oxide layer by a third deposition process; forming a P-type polysilicon layer on a side of the second tunneling silicon oxide layer away from the silicon substrate through a fourth deposition process; The silicon substrate after the fourth deposition process is subjected to an annealing process.

10. The method according to claim 9, characterized in that The temperature of the annealing treatment is 940° C.-980° C., and the time of the annealing treatment is 15 min-25 min.

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