Light emitting diode chip and preparation method thereof, LED

Abstract

The present invention relates to the field of optoelectronics, and in particular to a light-emitting diode chip, a method for manufacturing the same, and an LED. In the method for manufacturing the light-emitting diode chip provided by the present invention, a second photolithography process and a second dry etching process are performed on an N-type semiconductor layer in a preset area. The etching gases used in the second dry etching are SiCl4 gas and Ar gas, so that the Si doping concentration of the N-type semiconductor layer in the preset area is higher than the Si doping concentration of the N-type semiconductor layer in a non-preset area. An N-type electrode is prepared on the N-type semiconductor layer in the preset area, thereby achieving better ohmic contact between the N-type electrode and the N-type semiconductor, reducing the chip voltage without affecting the overall Si doping concentration of the N-type semiconductor, avoiding low luminous efficiency of the epitaxial layer and thus low chip brightness, and achieving voltage reduction without sacrificing luminous brightness.

Description

Technical Field

[0001] The present invention relates to the field of optoelectronic technology, and in particular to a light emitting diode chip and a preparation method thereof, and an LED. Background Art

[0002] An LED (Light Emitting Diode) is a semiconductor light-emitting device that converts electrical energy into light. With the development and advancement of LED chip manufacturing technology, it has gradually become the new mainstream lighting source after incandescent and fluorescent lamps. Its advantages include small size, fast response, long life, and environmental protection and energy saving. It is widely used in lighting, display screens and other fields.

[0003] LED chips are composed of epitaxial layers and chip layers. The epitaxial layer generally includes a substrate, an N-type semiconductor, a quantum well, and a P-type semiconductor; the chip layer consists of a current blocking layer, a transparent conductive layer, an electrode, and a passivation layer from bottom to top. Electrodes are divided into P-type electrodes and N-type electrodes. The N-type electrode is located on the surface of the N-type semiconductor and is connected to the negative pole of the power supply to achieve electrical connection. Exposing the N-type semiconductor requires a chip process called Mesa. Its principle is to etch the epitaxial layer to a certain depth through photolithography and dry etching, etching away the P-type semiconductor, quantum well, and part of the N-type semiconductor, thereby exposing the N-type semiconductor that needs to be electrically connected.

[0004] In the traditional Mesa process, the exposed N-type semiconductor has the same Si doping concentration as the N-type semiconductor elsewhere, which is the concentration of the N-type semiconductor itself in the epitaxial layer. To achieve better ohmic contact between the N-type electrode and the N-type semiconductor, the chip voltage can be lowered by increasing the Si concentration of the N-type semiconductor in the epitaxial layer. However, this results in lower luminous efficiency in the epitaxial layer, leading to lower chip brightness. Therefore, it is impossible to reduce the voltage without sacrificing brightness. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a light emitting diode chip and a preparation method thereof, which can reduce the chip voltage without affecting the brightness of the chip.

[0006] The technical problem to be solved by the present invention is to provide an LED.

[0007] In order to solve the above technical problems, the present invention provides a method for preparing a light emitting diode chip, comprising the following steps:

[0008] Providing an epitaxial layer, the epitaxial layer comprising a substrate, an N-type semiconductor layer, a multi-quantum well layer and a P-type semiconductor layer;

[0009] Performing a first photolithography process and a first dry etching on the epitaxial layer to expose a portion of the N-type semiconductor layer, where the exposed portion of the N-type semiconductor layer is the N-type semiconductor layer in a first region, and disposing an N-type electrode in the first region, where the first region includes a preset region and a non-preset region, and the preset region includes an orthographic projection region of the N-type electrode on the N-type semiconductor layer;

[0010] Performing a second photolithography process and a second dry etching on the N-type semiconductor layer in the preset area, wherein the etching gases used in the second dry etching are SiCl4 gas and Ar gas, so that the Si doping concentration of the N-type semiconductor layer in the preset area is higher than the Si doping concentration of the N-type semiconductor layer in the non-preset area;

[0011] Preparing an N-type electrode on the N-type semiconductor layer within the preset area, and making the orthographic projection area of ​​the N-type electrode on the N-type semiconductor layer within the preset area;

[0012] A P-type electrode is prepared on the P-type semiconductor layer.

[0013] In some embodiments, the predetermined area is an area formed by extending the edge of the orthographic projection area of ​​the N-type electrode on the N-type semiconductor layer outward by 0.5 μm to 2 μm.

[0014] In some embodiments, the Si doping concentration of the N-type semiconductor layer in the predetermined area is 1×10 18 atoms / cm 3 ~1×10 20 atoms / cm 3 ;

[0015] The Si doping concentration of the N-type semiconductor layer in the non-preset area is 1×10 18 atoms / cm 3 ~1×10 19 atoms / cm 3 .

[0016] In some embodiments, the etching gas used in the first dry etching is selected from one or more of Cl2 gas, BCl3 gas, and Ar gas.

[0017] In some embodiments, the process parameters of the first dry etching include: a flow rate of the Cl2 gas of 10 sccm to 250 sccm;

[0018] The flow rate of the BCl3 gas is 10 sccm to 250 sccm;

[0019] The flow rate of the Ar gas is 10 sccm to 250 sccm.

[0020] In some embodiments, the process parameters of the first dry etching further include: a pressure of 3mT to 5mT;

[0021] The upper electrode loading power is 300W~500W;

[0022] The lower electrode loading power is 100W to 300W.

[0023] In some embodiments, the process parameters of the second dry etching include: the flow rate of the SiCl4 gas is 10 sccm to 60 sccm;

[0024] The flow rate of the Ar gas is 5 sccm to 15 sccm.

[0025] In some embodiments, the process parameters of the second dry etching further include: a pressure of 3mT to 5mT;

[0026] The upper electrode loading power is 300W~500W;

[0027] The lower electrode loading power is 100W to 300W.

[0028] Accordingly, the present invention further provides a light emitting diode chip, which is manufactured using the light emitting diode chip manufacturing method described above, and an LED, which includes the light emitting diode chip.

[0029] The implementation of the present invention has the following beneficial effects:

[0030] In the method for preparing a light-emitting diode chip provided by the present invention, a second photolithography process and a second dry etching are performed on the N-type semiconductor layer in the preset area. The etching gases used in the second dry etching are SiCl4 gas and Ar gas, so that the Si doping concentration of the N-type semiconductor layer in the preset area is higher than the Si doping concentration of the N-type semiconductor layer in the non-preset area. An N-type electrode is prepared on the N-type semiconductor layer in the preset area, thereby achieving better ohmic contact between the N-type electrode and the N-type semiconductor, reducing the chip voltage, and at the same time not affecting the overall Si doping concentration of the N-type semiconductor. This avoids low luminous efficiency of the epitaxial layer and thus low chip brightness, thereby achieving voltage reduction without sacrificing luminous brightness. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 A schematic diagram of a semi-finished product during the process of performing a first photolithography process and a first dry etching process on the epitaxial layer in the method for preparing a light-emitting diode chip provided by the present invention;

[0032] Figure 2A schematic diagram of a preset area in the method for preparing a light-emitting diode chip provided by the present invention;

[0033] Figure 3 This is a schematic diagram of a semi-finished product in the process of performing a second photolithography process and a second dry etching on the epitaxial layer in the method for preparing a light emitting diode chip provided by the present invention. DETAILED DESCRIPTION

[0034] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and are not to be construed as limiting the present invention. In addition, it should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0035] In the description of the present invention, it should be understood that the terms "length", "width", "up", "down", "left", "right", "horizontal", "top", "bottom", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0036] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, features defined as "first" or "second" may explicitly or implicitly include one or more of the described features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined.

[0037] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they may refer to fixed connections, detachable connections, or integral connections; mechanical connections, electrical connections, or mutual communication; direct connections or indirect connections through an intermediate medium; and internal communication between two components or interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0038] In the present invention, unless otherwise expressly specified or limited, a first feature being "above" or "below" a second feature may include the first and second features being in direct contact, or may include the first and second features being in contact not directly but through another feature between them. Furthermore, a first feature being "above," "above," and "above" a second feature may include the first feature being directly above or obliquely above the second feature, or may simply mean that the first feature is higher in level than the second feature. A first feature being "below," "below," and "below" a second feature may include the first feature being directly below or obliquely below the second feature, or may simply mean that the first feature is lower in level than the second feature.

[0039] The disclosure below provides many different embodiments or examples for realizing different structures of the present invention. In order to simplify the disclosure of the present invention, the components and settings of specific examples are described below. Of course, they are merely examples and are not intended to limit the present invention. In addition, the present invention may repeat reference numerals and / or reference letters in different examples. Such repetition is for the purpose of simplicity and clarity and does not in itself indicate the relationship between the various embodiments and / or settings discussed. In addition, the present invention provides examples of various specific processes and materials, but those skilled in the art will appreciate the application of other processes and / or the use of other materials.

[0040] In the present invention, the terms "preferred" and "better" are merely used to describe preferred implementation methods or examples and should be understood not to limit the scope of protection of the present invention. In the present invention, technical features described as open-ended include both closed-ended technical solutions consisting of the listed features and open-ended technical solutions containing the listed features. In the present invention, references to numerical ranges include both endpoints of the numerical range unless otherwise specified.

[0041] To solve the above problems, the present invention provides a method for preparing a light emitting diode chip, comprising the following steps:

[0042] (1) Providing an epitaxial layer, wherein the epitaxial layer includes a substrate, an N-type semiconductor layer, a multi-quantum well layer, and a P-type semiconductor layer;

[0043] (2) performing a first photolithography process and a first dry etching on the epitaxial layer to expose a portion of the N-type semiconductor layer, wherein the exposed portion of the N-type semiconductor layer is the N-type semiconductor layer in a first region, and an N-type electrode is provided in the first region, wherein the first region includes a preset region and a non-preset region, and the preset region includes an orthographic projection region of the N-type electrode on the N-type semiconductor layer;

[0044] like Figure 1As shown, the epitaxial layer is subjected to a first photolithography process and a first dry etching process to expose a portion of the N-type semiconductor layer. The exposed portion of the N-type semiconductor layer is the N-type semiconductor layer of the first region 100. The blank area in the figure is the first region 100, and the shaded area is the photoresist mask area.

[0045] In actual production, not all of the exposed N-type semiconductor layer in the first region 100 is used to form the N-type electrode. Some of the exposed N-type semiconductor layer in the first region 100 is not used to form the N-type electrode. If a secondary SiCl4 gas etching is performed on the first region, the Si doping concentration in the N-type semiconductor layer will be too high, which will affect the luminous efficiency of the epitaxial layer and thus reduce the brightness of the chip. Therefore, the present invention performs a secondary SiCl4 gas etching in a predetermined region.

[0046] like Figure 2 As shown, in some embodiments, the predetermined region 110 is formed by extending the edge of the orthographic projection of the N-type electrode 120 on the N-type semiconductor layer outward by 0.5 μm to 2 μm. Preferably, the predetermined region 110 is formed by extending the edge of the orthographic projection of the N-type electrode 120 on the N-type semiconductor layer outward by 1 μm to 1.5 μm. When the predetermined region 110 is smaller than the area of ​​the N-type electrode 120, a voltage increase will occur. When the predetermined region 110 is larger than the area of ​​the N-type electrode 120, the Si doping concentration of the N-type semiconductor layer in the predetermined region 110 is higher than the Si doping concentration of the N-type semiconductor layer in the non-preset region 130, thereby ensuring a lower voltage.

[0047] In some embodiments, the etching gas used for the first dry etching is selected from one or more of Cl2 gas, BCl3 gas, and Ar gas. The use of the above etching gases for the first dry etching will not affect the Si doping concentration of the N-type semiconductor layer. In some embodiments, when Cl2 gas is used as the etching gas for the first dry etching, the flow rate of the Cl2 gas is 10 sccm to 250 sccm; when BCl3 gas is used as the etching gas for the first dry etching, the flow rate of the BCl3 gas is 10 sccm to 250 sccm; when Ar gas is used as the etching gas for the first dry etching, the flow rate of the Ar gas is 10 sccm to 250 sccm.

[0048] Preferably, the etching gases for the first dry etching are Cl2 gas and Ar gas, with the flow rate of the Cl2 gas being 100 sccm to 200 sccm and the flow rate of the Ar gas being 10 sccm to 30 sccm, thereby increasing the etching rate and achieving precise etching.

[0049] The process parameters of the first dry etching also include: pressure of 3mT to 5mT; upper electrode loading power of 300W to 500W; lower electrode loading power of 100W to 300W. Preferably, the pressure is 3.5mT to 4.5mT; upper electrode loading power of 350W to 450W; lower electrode loading power of 150W to 250W.

[0050] (3) performing a second photolithography process and a second dry etching on the N-type semiconductor layer in the preset area, wherein the etching gases used in the second dry etching are SiCl4 gas and Ar gas, so that the Si doping concentration of the N-type semiconductor layer in the preset area is higher than the Si doping concentration of the N-type semiconductor layer in the non-preset area;

[0051] like Figure 3 As shown, the N-type semiconductor layer in the preset area is subjected to a second photolithography process and a second dry etching process. The blank area in the figure is the preset area 110, and the shaded area is the photoresist mask area.

[0052] The etching gases used in the second dry etching of the present invention are SiCl4 gas and Ar gas. Using SiCl4 gas for etching will increase the Si doping concentration of the N-type semiconductor layer in the preset area, thereby achieving that the Si doping concentration of the N-type semiconductor layer in the preset area is higher than the Si doping concentration of the N-type semiconductor layer in the non-preset area, and an N-type electrode is prepared on the N-type semiconductor layer in the preset area, thereby achieving better ohmic contact between the N-type electrode and the N-type semiconductor, reducing the chip voltage, and at the same time not affecting the overall Si doping concentration of the N-type semiconductor, avoiding the low luminous efficiency of the epitaxial layer and thus the low brightness of the chip, and achieving voltage reduction without losing luminous brightness.

[0053] In some embodiments, the Si doping concentration of the N-type semiconductor layer in the predetermined area is 1×10 18 atoms / cm 3 ~1×10 20 atoms / cm 3 The Si doping concentration of the N-type semiconductor layer in the non-preset area is 1×10 18 atoms / cm 3 ~1×10 19 atoms / cm 3 .

[0054] In some embodiments, the process parameters of the second dry etching include: a flow rate of the SiCl4 gas of 10 sccm to 60 sccm; a flow rate of the Ar gas of 5 sccm to 15 sccm. Preferably, the flow rate of the SiCl4 gas is 20 sccm to 50 sccm; and a flow rate of the Ar gas is 7 sccm to 13 sccm.

[0055] In some embodiments, the process parameters of the second dry etching further include: a pressure of 3mT to 5mT; an upper electrode loading power of 300W to 500W; and a lower electrode loading power of 100W to 300W. Preferably, the pressure is 3.5mT to 4.5mT; the upper electrode loading power is 350W to 450W; and the lower electrode loading power is 150W to 250W.

[0056] (4) preparing an N-type electrode on the N-type semiconductor layer within the preset area, and ensuring that the orthographic projection area of ​​the N-type electrode on the N-type semiconductor layer is within the preset area;

[0057] (5) Preparing a P-type electrode on the P-type semiconductor layer.

[0058] Accordingly, the present invention also provides an LED chip, or light-emitting diode chip. The LED chip is the core component of an LED and determines key characteristics such as its luminous efficiency, wavelength, and chromaticity. Therefore, in the development of the LED industry, improving the quality and processing accuracy of LED chips and optimizing chip manufacturing processes are crucial for enhancing LED performance and application range. Furthermore, the present invention provides an LED device comprising the aforementioned LED chip.

[0059] The present invention is further described below with specific examples:

[0060] Example 1

[0061] This embodiment provides a method for preparing a light-emitting diode chip, comprising the following steps:

[0062] Providing an epitaxial layer, the epitaxial layer comprising a substrate, an N-type semiconductor layer, a multi-quantum well layer and a P-type semiconductor layer;

[0063] Performing a first photolithography process and a first dry etching on the epitaxial layer to expose a portion of the N-type semiconductor layer, where the exposed portion of the N-type semiconductor layer is the N-type semiconductor layer in a first region, and disposing an N-type electrode in the first region, where the first region includes a preset region and a non-preset region, and the preset region includes an orthographic projection region of the N-type electrode on the N-type semiconductor layer;

[0064] Performing a second photolithography process and a second dry etching on the N-type semiconductor layer in the preset area, wherein the etching gases used in the second dry etching are SiCl4 gas and Ar gas, so that the Si doping concentration of the N-type semiconductor layer in the preset area is higher than the Si doping concentration of the N-type semiconductor layer in the non-preset area;

[0065] preparing an N-type electrode on the N-type semiconductor layer within the preset area, and making the orthographic projection area of ​​the N-type electrode on the N-type semiconductor layer within the preset area;

[0066] A P-type electrode is prepared on the P-type semiconductor layer.

[0067] The preset area is an area formed by extending 1 μm outward from the edge of the orthographic projection area of ​​the N-type electrode on the N-type semiconductor layer.

[0068] The process parameters used in the first dry etching are as follows:

[0069] parameter Pressure (mT) 4 Upper electrode loading power (W) 400 Lower electrode loading power (W) 200 Ar(sccm) 20 <![CDATA[Cl2(sccm)]]> 150

[0070] The process parameters used in the second dry etching are as follows:

[0071] parameter Pressure (mT) 4 Upper electrode loading power (W) 400 Lower electrode loading power (W) 200 Ar(sccm) 10 <![CDATA[SiCl4(sccm)]]> 40

[0072] Comparative Example 1

[0073] This comparative example provides a method for preparing a light-emitting diode chip, comprising the following steps:

[0074] Providing an epitaxial layer, the epitaxial layer comprising a substrate, an N-type semiconductor layer, a multi-quantum well layer and a P-type semiconductor layer;

[0075] The epitaxial layer is subjected to a first photolithography process and a first dry etching process to expose a portion of the N-type semiconductor layer, an N-type electrode is prepared on the exposed portion of the N-type semiconductor layer, and a P-type electrode is prepared on the P-type semiconductor layer.

[0076] The light emitting diode chips prepared in Example 1 and Comparative Example 1 were tested, and the specific test results are shown in Table 1.

[0077] Table 1 Performance test results of the photodiode chips prepared in Example 1 and Comparative Example 1

[0078] Test current / mA Voltage / V Brightness / mW Wavelength / nm Comparative Example 1 120 3.08 186.2 453.5 Example 1 120 3.04 186.2 453.5

[0079] As can be seen from the above data, Example 1 has comparable brightness to Comparative Example 1, but the voltage is 0.04V lower, which is quite rare for a light-emitting diode chip. Therefore, in the method for preparing a light-emitting diode chip provided by the present invention, a second photolithography process and a second dry etching are performed on the N-type semiconductor layer in the predetermined region. The etching gases used in the second dry etching are SiCl4 gas and Ar gas, so that the Si doping concentration of the N-type semiconductor layer in the predetermined region is higher than the Si doping concentration of the N-type semiconductor layer in the non-preset region. An N-type electrode is then formed on the N-type semiconductor layer in the predetermined region. This achieves better ohmic contact between the N-type electrode and the N-type semiconductor, reduces the chip voltage, and does not affect the overall Si doping concentration of the N-type semiconductor. This avoids low luminous efficiency of the epitaxial layer and thus low chip brightness, thus achieving voltage reduction without sacrificing brightness.

[0080] Throughout this specification, reference to terms such as "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples" means that a specific feature, structure, material, or characteristic described in conjunction with an embodiment or example is included in at least one embodiment or example of the present application. In this specification, the illustrative use of the above terms does not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0081] The above is a preferred embodiment of the invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the invention. These improvements and modifications are also considered to be within the scope of protection of the present invention.

Claims

1. A method for preparing a light-emitting diode chip, characterized in that: The following steps are involved: Providing an epitaxial layer, the epitaxial layer comprising a substrate, an N-type semiconductor layer, a multi-quantum well layer and a P-type semiconductor layer; Performing a first photolithography process and a first dry etching on the epitaxial layer to expose a portion of the N-type semiconductor layer, where the exposed portion of the N-type semiconductor layer is the N-type semiconductor layer in a first region, and disposing an N-type electrode in the first region, where the first region includes a preset region and a non-preset region, and the preset region includes an orthographic projection region of the N-type electrode on the N-type semiconductor layer; Performing a second photolithography process and a second dry etching on the N-type semiconductor layer in the preset area, wherein the etching gases used in the second dry etching are SiCl4 gas and Ar gas, so that the Si doping concentration of the N-type semiconductor layer in the preset area is higher than the Si doping concentration of the N-type semiconductor layer in the non-preset area; preparing an N-type electrode on the N-type semiconductor layer within the preset area, and making the orthographic projection area of ​​the N-type electrode on the N-type semiconductor layer within the preset area; preparing a P-type electrode on the P-type semiconductor layer; The preset area is an area formed by extending the edge of the orthographic projection area of ​​the N-type electrode on the N-type semiconductor layer outward by 0.5 μm to 2 μm; The process parameters of the second dry etching include: the flow rate of the SiCl4 gas is 10 sccm to 60 sccm; The flow rate of the Ar gas is 5 sccm to 15 sccm; The process parameters of the second dry etching also include: a pressure of 3mT to 5mT; The upper electrode loading power is 300W~500W; The lower electrode loading power is 100W~300W.

2. The method for preparing a light emitting diode chip according to claim 1, wherein: The Si doping concentration of the N-type semiconductor layer in the preset area is 1×10 18 atoms / cm 3 ~1×10 20 atoms / cm 3 ; The Si doping concentration of the N-type semiconductor layer in the non-preset area is 1×10 18 atoms / cm 3 ~1×10 19 atoms / cm 3 .

3. The method for preparing a light emitting diode chip according to claim 1, wherein: The etching gas used in the first dry etching is selected from one or more of Cl2 gas, BCl3 gas, and Ar gas.

4. The method for preparing a light emitting diode chip according to claim 3, wherein: The process parameters of the first dry etching include: the flow rate of the Cl2 gas is 10 sccm to 250 sccm; The flow rate of the BCl3 gas is 10 sccm~250 sccm; The flow rate of the Ar gas is 10 sccm to 250 sccm.

5. The method for preparing a light emitting diode chip according to claim 1, wherein: The process parameters of the first dry etching also include: a pressure of 3mT to 5mT; The upper electrode loading power is 300W~500W; The lower electrode loading power is 100W~300W.

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