Filter device, multilayer substrate, and communication apparatus

Abstract

A filter device includes a multilayer substrate, a chip mounted on the multilayer substrate, a first filter at least partially included in the chip, and a first hybrid coupler connected to the first filter. A portion of the first mixer is included in the multilayer substrate and another portion of the first mixer is included in the chip.

Description

Technical Field

[0001] The present disclosure relates to a filter device having a filter and a hybrid coupler, a multilayer substrate that can be used in the filter device, and a communication device including the filter device. Background Art

[0002] Filter devices that combine filters and hybrid couplers are known (for example, Patent Documents 1 and 2). In addition, as hybrid couplers, couplers that use lumped parameter elements are known (for example, Patent Documents 3 to 5). In Patent Documents 3 to 5, inductors, capacitors, and resonators are listed as lumped parameter elements that constitute the hybrid coupler. The hybrid coupler performs the desired function (distribution of input signals, phase adjustment, and / or synthesis) at a specified operating frequency. Patent Documents 3 to 5 show the relationship between the operating frequency and the value of the inductance and / or capacitance of the lumped parameter element in various types of hybrid couplers. In addition, the contents of Patent Documents 1 to 5 can be incorporated by reference.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: International Publication No. 2022 / 054896

[0006] Patent Document 2: Japanese Patent Application Publication No. 2022-041537

[0007] Patent Document 3: Japanese Patent Application Laid-Open No. 8-335841

[0008] Patent Document 4: Japanese Patent Application Publication No. 2006-186960

[0009] Patent Document 5: International Publication No. 2019 / 163061 Summary of the invention

[0010] A filter device according to one embodiment of the present invention comprises: a multilayer substrate; a chip mounted on the multilayer substrate; a first filter, at least a portion of which is included in the chip; and a first hybrid coupler connected to the first filter, a portion of which is included in the multilayer substrate and another portion of which is included in the chip.

[0011] A multilayer substrate in one embodiment of the present disclosure comprises: a first surface; a pad located on the first surface and capable of mounting a chip; and a first circuit constituting a first hybrid coupler. The first circuit comprises: four inductors connected in series and electrically constituting a loop; and four ports electrically located between the four inductors. A first port among the four ports is connected to the pad. When the chip is not mounted on the pad, the first port is not connected to a reference potential portion.

[0012] A communication device according to one aspect of the present disclosure includes: the filter device described above; an antenna connected to the filter device; and an integrated circuit element connected to the antenna via the filter device. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is a perspective view showing the structure of the filter device according to the embodiment.

[0014] Figure 2 Yes means Figure 1 A schematic perspective view of a portion of the internal structure of a multilayer substrate of a filter device.

[0015] Figure 3 Yes means Figure 1 A circuit diagram of the structure of a portion of a filter device.

[0016] Figure 4 Yes means Figure 1 A schematic plan view of the structure of an elastic wave element included in a filter device.

[0017] Figure 5 Yes means Figure 1 Schematic plan view of the structure of a chip included in the filter device.

[0018] Figure 6 Yes means Figure 1 Circuit diagram of the structure of the filter device.

[0019] Figure 7 This is a block diagram showing the structure of a communication device according to an embodiment. DETAILED DESCRIPTION

[0020] The following describes the embodiments of the present disclosure with reference to the accompanying drawings. In addition, the drawings used in the following description are schematic. Therefore, for example, the dimensional ratios on the drawings may not be consistent with reality. In addition, the dimensional ratios, etc. are sometimes inconsistent between the drawings. Specific shapes and / or dimensions are sometimes exaggerated, or details are sometimes omitted. However, the above description does not deny that the actual shape and / or dimensions may differ from the attached drawings. Figure 1 or features of shape and / or size may be extracted from the accompanying drawings.

[0021] In the present disclosure, when the phase of a signal is "offset", etc., the phase may be advanced or delayed. However, for the sake of convenience, in the case described above, unless there is a contradiction, etc., "offset" etc. is common to various components and various signals, etc., and refers to only one of them. For example, when the phase of the second signal is offset by 90° relative to the phase of the first signal, and the phase of the fourth signal is offset by 90° relative to the phase of the third signal, the former offset and the latter offset are both offsets of 90° leading the phase, or both are offsets of 90° lagging the phase.

[0022] (Key Points of Filter Device According to Embodiment)

[0023] Figure 1 1 is a perspective view showing an example of the structure of the filter device 1 according to the embodiment. In addition, although the filter device 1 can be used in any direction as the top, in the following description, for convenience, the top direction is sometimes used as the bottom direction. Figure 1 The upper side in the figure (the side where the chip 5 is located on the multi-layer substrate 3) is expressed as the upper side.

[0024] The filter device 1 includes a multilayer substrate 3 and one or more chips 5 (two in the illustrated example) mounted on the multilayer substrate 3. The multilayer substrate 3 includes a plurality of external terminals 7. The filter device 1 filters a signal input from any of the plurality of external terminals 7, and outputs the signal from another of the plurality of external terminals 7.

[0025] Figure 3 is a circuit diagram showing an example of the structure of a part of the filter device 1 .

[0026] As described above, the filter device 1 includes the multilayer substrate 3 and the chip 5. In addition, in another viewpoint, the filter device 1 includes the first filter 9 and the mixer 11 connected to the first filter 9.

[0027] The first filter 9, for example, directly contributes to the filtering function of the filter device 1. More specifically, the first filter 9 is, for example, a bandpass filter that outputs a signal having a frequency within the passband by attenuating a signal having a frequency outside a predetermined passband among input signals. In addition, the mixer 11, for example, as described later, contributes to reducing the nonlinear distortion generated in the first filter 9.

[0028] The hybrid 11 is, for example, a 90° hybrid coupler of a lumped parameter type. The hybrid 11 has, for example, four series elements 15 (L1 to L4) connected in series to form a loop 13, and four parallel elements 17 (C1 to C4) connected to the portion between the four series elements 15 (four ports 19A to 19D). The four parallel elements 17 are grounded (connected to a reference potential portion). In the example shown in the figure, the four series elements 15 are inductors L1 to L4, and the four parallel elements 17 are four capacitors C1 to C4. In addition, in the following description, inductors L1 to L4 are sometimes not distinguished and are simply referred to as "inductors L". In addition, capacitors C1 to C4 are sometimes not distinguished and are simply referred to as "capacitors C". Ports 19A to 19D are sometimes not distinguished and are simply referred to as "port 19".

[0029] The first filter 9 is composed of one or more chips 5. In other words, the first filter 9 is included in one or more chips 5. A part of the mixer 11 is composed of the multilayer substrate 3 (is included in the multilayer substrate 3), and another part is composed of one or more chips 5 (is included in one or more chips 5). In the example shown in the figure, the loop 13 (series element 15) is included in the multilayer substrate 3, and the parallel element 17 (more specifically, the capacitor C2) is included in the chip 5.

[0030] According to such a structure, for example, the following effects can be achieved.

[0031] The mixer 11 does not perform the expected function for signals of all frequency bands, but performs the expected function for signals of a specific operating frequency (or a frequency band including the operating frequency, the same below, unless otherwise specified). The operating frequency of the mixer 11 is limited by the capacitance and inductance of the series element 15 and the parallel element 17.

[0032] Furthermore, the mixer 11 is connected to the first filter 9, for example, and is predetermined to perform a desired function on a signal passing through the first filter 9. Therefore, the operating frequency of the mixer 11 is set according to the passband of the first filter 9 to which the mixer 11 is connected.

[0033] According to the above, if the mixer 11 is entirely provided on the multilayer substrate 3, the multilayer substrate 3 must be a structure different from the first filter 9 (chip 5 from another point of view) having different passbands. That is, the filter devices 1 having different passbands have different multilayer substrates 3.

[0034] On the other hand, a part of the mixer 11 of the filter device 1 of the embodiment is provided on the chip 5. By adjusting the inductance and / or capacitance (capacitance in the example shown in the figure) of the above part, the operating frequency of the mixer 11 can correspond to the passband of the first filter 9. Therefore, the structure of the multilayer substrate 3 can be made common for the first filters 9 (chip 5) having different passbands. As a result, the productivity of the multilayer substrate 3 (filter device 1 from another point of view) is improved.

[0035] The above is the main point of the filter device 1 of the embodiment. Hereinafter, the filter device 1 will be described roughly in the following order.

[0036] 1. Overview of filter device 1 ( Figure 1 )

[0037] 2. Multilayer substrate 3 (excluding mixer 11)

[0038] 3. Basic features of mixer 11 ( Figure 3 )

[0039] 3.1. Operation of the mixer 11

[0040] 3.2. Circuit structure of mixer 11

[0041] 4. First filter 9

[0042] 4.1. Overview of the First Filter 9

[0043] 4.2. Example of elastic wave resonator ( Figure 4 )

[0044] 4.3. Ladder filter ( Figure 5 )

[0045] 5. Chip 5

[0046] 6. The portion of the mixer 11 located on the multilayer substrate 3 ( Figure 2 )

[0047] 7. The portion of the mixer 11 located on the chip 5 ( Figure 3 as well as Figure 5 )

[0048] 8. Example of overall circuit structure of filter device 1 ( Figure 6 )

[0049] 8.1. Basic characteristics of circuit structure

[0050] 8.2. Distribution of the Multilayer Substrate 3 and Chip 5 to the Filter Device 1

[0051] 9. A communication device comprising a filter device 1 ( Figure 7 )

[0052] 10. Summary of implementation methods

[0053] (1. Overview of filter equipment)

[0054] Figure 1 The filter device 1 shown is, for example, a chip-type electronic component of a surface mount type. For example, the filter device 1 has a layered conductor located on the lower surface as the above-mentioned multiple external terminals 7. The multiple external terminals 7 are bonded to the above-mentioned pads in a state opposite to each other with the pads located on the upper surface of the circuit board not shown in the figure through a conductive bonding material therebetween. The conductive bonding material is a protrusion in other viewpoints, and its material is, for example, solder (the same below). The number, position, shape, size, etc. of the multiple external terminals 7 can be appropriately set according to the function of the filter device 1, etc.

[0055] As described above, the filter device 1 has a multilayer substrate 3 and one or more chips 5. The number, position, shape, and size of the chips 5 can be appropriately set according to the functions required by the filter device 1. The filter device 1 may also have components other than those shown in the figure. As such components, for example, a sealing material or a cover covering the upper surface of the multilayer substrate 3 from above the chip 5 can be listed. The approximate shape and size of the filter device 1 as a chip-type electronic component are arbitrary. For example, the filter device 1 is generally a thin rectangular parallelepiped.

[0056] In addition, the filter device 1 may have various structures other than the illustrated examples as long as it includes the multilayer substrate 3 and the chip 5 (however, in the description of the embodiments, for convenience, the illustrated structure is sometimes used as a premise). In addition, the filter device 1 may be configured as a chip-type electronic component having only a filter function, or may be integrally and inseparably combined with an element having a function different from that of a filter.

[0057] For example, the filter device 1 may not be a chip-type electronic component. More specifically, for example, although not particularly illustrated, in a roughly plate-shaped module having a circuit board, an IC (integrated circuit) mounted or built into the circuit board, an antenna mounted or built into the circuit board, and the filter device 1, the multilayer substrate 3 may be the circuit board.

[0058] Furthermore, for example, the filter device 1 may include a container-shaped package that accommodates the multilayer substrate 3 and the chip 5. Furthermore, the external terminals provided on the package and the terminals (external terminals 7) of the multilayer substrate 3 may be electrically connected.

[0059] In addition, for example, the filter device 1 as a chip-type electronic component having an external terminal 7 on the multilayer substrate 3 is not limited to the type having a layered external terminal 7 on the lower surface. For example, the layered external terminal 7 located on the upper surface may also be connected to a circuit board not shown by a bonding wire. In addition, for example, the pin-shaped external terminal 7 may also be bonded to the multilayer substrate 3.

[0060] (2. Multilayer substrate)

[0061] The basic structure and material of the multilayer substrate 3 (circuit board) (except for the pattern and size of the specific conductor used to constitute the filter device 1) can be the same as the structure and material of various known printed substrates. For example, the multilayer substrate 3 can be an LTCC (Low Temperature Co-fi red Ceramics) substrate, an HTCC (High Temperature Co-fi red Ceramic) substrate, an IPD (Integrated Passive Device) substrate or an organic substrate.

[0062] Examples of LTCC substrates include substrates that can be fired at low temperatures (e.g., about 900°C) by adding glass-based materials to alumina. In LTCC substrates, for example, Cu or Ag can be used as conductive materials. Examples of HTCC substrates include substrates that use ceramics with alumina or aluminum nitride as the main component. In HTCC substrates, for example, tungsten or molybdenum can be used as conductive materials. Examples of IPD substrates include substrates in which passive components are formed on Si substrates. Examples of organic substrates include substrates in which a prepreg impregnated with resin is stacked on a base material made of glass or the like.

[0063] The multilayer substrate 3 has an insulating base 21 and a conductor 23 located inside and / or on the surface of the base 21. As can be understood from the description in the previous paragraph, the materials of the base 21 and the conductor 23 are arbitrary. The base 21 can have, for example, a plurality of insulating layers 21a stacked on each other. The shape and size of the base 21 are arbitrary. In the example shown in the figure, the base 21 is a thin rectangular parallelepiped. The conductor 23 can have, for example, a conductor layer (the reference numerals are omitted) located on the upper surface or lower surface (main surface) of the insulating layer 21a, and a via conductor (refer to Figure 2 , reference numerals are omitted). The number, position, shape, and size of the conductor layers and via conductors can be appropriately set according to the functions required of the multilayer substrate 3.

[0064] exist Figure 1In the example of the conductor 23 (conductor layer), the plurality of external terminals 7 and the plurality of pads 25 for mounting the chip 5 on the multilayer substrate 3 are illustrated. As an example of the overall circuit structure of the filter device 1 described later ( Figure 6 ) As understood by the above, each external terminal 7 and each pad 25 are connected to the wiring and / or components ( Figure 1 Therefore, the first filter 9 included in the chip 5 can filter the signal input from any external terminal 7 and output it to other external terminals 7.

[0065] For example, a plurality of pads 25 overlap on the upper surface of the substrate 21. For example, the plurality of pads 25 are bonded to the layered external terminals (not shown) located on the lower surface of the chip 5 via the conductive bonding material (not shown) therebetween in a state of being opposite to each other. Thus, the chip 5 is surface mounted on the multilayer substrate 3. The number, position, shape, and size of the plurality of pads 25 can be appropriately set according to the number of more than one chips 5 and the number, position, shape, and size of the external terminals of each chip 5. In addition, unlike the example shown in the figure, the pads 25 can also be electrically connected to the external terminals provided on the upper surface of the chip 5 through bonding wires.

[0066] (3. Basic characteristics of mixer)

[0067] (3.1. Working of the mixer)

[0068] As mentioned above, Figure 3 The mixer 11 shown is a 90° hybrid coupler having four ports 19. As is well known, the 90° hybrid coupler has functions as a distributor, a combiner, and a 90° phase shifter. Specifically, it is as follows. In addition, unless otherwise specified, the signal in the following description has a frequency that enables the mixer 11 to perform the desired function.

[0069] Ports 19A and 19B on the left side of the figure are connected to ports 19C and 19D on the right side of the figure, respectively. Here, connection means that a signal can flow. Therefore, for example, a signal input to port 19A can be output from ports 19C and 19D.

[0070] For convenience, the present embodiment may be described based on the positional relationship of the ports 19A to 19D in a diagram showing the mixer 11. However, the positional relationship of the four ports 19A to 19D in the diagram may not be consistent with the actual positional relationship of the four ports 19A to 19D.

[0071] The signal input to the port 19A on the left side of the figure is distributed to the ports 19C and 19D on the right side of the figure. The distribution ratio (ratio of the strength of the two distributed signals) is 1:1. In addition, the strength is, for example, voltage, current and / or power. The two distributed signals are offset from each other by 90° in phase.

[0072] The phase of the signal before distribution (e.g., the signal input to port 19A) and the phase of one of the two signals after distribution (e.g., the signal output from port 19C) may be the same. In addition, unlike the above, the phase of the signal before distribution may be different from the phase of both of the two signals after distribution. However, in the description of this embodiment, for convenience, the phase of the signal before distribution is sometimes described as the same as the phase of one of the two signals after distribution. Specifically, the phase of the signals of the ports (e.g., ports 19A and 19C) at the same position in the up-down direction in the figure are sometimes described as the same.

[0073] Although the case where a signal is input to port 19A is described as an example, the above operation is the same when a signal is input to other ports 19B to 19D. That is, a signal input to one of the two ports located in the left and right directions in the figure is distributed at a 1:1 distribution ratio and output from the other two ports located in the left and right directions in the figure. At this time, the phases of the two distributed signals are shifted by 90° from each other.

[0074] As described above, for convenience, when the phase is shifted, the various components and various signals are unified, and the phase shift refers to only one of leading and lagging. Moreover, in the expression of the drawings, the phase of the signal output from the port (for example, 19D) that is different from the port of the input signal in the vertical direction in the figure is shifted by 90° with respect to the signal output from the port (for example, 19C) that is at the same position in the vertical direction in the figure as the port of the input signal (for example, 19A).

[0075] In addition, since the mixer that operates as described above is called a 90° mixer, the relationship between the four ports of the mixer 11 can be determined only by the description related to a part of the ports. For example, it is described that port 19D is a port to which the following signal is allocated from port 19A, and the phase of the signal is shifted by 90° relative to the phase of the signal allocated from port 19A to port 19C. According to this description, it can be concluded that port 19A and the remaining port 19B are located on the same side in the left-right direction of the figure, port 19C and port 19D are located on the opposite side thereof, and port 19A and port 19C are located on the same side in the up-down direction of the figure, and port 19B and port 19D are located on the opposite side thereof. When the relationship between the four ports is described by the signal allocated from port 19A as described above, it is not necessary to set the mixer 11 in such a way that the signal is actually input from port 19A.

[0076] When signals are respectively input to ports 19A and 19B on the left side of the figure, each signal is allocated as described above, and the allocated signals are synthesized. For example, the signal input to port 19A is set to the first signal, and the signal input to port 19B is set to the second signal. The signals that make the first signal be allocated to ports 19C and 19D are used as the third signal and the fourth signal. The fourth signal is phase-shifted by 90° relative to the third signal. The signals that make the second signal be allocated to ports 19C and 19D are used as the fifth signal and the sixth signal. The fifth signal is phase-shifted by 90° relative to the sixth signal. At this time, the signal obtained by synthesizing the third signal and the fifth signal is output to port 19C, and the signal obtained by synthesizing the fourth signal and the sixth signal is output to port 19D. Although the example shows the case where the signal is input to the two ports 19A and 19B on the left side of the figure, the case where the signal is input to the two ports 19C and 19D on the right side of the figure is the same.

[0077] As described above, for example, there may be a phase difference between the first signal (input to port 19A) and the third signal (distributed to port 19C without phase shift), and there may also be a phase difference between the second signal (input to port 19B) and the sixth signal (distributed to port 19D without phase shift). In this case, the two phase differences are the same. The two phase differences when the directions of the signals are opposite are also the same as the two phase differences.

[0078] (3.2. Circuit structure of mixer)

[0079] The circuit structure of the mixer 11 (the basic structure except for the specific shape and size of the conductor, etc.) can be set in various ways, for example, it can be set to a known structure as long as it can achieve the above-mentioned functions and can separate a part (the part included in the multi-layer substrate 3) and another part that can adjust the operating frequency (the part included in the chip 5).

[0080] In the example shown in the figure, as described above, the mixer 11 includes four series elements 15 constituting the loop 13, and four parallel elements 17 for grounding the four ports 19. As another configuration, for example, the following configuration can be cited: each of the four series elements 15 includes two elements, and a parallel element 17 for grounding a portion between the two elements is provided instead of the parallel element 17 for grounding the port (for example, FIG. 8 of the aforementioned Patent Document 4).

[0081] In the mixer 11 having four series elements 15 constituting a loop 13 and four parallel elements 17 for grounding four ports 19, the series elements 15 and the parallel elements 17 can be various electronic elements (for example, inductors, capacitors, and resonators). In the example shown in the figure, as described above, the four series elements 15 are four inductors, and the four parallel elements 17 are four capacitors.

[0082] As structures other than the illustrated examples, for example, the following structures can be cited. A structure in which the four series elements 15 are four capacitors and the four parallel elements 17 are four inductors. A structure in which two series elements 15 are two inductors, the remaining two series elements 15 connecting the two inductors are two capacitors, and the four parallel elements 17 are four capacitors. A structure in which the two series elements 15 are two inductors, the remaining two series elements 15 connecting the two inductors are two parallel resonant circuits, and the four parallel elements 17 are four capacitors. A structure in which the four series elements 15 are four parallel resonant circuits, and the four parallel elements 17 are four capacitors. A structure in which the four series elements 15 are four inductors, and the four parallel elements 17 are four series resonant circuits.

[0083] The illustrated examples and the various methods listed in the previous paragraph are disclosed in the above-mentioned patent documents 3 to 5. In addition, the relationship between the values ​​of various parameters of the series element 15 and the parallel element 17 (such as inductors and capacitors) and the operating frequency is also a well-known conventional technology, or is described in the above-mentioned patent documents 3 to 5. Therefore, all the relationships between the values ​​of the parameters in various methods and the operating frequency are not described here.

[0084] In the example shown in the figure, the inductances of the inductors L1 and L3 are the same. The inductances of the inductors L2 and L4 are the same. The inductances of the inductors L1 and L3 and the inductances of the inductors L2 and L4 are usually different. In addition, the capacitances of the capacitors C1 to C4 are the same. If the capacitances of the capacitors C1 to C4 are increased, for example, the operating frequency of the mixer 11 becomes lower.

[0085] In the description of the embodiments, for convenience, the structure of the mixer 11 is sometimes referred to as Figure 3The following description is based on the premise that the examples are the same as those in the previous section.

[0086] Each series element 15 may be composed of two or more elements. In addition, part or all of each series element 15 may be shared with part or all of the elements other than the mixer 11. The same is true for the parallel element 17. Figure 3 In the example of , as described in detail later, the capacitor C2 includes a capacitor C2a dedicated to the mixer 11 and a parallel resonator 29P of the first filter 9. That is, the parallel resonator 29P of the first filter 9 is shared by the mixer 11 as a part of the capacitor C2.

[0087] (4. First filter)

[0088] (4.1. Overview of the first filter)

[0089] As described above, the first filter 9 is, for example, a bandpass filter that allows a signal of a specified passband to pass. The passband (center frequency and bandwidth) is arbitrary. For example, the passband may be within the range of 300 MHz to 10 GHz. In addition, the passband may be a passband that complies with a specified standard. The passband may correspond to a passband determined by the standard, or may include more than two passbands determined by the standard.

[0090] The specific structure of the first filter 9 can be various structures, for example, it can be a well-known structure. More specifically, for example, the first filter 9 can be a piezoelectric filter including a piezoelectric body, a dielectric filter using electromagnetic waves in a dielectric, an LC filter combining an inductor and a capacitor, or a combination of two or more thereof. The piezoelectric filter can be an elastic wave filter using elastic waves, or a filter that does not use elastic waves (for example, a filter using a piezoelectric oscillator).

[0091] As long as elastic waves are used, elastic wave filters may be of various types. For example, an elastic wave filter may be a filter that excites elastic waves by using an IDT (interdigital transducer) electrode located on the surface of a piezoelectric body, or a filter that excites elastic waves by using electrodes that are opposite to each other with a piezoelectric film sandwiched therebetween (a piezoelectric thin film resonator). In addition, for example, an elastic wave filter may be a ladder filter in which a plurality of elastic wave resonators are connected in a ladder shape, or a multimode filter (including a dual-mode filter) in which a plurality of IDT electrodes are arranged in the propagation direction of the elastic wave, or a transverse filter that receives and transmits elastic waves between two IDT electrodes.

[0092] The elastic wave may be, for example, a SAW (Surface Acoustic Wave), a BAW (Bulk Acoustic Wave), a boundary elastic wave, or a plate wave. However, these elastic waves cannot necessarily be clearly distinguished.

[0093] In the description of the embodiment, for convenience, a ladder filter in which elastic wave resonators using IDT electrodes are connected in a ladder shape is mainly used as an example as the first filter 9. Figure 4 , an example of an elastic wave resonator is described. Figure 5 , the ladder filter is explained.

[0094] (4.2. Example of elastic wave resonator)

[0095] Figure 4 1 is a plan view schematically showing the structure of elastic wave resonator 29 (hereinafter, sometimes simply referred to as “resonator 29 ”).

[0096] The resonator 29 can be upward or downward in any direction, but for convenience, an orthogonal coordinate system consisting of the D1 axis, the D2 axis, and the D3 axis is given in the drawings, and the +D3 side is regarded as the upward direction, and sometimes the terms such as the upper surface or the lower surface are used. In addition, the D1 axis is defined as being parallel to the propagation direction of the elastic wave propagating along the upper surface of the piezoelectric body described later, the D2 axis is defined as being parallel to the upper surface of the piezoelectric body and being orthogonal to the D1 axis, and the D3 axis is defined as being orthogonal to the upper surface of the piezoelectric body.

[0097] The resonator 29 is composed of a so-called one-port elastic wave resonator. For example, the resonator 29 outputs a signal input from one of the two terminals 28 schematically shown on both sides of the figure from the other of the two terminals 28. At this time, the resonator 29 converts the electrical signal into an elastic wave and converts the elastic wave into an electrical signal. In addition, the terminal 28 can be understood as a reference numeral 28 described later. Figure 6 The antenna terminal, the transmission terminal, the reception terminal, or the terminal described are abstracted from the reference potential portion.

[0098] The resonator 29 includes, for example, a piezoelectric substrate 31 (at least a portion of the upper surface 31a side thereof), an IDT electrode 33 (an excitation electrode in a higher concept) located on the upper surface 31a, and a pair of reflectors 35 located on both sides of the IDT electrode 33. A plurality of resonators 29 may be formed on one piezoelectric substrate 31. That is, the piezoelectric substrate 31 may be shared by a plurality of resonators 29. In the following description, in order to distinguish between a plurality of resonators 29 sharing the same piezoelectric substrate 31, for convenience, it is sometimes expressed that, for example, a combination of an IDT electrode 33 and a pair of reflectors 35 (electrode portion of the resonator 29) is a resonator 29 (for example, the resonator 29 does not include the piezoelectric substrate 31).

[0099] The piezoelectric substrate 31 has piezoelectricity at least in the region where the resonator 29 is provided on the upper surface 31a. As such a piezoelectric substrate 31, for example, a substrate in which the entire substrate is composed of a piezoelectric body. In addition, for example, a so-called bonded substrate can be cited. The bonded substrate includes: a substrate (piezoelectric substrate) composed of a piezoelectric body having an upper surface 31a, and a supporting substrate directly bonded to the side of the piezoelectric substrate opposite to the upper surface 31a with or without an adhesive. The supporting substrate may have a cavity below the piezoelectric substrate, or may not have a cavity. In addition, as the piezoelectric substrate 31, for example, a supporting substrate and a substrate in which a film (piezoelectric film) composed of a piezoelectric body or a plurality of films including a piezoelectric film is formed on a part of the main surface on the +D3 side of the supporting substrate or on the entire main surface.

[0100] The piezoelectric body 31b constituting at least the region where the resonator 29 is provided in the piezoelectric substrate 31 is composed of, for example, a single crystal having piezoelectricity. Examples of materials constituting such a single crystal include lithium tantalate (LiTaO3), lithium niobate (LiNbO3), and quartz (SiO2). The cut angle, plane shape, and various dimensions can be appropriately set.

[0101] The IDT electrode 33 and the reflector 35 are composed of a layered conductor disposed on the piezoelectric substrate 31. The IDT electrode 33 and the reflector 35 are, for example, made of the same material and thickness. The layered conductor that constitutes them is, for example, a metal. The metal is, for example, Al or an alloy having Al as a main component (Al alloy). The Al alloy is, for example, an Al-Cu alloy. The layered conductor may also be composed of a plurality of metal layers. The thickness of the layered conductor is appropriately set according to the electrical characteristics required for the resonator 29, etc. As an example, the thickness of the layered conductor is greater than 50 nm and less than 600 nm.

[0102] The IDT electrode 33 includes a pair of comb-tooth electrodes 37 (one of which is hatched for better visibility). Each comb-tooth electrode 37 includes, for example, a bus bar 39, a plurality of electrode fingers 41 extending in parallel from the bus bar 39, and a plurality of dummy electrodes 43 protruding from the bus bar 39 between the plurality of electrode fingers 41. The pair of comb-tooth electrodes 37 is configured so that the plurality of electrode fingers 41 mesh with each other (intersect).

[0103] The bus bar 39 is, for example, formed roughly in the shape of a long strip extending linearly in the propagation direction of the elastic wave (direction D1) with a constant width. In addition, a pair of bus bars 39 are opposite to each other in a direction (direction D2) orthogonal to the propagation direction of the elastic wave. In addition, the bus bar 39 may have a variable width or be inclined relative to the propagation direction of the elastic wave.

[0104] Each electrode finger 41 is, for example, roughly formed into a strip shape extending linearly in a direction (D2 direction) perpendicular to the propagation direction of the elastic wave with a constant width. In addition, the width of the electrode finger 41 may also be variable. In each comb-tooth electrode 37, a plurality of electrode fingers 41 are arranged along the propagation direction of the elastic wave. In addition, the plurality of electrode fingers 41 of one comb-tooth electrode 37 and the plurality of electrode fingers 41 of another comb-tooth electrode 37 are basically arranged alternately.

[0105] The pitch p of the plurality of electrode fingers 41 (for example, the distance between the centers of two adjacent electrode fingers 41) is basically constant in the IDT electrode 33. However, a narrow pitch portion having a pitch p narrower than that of the majority of the other portions, or a wide pitch portion having a pitch p wider than that of the majority of the other portions may be provided in a portion of the IDT electrode 33. Furthermore, a spaced-out portion in which the electrode fingers 41 are substantially removed may exist in a portion of the IDT electrode 33.

[0106] In the description of the embodiments, unless otherwise specified, when the pitch p is mentioned, it refers to the pitch of the portion (most of the plurality of electrode fingers 41) excluding the special portions such as the narrow pitch portion, the wide pitch portion, or the spaced-out portion. In addition, in the majority of the electrode fingers 41 excluding the special portions, when the pitch varies, the average value of the pitch of the majority (for example, 80% of the total number of electrode fingers 41 selected in such a way as to minimize the variance) can be used as the value of the pitch p.

[0107] The number of electrode fingers 41 can be appropriately set according to the electrical characteristics required of the resonator 29 and the like. Figure 4 This is a schematic diagram, so the number of electrode fingers 41 is shown to be small. In fact, more electrode fingers 41 than shown in the figure can be arranged. The same applies to the strip electrodes 47 of the reflector 35 described later.

[0108] The lengths of the plurality of electrode fingers 41 are, for example, the same as each other. In addition, the IDT electrode 33 may be subjected to so-called apodization in which the lengths of the plurality of electrode fingers 41 (in other viewpoints, the staggered width W) vary according to the position in the propagation direction. The length and width of the electrode fingers 41 may also be appropriately set according to the required electrical characteristics, etc.

[0109] The dummy electrode 43 protrudes in a direction perpendicular to the propagation direction of the elastic wave with a substantially constant width, for example. Its width is, for example, equal to the width of the electrode finger 41. In addition, the plurality of dummy electrodes 43 are arranged at the same pitch as the plurality of electrode fingers 41, and the distal end of the dummy electrode 43 of one comb-tooth electrode 37 is opposite to the distal end of the electrode finger 41 of another comb-tooth electrode 37 with a gap therebetween. In addition, the IDT electrode 33 may not include the dummy electrode 43.

[0110] A pair of reflectors 35 are located on both sides of the IDT electrode 33 in the propagation direction of the elastic wave. Each reflector 35 may be in an electrically floating state, for example, or may be given a reference potential. Each reflector 35 may be formed in a lattice shape, for example. That is, the reflector 35 includes: a pair of bus bars 45 facing each other and a plurality of strip electrodes 47 extending between the pair of bus bars 45. The spacing between the plurality of strip electrodes 47 and the spacing between the electrode fingers 41 and the strip electrodes 47 adjacent to each other are substantially the same as the spacing between the plurality of electrode fingers 41.

[0111] When a voltage is applied to the pair of comb-tooth electrodes 37, a voltage is applied to the piezoelectric body 31b through the plurality of electrode fingers 41, and the piezoelectric body 31b vibrates. That is, an elastic wave is excited. Among elastic waves of various wavelengths propagating in various directions, an elastic wave propagating in the arrangement direction of the plurality of electrode fingers 41 with a pitch p of the plurality of electrode fingers 41 being approximately half a wavelength (λ / 2) tends to have a large amplitude because the plurality of waves excited by the plurality of electrode fingers 41 overlap in phase.

[0112] In addition, the elastic wave propagating in the piezoelectric body 31b is converted into an electrical signal through the plurality of electrode fingers 41. At this time, similarly to when the elastic wave is excited, the intensity of the electrical signal after the elastic wave propagating in the arrangement direction of the plurality of electrode fingers 41 with the pitch p of the plurality of electrode fingers 41 being approximately half a wavelength (λ / 2) tends to become stronger.

[0113] By the above-mentioned action (and other actions not described here), the resonator 29 functions as a resonator that resonates at a frequency of an elastic wave having a pitch p of approximately half the wavelength (λ / 2). The pair of reflectors 35 contribute to locking the elastic wave.

[0114] Although not particularly shown in the figure, the resonator 29 may also include a protective film (not shown) covering the upper surface 31a of the piezoelectric substrate 31 from above the IDT electrode 33 and the reflector 35. This protective film is made of an insulating material such as SiO2, for example, and helps to reduce the possibility of corrosion of the IDT electrode 33 and the like, and / or compensate for the change in characteristics caused by the temperature change of the resonator 29. In addition, the resonator 29 may also include an additional film having a shape that overlaps with the upper surface or the lower surface of the IDT electrode 33 and the reflector 35 and is basically accommodated in the IDT electrode 33 and the reflector 35 in a top perspective view. This additional film is made of an insulating material or a metal material having acoustic characteristics different from those of the material of the IDT electrode 33 and the like, for example, and helps to improve the reflection coefficient of the elastic wave.

[0115] (4.3. Ladder filter)

[0116] Figure 5 1 is a plan view showing a ladder filter as an example of the first filter 9. As can be understood from the orthogonal coordinate system D1D2D3, this figure is Figure 4 Similarly, the upper surface 31a of the piezoelectric substrate 31 (piezoelectric body 31b) is shown. In addition, in another viewpoint, Figure 5 It can also be understood as a schematic diagram of looking down at the piezoelectric substrate 31 included in the chip 5 from the multi-layer substrate 3 side.

[0117] The first filter 9 outputs a signal having a frequency within a predetermined passband among signals input to the input terminal 49I to the output terminal 49O. A signal having a frequency outside the passband is released to the GND terminal 49G to which a reference potential is given. In addition, these terminals are sometimes collectively referred to as the terminal 49.

[0118] The first filter 9 is formed by connecting a plurality of resonators 29 (29S and 29P) in a ladder shape. That is, the first filter 9 has a plurality of (one or more) series resonators 29S and a plurality of (one or more) parallel resonators 29P (parallel arms), wherein the series resonator 29S is connected in series between the input terminal 49I and the output terminal 49O, and the parallel resonator 29P is connected in parallel between the series line (series arm 51) of the series resonator 29S and the GND terminal 49G (reference potential portion). Each parallel resonator 29P is connected to the input terminal 49I side or the output terminal 49O side with respect to any series resonator 29S. That is, the plurality of parallel resonators 29P connect a plurality of electrically different positions in the series arm 51 to the GND terminal 49G.

[0119] Although not specifically shown in the figure, the impedance of each resonator 29 is a minimum value at the resonant frequency, and the impedance is a maximum value at the anti-resonant frequency. In the plurality of series resonators 29S, the resonant frequencies are set to be substantially the same as each other, and the anti-resonant frequencies are set to be substantially the same as each other. In addition, in the plurality of parallel resonators 29P, the resonant frequencies are set to be substantially the same as each other, and the anti-resonant frequencies are set to be substantially the same as each other. The resonant frequency of the series resonator 29S and the anti-resonant frequency of the parallel resonator 29P are set to be substantially the same.

[0120] By the above connection relationship and the setting of the resonant frequency and the anti-resonant frequency, a bandpass filter can be realized. The center frequency of the passband is substantially the same as the resonant frequency of the series resonator 29S and the anti-resonant frequency of the parallel resonator 29P. The width of the passband is slightly narrower than the width from the resonant frequency of the parallel resonator 29P to the anti-resonant frequency of the series resonator 29S.

[0121] The number of series resonators 29S and parallel resonators 29P is arbitrary. In addition, the first filter 9 may have a parallel resonator 29P (the example shown in the figure), wherein the parallel resonator 29P is connected to the side closer to the input terminal 49I than the series resonator 29S electrically closest to the input terminal 49I, or may not have the parallel resonator 29P. Similarly, the first filter 9 may have a parallel resonator 29P (the example shown in the figure), wherein the parallel resonator 29P is connected to the side closer to the output terminal 49O than the series resonator 29S electrically closest to the output terminal 49O, or may not have the parallel resonator 29P.

[0122] Although not specifically shown, each series resonator 29S may be divided into two or more. For example, each series resonator 29S may have a plurality of resonators 29 connected in series with each other. Similarly, each parallel resonator 29P may be divided into two or more. The specific positions of the series resonators 29S and the parallel resonators 29P on the upper surface 31a of the piezoelectric body 31b, the shape and size of each resonator 29, etc., may be appropriately set according to the characteristics required by the first filter 9, etc. In addition, the first filter 9 may also have a structure other than the resonator 29. For example, an inductor or a capacitor connected in series or in parallel with the resonator 29 may also be provided.

[0123] (5. Chip)

[0124] The chip 5 may be composed of a piezoelectric substrate 31 for most of it. Specifically, for example, the chip 5 may have a piezoelectric substrate 31 and a relatively thin layer overlapping the surface of the piezoelectric substrate 31. As the relatively thin layer, for example, there can be listed: a conductive layer (IDT electrode 33, etc.) overlapping the upper surface 31a of the piezoelectric substrate 31, and a protective film (not shown) covering most of the upper surface 31a from above the conductive layer. In addition, the protective film does not cover the terminals (49I, 49O and 49G). In addition, the chip 5 may also have a layer covering the side or lower surface of the piezoelectric substrate 31.

[0125] The chip 5 of the structure described in the previous paragraph is, for example, such that the upper surface 31a is aligned with the upper surface ( Figure 1 The chip 5 is mounted on the multilayer substrate 3 with the upper surface of the chip 5 facing each other. At this time, the terminal 49 of the chip 5 and the pad 25 of the multilayer substrate 3 face each other and are bonded by a conductive bonding material (not shown) therebetween. Between the chip 5 and the multilayer substrate 3 (on the resonator 29 in other viewpoints), a space having a height substantially equivalent to the thickness of the bonding material bonding the terminal 49 and the pad 25 is formed.

[0126] In addition, for example, although not specifically shown in the figure, in addition to the above structure, the chip 5 may also have a box-shaped insulating cover covering the upper surface 31a of the piezoelectric substrate 31. The cover forms a space above the resonator 29. The chip 5 has, for example, a columnar terminal located above the terminal 49 and penetrating the cover. The chip 5 is a structure in which the upper surface of the cover is connected to the upper surface ( Figure 1 At this time, the upper surface of the columnar terminal and the pad 25 of the multilayer substrate 3 face each other and are bonded with a conductive bonding material (not shown) therebetween.

[0127] For example, Figure 5 As shown in the example, one chip 5 may include one first filter 9. In addition, one chip 5 may include only a portion of one first filter 9. For example, a plurality of series resonators 29S and a plurality of parallel resonators 29P constituting the same first filter 9 may be provided in chips 5 independent of each other. In addition, one chip 5 may also include more than two first filters 9. The number of terminals 49 that one chip 5 has may be appropriately set according to the different structures as described above.

[0128] (6. Part of the multilayer substrate located in the mixer)

[0129] Figure 2 1 is a perspective view showing a portion of the hybrid 11 located on the multilayer substrate 3. In this figure, the outline of the multilayer substrate 3 is shown by a dotted line, and a conductor constituting a portion of the hybrid 11 is shown by a solid line.

[0130] The portion of the mixer 11 located on the multilayer substrate 3 can be selected arbitrarily. Figure 2 In the example of , the multilayer substrate 3 has four series elements 15 (more specifically, four inductors L). In other words, the multilayer substrate 3 does not have four parallel elements 17 (more specifically, four capacitors C).

[0131] Different from the example shown in the figure, for example, the multilayer substrate 3 may include 1 to 3 of the four series elements 15 (conversely, it may not include 1 to 3 series elements 15). In addition, for example, the multilayer substrate 3 may include 1 to 4 of the four parallel elements 17 as long as it does not include all of the mixers 11. In the multilayer substrate 3, the combination of the number of series elements 15 and the number of parallel elements 17 is also arbitrary.

[0132] Furthermore, unlike the illustrated example, the multilayer substrate 3 may also include a portion of a series element 15 and / or a portion of a parallel element 17. For example, the capacitance required by the capacitor C1 may be realized by a combined capacitance of the capacitance of the capacitor provided in the multilayer substrate 3 and the capacitance of the capacitor provided in the chip 5. Furthermore, adjustment corresponding to the operating frequency may be realized, for example, by the capacitance of the capacitor provided in the chip 5.

[0133] The specific structure of the series element 15 and / or the parallel element 17 possessed by the multilayer substrate 3 (in other words, built into the multilayer substrate 3) is arbitrary. For example, the series element 15 and / or the parallel element 17 may be an element manufactured in the multilayer substrate 3, or a chip embedded in the multilayer substrate 3, or a combination of the two. As the element manufactured in the multilayer substrate 3, in more detail, for example, there can be listed: Figure 1 ) is an element composed of overlapping conductor layers (reference numerals omitted), and / or via conductors (reference numerals omitted) penetrating the insulating layer 21a.

[0134] In the description of the embodiment, unless otherwise specified, the elements (15 and 17, etc.) of the multilayer substrate 3 refer to, for example, elements that cannot be separated from the multilayer substrate 3 unless the multilayer substrate 3 is destroyed. Therefore, for example, the elements of the multilayer substrate 3 do not include elements (such as chips) mounted on the surface of the multilayer substrate 3 by conductive bonding materials. In addition, the elements of the multilayer substrate 3 may be located entirely inside the multilayer substrate 3 or partially exposed outside the multilayer substrate 3.

[0135] The specific structure of the inductor and / or capacitor in the case where the inductor and / or capacitor is manufactured in the multilayer substrate 3 is also arbitrary. For example, the inductor can be composed of a conductor extending in a spiral shape, or a layered conductor extending in a vortex shape, or a layered conductor extending in a meandering shape. The capacitor can be composed of two layers of layered conductors (parallel plates) facing each other across the insulating layer 21a, or layered conductors (parallel plates) in the same layer facing each other on the surface of the insulating layer 21a, or a pair of comb-tooth electrodes (refer to the IDT electrode 33) located on the surface of the insulating layer 21a. In other viewpoints, the inductor and / or capacitor can be three-dimensional or two-dimensional.

[0136] exist Figure 2 In the example of FIG. 1 , the inductors L1 to L4 are manufactured in the multilayer substrate 3. Specifically, the multilayer substrate 3 is provided with a plurality of insulating layers 21a ( Figure 1 ) is a three-dimensional coil shape with the stacking direction being axial. More specifically, although no particular reference numeral is given, the inductor has: a plurality of conductor layers extending between the plurality of insulating layers 21a in a manner that is less than one circle (half a circle in the example shown in the figure), and a plurality of via conductors that penetrate the plurality of insulating layers 21a and connect the plurality of conductor layers to each other. In addition, the three-dimensional coil-shaped inductors L1 to L4 manufactured in the multilayer substrate 3 may be different from the example shown in the figure, and may be composed of conductor layers and via conductors with the direction along the insulating layer 21a as the axial direction.

[0137] The portion between the four inductors L becomes port 19. In addition, Figure 2 , for convenience, reference numerals of ports 19A to 19D are given to four via conductors extending upward from four layered wirings (reference numerals omitted) that connect four inductors L in series. However, from an electrical point of view (ignoring the inductance of the wiring, etc.), not only the above-mentioned four via conductors but also any positions of the above-mentioned four layered wirings or unillustrated conductors connected to the upper ends of the via conductors can be regarded as ports 19A to 19D.

[0138] (7. The part of the chip located in the mixer)

[0139] The portion of the mixer 11 located in the chip 5 can be arbitrarily selected. The description of the example of the arbitrarily selected portion is omitted because it is the opposite of the description of the example of the portion selected as the portion located in the multilayer substrate 3 in the above-mentioned mixer 11. In the description of the embodiment, for convenience, unless otherwise specified, the capacitors C1 to C4 as the parallel elements 17 of the mixer 11 are mainly taken as an example to be located in the chip 5, and the description is sometimes given based on this method.

[0140] The specific structure of the series element 15 and / or parallel element 17 of the chip 5 is arbitrary. For example, as in the case of being set on the multilayer substrate 3, the series element 15 and / or parallel element 17 can be manufactured in the substrate (e.g., piezoelectric substrate 31) included in the chip 5, or can be buried in the substrate (e.g., piezoelectric substrate 31) included in the chip 5. In addition, unlike the case of the multilayer substrate 3, the element (15 and / or 17) can also be a chip mounted on the surface of the substrate (e.g., piezoelectric substrate 31) included in the chip 5. In addition, in the embodiment in which the chip 5 has a cover covering the piezoelectric substrate 31 as described above, the element (15 and / or 17) can also be composed of a conductor (conductor layer and / or through conductor) located on the surface and / or inside of the cover. The element (15 and / or 17) can be realized by a combination of the above-mentioned various structures. In any case, when the chip 5 is mounted on the multilayer substrate 3, the series element 15 and / or parallel element 17 of the chip 5 is electrically connected to the rest of the mixer 11.

[0141] The specific structure of the inductor and / or capacitor in the case where the inductor and / or capacitor is manufactured in the cover portion covering the piezoelectric substrate 31 or the cover portion covering the piezoelectric substrate 31 is arbitrary, as is the case where the inductor and / or capacitor is manufactured in the multilayer substrate 3. For example, the inductor may be a spiral, vortex, or meandering shape, and the capacitor may be a parallel flat plate of two layers, a parallel flat plate in one layer, or a pair of comb-tooth electrodes.

[0142] exist Figure 5 In the example shown, the capacitor C2 as the parallel element 17 is formed of a conductor located on the upper surface of the piezoelectric substrate 31 (piezoelectric body 31b). Specifically, the capacitor C2 includes a capacitor C2a and a capacitor C2b.

[0143] exist Figure 5 In the description of , among the plurality of terminals 49, the output terminal 49O is a terminal directly connected (not through other filters or other mixers) to the portion (loop 13) located in the multilayer substrate 3 in the mixer 11. That is, the output terminal 49O is directly connected to any one of the ports 19A to 19D. Here, for convenience, the output terminal 49O is connected to the multilayer substrate 3 directly (not through other filters or other mixers). Figure 3 , the output terminal 49O is connected to the port 19B. Furthermore, the capacitor C2 is connected to a position closer to the output terminal 49O than the series resonator 29S located closest to the output terminal 49O (port 19B in other viewpoints). Thus, the capacitor C2 functions as the parallel element 17 constituting the mixer 11.

[0144] Furthermore, since both capacitors C2a and C2b are connected to a position closer to the output terminal 49O than the series resonator 29S located closest to the output terminal 49O, the combined capacitance of both becomes the capacitance of the parallel element 17 (capacitor C2). More specifically, since capacitors C2a and C2b are connected in parallel between the output terminal 49O (port 19B) and the GND terminal 49G, the sum of the capacitances of capacitors C2a and C2b becomes the capacitance of capacitor C2.

[0145] exist Figure 5 In the example of FIG. 1 , the connection position of capacitor C2a with respect to series arm 51 is, for example, closer to output terminal 49O than the connection position of capacitor C2b with respect to series arm 51 (in the example shown in the figure). However, unlike the example shown in the figure, the former position may be the same as the latter position, or may be farther from output terminal 49O. In addition, for example, the wiring extending from series arm 51 may branch and extend to capacitors C2a and C2b.

[0146] exist Figure 5 In the example of FIG. 1 , capacitors C2a and C2b are connected to the same GND terminal 49G, for example. Unlike the example shown in the figure, the wiring extending from capacitors C2a and C2b may merge and extend to the GND terminal 49G. In addition, capacitors C2a and C2b may be connected to different GND terminals 49G.

[0147] exist Figure 5 In the example, capacitor C2a is composed of a pair of comb-tooth electrodes (illustration marks omitted) that are the same as the IDT electrode 33. However, since capacitor C2a does not use elastic waves, the arrangement direction of the multiple electrode fingers may not be parallel to the propagation direction of the elastic waves (D1 direction). In the example shown in the figure, the arrangement direction of the multiple electrode fingers in capacitor C2a is orthogonal to the propagation direction of the elastic waves. In addition, it should be noted that the arrangement direction of the multiple electrode fingers in capacitor C2a can be parallel to the propagation direction of the elastic waves, or can be inclined at an angle less than 90°.

[0148] In addition, since the capacitor C2a does not use elastic waves, unlike the IDT electrode 33 of the resonator 29, reflectors may not be provided on both sides of a pair of comb-tooth electrodes (the example shown in the figure). However, unlike the example shown in the figure, in order to reduce the possibility that the elastic waves generated by the capacitor C2a will have an unexpected effect on the resonator 29, etc., one or two reflectors adjacent to the capacitor C2a may also be provided. In addition, the capacitor C2a may not have the dummy electrode 43, and the spacing of the electrode fingers may also be set arbitrarily. For example, the spacing of the capacitor C2a may be smaller than the spacing of the elastic wave resonator.

[0149] The pair of comb-shaped electrodes of the capacitor C2a are made of, for example, the same material and thickness as those of the IDT electrode 33 of the resonator 29. However, the materials and thicknesses of the two electrodes may be different.

[0150] The capacitor C2b is formed by the IDT electrode 33 of the parallel resonator 29P. That is, the parallel resonator 29P connected to the output terminal 49O side relative to the series resonator 29S closest to the output terminal 49O is shared by the capacitor C2b.

[0151] Furthermore, unlike the example shown in the figure, the capacitor C2 may be constituted only by the capacitor C2 a which is not shared by the first filter 9 , or conversely, may be constituted only by the capacitor C2 b which is shared by the first filter 9 .

[0152] (8. Example of Overall Circuit Configuration of Filter Device 1)

[0153] (8.1. Basic characteristics of circuit structure)

[0154] The overall circuit structure of the filter device 1 having the first filter 9 and the mixer 11 described above (except for the features related to the structure in which the parallel element 17 is provided on the chip 5, etc.) can be of various types, for example, it can be the same as a known structure. An example of the overall circuit structure of the filter device 1 is shown below.

[0155] Figure 6 1 is a schematic diagram showing an example of the overall circuit configuration of the filter device 1 .

[0156] Figure 6 The filter device 1 shown in the example is configured as a splitter (more specifically, a duplexer). The filter device 1 has, for example, a transmission path 2T, wherein the transmission path 2T filters the transmission signal from the transmission terminal 7T and outputs it to the antenna terminal 7A, and the reception path 2R filters the reception signal from the antenna terminal 7A and outputs it to the reception terminal 7R. The transmission terminal 7T, the reception terminal 7R, and the antenna terminal 7A are respectively Figure 1 An example of the external terminal 7 is shown.

[0157] The transmission path 2T has a transmission filter system 12 that is directly responsible for filtering the transmission signal. The transmission filter system 12 includes transmission filters 9TA and 9TB (in addition, sometimes the two are not distinguished and only the transmission filter 9T is called). In addition, the reception path 2R has a reception filter system 14 that is directly responsible for filtering the reception signal. The reception filter system 14 has a reception filter 9R. The transmission filter 9T and the reception filter 9R are respectively an example of the first filter 9. The transmission filter system 12 (transmission filter 9T) corresponds to the transmission frequency band. The reception filter system 14 (reception filter 9R) corresponds to the reception frequency band. In other words, the passbands of the transmission filter 9T and the reception filter 9R are different from each other (do not overlap each other).

[0158] In addition, the filter device 1 has a first mixer 11A and a second mixer 11B. The first mixer 11A and the second mixer 11B are each an example of the mixer 11. The first mixer 11A is located between the antenna terminal 7A, the transmission filters 9TA and 9TB, and the reception filter 9R. The second mixer 11B is located between the transmission terminal 7T, the transmission filters 9TA and 9TB, and the terminal resistor 61. Between the first mixer 11A and the second mixer 11B, a signal path via the transmission filter 9TA and a signal path via the transmission filter 9TB are formed.

[0159] The first mixer 11A and the second mixer 11B distribute, phase-adjust and / or synthesize the transmission signal and / or the reception signal. In this process, for example, the nonlinear distortion generated in the transmission filter 9T and / or the reception filter 9R is distributed, and the distributed nonlinear distortions are mutually inverted, and then the inverted nonlinear distortions are synthesized and cancel each other out. That is, the nonlinear distortion is reduced. On the other hand, the filter device 1 basically maintains the strength of the transmission signal and the reception signal.

[0160] The specific connection relationship of the above-mentioned circuit structure and the principle of the above-mentioned effect are described in Patent Document 1. Therefore, the main points of the circuit structure of the illustrated example will be briefly described below.

[0161] Transmit filters 9TA and 9TB correspond to the same passband (transmit frequency band). That is, the passbands of the two are substantially and / or identical in design. Transmit filters 9TA and 9TB are set to structures that are identical or similar to each other, and substantially or in design have the same characteristics as each other. However, transmit filters 9TA and 9TB may also be fine-tuned so that the passbands are slightly different and / or the characteristics are slightly different.

[0162] In the first hybrid 11A, the port 19A is connected to the antenna terminal 7A. The port 19B is connected to the reception filter 9R. The port 19C is connected to the transmission filter 9TA. The port 19D is connected to the transmission filter 9TB.

[0163] In the second hybrid 11B, the port 19A is connected to the transmission filter 9TA. The port 19B is connected to the transmission filter 9TB. The port 19C is connected to the terminal resistor 61. The port 19D is connected to the transmission terminal 7T.

[0164] In other viewpoints, the transmit filter system 12 is connected to the antenna terminal 7A via the first mixer 11A and to the transmit terminal 7T via the second mixer 11B. The receive filter system 14 is connected to the antenna terminal 7A via the first mixer 11A and directly to the receive terminal 7R.

[0165] When a signal (e.g., a transmission signal) is input from the outside to the transmission terminal 7T, two signals whose phases are mutually shifted by 90° by the second mixer 11B are distributed to the transmission filters 9TA and 9TB. The two distributed signals pass through the transmission filters 9TA and 9TB and are input to the first mixer 11A. The two signals input to the first mixer 11A are converted into in-phase signals and output to the antenna terminal 7A.

[0166] On the other hand, the two signals input to the first mixer 11A are not output to the receiving filter 9R (ideally). This is because the two signals become inverted when they go to the port 19B and cancel each other out. In the above description, the transmission signal is used as an example, but the nonlinear distortion generated in the transmission filter 9T also cancels each other out in the same way.

[0167] When a signal (e.g., a received signal) is input from the antenna to the antenna terminal 7A, two signals whose phases are mutually shifted by 90° by the first mixer 11A are distributed to the transmission filters 9TA and 9TB. The two distributed signals are reflected by the transmission filters 9TA and 9TB and return to the first mixer 11A. The two signals returned to the first mixer 11A are converted into in-phase signals and output to the reception filter 9R.

[0168] The two signals returned to the first hybrid 11A are not output to the antenna terminal 7A (ideally), and no insertion loss occurs in the first hybrid 11A. This is because the two signals become inversely phased when traveling toward the port 19A and cancel each other out.

[0169] As described above, a signal input to the antenna terminal 7A is reflected by the transmission filter system 12 and output to the reception filter 9R. In the present disclosure, even in this manner, it is shown that the reception filter 9R is connected to the antenna terminal 7A via the first mixer 11A.

[0170] The terminal resistor 61 has a predetermined resistance value, for example, and connects the second mixer 11B and the reference potential section. This reduces reflection of a signal flowing from the port 19A and / or 19B to the port 19C, for example. Although not particularly shown, the filter device 1 may have a matching circuit for impedance matching at an appropriate position.

[0171] Although not particularly shown, the following examples are given as other examples of the overall circuit configuration of the filter device 1. The specific configuration and effects of any of the following examples are described in Patent Document 1, and therefore only the main points are described here.

[0172] For example, in Figure 6 In the example, the structures of the sending side and the receiving side can be opposite. Figure 6 The two terminals represented as the receiving terminal 7R and the transmitting terminal 7T in FIG. 7 are used as the transmitting terminal 7T and the receiving terminal 7R. Figure 6 The filter indicated as the receiving filter 9R in FIG. 1 is used as the transmitting filter 9T. Figure 6 The two filters indicated as two transmit filters 9T in FIG. 1 serve as two receive filters 9R.

[0173] In this case, when a signal (for example, a received signal) is input from an antenna to the antenna terminal 7A, the signals whose phases are mutually shifted by 90° by the first mixer 11A are distributed to the two receiving filters 9R. The distributed signals pass through the two receiving filters 9R, and are converted into in-phase signals by the second mixer 11B and output to the receiving terminal 7R.

[0174] In addition, for example, it is also possible to combine Figure 6 Specifically, a new terminal resistor is connected to the port 19B of the first mixer 11A. In addition, two second mixers 11B are provided. Figure 6 Similarly to the example of FIG. 1 , ports 19C and 19D of the second mixer 11B on one side connect ports 19C and 19D of the first mixer 11A to the transmission terminal 7T and the terminal resistor 61 via two transmission filters 9T. Similarly to the example not shown above, ports 19C and 19D of the second mixer 11B on the other side connect ports 19C and 19D of the first mixer 11A to the reception terminal 7R and the terminal resistor 61 via two reception filters 9R.

[0175] In the example shown in the figure, the first filter 9 receives an unbalanced signal as input and outputs an unbalanced signal. The unbalanced signal may be, for example, a signal whose signal level changes relative to a reference potential. However, the first filter 9 may also be a filter that receives a balanced signal as input and / or outputs a balanced signal. The balanced signal may be, for example, two signals whose phases are opposite to each other.

[0176] (8.2. Distribution of multilayer substrates and chips to filter devices)

[0177] exist Figure 6 Below, as indicated by the reference numerals of the multilayer substrate 3 and the chip 5 , it is also shown that the constituent elements of the filter device 1 are arranged in one of the multilayer substrate 3 and the chip 5 .

[0178] The reference numerals of the multilayer substrate 3 are shown in a plurality of positions, but it can be understood from the description so far that the number of the multilayer substrate 3 is one. Figure 6 The description is different. Figure 1 The filter device 1 shown may only constitute Figure 6 That is, unlike the description here, the number of multilayer substrates 3 may be more than two.

[0179] In addition, as can be understood from the description so far, the number of chips 5 is arbitrary. For example, only one chip 5 may be provided corresponding to the first filter 9, or one chip 5 may be provided for each first filter 9, one chip 5 may be provided corresponding to the transmission filter system 12 and the reception filter system 14 (two chips 5 in total), or one first filter 9 may be dispersed to two or more chips 5.

[0180] The chip 5 includes, for example, at least a portion of the first filter 9. Therefore, the reference numerals of the chip 5 are given to the range (not including the first filter 9) Figure 6 The rightmost chip 5 in the figure does not mean a chip that does not include the first filter 9, but refers to any one of the chips 5 that include the first filter 9. Figure 6 In the expression of , the first filter 9 is simply not included. However, unlike the description here, a chip 5 that does not include the first filter 9 may also exist.

[0181] In such Figure 6 In the example shown in the figure, in the case where the filter device 1 has two or more mixers 11, the technical feature of setting a part of the mixer 11 on the chip 5 can also be applied to any mixer 11. In the example shown in the figure, the technical feature of setting a part of the mixer 11 on the chip 5 is applied to the first mixer 11A and the second mixer 11B (in other viewpoints, all the mixers 11 included in the filter device 1).

[0182] according to Figure 6 It is understood that the four ports 19 of each mixer 11 can be directly connected to the external terminal 7 (not via the first filter 9 or other mixers 11), or can be connected to the first filter 9 with different functions. A part or all of the parallel elements 17 (such as capacitors) set in the chip 5 can be connected to any of the above-mentioned various ports. In other viewpoints, the technical feature of setting a part or all of the parallel elements 17 in the chip 5 can be applied to any number of the four ports 19. In the example shown in the figure, the above-mentioned features are applicable to all ports 19.

[0183] In addition, for example, Figure 5 As shown, the parallel element 17 connected to the port 19 directly connected to the first filter 9 (for example, the ports 19B to 19C of the first mixer 11A) can be connected to the terminal 49 for connecting the first filter 9 to the multilayer substrate 3 (the port 19 in other viewpoints). The parallel element 17 connected to the port 19 directly connected to the external terminal 7 (for example, the port 19A of the first mixer 11A) can be connected to the terminal 49 provided for the parallel element 17. In more detail, for example, although not particularly shown, in addition to the first filter 9, the chip 5 can also have: a terminal 49 connected to the port 19, a terminal 49 connected to the external terminal 7, and a wiring connecting the two. In addition, the parallel element 17 can connect the above wiring and the GND terminal 49G.

[0184] Unlike the example shown in the figure, the parallel element 17 connected to the port 19 directly connected to the external terminal 7 can be provided outside the filter device 1. For example, the parallel element 17 can be provided on a circuit board (not shown) on which the filter device 1 is mounted, and the external terminal 7 and the reference potential portion of the circuit board (not shown) can be connected. In addition, it is not impossible to provide any of the parallel elements 17 connected to the port 19 directly connected to the first filter 9 outside the filter device 1.

[0185] The four parallel elements 17 (capacitors C1 to C4) constituting one mixer 11 may be provided on the same chip 5 or on different chips 5. For example, in a method in which one chip 5 is provided for each first filter 9, the capacitor C2 of the first mixer 11A may be provided on the chip 5 having the reception filter 9R, the capacitor C4 of the first mixer 11A may be provided on the chip 5 having the transmission filter 9TA, and the capacitor C3 of the first mixer 11A may be provided on the chip 5 having the transmission filter 9TB.

[0186] In the example shown in the figure, the terminal resistor 61 is provided in the chip 5. However, the terminal resistor 61 may also be provided in the multilayer substrate 3. As long as the reference potential is assumed to be given, the reference potential portion to which the parallel element 17 is connected may also be various conductors of the multilayer substrate 3, various conductors of the chip 5, or various conductors of a circuit board (not shown) on which the filter device 1 is mounted. In addition, unless otherwise specified or unless there is a contradiction, the term "reference potential portion" may refer to all of the above-mentioned various conductors or may refer to various conductors.

[0187] (9. Communication device including filter equipment)

[0188] Figure 7 1 is a block diagram showing the main parts of a communication device 151 as an application example of the filter device 1. The communication device 151 includes a module 171 and a housing 173 for storing the module 171. The module 171 performs wireless communication using radio waves and includes the filter device 1. Here, the filter device 1 schematically shows only the transmission filter system 12 and the reception filter system 14.

[0189] In module 171, a transmission information signal TIS including information to be transmitted is modulated and up-converted (converted into a high-frequency signal having a carrier frequency) by RF-IC (Radio Frequency Integrated Circuit) 153 (an example of an integrated circuit element), thereby forming a transmission signal TS. The transmission signal TS is removed from unnecessary components outside the transmission passband by a bandpass filter 155, amplified by an amplifier 157, and input to the filter device 1 (transmission terminal 7T). Then, the filter device 1 (transmission filter system 12) removes unnecessary components outside the transmission passband from the input transmission signal TS, and outputs the removed transmission signal TS from the antenna terminal 7A to the antenna 159. The antenna 159 converts the input electrical signal (transmission signal TS) into a wireless signal (radio wave) and transmits it.

[0190] In addition, in the module 171, the wireless signal (radio wave) received by the antenna 159 is converted into an electrical signal (received signal RS) by the antenna 159 and input to the filter device 1 (antenna terminal 7A). The filter device 1 (receive filter system 14) removes unnecessary components outside the passband for reception from the input received signal RS and outputs it from the receiving terminal 7R to the amplifier 161. The output received signal RS is amplified by the amplifier 161, and unnecessary components outside the passband for reception are removed by the bandpass filter 163. Then, the received signal RS is down-converted and demodulated by the RF-IC 153 to form a received information signal RIS.

[0191] In addition, the transmitted information signal TIS and the received information signal RIS can be low-frequency signals (baseband signals) containing appropriate information, such as analog sound signals or digitized sound signals. The passband of the wireless signal can be appropriately set. The modulation method can be any one of phase modulation, amplitude modulation, frequency modulation, or a combination of any two or more of them. The circuit method illustrates a direct conversion method, but it can also be set to other appropriate methods, such as a double superheterodyne method. In addition, Figure 7 The diagram schematically shows only the main parts, and a low-pass filter, an isolator, etc. may be added at appropriate positions, and the positions of the amplifiers, etc. may also be changed.

[0192] In the module 171, the components from the RF-IC 153 to the antenna 159 are installed or built into the same circuit board, for example. Thus, the filter device 1 is combined with other components and modularized. In addition, the filter device 1 may be included in the communication device 151 without being modularized. In addition, the components exemplified as components of the module 171 may be located outside the module or may not be housed in the housing 173. For example, the antenna 159 may be exposed outside the housing 173.

[0193] (10. Summary of implementation methods)

[0194] As described above, the filter device 1 includes: the multilayer substrate 3, the chip 5 mounted on the multilayer substrate 3, the first filter 9 at least a part of which is included in the chip 5, and the first hybrid coupler (hybrid 11) connected to the first filter 9. A part of the hybrid 11 (for example, the loop 13) is included in the multilayer substrate 3, and another part (for example, one or more parallel elements 17) is included in the chip 5.

[0195] In this case, for example, as described at the beginning of the description of the embodiment, the operating frequency can be adjusted by the chip 5 to form a mixer 11, and the mixer 11 has an operating frequency corresponding to the passband of the first filter 9 possessed by the chip 5. As a result, for mutually different passbands (mutually different chips 5), the multilayer substrate 3 is made common, and productivity can be improved. In addition, for example, although it also depends on the structure of the multilayer substrate 3, by using the piezoelectric body 31b of the chip 5 having a higher dielectric constant than the multilayer substrate 3 to form the capacitor C, the filter device 1 can be miniaturized.

[0196] The first hybrid coupler (hybrid 11) may include four series elements 15 connected in series to electrically form a loop 13, four ports 19 electrically located between the four series elements 15, and four parallel elements 17 connecting the four ports 19 and a reference potential portion (for example, a GND terminal 49G). The first parallel element (any parallel element 17) of the four parallel elements 17 may include an on-chip element included in the chip 5 (in the embodiment, the entire first parallel element).

[0197] In this case, for example, as described later, it is easy to place a part of the mixer 11 on the chip 5. In addition, the four series elements 15 electrically constitute the loop 13, and on the other hand, since the four parallel elements 17 are electrically branched from the loop 13, respectively, when a part of the mixer 11 is structurally separated, the method of separating the parallel elements 17 is easier to be simple in structure than the method of separating the series elements 15.

[0198] The on-chip element included in the first parallel element (any parallel element 17 ) among the four parallel elements 17 may include a first capacitor (in the embodiment, the capacitor C (any one of C1 to C4 ) as the entire first parallel element).

[0199] In this case, for example, it is possible to use Figure 3 The hybrid 11 is composed of four inductors L and four capacitors C as exemplified in the examples of FIG. 1 and FIG. 2 . In addition, for example, the piezoelectric body 31b of the chip 5 having a higher dielectric constant than the multilayer substrate 3 can be used for the capacitor C as described above.

[0200] The first filter 9 may include an elastic wave filter (in the embodiment, the first filter 9 as a whole is an elastic wave filter). The chip 5 may include a piezoelectric body 31b and an excitation electrode (IDT electrode 33). The IDT electrode 33 may be located on the piezoelectric body 31b to form an elastic wave filter. The first capacitor (capacitor C provided in the chip 5) may be located on the piezoelectric body 31b.

[0201] In this case, for example, as described above, the piezoelectric body 31b of the chip 5 having a higher dielectric constant than the multilayer substrate 3 can be used for the capacitor C. Since the piezoelectric body 31b already exists due to the elastic wave filter, the possibility of increasing the size of the filter device 1 due to the use of the piezoelectric body for the capacitor C can be reduced.

[0202] In the embodiment in which the first filter 9 has an elastic wave filter, the first port (for example, Figure 6Any one of the ports 19B to 19D of the first hybrid 11A) and the elastic wave filter may be connected without intervening other filters or other hybrid couplers.

[0203] In this case, for example, the first port to which the chip component is connected is a port that is to be connected to the terminal 49 (input terminal 49I or output terminal 49O) of the chip 5 having the elastic wave filter. Therefore, if the chip component is connected to the terminal 49 connected to the first port, it is connected to the first port. That is, the first port is connected to the external terminal 7 (for example, Figure 6 Unlike the case of the port 19A of the first hybrid 11A, there is no need to provide a dedicated terminal 49 (a new terminal 49 different from the terminal 49 for the elastic wave filter) for connecting the first port and the on-chip element.

[0204] The first filter 9 (elastic wave filter) may have a plurality of series resonators 29S and a plurality of parallel resonators 29P. The plurality of series resonators 29S may be connected in series with each other. The plurality of parallel resonators 29P may be connected in parallel with each other between the series arm 51 including the plurality of series resonators 29S and the reference potential portion (GND terminal 49G). The first port (any port 19) of the mixer 11 connected with the first capacitor (capacitor C located in the chip 5) may be connected to one end of the series arm 51. The plurality of parallel resonators 29P may include a first parallel resonator (parallel resonator 29P), wherein the first parallel resonator is connected on a side closer to the first port than the series resonator 29S electrically located closest to the first port. The first parallel resonator may be connected by at least a portion of the first capacitor (e.g. Figure 5 The capacitor C2b) is shared.

[0205] In this case, for example, by making the parallel resonator 29P shared by the capacitor C, the filter device 1 can be miniaturized.

[0206] In addition to the capacitor shared by the parallel resonator 29P, the first capacitor (eg Figure 5 The capacitor C2) may also have a second capacitor (eg Figure 5 The second capacitor is included in the chip 5 and is not shared by the parallel resonator 29P of the elastic wave filter.

[0207] In this case, for example, as described above, by using the parallel resonator 29P in common with a part of the capacitor C (capacitor C2b), it is possible to achieve miniaturization, while the capacitance of the capacitor C can be easily adjusted by the capacitor C2a.

[0208] The first port (eg, Figure 6The port 19A of the first mixer 11A) and the external terminal 7 of the filter device 1 (for example, Figure 6 The antenna terminal 7A) can be connected without passing through the first filter 9 and other filters.

[0209] In other words, a part of the parallel element 17 directly connected to the external terminal can be provided in the chip 5. In this case, compared with a method in which the parallel element 17 is provided outside (for example, a circuit board (not shown) on which the filter device 1 is mounted), since the mixer 11 is completed in the filter device 1, it is easy to handle.

[0210] The four parallel elements 17 may be four capacitors C1 to C4 having the same capacitance as one another.

[0211] In this case, for example, it is possible to use Figure 3 The mixer 11 shown in the example has four inductors L1 to L4 and four capacitors C1 to C4. In addition, since the capacitances of the capacitors C1 to C4 need only be adjusted uniformly, the operating frequency of the mixer 11 can be easily adjusted.

[0212] like Figure 6As illustrated, the filter device 1 may have a first 90° hybrid coupler (first mixer 11A), a second 90° hybrid coupler (second mixer 11B), a first filter system (transmit filter system 12), and a second filter system (receive filter system 14). The first 90° hybrid coupler may also be connected to a common terminal (antenna terminal 7A). The second 90° hybrid coupler may also be connected to the first terminal (transmit terminal 7T). The first filter system may be connected to the common terminal via the first 90° hybrid coupler and to the first terminal via the second 90° hybrid coupler, and may also allow signals of the first passband (transmit frequency band) to pass. The second filter system may be connected to the common terminal and to the second terminal (receive terminal 7R) via the first 90° hybrid coupler, and may allow signals of a second passband (receive frequency band) different from the first passband to pass. The transmit filter system 12 may have a second filter and a third filter (transmit filters 9TA and 9TB) that respectively allow signals of the first passband to pass. The second filter and the third filter can be connected to the first 90° hybrid coupler and the second 90° hybrid coupler in the following connection relationship: when a signal is input to one of the common terminal and the first terminal, signals with phases shifted by 90° are distributed to the second filter and the third filter, and the distributed signals are converted into in-phase signals and output to the other of the common terminal and the first terminal. The first 90° hybrid coupler or the second 90° hybrid coupler can be a first hybrid coupler (a part of which is set in the mixer 11 of the chip 5). The second filter, the third filter or the second filter system can have a first filter 9 (a filter provided in the chip 5 having a part of the mixer 11). That is, at least one of the second filter, the third filter and the second filter system can be provided at least in part in the chip 5 having a part of the mixer 11.

[0213] In the above configuration, for example, as described above, nonlinear distortion can be reduced in the process of distributing and synthesizing signals.

[0214] In addition, in a viewpoint different from the above viewpoint, the multilayer substrate 3 may have a first surface (upper surface), a pad 25, and a first circuit (e.g., loop 13). The pad 25 may be located on the upper surface of the multilayer substrate 3 and may be capable of mounting the chip 5. The first circuit may constitute a first hybrid coupler (hybrid 11). In addition, the first circuit may have: four inductors L connected in series to each other and electrically constituting a loop 13, and four ports 19 electrically located between the four inductors L, respectively. A first port (e.g., Figure 3The first port 19B in the external terminal 7 can be connected to the pad 25. In a state where the chip 5 is not mounted on the pad 25, the first port and the reference potential portion (for example, the terminal to which the reference potential is assigned among the external terminals 7, and the pad 25 to which the reference potential is assigned to the chip 5) may not be connected. In other words, when the chip 5 is mounted, the first port can be connected to the reference potential portion via the parallel element 17 of the chip 5.

[0215] Such a multilayer substrate 3 can be used for a filter device 1 that configures a hybrid 11 by mounting the above-mentioned chip 5 on the multilayer substrate 3. In addition, the multilayer substrate 3 may be distributed in a state where the chip 5 is not mounted.

[0216] Furthermore, further, in another viewpoint, the communication device 151 may include: the filter device 1, the antenna 159 connected to the filter device 1, and an integrated circuit element (RF-IC 153) connected to the antenna 159 via the filter device 1.

[0217] As described above, for example, since the filter device 1 can improve productivity, the productivity of the communication apparatus 151 including the filter device 1 can also be improved.

[0218] In addition, in the above embodiment, the mixer 11, the first mixer 11A, and the second mixer 11B are each an example of a first hybrid coupler. The first filter 9, the transmission filters 9TA and 9TB, and the reception filter 9R are each an example of a first filter, and are also examples of elastic wave filters. The capacitors C1 to C4 are each an example of a first parallel element, an example of an on-chip element, and an example of a first capacitor. The GND terminal 49G is an example of a reference potential portion. The IDT electrode 33 is an example of an excitation electrode. The ports 19A to 19D are each an example of a first port. Figure 3 The capacitor C2b is an example of a second capacitor that is not shared by the parallel resonator. The antenna terminal 7A is an example of a common terminal. The transmission terminal 7T is an example of a first terminal. The first mixer 11A is an example of a first 90° hybrid coupler. The second mixer 11B is an example of a second 90° hybrid coupler. The transmission filter system 12 is an example of a first filter system. The reception filter system 14 is an example of a second filter system. The transmission filters 9TA and 9TB are examples of a second filter and a third filter. The loop 13 is an example of a first circuit. The RF-IC 153 is an example of an integrated circuit element.

[0219] The technology of the present disclosure is not limited to the above-mentioned embodiments, and can be implemented in various forms.

[0220] In the description of the embodiments, for convenience, the following are mainly cited: the operating frequency of the hybrid coupler can be adjusted by setting a part of the chip in the hybrid coupler, and the effect of making the multilayer substrate common to various chips (the effect of improving productivity). However, the technology disclosed in the present invention can also be implemented in a manner that does not achieve such an effect. Even in this case, for example, the effect of being able to use the high dielectric constant piezoelectric body of the chip as the capacitor of the hybrid coupler can be achieved.

[0221] The filter device is not limited to a duplexer. For example, the filter device may have two receiving paths with mutually different passbands as a first filter system and a second filter system, or may have two transmitting paths with mutually different passbands as a first filter system and a second filter system. In addition to the first filter system and the second filter system, the filter device may also have a filter system. For example, the filter device may be a triplexer with three filter systems, or may be a quadruplexer with four filter systems. In addition, the filter device may also have only one first filter (i.e., filter).

[0222] The hybrid coupler is not limited to a 90° hybrid coupler, and may be a 180° hybrid coupler. For example, Patent Document 2 describes a filter device that combines a 180° hybrid coupler and a filter.

[0223] Explanation of symbols

[0224] 1: filter device; 3: multi-layer substrate; 5: chip; 9: first filter; 11: hybrid (first hybrid coupler).

Claims

1. Filter equipment, having: Multi-layer substrates; A chip mounted on the multi-layer substrate; A first filter, at least a portion of which is included in the chip; and A first hybrid coupler is connected to the first filter, and a portion of the first hybrid coupler is included in the multi-layer substrate and another portion of the first hybrid coupler is included in the chip.

2. The filter device according to claim 1, wherein the first hybrid coupler has: Four series elements are connected in series with each other and electrically form a loop; Four ports are electrically located between the four series elements respectively; Four parallel elements connecting the four ports and the reference potential portion; A first parallel element of the four parallel elements has an on-chip element included in the chip. The filter device according to claim 2 , wherein the on-chip element has a first capacitor.

4. The filter device according to claim 3, The first filter comprises an elastic wave filter; The chip has: Piezoelectric body; The excitation electrode of the elastic wave filter is located on the piezoelectric body; The first capacitor is located on the piezoelectric body.

5. The filter device according to any one of claims 2 to 4, The first filter comprises an elastic wave filter; Of the four ports, the first port to which the first parallel element is connected and the elastic wave filter are connected without interposing other filters and other hybrid couplers.

6. The filter device according to claim 3 or 4, The first filter comprises an elastic wave filter; The first port of the four ports connected to the first parallel element and the elastic wave filter are connected without passing through other filters and other hybrid couplers; The elastic wave filter has: A plurality of series resonators are connected in series with each other; A plurality of parallel resonators connected in parallel with each other between a series arm including the plurality of series resonators and the reference potential portion; The first port is connected to one end of the series arm; The plurality of parallel resonators include a first parallel resonator connected on a side closer to the first port than a series resonator electrically located most on the first port side; The first parallel resonator is shared by at least a portion of the first capacitor. 7 . The filter device according to claim 6 , wherein the first capacitor has a second capacitor, the second capacitor is included in the chip and is not shared by the parallel resonator of the elastic wave filter. 8 . The filter device according to claim 2 , wherein a first port to which the first parallel element is connected among the four ports is connected to an external terminal of the filter device without interposing the first filter and other filters. 9 . The filter device according to claim 2 , wherein the four parallel elements are four capacitors having the same capacitance as one another.

10. The filter device according to any one of claims 1 to 9, comprising: a first 90° hybrid coupler connected to the common terminal; a second 90° hybrid coupler connected to the first terminal; a first filter system connected to the common terminal via the first 90° hybrid coupler and connected to the first terminal via the second 90° hybrid coupler, and passing signals of a first passband; a second filter system connected to the common terminal and to a second terminal via the first 90° hybrid coupler and passing signals of a second passband different from the first passband; The first filter system comprises a second filter and a third filter which respectively pass signals of the first passband; The second filter and the third filter are connected to the first 90° hybrid coupler and the second 90° hybrid coupler in the following connection relationship: when a signal is input to one of the common terminal and the first terminal, signals with phases shifted by 90° from each other are distributed to the second filter and the third filter, and the distributed signals are converted into signals of the same phase and output to the other of the common terminal and the first terminal; The first 90° hybrid coupler or the second 90° hybrid coupler is the first hybrid coupler; The second filter, the third filter or the second filter system has the first filter.

11. Multilayer substrate, having: a first surface; A pad, located on the first surface and capable of mounting a chip; A first circuit constituting a first hybrid coupler; The first circuit has: Four inductors are connected in series and electrically form a loop; Four ports are electrically located between the four inductors respectively; A first port of the four ports is connected to the pad; When the chip is not mounted on the pad, the first port and the reference potential portion are not connected.

12. A communication device having: The filter device according to any one of claims 1 to 10; an antenna connected to the filter device; An integrated circuit element is connected to the antenna via the filter device.

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