On-board capacitor test circuit, electronic equipment and on-board capacitor test method

Abstract

The invention provides an on-board capacitor test circuit, electronic equipment and an on-board capacitor test method, which are applied to the technical field of capacitance measurement. Wherein the charging and discharging circuit is connected with the to-be-tested capacitor through the charging path and the discharging path, so that the charging and discharging circuit charges the to-be-tested capacitor through the charging path, and the to-be-tested capacitor discharges the charging and discharging circuit through the discharging path; the control circuit is connected with the control end of the charging path and the control end of the discharging path, and the control circuit is connected with the capacitor to be detected and is used for controlling the on-off of the charging path and the discharging path according to the corresponding relation between the capacitor voltage corresponding to the capacitor to be detected and the charging threshold voltage; the capacitance corresponding to the to-be-measured capacitor is determined according to the charging time of the charging and discharging circuit for charging the to-be-measured capacitor through the charging path and the charging threshold voltage. Therefore, the capacitance of the capacitor to be measured is calculated through on-off of the two paths, the overall operation is simple, and the product cost is reduced.

Description

Technical Field

[0001] The invention relates to the technical field of capacitance measurement, and in particular to an on-board capacitance testing circuit, electronic equipment and an on-board capacitance testing method. Background Art

[0002] In electronic devices, the central processing unit (CPU) is the most important component, and the stability of the CPU power supply directly affects the performance and reliability of the CPU. In order to meet the requirements of high CPU load current and fast transient response, in addition to using a multi-phase voltage regulator module (VRM) for power supply, more capacitors must be placed at the VRM output end and the CPU power supply end.

[0003] At present, the design of specifications and quantity of multiple capacitors requires reference to the manufacturer's recommendations on the one hand, and verification through test results on the other. The current common capacitance measurement method is for non-board, single capacitors, and cannot be used for on-board, multiple parallel, and large-capacity scenarios. In order to evaluate the total capacitance of the capacitor on the board, the method usually used is theoretical calculation, that is, according to the DC bias characteristics of the capacitor, the capacity under the actual working voltage is calculated, and then the total capacitance is obtained by cumulative calculation. However, the capacitor itself has a capacity deviation, the initial capacity is different from the standard value, and the capacitor has a DC bias characteristic, and the DC bias characteristics of capacitors from different manufacturers are also different, which leads to the final capacitance calculated based on the working voltage being low.

[0004] It can be seen that how to provide a circuit suitable for measuring capacitance on a board is a problem that those skilled in the art need to solve. Summary of the invention

[0005] The purpose of the embodiments of the present invention is to provide an on-board capacitance testing circuit, an electronic device and an on-board capacitance testing method, which can solve the problem in the prior art that the capacitance calculated by using capacitance theory is lower than the actual capacitance, and solve the problem in the prior art that the capacitance of the on-board capacitance cannot be calculated.

[0006] To solve the above technical problems, on the one hand, an embodiment of the present invention provides an on-board capacitance test circuit, including: a charge and discharge circuit, a charge path, a discharge path and a control circuit;

[0007] The charge-discharge circuit is connected to the capacitor to be measured through a charge path and a discharge path, so that the charge-discharge circuit charges the capacitor to be measured through the charge path, and the capacitor to be measured discharges to the charge-discharge circuit through the discharge path;

[0008] The control circuit is connected to the control end of the charging path and the control end of the discharging path, and the control circuit is connected to the capacitor to be measured, and is used to control the on and off of the charging path and the discharging path according to the corresponding relationship between the capacitor voltage corresponding to the capacitor to be measured and the charging threshold voltage, so as to determine the capacitance corresponding to the capacitor to be measured according to the charging time and the charging threshold voltage of the charging and discharging circuit charging the capacitor to be measured through the charging path.

[0009] In some embodiments, the charge and discharge circuit includes: a constant current source circuit and a discharge circuit;

[0010] Wherein, a first end of the constant current source circuit is connected to the first power source, and a second end of the constant current source circuit is connected to a first end of the charging path and a first end of the discharging path;

[0011] The first end of the discharge circuit is connected to the second end of the discharge path, and the second end of the discharge circuit is connected to the first end of the capacitor to be measured.

[0012] In some embodiments, the constant current source circuit includes: a current mirror, a voltage stabilization circuit, and a detection circuit;

[0013] The first end of the current mirror is connected to the first power supply as the first end of the constant current source circuit, the second end of the current mirror is connected to the first end of the voltage stabilizing circuit, and the third end of the current mirror is connected to the first end of the charging path and the first end of the discharging path as the second end of the constant current source circuit;

[0014] The second terminal of the voltage stabilizing circuit is grounded;

[0015] The first end of the detection circuit is connected to the third end of the discharge path, and the second end of the detection circuit is connected to the first end of the capacitor to be measured and is grounded.

[0016] In some embodiments, the current mirror includes: a first resistor, a second resistor, a first transistor, a second transistor, and a diode;

[0017] A first end of the first resistor is connected to a first end of the second resistor, and the first end of the first resistor and the second resistor and the first end of the second resistor are connected to the first power supply as a current mirror;

[0018] The second end of the first resistor is connected to the emitter of the first transistor;

[0019] The second end of the second resistor is connected to the emitter of the second triode;

[0020] The collector of the first triode is connected to the base of the first triode and the base of the second triode, and the second end of the current mirror is connected to the first end of the voltage stabilizing circuit.

[0021] The collector of the second transistor is connected to the anode of the diode;

[0022] The cathode of the diode is connected to the first end of the charging path and the first end of the discharging path as the third end of the current mirror.

[0023] In some embodiments, the voltage stabilizing circuit includes: a voltage stabilizing diode, a third resistor, and a fourth resistor;

[0024] The first end of the voltage regulator tube is connected to the first end of the third resistor, and together they serve as the first end of the voltage regulator circuit connected to the second end of the current mirror;

[0025] The second end of the voltage regulator is connected to the second end of the third resistor and the first end of the fourth resistor;

[0026] The third end of the voltage regulator tube is connected to the second end of the fourth resistor, and they are grounded together as the second end of the voltage regulator circuit.

[0027] In some embodiments, the detection circuit is a fifth resistor;

[0028] The first end of the fifth resistor is connected to the third end of the discharge path as the first end of the detection circuit;

[0029] The second end of the fifth resistor is connected to the first end of the capacitor to be measured as the second end of the detection circuit and is grounded.

[0030] In some embodiments, the discharge circuit is a sixth resistor;

[0031] The first end of the sixth resistor is connected to the second end of the discharge path as the first end of the discharge circuit;

[0032] The second end of the sixth resistor serves as the second end of the discharge circuit and is connected to the first end of the capacitor to be measured.

[0033] In some embodiments, the charging path includes a first MOS transistor;

[0034] The drain of the first MOS tube is connected to the third end of the current mirror as the first end of the charging path;

[0035] The source of the first MOS tube is connected to the second end of the capacitor to be measured as the second end of the charging path;

[0036] The gate of the first MOS tube is connected to the first output end of the control circuit as the control end of the charging path.

[0037] In some embodiments, the discharge path includes: a second MOS transistor and a third MOS transistor;

[0038] The drain of the second MOS tube is connected to the third end of the current mirror as the first end of the discharge path;

[0039] The source of the second MOS tube is connected to the first end of the detection circuit as the third end of the discharge path;

[0040] The gate of the second MOS tube is connected to the second output end of the control circuit as the first control end of the discharge path;

[0041] The drain of the third MOS tube is connected to the second end of the capacitor to be measured as the fourth end of the discharge path;

[0042] The source of the third MOS tube is connected to the first end of the discharge circuit as the second end of the discharge path;

[0043] The gate of the third MOS tube is connected to the second output end of the control circuit as the second control end of the discharge path.

[0044] In some embodiments, the control circuit includes a hysteresis comparator circuit and a level shifting circuit;

[0045] A first terminal of the hysteresis comparator circuit is connected to the second power supply, and a second terminal of the hysteresis comparator circuit is connected to a first terminal of the level conversion circuit;

[0046] The first output end of the level conversion circuit is connected to the gate of the first MOS tube as the first output end of the control circuit;

[0047] The second output end of the level conversion circuit is connected to the gate of the second MOS tube and the gate of the third MOS tube as the second output end of the control circuit.

[0048] In some embodiments, the hysteresis comparator circuit includes: an operational amplifier, a seventh resistor, an eighth resistor, a ninth resistor, and a tenth resistor;

[0049] The inverting input terminal of the operational amplifier is connected to the second terminal of the capacitor to be measured;

[0050] The non-inverting input terminal of the operational amplifier is connected to the first terminal of the seventh resistor, the first terminal of the eighth resistor and the first terminal of the ninth resistor;

[0051] The first pin end of the operational amplifier is connected to a third power supply;

[0052] The second pin of the operational amplifier is grounded;

[0053] The output end of the operational amplifier is connected to the second end of the ninth resistor and the first end of the tenth resistor, and together serve as the second end of the hysteresis comparator circuit connected to the first end of the level conversion circuit;

[0054] The second end of the seventh resistor is connected to the second power supply as the first end of the hysteresis comparator circuit;

[0055] The second end of the eighth resistor is grounded;

[0056] A second end of the tenth resistor is connected to the third power source.

[0057] In some embodiments, the level conversion circuit includes: a first-stage inverter circuit and a second-stage inverter circuit;

[0058] The first end of the first-stage inverter circuit is connected to the second end of the hysteresis comparator circuit as the first end of the level conversion circuit;

[0059] The second end of the first-stage inverter circuit is connected to the first end of the second-stage inverter circuit, and is connected to the gate of the second MOS tube and the gate of the third MOS tube as the second output end of the level conversion circuit;

[0060] The second end of the second-stage inverter circuit is connected to the gate of the first MOS tube as the first output end of the level conversion circuit.

[0061] In some embodiments, the first-stage inverter circuit includes: an eleventh resistor and a fourth MOS tube;

[0062] The gate of the fourth MOS tube is connected to the second end of the hysteresis comparator circuit as the first end of the first-stage inverter circuit;

[0063] The source of the fourth MOS tube is grounded;

[0064] The drain of the fourth MOS tube is connected to the first end of the eleventh resistor, and together they serve as the second end of the first-stage inverter circuit and are connected to the first end of the second-stage inverter circuit;

[0065] The second end of the eleventh resistor is connected to the first power source.

[0066] In some embodiments, the second-stage inverter circuit includes: a twelfth resistor and a fifth MOS tube;

[0067] The gate of the fifth MOS tube is connected to the second end of the first-stage inverter circuit as the first end of the second-stage inverter circuit;

[0068] The source of the fifth MOS tube is grounded;

[0069] The drain of the fifth MOS tube is connected to the first end of the twelfth resistor, and together they serve as the second end of the second-stage inverter circuit;

[0070] The second end of the twelfth resistor is connected to the first power source.

[0071] On the other hand, the present invention further provides an electronic device, comprising the above-mentioned on-board capacitance testing circuit.

[0072] On the other hand, the present invention further provides an on-board capacitance testing method, which is applied to the above-mentioned on-board capacitance testing circuit, and the method comprises:

[0073] Obtaining the capacitor voltage corresponding to the capacitor to be tested;

[0074] Based on the corresponding relationship between the capacitor voltage and the charging threshold voltage, the charging path and the discharging path are controlled to be turned on and off, so that the charging and discharging circuit charges the capacitor to be tested through the charging path, and the capacitor to be tested discharges to the charging and discharging circuit through the discharging path;

[0075] Obtaining the charging time of the charge-discharge circuit to charge the capacitor to be tested through the charging path;

[0076] The capacitance corresponding to the capacitor to be tested is determined based on the charging time and the charging threshold voltage.

[0077] In some embodiments, controlling the on / off of the charging path and the discharging path based on the corresponding relationship between the capacitor voltage and the charging threshold voltage includes:

[0078] When the voltage of the capacitor to be tested is less than the lower threshold voltage, the charging path is controlled to be turned on and the discharging path is turned off, so that the charging and discharging circuit charges the capacitor to be tested through the charging path;

[0079] When the capacitor voltage is greater than the upper threshold voltage, the discharge path is controlled to be turned on and the charging path is turned off, so that the capacitor to be tested discharges to the charge and discharge circuit through the discharge path, wherein the lower threshold voltage and the upper threshold voltage are used together as the charging threshold voltage.

[0080] As can be seen from the above technical scheme, the present invention provides a circuit for testing capacitance on a board, including: a charging and discharging circuit, a charging path, a discharging path and a control circuit; the charging and discharging circuit is connected to the capacitor to be tested through the charging path and the discharging path, so that the charging and discharging circuit charges the capacitor to be tested through the charging path, and the capacitor to be tested discharges to the charging and discharging circuit through the discharging path; the control circuit is connected to the control end of the charging path and the control end of the discharging path, and the control circuit is connected to the capacitor to be tested, and is used to control the on-off of the charging path and the discharging path according to the corresponding relationship between the capacitor voltage corresponding to the capacitor to be tested and the charging threshold voltage, so as to determine the capacitance corresponding to the capacitor to be tested according to the charging time and the charging threshold voltage of the charging and discharging circuit charging the capacitor to be tested through the charging path. It can be seen from this that the present invention controls the on-off of the charging path and the discharging path by the control circuit to realize the charging of the capacitor to be tested and the discharging of the capacitor to be tested, and in the process of charging the capacitor to be tested, the more accurate capacitance is determined by the charging time and the charging threshold voltage. Its overall operation is simple, and the cost of the product can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0081] In order to more clearly illustrate the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0082] Figure 1 A structural diagram of an on-board capacitance test circuit provided by an embodiment of the present invention;

[0083] Figure 2 A voltage waveform diagram provided by an embodiment of the present invention;

[0084] Figure 3 A circuit diagram of a charge and discharge circuit, a charge path, and a discharge path provided in an embodiment of the present invention;

[0085] Figure 4 A circuit diagram of a control circuit provided by an embodiment of the present invention;

[0086] Figure 5 A circuit diagram of a power supply circuit provided in an embodiment of the present invention;

[0087] Figure 6 The present invention provides a flow chart of a method for testing on-board capacitance. DETAILED DESCRIPTION

[0088] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the protection scope of the present invention.

[0089] The terms "including" and "having" in the specification of the present invention and the above-mentioned drawings, as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device including a series of steps or units is not limited to the listed steps or units, but may include steps or units that are not listed.

[0090] In order to enable those skilled in the art to better understand the solution of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0091] Next, an on-board capacitance testing circuit provided by an embodiment of the present invention is described in detail. Figure 1 A structural diagram of a circuit for testing on-board capacitance provided by an embodiment of the present invention, such as Figure 1 As shown, the on-board capacitance test circuit includes: a charge and discharge circuit 1, a charge path 2, a discharge path 3 and a control circuit 4. In addition, Figure 1 The structure shown also includes: a data processing device 5 (eg, an oscilloscope), a power supply circuit 6, and a capacitor to be measured 7. Figure 1The connection relationship of the on-board capacitor test circuit shown is: the charge and discharge circuit 1 is connected to the capacitor 7 to be tested through the charging path 2 and the discharging path 3; the data processing device 5 is connected to the capacitor 7 to be tested; and the power supply circuit 6 is connected to the control circuit 4.

[0092] In the embodiment, the charge and discharge circuit 1 is connected to the capacitor 7 to be measured through the charge path 2 and the discharge path 3, and when the control circuit 4 controls the charge path 2 to be turned on and the discharge path 3 to be turned off, the capacitor 7 to be measured is charged; when the control circuit 4 controls the charge path 2 to be turned off and the discharge path 3 to be turned on, the capacitor 7 to be measured performs a discharge operation to the charge and discharge circuit 1. The control circuit 4 controls the charge path 2 to be turned on, and the discharge path 3 is turned off and switched to the charge path 2 to be turned off. The switching point of the discharge path 3 being turned on is when the capacitor voltage of the capacitor 7 to be measured reaches the upper threshold voltage; and the control circuit 4 controls the charge path 2 to be turned off, and the discharge path 3 is turned on and switched to the charge path 2 to be turned on. The switching point of the discharge path 3 being turned off is when the capacitor voltage of the capacitor to be measured reaches the lower threshold voltage. Since the data processing device 5 is connected to the capacitor 7 to be measured, the waveform of the voltage corresponding to the capacitor 7 to be measured can be displayed in real time. At this time, the voltage waveform displayed on the data processing device 5 is as shown in FIG. Figure 2 As shown by Figure 2 It can be seen that the voltage waveform of the capacitor 7 to be tested when it is charged is a standard function image, and the voltage waveform of the capacitor 7 to be tested when it is discharged is a curve. Therefore, it is convenient to calculate the capacitance of the capacitor 7 to be tested according to the waveform of the capacitor 7 to be tested when it is charged. Figure 2 V H is the upper threshold voltage, V L is the lower threshold voltage, T RISE is the charging time, t is the time, and V is the voltage. Its upper threshold voltage V H and the lower threshold voltage V L is the charging threshold voltage.

[0093] That is to say, the steps of determining the corresponding capacitance according to the on-board capacitance test circuit provided by the present invention are as follows:

[0094] Step 1: The control circuit 4 controls the charging path 2 to be turned on and the discharging path 3 to be turned off, so that the charging and discharging circuit 1 charges the capacitor 7 to be tested. At this time, the constant charging current is I S .

[0095] Step 2: The control circuit 4 detects the voltage of the capacitor 7 to be tested. When the voltage of the capacitor 7 to be tested reaches the upper threshold voltage V H , the charging path 2 is controlled to be turned off and the discharging path 3 is turned on. At this time, the capacitor 7 to be tested discharges to the charging and discharging circuit 1.

[0096] Step 3: The control circuit 4 detects the voltage of the capacitor 7 to be tested again. When the voltage of the capacitor 7 to be tested reaches the lower threshold voltage V L , the control circuit 4 controls the charging path 2 to be turned on and the discharging path 3 to be turned off. At this time, the capacitor 7 to be tested stops charging, and the charging and discharging circuit 1 charges the capacitor 7 to be tested again.

[0097] Step 4: The data processing device 5 records the charging time T according to the voltage waveform of the capacitor 7 to be tested RISE .

[0098] Step 5: Determine the upper threshold voltage V according to the calculation formula H and charging time T RISE The corresponding capacitance C.

[0099] The calculation formula is:

[0100] ;

[0101] Among them, V H is the upper threshold voltage, V L is the lower threshold voltage, T RISE is the charging time, I S is a constant charging current.

[0102] It should also be noted that the formula provided in this embodiment of the present invention is only one possible implementation method, but is not limited to only this implementation method and can be set according to the needs of the user.

[0103] As can be seen from the above technical scheme, the present invention provides a circuit for testing capacitance on a board, including: a charging and discharging circuit, a charging path, a discharging path and a control circuit; the charging and discharging circuit is connected to the capacitor to be tested through the charging path and the discharging path, so that the charging and discharging circuit charges the capacitor to be tested through the charging path, and the capacitor to be tested discharges to the charging and discharging circuit through the discharging path; the control circuit is connected to the control end of the charging path and the control end of the discharging path, and the control circuit is connected to the capacitor to be tested, and is used to control the on-off of the charging path and the discharging path according to the corresponding relationship between the capacitor voltage corresponding to the capacitor to be tested and the charging threshold voltage, so as to determine the capacitance corresponding to the capacitor to be tested according to the charging time and the charging threshold voltage of the charging and discharging circuit charging the capacitor to be tested through the charging path. It can be seen from this that the present invention controls the on-off of the charging path and the discharging path by the control circuit to realize the charging of the capacitor to be tested and the discharging of the capacitor to be tested, and in the process of charging the capacitor to be tested, the more accurate capacitance is determined by the charging time and the charging threshold voltage. Its overall operation is simple, and the cost of the product can be reduced.

[0104] In some embodiments, the charge and discharge circuit 1 includes: a constant current source circuit and a discharge circuit. The connection relationship of the circuit is: the first end of the constant current source circuit is connected to the first power supply 12V, the second end of the constant current source circuit is connected to the first end of the charging path 2 and the first end of the discharge path 3; the first end of the discharge circuit is connected to the second end of the discharge path 3, and the second end of the discharge circuit is connected to the first end of the capacitor 7 to be measured.

[0105] In a specific embodiment, the function of the charge and discharge circuit 1 is to provide a constant charging current during charging and a discharge current during discharging. The whole circuit is composed of a constant current source circuit and a discharge circuit. The constant current source circuit provides a constant charging current I during charging. S , and the discharge circuit provides the discharge current during discharge.

[0106] Furthermore, the constant current source circuit includes: a current mirror, a voltage stabilizing circuit and a detection circuit; the connection relationship of the constant current source is: the first end of the current mirror is connected to the first power supply as the first end of the constant current source circuit, the second end of the current mirror is connected to the first end of the voltage stabilizing circuit, and the third end of the current mirror is connected to the first end of the charging path and the first end of the discharge path 3 as the second end of the constant current source circuit; the second end of the voltage stabilizing circuit is grounded; the first end of the detection circuit is connected to the third end of the discharge path 3, and the second end of the detection circuit is connected to the first end of the capacitor 7 to be measured and grounded.

[0107] In a specific embodiment, the constant current source circuit in the charge and discharge circuit 1 is composed of a current mirror, a voltage stabilizing circuit and a detection circuit, wherein the current mirror is used to provide a charging current I S and mirror current I c ; The voltage regulator circuit is used to adjust the charging current I S ; The detection circuit is also used to adjust the charging current I S .

[0108] Further, such as Figure 3 As shown, the current mirror in the charge and discharge circuit 1 includes: a first resistor R1, a second resistor R2, a first transistor Q1, a second transistor Q2 and a diode D1; the connection relationship of the current mirror is: the first end of the first resistor R1 is connected to the first end of the second resistor R2, and they are connected to the first power supply 12V as the first end of the current mirror; the second end of the first resistor R1 is connected to the emitter of the first transistor Q1; the second end of the second resistor R2 is connected to the emitter of the second transistor Q2; the collector of the first transistor Q1 is connected to the base of the first transistor Q1 and the base of the second transistor Q2, and they are connected to the first end of the voltage stabilizing circuit as the second end of the current mirror; the collector of the second transistor Q2 is connected to the positive electrode of the diode D1; the cathode of the diode D1 is connected to the first end of the charging path 2 and the first end of the discharging path 3 as the third end of the current mirror.

[0109] In a specific embodiment, the current mirror in the charge and discharge circuit 1 is composed of a first resistor R1, a second resistor R2, a first transistor Q1, a second transistor Q2 and a diode D1. The current mirror in the current structure makes the charging current I S Mirrored to the mirror current I C , the expression of its mirror formula is as follows:

[0110] ;

[0111] Among them, I S is the charging current; I C is the mirror current; V BE-Q1 is the starting voltage of the first transistor; U A for Figure 3 The voltage at point A in the middle; R1 is the resistance value of the first resistor, and 12V is the first power supply.

[0112] Among them, the starting voltage V of the first transistor Q1 BE-Q1 can be 0.6V; the first resistor R1 can be selected as a resistor with a resistance of 140ohm; the second resistor R2 can also be selected as a resistor with a resistance of 140ohm; the charging current I S It can be 0.01A.

[0113] like Figure 3 As shown, the voltage stabilizing circuit in the charge and discharge circuit 1 includes: a voltage stabilizing tube U1, a third resistor R3 and a fourth resistor R4; the connection relationship of the circuit is: the first end of the voltage stabilizing tube U1 is connected to the first end of the third resistor R3, and they are connected to the second end of the current mirror as the first end of the voltage stabilizing circuit; the second end of the voltage stabilizing tube U1 is connected to the second end of the third resistor R3 and the first end of the fourth resistor R4; the third end of the voltage stabilizing tube U1 is connected to the second end of the fourth resistor R4, and they are grounded as the second end of the voltage stabilizing circuit.

[0114] In a specific embodiment, the voltage stabilizing circuit in the charge and discharge circuit 1 is composed of a voltage stabilizing tube U1, a third resistor R3 and a fourth resistor R4, wherein the third resistor R3 is a variable resistor (sliding resistor), and the fourth resistor R4 is a fixed value resistor. The voltage at point A can be changed by adjusting the resistance value of the third resistor R3, thereby adjusting the charging current I S , the expression of the adjustment formula is as follows:

[0115] ;

[0116] Among them, U A for Figure 3 The voltage at point A; V REF is the reference voltage; R3 is the resistance value of the third resistor R3; R4 is the resistance value of the fourth resistor R4.

[0117] Among them, the model of the voltage regulator UI can be selected as TL431; and the reference voltage V REF can be 2.5V; the third resistor R3 can be a variable resistor with a resistance range not exceeding 30kohm; the fourth resistor R4 can be a fixed resistor with a resistance of 10kohm; the voltage U at point A A It can be 10V.

[0118] like Figure 3 As shown, the detection circuit in the charge and discharge circuit 1 is the fifth resistor R5; its connection relationship is: the first end of the fifth resistor R5 is connected to the third end of the discharge path 3 as the first end of the detection circuit; the second end of the fifth resistor R5 is connected to the first end of the capacitor to be measured 7 as the second end of the detection circuit, and is grounded.

[0119] In a specific embodiment, the fifth resistor R5 is used as a detection circuit in the charge and discharge circuit 1. By measuring the voltage on the fifth resistor R5, the charging current I S The actual value of the charging current I is adjusted to adjust the third resistor R3 S Equal to the set value, its charging current I S The actual value of is calculated as follows:

[0120] ;

[0121] Among them, U R5 is the voltage on the fifth resistor R5; R5 is the resistance value of the fifth resistor R5.

[0122] The fifth resistor R5 may be a resistor with a resistance of 100 ohm.

[0123] like Figure 3 As shown, the discharge circuit in the charge and discharge circuit 1 is the sixth resistor R6; its connection relationship is: the first end of the sixth resistor R6 is connected to the second end of the discharge path 3 as the first end of the discharge circuit; the second end of the sixth resistor R6 is connected to the first end of the capacitor to be measured 7 as the second end of the discharge circuit.

[0124] In a specific embodiment, the sixth resistor R6 serves as a discharge circuit in the charge-discharge circuit 1 , and the charge in the capacitor 7 to be measured is discharged through the sixth resistor R6 .

[0125] The sixth resistor R6 may be a resistor with a resistance of 100 ohms. The smaller the resistance, the faster the discharge speed.

[0126] It should be noted that the embodiment provided by the present invention is only one possible implementation method, but is not limited to only this implementation method and can be set according to the needs of the user.

[0127] At the same time, it should be noted that the formula provided in the embodiment of the present invention is related to the above-mentioned specific circuit structure. When the circuit structure changes, the formula will also change, so it can be adjusted according to the needs of the user.

[0128] The present invention provides a specific structure of a charging and discharging circuit, under which the specific value of the charging current can be adjusted to ensure the stability of current transmission and improve the discharge efficiency.

[0129] In some embodiments, Figure 3 As shown, the charging path 2 includes a first MOS transistor M1; the connection relationship of the circuit is: the drain of the first MOS transistor M1 is connected to the third end of the current mirror (the negative electrode of the diode D1) as the first end of the charging path 2; the source of the first MOS transistor M1 is connected to the second end of the capacitor 7 to be measured as the second end of the charging path 2; the gate of the first MOS transistor M1 is connected to the first output end of the control circuit 4 as the control end of the charging path 2.

[0130] In a specific embodiment, when the first MOS tube M1 is turned on, the constant current source circuit in the charge and discharge circuit 1 charges the capacitor to be measured.

[0131] like Figure 3 As shown, the discharge path 3 includes: a second MOS tube M2 and a third MOS tube M3; the connection relationship of the circuit is: the drain of the second MOS tube M2 is connected to the third end of the current mirror (the negative electrode of the diode D1) as the first end of the discharge path 3; the source of the second MOS tube M2 is connected to the first end of the detection circuit (the first end of the fifth resistor R5) as the third end of the discharge path 3; the gate of the second MOS tube M2 is connected to the second output end of the control circuit 4 as the first control end of the discharge path 3; the drain of the third MOS tube M3 is connected to the second end of the capacitor 7 to be measured as the fourth end of the discharge path 3; the source of the third MOS tube M3 is connected to the first end of the discharge circuit (the first end of the sixth resistor) as the second end of the discharge path 3; the gate of the third MOS tube M3 is connected to the second output end of the control circuit 4 as the second control end of the discharge path 3.

[0132] In a specific embodiment, the second MOS tube M2 and the third MOS tube M3 are in the same state. When the first MOS tube M1 is in the off state, the second MOS tube M2 and the third MOS tube M3 are turned on so that the capacitor 7 to be tested discharges to the charge and discharge circuit 1 .

[0133] The control logic of the first MOS tube M1, the second MOS tube M2 and the third MOS tube M3 is shown in Table 1:

[0134] Table 1

[0135]

[0136] in, Figure 3 The capacitor 7 to be tested is shown to be composed of a plurality of capacitors (C1-CN) connected in parallel, and Vtest is the voltage of the capacitor 7 to be tested.

[0137] It should be noted that the first MOS tube M1 , the second MOS tube M2 and the third MOS tube M3 may all be N-type MOS tubes.

[0138] It should also be noted that the embodiment provided by the present invention is only one possible implementation method, but is not limited to only this implementation method and can be set according to the needs of the user.

[0139] The present invention provides a specific structure of a charging path and a discharging path. Under this structure, a control circuit can realize the on and off of the charging path and the discharging path by controlling the gates of a first MOS tube, a second MOS tube and a third MOS tube, thereby realizing charging and discharging of the circuit.

[0140] In some embodiments, the control circuit 4 includes a hysteresis comparator circuit and a level conversion circuit; the connection relationship of the control circuit is: the first end of the hysteresis comparator circuit is connected to the second power supply 1V, and the second end of the hysteresis comparator circuit is connected to the first end of the level conversion circuit; the first output end of the level conversion circuit is connected to the gate of the first MOS tube M1 as the first output end of the control circuit 4; the second output end of the level conversion circuit is connected to the gate of the second MOS tube M2 and the gate M3 of the third MOS tube as the second output end of the control circuit.

[0141] Further, if Figure 4 As shown, the hysteresis comparator circuit in the control circuit 4 includes: an operational amplifier U2, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9 and a tenth resistor R10; the connection relationship of the circuit is: the inverting input terminal of the operational amplifier U2 is connected to the second end of the capacitor 7 to be tested, for obtaining the voltage Vtest; the non-inverting input terminal of the operational amplifier U2 is connected to the first end of the seventh resistor R7, the first end of the eighth resistor R8 and the first end of the ninth resistor R9; the first pin end of the operational amplifier U2 is connected to the third power supply 5V; the second pin end of the operational amplifier U2 is grounded; the output end of the operational amplifier U2 is connected to the second end of the ninth resistor R9 and the first end of the tenth resistor R10, and together as the second end of the hysteresis comparator circuit is connected to the first end of the level conversion circuit; the second end of the seventh resistor R7 is connected to the second power supply 1V as the first end of the hysteresis comparator circuit; the second end of the eighth resistor R8 is grounded; the second end of the tenth resistor R10 is connected to the third power supply 5V.

[0142] In a specific embodiment, in the hysteresis comparator circuit, the seventh resistor R7, the eighth resistor R8, the ninth resistor R9 and the tenth resistor R10 form a positive feedback circuit, and the voltage Vtest of the capacitor 7 to be tested is connected to the inverting input terminal of the operational amplifier.

[0143] Initially, when the voltage Vtest of the capacitor 7 to be tested is less than 1V of the third power supply 1V connected to the operational amplifier U2 through the seventh resistor R7, the voltage U C is high level, the capacitor 7 to be tested is charged, and then the voltage Vtest of the capacitor 7 to be tested increases. At this time, the voltage U at point B B is the upper threshold voltage V H , its specific calculation expression is as follows:

[0144] ;

[0145] When the voltage Vtest of the capacitor 7 to be tested increases to the upper threshold voltage V H When the voltage U at the output terminal C of the operational amplifier U2 is C is low level, the capacitor 7 to be tested begins to discharge, and then the voltage Vtest of the capacitor 7 to be tested decreases. At this time, the voltage U B is the lower threshold voltage V L , its specific calculation expression is as follows:

[0146] ;

[0147] When the voltage Vtest of the capacitor 7 decreases to V L When the voltage U at the output terminal C of the operational amplifier U2 is C becomes high level, and the capacitor 7 to be tested starts to charge again.

[0148] In some embodiments, the level conversion circuit in the control circuit 4 includes: a first-stage inverter circuit and a second-stage inverter circuit; the connection relationship of the circuits is as follows: the first end of the first-stage inverter circuit is connected to the second end of the hysteresis comparator circuit (the output end of the operational amplifier U2, the second end of the ninth resistor R9, and the first end of the tenth resistor R10) as the first end of the level conversion circuit; the second end of the first-stage inverter circuit is connected to the first end of the second-stage inverter circuit, and together serve as the second output end of the level conversion circuit and are connected to the gate of the second MOS tube M2 and the gate of the third MOS tube M3; the second end of the second-stage inverter circuit is connected to the gate of the first MOS tube M1 as the first output end of the level conversion circuit.

[0149] In a specific embodiment, the first end of the first-stage inverter circuit is connected to the second end of the hysteresis comparator circuit, and the output logic is opposite to the output of the hysteresis comparator circuit; the first end of the second-stage inverter circuit is connected to the second end of the first-stage inverter circuit, and the output logic is the same as the output of the hysteresis comparator circuit.

[0150] Further, such as Figure 4 As shown, the first-stage inverter circuit in the control circuit 4 includes: an eleventh resistor R11 and a fourth MOS transistor M4; the connection relationship of the first-stage inverter circuit is as follows: the gate of the fourth MOS transistor M4 is connected to the second end of the hysteresis comparator circuit (the output end of the operational amplifier U2, the second end of the ninth resistor R9 and the first end of the tenth resistor R10) as the first end of the first-stage inverter circuit; the source of the fourth MOS transistor M4 is grounded; the drain of the fourth MOS transistor M4 is connected to the first end of the eleventh resistor R11, and together serve as the second end of the first-stage inverter circuit and are connected to the first end of the second-stage inverter circuit; the second end of the eleventh resistor R11 is connected to the first power supply 12V.

[0151] Further, such as Figure 4 As shown, the second-stage inverter circuit in the control circuit 4 includes: a twelfth resistor R12 and a fifth MOS tube M5; the connection relationship of the second-stage inverter circuit is as follows: the gate of the fifth MOS tube M5 is connected to the second end of the first-stage inverter circuit as the first end of the second-stage inverter circuit; the source of the fifth MOS tube M5 is grounded; the drain of the fifth MOS tube M5 is connected to the first end of the twelfth resistor R12, and together they serve as the second end of the second-stage inverter circuit; the second end of the twelfth resistor R12 is connected to the first power supply 12V.

[0152] In a specific embodiment, the first-stage inverter circuit in the control circuit 4 is composed of an eleventh resistor R11 and a fourth MOS tube M4, and the signal output by the drain of the fourth MOS tube M4 is used to control the second MOS tube M2 and the third MOS tube M3. The second-stage inverter circuit of the control circuit 4 is composed of a twelfth resistor R12 and a fifth MOS tube M5, and the signal output by the drain of the fifth MOS tube M5 is used to control the first MOS tube M1.

[0153] Among them, when the output end of the operational amplifier U2 outputs a high-level signal, the signal output by the drain of the fourth MOS tube M4 is a low-level signal, and the second MOS tube M2 and the third MOS tube M3 are turned off; at this time, the signal output by the drain of the fifth MOS tube M5 is a high-level signal, and the first MOS tube M1 is turned on. At this time, the charge-discharge circuit 1 charges the capacitor 7 to be measured.

[0154] When the output end of the operational amplifier U2 outputs a low level signal, the signal output by the drain of the fourth MOS tube M4 is a high level signal, and the second MOS tube M2 and the third MOS tube M3 are turned on; at this time, the signal output by the drain of the fifth MOS tube M5 is a low level signal, and the first MOS tube M1 is turned off, and the capacitor 7 to be measured is discharged.

[0155] besides, Figure 1 The specific structure of the power supply circuit 6 is as follows Figure 5 As shown, the power supply circuit 6 is mainly composed of two voltage regulator modules (VRM), one of which is VRM_5V and the other is VRM_1V. The current power supply circuit 6 has three power output terminals, the first of which is 12V (which can be understood as the first power supply mentioned above), the second is 1V (which can be understood as the second power supply mentioned above), and the third is 5V (which can be understood as the third power supply mentioned above).

[0156] In addition, since the specific structure of the control circuit 4 provided by the present invention is relatively complex, and the main function of the control circuit 4 is to control the on and off of the charging path 2 and the discharging path 3 through the fourth MOS tube M4 and the fifth MOS tube M5, the signals output by the fourth MOS tube M4 and the fifth MOS tube M5 are particularly important.

[0157] Therefore, the on-board capacitance test circuit provided by the present invention may also include a signal detection circuit, wherein the first end of the signal detection circuit is connected to the output end of the operational amplifier U2, and the second end of the signal detection circuit is connected to the drain of the fourth MOS tube M4 and the drain of the fifth MOS tube M5. Since the signal output by the drain of the fourth MOS tube M4 is logically opposite to the signal output by the output end of the operational amplifier U2, and the signal output by the drain of the fifth MOS tube M5 is logically the same as the signal output by the output end of the operational amplifier U2, it is possible to determine whether the output signal of the operational amplifier U2, the output signal of the fourth MOS tube M4, and the output signal of the fifth MOS tube M5 obtained conform to the operational logic according to the signal detection circuit. When the three output signals conform to the operational logic, it indicates that the control circuit 4 is fault-free; when the three output signals do not conform to the operational logic, it indicates that the control circuit 4 is faulty and needs to be repaired.

[0158] It should be noted that the embodiment provided by the present invention is only one possible implementation method, but is not limited to only this implementation method and can be set according to the needs of the user.

[0159] From the above circuit structure, it can be seen that the overall design of the on-board capacitance test circuit provided by the present invention includes the following steps:

[0160] Step 1: Select a constant charging current I according to the application scenario of the capacitor 7 to be tested S ; Upper threshold voltage V H ;Lower threshold voltage V L The target value of the parameter. For example: S =0.01A; V H =1.8V; V L =0.1V.

[0161] Step 2: Design of the charge and discharge circuit 1: The charge and discharge circuit 1 is composed of a constant current source circuit and a discharge circuit, and the constant current source circuit is composed of a current mirror, a voltage stabilizing circuit and a detection circuit.

[0162] The current mirror includes: a first resistor R1, a second resistor R2, a first transistor Q1, a second transistor Q2 and a diode D1. The connection relationship of the current mirror is: the first end of the first resistor R1 is connected to the first end of the second resistor R2, and together as the first end of the current mirror connected to the first power supply 12V; the second end of the first resistor R1 is connected to the emitter of the first transistor Q1; the second end of the second resistor R2 is connected to the emitter of the second transistor Q2; the collector of the first transistor Q1 is connected to the base of the first transistor Q1 and the base of the second transistor Q2, and together as the second end of the current mirror connected to the first end of the voltage stabilizing circuit; the collector of the second transistor Q2 is connected to the positive electrode of the diode D1; the negative electrode of the diode D1 is connected to the first end of the charging path 2 and the first end of the discharging path 3 as the third end of the current mirror. The first transistor Q1 and the second transistor Q2 can use PNP transistors with the same signal, and the starting voltage V of the first transistor Q1 is BE-Q1 can be 0.6V; the first resistor R1 can be selected as a resistor with a resistance of 140ohm; the second resistor R2 can be selected as a resistor with a resistance of 140ohm; the charging current I S It can be 0.01A.

[0163] The voltage stabilizing circuit includes: a voltage stabilizing tube U1, a third resistor R3 and a fourth resistor R4. The connection relationship of the current voltage stabilizing circuit is: the first end of the voltage stabilizing tube U1 is connected to the first end of the third resistor R3, and they are connected to the second end of the current mirror as the first end of the voltage stabilizing circuit; the second end of the voltage stabilizing tube U1 is connected to the second end of the third resistor R3 and the first end of the fourth resistor R4; the third end of the voltage stabilizing tube U1 is connected to the second end of the fourth resistor R4, and they are grounded as the second end of the voltage stabilizing circuit. The model of the voltage stabilizing tube UI can be TL431; the third resistor R3 can be a variable resistor with a resistance range not exceeding 30Kkohm; the fourth resistor R4 can be a fixed resistor with a resistance of 10kohm.

[0164] In the detection circuit, a single fifth resistor R5 constitutes the detection circuit. The overall connection relationship is as follows: the first end of the fifth resistor R5 is connected to the third end of the discharge path 3 as the first end of the detection circuit; the second end of the fifth resistor R5 is connected to the first end of the capacitor 7 to be measured as the second end of the detection circuit and is grounded. The fifth resistor R5 can be a resistor with a resistance value of 100 ohms.

[0165] In the discharge circuit, a separate sixth resistor R6 is used as the discharge circuit. The overall connection relationship is: the first end of the sixth resistor R6 is connected to the second end of the discharge path 3 as the first end of the discharge circuit; the second end of the sixth resistor R6 is connected to the first end of the capacitor 7 to be measured as the second end of the discharge circuit. The sixth resistor R6 can be selected to have a resistance of 100 ohms.

[0166] Step 3: Design of charging path 2 and discharging path 3.

[0167] In the charging path 2, the first MOS transistor M1 constitutes the charging path 2. The overall connection relationship is: the drain of the first MOS transistor M1 is connected to the third end of the current mirror (the negative electrode of the diode D1) as the first end of the charging path 2; the source of the first MOS transistor M1 is connected to the second end of the capacitor 7 to be measured as the second end of the charging path 2; the gate of the first MOS transistor M1 is connected to the first output end of the control circuit 4 as the control end of the charging path 2.

[0168] The discharge path 3 includes a second MOS tube M2 and a third MOS tube M3. The connection relationship of the discharge path 3 is as follows: the drain of the second MOS tube M2 is connected to the third end of the current mirror (the negative electrode of the diode D1) as the first end of the discharge path 3; the source of the second MOS tube M2 is connected to the first end of the detection circuit (the first end of the fifth resistor R5) as the third end of the discharge path 3; the gate of the second MOS tube M2 is connected to the second output end of the control circuit 4 as the first control end of the discharge path 3; the drain of the third MOS tube M3 is connected to the second end of the capacitor 7 to be measured as the fourth end of the discharge path 3; the source of the third MOS tube M3 is connected to the first end of the discharge circuit (the first end of the sixth resistor) as the second end of the discharge path 3; and the gate of the third MOS tube M3 is connected to the second output end of the control circuit 4 as the second control end of the discharge path 3.

[0169] The first MOS tube M1 , the second MOS tube M2 , and the third MOS tube M3 may all be N-type MOS tubes.

[0170] Step 4: Design of control circuit 4. Control circuit 4 is composed of a hysteresis comparator circuit and a level conversion circuit, and the level conversion circuit is composed of a first-stage inverter circuit and a second-stage inverter circuit.

[0171] The hysteresis comparator circuit includes: an operational amplifier U2, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9 and a tenth resistor R10; the connection relationship of the circuit is: the inverting input terminal of the operational amplifier U2 is connected to the second end of the capacitor 7 to be tested, for obtaining the voltage Vtest; the non-inverting input terminal of the operational amplifier U2 is connected to the first end of the seventh resistor R7, the first end of the eighth resistor R8 and the first end of the ninth resistor R9; the first pin terminal of the operational amplifier U2 is connected to the third power supply 5V; the second pin terminal of the operational amplifier U2 is grounded; the output terminal of the operational amplifier U2 is connected to the second end of the ninth resistor R9 and the first end of the tenth resistor R10, and together as the second end of the hysteresis comparator circuit is connected to the first end of the level conversion circuit; the second end of the seventh resistor R7 is connected to the second power supply 1V as the first end of the hysteresis comparator circuit; the second end of the eighth resistor R8 is grounded; the second end of the tenth resistor R10 is connected to the third power supply 5V. The operational amplifier U2 can be a conventional operational amplifier; the eighth resistor R8 and the ninth resistor R9 can be selected as resistors with a resistance value of 2kohm; and the seventh resistor R7 can be selected as a resistor with a resistance value of 9kohm.

[0172] The first-stage inverter circuit includes: an eleventh resistor R11 and a fourth MOS tube M4; the connection relationship of the first-stage inverter circuit is as follows: the gate of the fourth MOS tube M4 is connected to the second end of the hysteresis comparator circuit (the output end of the operational amplifier U2, the second end of the ninth resistor R9 and the first end of the tenth resistor R10) as the first end of the first-stage inverter circuit; the source of the fourth MOS tube M4 is grounded; the drain of the fourth MOS tube M4 is connected to the first end of the eleventh resistor R11, and together as the second end of the first-stage inverter circuit, is connected to the first end of the second-stage inverter circuit; the second end of the eleventh resistor R11 is connected to the first power supply 12V. The fourth MOS tube M4 can be selected from V GS Withstand voltage>5V, V DS For N-MOS tubes with a withstand voltage of >12V, the eleventh resistor R11 can be a 10kohm resistor.

[0173] The second-stage inverter circuit includes: a twelfth resistor R12 and a fifth MOS tube M5; the connection relationship of the second-stage inverter circuit is: the gate of the fifth MOS tube M5 is connected to the second end of the first-stage inverter circuit as the first end of the second-stage inverter circuit; the source of the fifth MOS tube M5 is grounded; the drain of the fifth MOS tube M5 is connected to the first end of the twelfth resistor R12, and together serves as the second end of the second-stage inverter circuit; the second end of the twelfth resistor R12 is connected to the first power supply 12V. The fifth MOS tube M5 can be selected from V GS Withstand voltage>5V, V DS For N-MOS tubes with a withstand voltage of >12V, the twelfth resistor R12 can be a 10kohm resistor.

[0174] Step 5: Design of power supply circuit 6.

[0175] The power supply circuit 6 includes two VRMs, which mainly output three voltages.

[0176] Through the above steps, a completed on-board capacitance test circuit can be constructed.

[0177] It can be seen from the above technical scheme that the present invention provides an on-board capacitor test circuit, including: a charge and discharge circuit, a charging path, a discharge path and a control circuit; the charge and discharge circuit is connected to the capacitor to be tested through the charging path and the discharge path, so that the charge and discharge circuit charges the capacitor to be tested through the charging path, and the capacitor to be tested discharges to the charge and discharge circuit through the discharge path; the control circuit is connected to the control end of the charging path and the control end of the discharge path, and the control circuit is connected to the capacitor to be tested, and is used to control the on and off of the charging path and the discharge path according to the corresponding relationship between the capacitor voltage corresponding to the capacitor to be tested and the charging threshold voltage, so as to determine the capacitance corresponding to the capacitor to be tested according to the charging time and the charging threshold voltage of the charge and discharge circuit charging the capacitor to be tested through the charging path. It can be seen that the present invention controls the on and off of the charging path and the discharge path through the control circuit to realize the charging of the capacitor to be tested and the discharging of the capacitor to be tested. In the process of charging the capacitor to be tested, a more accurate capacitance is determined by the charging time and the charging threshold voltage. Its overall operation is simple, and the cost of the product can be reduced. And when the on-board capacitor test circuit is specifically as follows Figure 3 and Figure 4 As shown, the on-board capacitance test circuit also has the advantages of strong adaptability and high flexibility.

[0178] On the other hand, the present invention further provides an electronic device, comprising the above-mentioned on-board capacitance testing circuit.

[0179] In a specific embodiment, the electronic device includes an on-board capacitor test circuit, and the on-board capacitor test circuit includes: a charge-discharge circuit, a charging path, a discharge path, and a control circuit. The working principle of the electronic device under its current structure is: the charge-discharge circuit is connected to the capacitor to be tested through the charging path and the discharge path, so that the charge-discharge circuit charges the capacitor to be tested through the charging path, and the capacitor to be tested discharges to the charge-discharge circuit through the discharge path; the control circuit is connected to the control end of the charging path and the control end of the discharge path, and the control circuit is connected to the capacitor to be tested, and is used to control the on-off of the charging path and the discharge path according to the corresponding relationship between the capacitor voltage corresponding to the capacitor to be tested and the charging threshold voltage, so as to determine the capacitance corresponding to the capacitor to be tested according to the charging time and the charging threshold voltage of the charge-discharge circuit charging the capacitor to be tested through the charging path. The operation of the electronic device to measure the capacitor to be tested under its current structure is simple, and the cost of the product is reduced.

[0180] On the other hand, the present invention also provides an on-board capacitance testing method, which is applied to the above-mentioned on-board capacitance testing circuit, such as Figure 6 As shown, the method comprises the following steps:

[0181] S10: Obtain the capacitor voltage corresponding to the capacitor to be measured.

[0182] S11: controlling the on / off of the charging path and the discharging path based on the corresponding relationship between the capacitor voltage and the charging threshold voltage, so that the charging and discharging circuit charges the capacitor to be tested through the charging path, and the capacitor to be tested discharges to the charging and discharging circuit through the discharging path.

[0183] S12: Obtain the charging time of the charge-discharge circuit charging the capacitor to be tested through the charging path.

[0184] S13: Determine the capacitance corresponding to the capacitor to be tested according to the charging time and the charging threshold voltage.

[0185] The specific implementation method of step S11 is: when the capacitor voltage is less than the lower threshold voltage, the charging path is controlled to be turned on and the discharging path is turned off, so that the charging and discharging circuit charges the capacitor to be tested through the charging path; when the capacitor voltage is greater than the upper threshold voltage, the discharging path is controlled to be turned on and the charging path is turned off, so that the capacitor to be tested discharges to the charging and discharging circuit through the discharging path, wherein the lower threshold voltage and the upper threshold voltage are jointly used as the charging threshold voltage.

[0186] Since the embodiment of an on-board capacitance testing method provided by the present invention is the same as the embodiment of the on-board capacitance testing circuit described above and has the same beneficial effects, the present invention will not be described in detail herein.

[0187] The above is a detailed introduction to an on-board capacitance test circuit, an electronic device and an on-board capacitance test method provided by the present invention. This article uses specific examples to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. It should be pointed out that for ordinary technicians in this technical field, without departing from the principle of the present invention, the present invention can also be improved and modified, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.

Claims

1. A circuit for testing capacitance on a board, characterized in that: include: Charging and discharging circuit, charging path, discharging path and control circuit; The charging and discharging circuit is connected to the capacitor to be measured through the charging path and the discharging path, so that the charging and discharging circuit charges the capacitor to be measured through the charging path, and the capacitor to be measured discharges to the charging and discharging circuit through the discharging path; The control circuit is connected to the control end of the charging path and the control end of the discharging path, and is also connected to the capacitor to be measured, and is used to control the on and off of the charging path and the discharging path according to the corresponding relationship between the capacitor voltage corresponding to the capacitor to be measured and the charging threshold voltage, so as to determine the capacitance corresponding to the capacitor to be measured according to the charging time of the charging and discharging circuit charging the capacitor to be measured through the charging path and the charging threshold voltage.

2. The on-board capacitance test circuit according to claim 1, characterized in that: The charging and discharging circuit comprises: a constant current source circuit and a discharging circuit; Wherein, a first end of the constant current source circuit is connected to a first power source, and a second end of the constant current source circuit is connected to a first end of the charging path and a first end of the discharging path; The first end of the discharge circuit is connected to the second end of the discharge path, and the second end of the discharge circuit is connected to the first end of the capacitor to be measured.

3. The on-board capacitance test circuit according to claim 2, characterized in that: The constant current source circuit comprises: a current mirror, a voltage stabilizing circuit and a detection circuit; The first end of the current mirror is connected to the first power supply as the first end of the constant current source circuit, the second end of the current mirror is connected to the first end of the voltage stabilizing circuit, and the third end of the current mirror is connected to the first end of the charging path and the first end of the discharging path as the second end of the constant current source circuit; The second terminal of the voltage stabilizing circuit is grounded; The first end of the detection circuit is connected to the third end of the discharge path, and the second end of the detection circuit is connected to the first end of the capacitor to be measured and is grounded.

4. The on-board capacitance test circuit according to claim 3, characterized in that: The current mirror comprises: a first resistor, a second resistor, a first triode, a second triode and a diode; The first end of the first resistor is connected to the first end of the second resistor, and the two are connected to the first power supply together as the first end of the current mirror; The second end of the first resistor is connected to the emitter of the first transistor; The second end of the second resistor is connected to the emitter of the second transistor; The collector of the first transistor is connected to the base of the first transistor and the base of the second transistor, and together serve as the second end of the current mirror connected to the first end of the voltage stabilizing circuit; The collector of the second triode is connected to the anode of the diode; The cathode of the diode is connected to the first end of the charging path and the first end of the discharging path as the third end of the current mirror.

5. The on-board capacitance test circuit according to claim 3, characterized in that: The voltage stabilizing circuit comprises: a voltage stabilizing tube, a third resistor and a fourth resistor; The first end of the voltage regulator tube is connected to the first end of the third resistor, and together they serve as the first end of the voltage regulator circuit and are connected to the second end of the current mirror; The second end of the voltage regulator tube is connected to the second end of the third resistor and the first end of the fourth resistor; The third end of the voltage regulator tube is connected to the second end of the fourth resistor, and they are grounded together as the second end of the voltage regulator circuit.

6. The on-board capacitance test circuit according to claim 3, characterized in that: The detection circuit is a fifth resistor; The first end of the fifth resistor is connected to the third end of the discharge path as the first end of the detection circuit; The second end of the fifth resistor is connected to the first end of the capacitor to be measured as the second end of the detection circuit and is grounded.

7. The on-board capacitance test circuit according to any one of claims 2 to 6, characterized in that: The discharge circuit is a sixth resistor; The first end of the sixth resistor is connected to the second end of the discharge path as the first end of the discharge circuit; The second end of the sixth resistor serves as the second end of the discharge circuit and is connected to the first end of the capacitor to be measured.

8. The on-board capacitance test circuit according to claim 3, characterized in that: The charging path includes a first MOS tube; The drain of the first MOS tube is connected to the third end of the current mirror as the first end of the charging path; The source of the first MOS tube is connected to the second end of the capacitor to be measured as the second end of the charging path; The gate of the first MOS tube is connected to the first output end of the control circuit as the control end of the charging path.

9. The on-board capacitance test circuit according to claim 8, characterized in that: The discharge path includes: a second MOS tube and a third MOS tube; The drain of the second MOS tube is connected to the third end of the current mirror as the first end of the discharge path; The source of the second MOS tube is connected to the first end of the detection circuit as the third end of the discharge path; The gate of the second MOS tube is connected to the second output end of the control circuit as the first control end of the discharge path; The drain of the third MOS tube is connected to the second end of the capacitor to be measured as the fourth end of the discharge path; The source of the third MOS tube is connected to the first end of the discharge circuit as the second end of the discharge path; The gate of the third MOS tube is connected to the second output end of the control circuit as the second control end of the discharge path.

10. The on-board capacitance test circuit according to claim 9, characterized in that: The control circuit includes a hysteresis comparator circuit and a level conversion circuit; A first end of the hysteresis comparator circuit is connected to a second power supply, and a second end of the hysteresis comparator circuit is connected to a first end of the level conversion circuit; The first output end of the level conversion circuit is connected to the gate of the first MOS transistor as the first output end of the control circuit; The second output end of the level conversion circuit is connected to the gate of the second MOS transistor and the gate of the third MOS transistor as the second output end of the control circuit.

11. The on-board capacitance test circuit according to claim 10, characterized in that: The hysteresis comparator circuit comprises: an operational amplifier, a seventh resistor, an eighth resistor, a ninth resistor and a tenth resistor; The inverting input terminal of the operational amplifier is connected to the second terminal of the capacitor to be measured; The non-inverting input terminal of the operational amplifier is connected to the first end of the seventh resistor, the first end of the eighth resistor and the first end of the ninth resistor; The first pin end of the operational amplifier is connected to a third power supply; The second pin end of the operational amplifier is grounded; The output end of the operational amplifier is connected to the second end of the ninth resistor and the first end of the tenth resistor, and together serves as the second end of the hysteresis comparator circuit connected to the first end of the level conversion circuit; The second end of the seventh resistor is connected to the second power supply as the first end of the hysteresis comparator circuit; The second end of the eighth resistor is grounded; The second end of the tenth resistor is connected to the third power supply.

12. The on-board capacitance test circuit according to claim 11, characterized in that: The level conversion circuit comprises: a first-stage inverter circuit and a second-stage inverter circuit; The first end of the first-stage inverter circuit is connected to the second end of the hysteresis comparator circuit as the first end of the level conversion circuit; The second end of the first-stage inverter circuit is connected to the first end of the second-stage inverter circuit, and together serves as the second output end of the level conversion circuit and is connected to the gate of the second MOS transistor and the gate of the third MOS transistor; The second end of the second-stage inverter circuit is connected to the gate of the first MOS transistor as the first output end of the level conversion circuit.

13. The on-board capacitance test circuit according to claim 12, characterized in that: The first-stage inverter circuit comprises: an eleventh resistor and a fourth MOS tube; The gate of the fourth MOS tube is connected to the second end of the hysteresis comparator circuit as the first end of the first-stage inverter circuit; The source of the fourth MOS tube is grounded; The drain of the fourth MOS tube is connected to the first end of the eleventh resistor, and together serve as the second end of the first-stage inverter circuit and are connected to the first end of the second-stage inverter circuit; The second end of the eleventh resistor is connected to the first power source.

14. The on-board capacitance test circuit according to claim 13, characterized in that: The second-stage inverter circuit comprises: a twelfth resistor and a fifth MOS tube; The gate of the fifth MOS tube is connected to the second end of the first-stage inverter circuit as the first end of the second-stage inverter circuit; The source of the fifth MOS tube is grounded; The drain of the fifth MOS tube is connected to the first end of the twelfth resistor, and together serve as the second end of the second-stage inverter circuit; The second end of the twelfth resistor is connected to the first power source.

15. An electronic device, characterized in that: The invention comprises the on-board capacitance testing circuit as described in any one of claims 1 to 14.

16. A method for testing on-board capacitance, characterized in that: Applied to the on-board capacitance test circuit of claim 1, the method comprises: Obtaining the capacitor voltage corresponding to the capacitor to be measured; Based on the corresponding relationship between the capacitor voltage and the charging threshold voltage, the charging path and the discharging path are controlled to be turned on and off, so that the charging and discharging circuit charges the capacitor to be tested through the charging path, and the capacitor to be tested discharges to the charging and discharging circuit through the discharging path; Acquire the charging time of the charge-discharge circuit charging the capacitor to be tested through the charging path; The capacitance corresponding to the capacitor to be tested is determined according to the charging time and the charging threshold voltage.

17. The on-board capacitance testing method according to claim 16, characterized in that: The controlling of the on and off of the charging path and the discharging path based on the corresponding relationship between the capacitor voltage and the charging threshold voltage includes: When the capacitor voltage is less than the lower threshold voltage, the charging path is controlled to be turned on and the discharging path is turned off, so that the charging and discharging circuit charges the capacitor to be tested through the charging path; When the capacitor voltage is greater than the upper threshold voltage, the discharge path is controlled to be turned on and the charging path is turned off, so that the capacitor to be tested discharges to the charge and discharge circuit through the discharge path, wherein the lower threshold voltage and the upper threshold voltage are used together as the charging threshold voltage.

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