Multi-format data objects in memory

Abstract

The invention relates to a multi-format data object in a memory. To implement a multi-format data object in a memory, a device may receive an allocation request for a data object containing a set of data elements. This allocation request contains respective details of a set of formats of the data object, such as details of a first format in the set of formats. The details may include memory address information and a mapping between a first data element of the data object in the first format and a second data element in a second format of the set of formats. The details may also include an identification of a conversion function configured to convert the first data element to the second data element. The device may provide access to the data object in the second format from the data object in the first format in the memory based on a mapped data structure or a converted data structure.

Description

Technical Field

[0001]

[0013] Embodiments described herein relate generally to computer memory, and more particularly, to multi-format data objects in memory. Background Art

[0002] Memory devices used in computers or other electronic devices can be classified as volatile and non-volatile memory. Volatile memory uses power to maintain its data (e.g., is periodically refreshed), and includes random access memory (RAM), dynamic random access memory (DRAM), or synchronous dynamic random access memory (SDRAM), etc. Non-volatile memory generally retains stored data in the absence of power, and includes flash memory, read-only memory (ROM), electrically erasable programmable ROM (EEPROM), static RAM (SRAM), erasable programmable ROM (EPROM), resistance variable memory, phase change memory, storage class memory, resistive random access memory (RRAM), and magnetoresistive random access memory (MRAM), etc. Persistent memory is an architectural attribute of a system, where data stored in the media is available after a system reset or power cycle. In an example, non-volatile memory media can be used to build a system with a persistent memory model.

[0003] The memory device may be coupled to a host (e.g., a host computing device) to store data, commands, or instructions for use by the host when the computer or electronic system is operating. For example, data, commands, or instructions may be transferred between the host and the memory device during operation of the computing system or other electronic system.

[0004] Various protocols or standards may be applied to facilitate communication between a host and one or more other devices such as memory buffers, accelerators, or other input / output devices. In an example, an out-of-order protocol such as Compute Express Link (CXL) may be used to provide high bandwidth and low latency connectivity. Summary of the invention

[0005] In one aspect, the present application provides a device for implementing multi-format data objects in a memory, the device comprising: an interface configured to communicate with an external entity; and a processing circuit system configured to: receive an allocation request for a data object at the interface, the data object comprising a set of data elements, the allocation request comprising corresponding details of a set of formats of the data object; allocate space for a first version of the data object in a first format in a memory managed by the device based on the details of the first format in the allocation request; store a mapping of the details from the first format in a mapping data structure corresponding to the data object; store an identification of a conversion function from the details of the first format in a conversion data structure corresponding to the data object; and provide access to a data object in a second format from the data object in the first format in the memory based on the mapping data structure or the conversion data structure.

[0006] In another aspect, the present application provides a method for multi-format data objects in a memory, the method comprising: receiving an allocation request for a data object at an interface of a memory device, the data object comprising a set of data elements, the allocation request comprising corresponding details of a set of formats of the data object; allocating space for a first version of the data object in a first format in a memory of the memory device based on the details of the first format in the allocation request by a circuit system of the memory device; storing a mapping of the details from the first format in a mapping data structure corresponding to the data object; storing an identification of a conversion function from the details of the first format in a conversion data structure corresponding to the data object; and providing access to a data object in a second format from the data object in the first format in the memory based on the mapping data structure or the conversion data structure.

[0007] In another aspect, the present application provides a machine-readable medium comprising instructions for implementing multi-format data objects in a memory, wherein the instructions, when executed by a processing circuit system of a device, cause the device to perform operations including: receiving an allocation request for a data object at an interface of a memory device, the data object comprising a set of data elements, the allocation request comprising corresponding details of a set of formats of the data object; allocating space in a memory of the memory device for a first version of the data object in a first format based on the details of the first format in the allocation request by the circuit system of the memory device; storing a mapping of the details from the first format in a mapping data structure corresponding to the data object; storing an identification of a conversion function from the details of the first format in a conversion data structure corresponding to the data object; and providing access to a data object in a second format from the data object in the first format in the memory based on the mapping data structure or the conversion data structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In the drawings, which are not necessarily drawn to scale, like reference numerals may describe similar components in different views. Like reference numerals with different letter suffixes may represent different instances of similar components. The drawings generally illustrate various embodiments discussed in this document by way of example and not limitation.

[0009] Figure 1 is a block diagram of an example of an environment including a system for multi-format data objects in memory according to an embodiment.

[0010] Figure 2 An example of a system in which multiple hosts can access multi-format data objects through a memory device according to an embodiment is shown.

[0011] Figure 3 An example of host and memory device interaction to write a multi-format object is shown according to an embodiment.

[0012] Figure 4 An example of host and memory device interaction for reading a multi-format object is shown according to an embodiment.

[0013] Figure 5 An example of a host connected to a CXL device is depicted according to an embodiment.

[0014] Figure 6 Example components of a memory device are depicted in accordance with an embodiment.

[0015] Figure 7 A flow chart illustrating an example of a method for hybrid cache coherence according to an embodiment is shown.

[0016] Figure 8 is a block diagram illustrating an example of a machine upon which one or more embodiments may be implemented. DETAILED DESCRIPTION

[0017] Compute Express Link (CXL) is an open standard interconnect configured for high-bandwidth, low-latency connectivity between host devices and other devices such as accelerators, memory buffers, or intelligent input-output (I / O) devices. CXL is designed to facilitate high-performance computing workloads by supporting heterogeneous processing and memory systems. CXL provides memory semantics and mechanisms for cache coherence on top of PCI Express (PCIe)-based I / O semantics to optimize performance.

[0018] System configurations that integrate several different devices via interconnects such as CXL can provide efficient workload processing at several connected entities. Typically, data can be kept in interconnect-attached memory and shared between processing elements, such as processors, graphics processors, accelerators, etc. However, there may be use cases where the same data is used in different formats at different times. For large, scalable shared memory subsystems, the available internal device memory bandwidth can significantly exceed the memory-to-processor (e.g., host) bandwidth. When the memory system has processing power, the internal device bandwidth of the memory system can be used to reduce the memory-to-processor bandwidth by maintaining multiple formats (e.g., versions, types, etc.) of the data. The generation of various formats can be on-demand (e.g., processed when read by the host) or pre-generated (e.g., generated and stored in memory for later reading by the host).

[0019] When maintaining data in multiple formats or storing a single format but receiving and responding to requests in a different format, it can be difficult to maintain consistency between formats. This problem can be solved by providing a mapping or conversion function to the memory system when an object is allocated in the memory system. Here, allocation reserves space in memory for an object, but the object has not yet been created.

[0020] When an object is allocated in a memory system, the requester specifies a mapping between the elements of the object. Consider a data object, which is a block of data allocated by a user program and composed of data elements. Each data element is a single data unit within the object, such as an integer, a database record, a node in a graph, or an element of a matrix. The mapping provides a correlation between a data element A in format Z and a data element M in format Y. For example, if the data object is a list of names, and the first format is sorted in ascending order by first name and descending order by last name, and there is a name AA, then the mapping will enable the reader to transfer from the data element at index zero of the format Z data structure to the last data element in the format Y data structure. In this way, any change to a data element in the first data structure can be propagated to the corresponding data element in the other format data structures of the same data.

[0021] The allocation may also include a conversion function. The conversion function operates similarly to a map with respect to the correspondence of data elements between formats of the same data, and in an example, a map may be used to accomplish the mapping aspect of the conversion. However, the conversion function also modifies the content of the data element from the source format to a data element in the destination format. These features enable the memory system to maintain the consistency of data objects in multiple formats and expose these multiple formats to an application (e.g., a processing circuit system running software) upon request.

[0022] These techniques can be applied to several scenarios that arise in modern computing. For example, multi-format data objects in memory can implement data compression, conversion between compressed sparse matrix formats, data replication, data precision adjustment, normalization or other preprocessing (e.g., for deep neural networks), application of error correction codes (ECC), encryption, or maintaining pseudo-random number distributions, etc. This can be achieved by leveraging the processing power on the memory system (including the generally higher internal bandwidth of the memory system) to perform background processing of data formatted in different ways while the requester (e.g., host) is processing other things. When the host needs data in a specific format, the host can read the data in a second format from the memory system. Subsequently, the memory system provides a pre-processed version of the requested format, or the memory system processes the data object in the first format to match the second format before delivering the data object to the host in the requested format. Therefore, multi-format data objects in memory can improve system performance by running data conversion and maintenance in parallel with other processors in the system. This improves energy efficiency by computing conversions close to the data (e.g., near-memory computing) and can be applied to a wide range of data types and applications. Additional details and examples are described below.

[0023] Figure 1 An example of an environment including a system 105 for hybrid consistency according to an embodiment is depicted. The system 105 includes a first host 110 (e.g., a central processing unit (CPU)) and a second host 160 (e.g., an accelerator), and a memory system 125. The first host 110 may have a directly attached host memory 115 in the system 105. In an example, the system 105 is or is a part of a server computer, a workstation, a personal laptop computer, a desktop computer, a digital camera, a smart phone, a memory card reader, an Internet of Things-enabled device, etc. The first host 110 or the second host 160 may include one or more processor cores, a system of parallel processors, or other CPU arrangements.

[0024] The memory system 125 includes a controller 130, a buffer 135 (e.g., an internal state memory), a cache 140, and a first memory device 145. The first memory device 145 may include, for example, one or more memory modules (e.g., a single in-line memory module, a dual in-line memory module, etc.). The first memory device 145 may include volatile memory or non-volatile memory. The first memory device 145 may include a multi-chip device that includes one or more different memory types or modules. In an example, the system 105 includes a second memory device 150 that interfaces with the memory system 125 and the first host 110.

[0025] The system 105 may include a backplane and may include a plurality of processing resources (e.g., one or more processors, microprocessors, or some other type of control circuitry) that include (or additionally include) a first host 110 and a second host 160. The system 105 may optionally include separate integrated circuits for the first host 110, the second host 160, the memory system 125, the controller 130, the buffer 135, the cache 140, the first memory device 145, the second memory device 150, any one or more of which may include respective chiplets that may be connected and used together. In an example, the system 105 includes a server system or a high performance computing (HPC) system or a portion thereof. Embodiments of the first host 110 or other components of the system 105 may be implemented in a Von Neumann or non-Von Neumann architecture, which may include one or more components typically associated with a Von Neumann architecture (e.g., CPU, ALU, etc.), or these components may be omitted.

[0026] In an example, the first memory device 145 may provide main memory for the system 105, or the first memory device 145 may include auxiliary memory or storage devices for use by the system 105. In an example, the first memory device 145 or the second memory device 150 includes one or more arrays of memory cells, such as volatile or non-volatile memory cells. For example, the array may be a flash array with a NAND architecture. The embodiments are not limited to a particular type of memory device. For example, the memory device may include RAM, ROM, DRAM, SDRAM, PCRAM, RRAM, and flash memory, etc.

[0027] In embodiments where the first memory device 145 includes persistent or nonvolatile memory, the first memory device 145 may include a flash memory device, such as a NAND or NOR flash memory device. The first memory device 145 may include other nonvolatile memory devices, such as nonvolatile random access memory devices (e.g., NVRAM, ReRAM, FeRAM, MRAM, PCM). Some memory devices, such as ferroelectric RAM (FeRAM) devices including ferroelectric capacitors, may exhibit hysteresis characteristics, such as 3-D cross point (3D XP) memory devices, or a combination thereof.

[0028] In an example, the interface 120 or the interface 165 may include any type of communication path, bus, interconnect, etc. that enables information to be transferred between the first host 110 or the second host 160 or other devices of the system 105 and the memory system 125, respectively. Non-limiting examples of interfaces may include a peripheral component interconnect (PCI) interface, a peripheral component interconnect express (PCIe) interface, a serial advanced technology attachment (SATA) interface, a universal serial bus (USB) interface, a Thunderbolt interface, or a micro serial advanced technology attachment (mSATA) interface, etc. In an example, the interface 120 includes a PCIe 5.0 interface that complies with the Compute Express Link (CXL) protocol standard. Therefore, in some embodiments, the interface 120 supports a transfer speed of at least 32GT / s.

[0029] CXL is a high-speed central processing unit (CPU) to device and CPU to memory interconnect designed to improve computing performance. CXL maintains memory consistency between the CPU memory space (e.g., host memory 115 or a cache maintained by the first host 110) and the memory on the attached device or accelerator (e.g., the first memory device 145 or the second memory device 150). Compared with other interconnect arrangements, this arrangement enables resource sharing with higher performance, reduced software stack complexity and lower overall system cost. CXL is an industry open standard interface for high-speed communication to accelerators, which are increasingly used to supplement CPUs to support emerging data-rich and compute-intensive applications such as artificial intelligence and machine learning. The memory system 125 is illustrated as having an atomic processing circuit system 155 as an accelerator to perform near-memory operations. In general, the atomic memory operations (AMOs) performed by the atomic processing circuit system 155 include small operations, such as incrementing a number at a memory address or multiplying numbers in two memory addresses. Although AMOs are commonly used for such operations, the manipulation of memory is not so limited. For example, modern artificial neural network architectures typically involve applying small addition or multiplication operations or thresholding on a large number of artificial neurons. Because the calculations are typically simple but the data is large, near-memory execution of such operations is possible and beneficial with the depicted architecture.

[0030] In an example, the controller 130 includes a media controller, such as a non-volatile memory express (NVMe) controller. The controller 130 may be configured to perform operations on the first memory device 145, such as copying, writing, reading, error correction, etc. In an example, the controller 130 may include circuit systems or instructions for specific purposes to perform various operations. That is, in some embodiments, the controller 130 may include circuit systems or may be configured to execute instructions to control the movement of data or addresses associated with data, such as between the buffer 135, the cache 140, or the first memory device 145 or the second memory device 150.

[0031] In an example, at least one of the first host 110 or the controller 130 includes a command manager (CM) for the memory system 125. The CM may receive a read command for a specific logical row address in the first memory device 145 or the second memory device 150. In an example, the CM may determine that the logical row address is associated with the first row based at least in part on a pointer stored in a register of the controller 130. In an example, the CM may receive a write command for the logical row address from the first host 110 or the second host 160. In an example, the write command is associated with the second data. In an example, the CM may be configured to issue an access command associated with the first memory device 145 or the second memory device 150 to the non-volatile memory and between issuing the read command and the write command. In an example, the CM may issue an access command associated with the first memory device 145 or the second memory device 150 to the non-volatile memory and between issuing the read command and the write command.

[0032] In an example, buffer 135 includes a data buffer circuit that includes an area of ​​physical memory for temporarily storing data, such as while the data is being moved from one location to another. Buffer 135 may include a first-in, first-out (FIFO) queue, where the oldest (e.g., first-in) data is processed first. In some embodiments, buffer 135 includes a hardware shift register, a circular buffer, or a list.

[0033] In an example, the cache 140 includes an area of ​​physical memory for temporarily storing specific data from the first memory device 145 or the second memory device 150. In general, the cache 140 provides faster data access than the backing memory. The cache 140 may include a pool of data entries. In an example, the cache 140 may be configured to operate according to a write-back policy in which data is written to the cache without being simultaneously written to the first memory device 145. Therefore, in some embodiments, data written to the cache 140 does not have a corresponding data entry in the first memory device 145. This may occur, for example, when data is written to the cache and deleted before a write-back is triggered to write the data to the first memory device 145.

[0034] In an example, cache 140 is implemented as a multi-way associative cache. Here, cache entries are partitioned by some portion of a memory address (e.g., a set number of valid bits). A group of cache entries (e.g., cache lines or ways), referred to herein as a cache set, may be commonly associated with the same set of bits from a memory address. Typically, the number of ways in a cache set is less than the total number of memory addresses associated with the ways. Therefore, ways associated with new memory addresses within a range may be evicted at various points. Figure 6 Some elements of this type of associative cache are shown.

[0035] In an example, the controller 130 may receive write requests involving the cache 140 and cause data associated with each of the write requests to be written to the cache 140. The controller 130 may similarly receive read requests and cause data stored in, for example, the first memory device 145 or the second memory device 150 to be retrieved and written to, for example, the first host 110 via the interface 120 or to the second host 160 via the interface 165. In an example, the controller 130 processes all requests for the memory it controls through the cache 140. Thus, a read request will first check the cache 140 to determine if the data has been cached. If not, then a read is made to the first memory device 145 to retrieve the data. The data is then written to the cache 140. In an example, the data is then read from the cache 140 and transmitted to the requesting entity, such as the first host 110 or the second host 160. Working exclusively through the cache can simplify some elements of the controller 130 hardware at the expense of a little latency.

[0036] In the case of system 105, controller 130 may be configured to implement a multi-format data object in memory system 125. To this end, controller 130 may be configured to receive (e.g., via software, instructions, hardwired circuitry, or a combination thereof) an allocation request for a data object. This data object is composed of a set of data elements. For example, a data object may be a geographic location having three integer data elements, namely, latitude, longitude, and altitude.

[0037] The received request also includes details of a set of formats for the data object. Formats represent different possible versions of the same data. However, some formats may have more data, and some formats may have less data. Consider the geographic coordinates above. A second format may contain only latitude and longitude, without altitude. Although the second format does not have altitude, the "same data" here ensures that the latitude and longitude are consistent in both formats. Other types of formatting may include whether words are big endian or little endian, whether fields are defined by bit or byte counts or have field headers, footers, etc.

[0038] The details about the format include elements to allocate space in memory (e.g., the first memory device 145) and to handle read or write requests in the various supported formats represented by the set of formats. In an example, the format details of the first format include a size. Thus, the controller 130 is told how much memory will be needed to store data in the first format to the first memory device 145. In an example, the details of the first format include a base memory address. This enables the host 110, for example, to specify where the various formats will be stored in memory, thereby enabling the host to read directly from the appropriate format.

[0039] The details about the first format include one or both of the mapping or identification of a conversion function between a first data element of a data object in the first format and a second data element in the second format in the set of formats. In this example, the first data element and the second data element represent the same data (e.g., derived from the same data or a version of the same data), such as both representing latitude in the above example. The conversion function is hardware or software configured to (or causes the processing circuit system to be configured to) convert the first data element to the second data element. In general, if the data elements have the same size, then the conversion function will only be a copy. However, for encryption, compression, changed precision (e.g., downsampling the data from the first element to a smaller size in the second element), the conversion is transformed, but ultimately represents the same data.

[0040] The controller 130 is configured to allocate space in a memory (e.g., the first memory device 145 or the second memory device 150) for a first version of a data object in a first format. The term "version" is used here to distinguish the creation of a data object from the possibility of the data object in terms of format. Thus, the first version is the creation of a first instantiation of a data object that just conforms to the details of the first format. In an example, the allocation is based on the base memory address and size in the allocation request. Thus, if given, a fragment of memory of the specified size and starting at the base memory address is allocated to the requestor.

[0041] Controller 130 is configured to store mapping in a mapping data structure corresponding to a data object. In an example, for each data object, there are different mapping data structures. In an example, for each type (e.g., or category) of data objects, there are different mapping data structures (e.g., two different geographic coordinate data objects share the same mapping data structure). In an example, the mapping data structure is unified between different types of data objects. The mapping data structure can be a lookup table, in which a source element (e.g., an element index) is used to locate the entry of the corresponding element pointing to another format. No matter how to implement, the mapping table enables the corresponding relationship between the data elements between different versions (created formats) of the data object to be determined. The mapping data structure can be stored in the working memory of controller 130, the first memory device 145 or other storage devices accessible to controller 130.

[0042] The controller 130 is configured to store the identification of the conversion function in a conversion data structure corresponding to the data object. Similar to a mapping, the conversion function embodies the correspondence between the data elements between the versions of the data object. However, the conversion function can also transform the underlying bits between these data elements. In an example, the conversion function is software executed on the controller 130 or on a processor (e.g., atomic processing circuit system 155) of the controller 130. In an example, the identification of the conversion function is the address of the code (e.g., instruction) of the conversion function in a memory (e.g., first memory device 145). In this example, the host (e.g., host 110) will usually first write the conversion function to the first memory device 145. Subsequently, the address of the conversion function is delivered in the allocation request. In an example, the identification of the conversion function is the code of the conversion function. This last example confirms that the conversion function can be delivered as part of the allocation request. In addition, in an example where the memory system 125 has built-in atoms, the identification can identify the atomic operation to be performed.

[0043] Once the allocation of the data object is performed, at least once the mapping or conversion function data structure is updated, the controller 130 can service read or write requests for the data object in any format. For example, the controller 130 is configured to provide access to a data object in a second format from a data object in a first format in memory based on a mapping data structure or a conversion data structure. Consider the scenario of allocating a geographic data object in a first format of three elements. The host 160 requests the data object in a second two-element format. The controller uses the mapping data structure to locate the latitude and longitude from the first version, but fails to locate the mapping for the altitude, and therefore omits the altitude. Therefore, the second version (second format) of the data object is returned to the host 160.

[0044] In an example, to provide access to a data object in a second format, the controller 130 is configured to receive a write request for the same data element of the data object. In an example, the write request includes an identifier of a first data element, an identifier of a second data element or a second format. The controller 130 is configured to subsequently convert the second data element to the first data element using a conversion function in a conversion data structure. In an example, the conversion function is located (e.g., retrieved, indexed, etc.) in the conversion data structure based on the identifier of the second format in the write request and the identifier of the same data element. To reiterate, these examples indicate an attempt to write (e.g., by the host 160) a data element of an allocated data object (which is in the first format) in the second format. The controller 130 uses the conversion function identified in the original allocation request and stored in the conversion data structure to convert the data being written into data suitable for the first format version allocated in the memory.

[0045] In an example, the identifier of the first data element includes the memory address of the first data element. In an example, the identifier of the first data element includes the base memory address of the data object in the first format in the memory and an offset relative to the base memory address of the first data element. In these examples, if the format is fixed (e.g., a finite number of fields of a set number of bits), the base memory address may be sufficient. However, in the case of a base address and an offset, the controller 130 may directly locate the data element.

[0046] In an example, to provide access to a data object in a second format, the controller 130 is configured to receive a read request including an identification of a second data element. In an example, a first data element from the memory is converted to a second data element using a conversion function identified in the conversion data structure. The controller 130 may then communicate a response to the read request including the second data element. These examples represent reads that perform conversions on the fly or on demand.

[0047] In an example, the controller 130 is configured to allocate a second space in the memory for a second version of the data object in the second format based on the second base memory address and the second size provided in the allocation request or in the second allocation request. In this example, the conversion between the data elements in the first version of the data object and the corresponding data elements in the second version of the data object can be performed using the conversion function identified in the conversion data structure. This example is a pre-processed second version of the data object, rather than the on-demand implementation described above.

[0048] Once the second version of the data object has been preprocessed, the read may simply be read into the second version. Thus, in an example, to provide access to the data object in the second format, the controller 130 is configured to receive a read request that identifies the first data element and specifies a response in the second format. The controller 130 retrieves the second data element from the second version of the data object in memory (e.g., the first memory device 145) based on the mapping in the mapping data structure. In this example, the mapping provides a location in memory from the first data element to the second data element. Subsequently, a response may be made to the read request that includes the second data element.

[0049] In an example, the controller 130 is configured to maintain a cache coherence data structure for a data object. In an example, the cache coherence data structure for the data object includes an entry corresponding to a first data element. In this example, the entry for the first data element is marked as valid after a write request is completed. In an example, when exclusive access to the first data element is granted to another device, the entry for the first data element is marked as invalid. These examples illustrate how cache coherence signaling can be maintained on a multi-formatted data object.

[0050] Figure 2 An example of a system in which multiple hosts can access multi-format data objects through a memory device according to an embodiment is shown. As shown, a number of hosts (e.g., CPUs, GPUs, FPGAs, or other processors) (e.g., hosts 205) are connected to memory devices, such as memory device 220, through an interconnection switch 215. The interconnection switch can be implemented using various hardware or software standards, such as the CXL series standard. The host 205 includes a host controller 210 to interface with the interconnection switch 215 and interact with the memory device 220.

[0051] The memory device 220 includes a version control engine 225. The version control engine 225 is implemented in the processing circuitry of the memory device 220 and may be a separate block or component of the memory device 220, or the version control engine 225 may be included in a memory controller or other standard component of the memory device 220. The version control engine 225 operates on requests from the host 205 to transfer or convert requests between different formats of the same data object held by the memory device 220. The version control engine 225 performs these tasks using mapping or conversion functions provided by the host 205 at the time of data object allocation.

[0052] In the context of the depicted system, the following example may be considered. Consider configuring a multi-format data object. When allocating storage for all possible versions of the data object, the host 205 may inform the version control engine 225 on the target storage device 220 of the following information:

[0053] ●The base address and size of each version of the data object.

[0054] - A matrix of mapping functions or function pointers from X (rows) to Y (columns). These mapping functions provide a method to convert between any pair of formats. In the example, there is at least one pointer in each row and column.

[0055] A matrix of conversion functions similar to the mapping functions above, which also converts the data elements of the data object into a new format. The following is an example of a conversion function mapping table (eg, data structure):

[0056] From / To Version 0 Version 1 Version 2 Version 0 N / A F01 Version 1 N / A F12 Version 2 F20 N / A

[0057] In the example of this table, if a user writes an element of version 0 of a data object, version 1 of the data object is updated by calling F01 and version 2 of the data object is updated by calling F12. Generally speaking, the greater the number of functions, the more updates can be performed in parallel, thereby providing better system performance.

[0058] Now, consider using a programmable function to convert formats. A mapping function can be used by the version control engine 225 for a read request that specifies a data element ID or offset. The mapping function obtains these inputs and provides the location of the byte address of the data element in the memory as output. In an example, the mapping function can accept the address of the data element accessed in the current version and the target version as input. The mapping function can provide the byte address of the data element in the target version as output.

[0059] For example, in response to a read request for an invalid data element of the current version during a deferred (e.g., on-demand) implementation or in response to a write to another version during an active implementation (e.g., pre-allocation), a conversion function may be used by the version control engine 225 to update an inconsistent version. In an example, the conversion function may accept as input the address of the data element accessed in the current version, the target version, and the data value. The conversion function overwrites the target data element in the target version reference in the input with the data from the input.

[0060] Cache coherence may be affected by multiple formatted objects in memory. It is possible that when a data element is written to the memory device 220, another device (e.g., memory device 2) or a host (e.g., host 1) has a version of the data element in its local cache. Typically, all memory addresses in the system will be under the control of a cache coherence protocol (e.g., defined by CXL or the standard Modified Exclusive Shared Invalid (MESI) protocol).

[0061] When the host 205 writes a data element into a data object, the modification to the data element typically causes a modified state change in the local (to the writer) cache (e.g., in the MESI protocol). The coherence protocol invalidates all other copies of the address in other caches, e.g., to cause those other entities to re-read the data element from the memory device 220. However, these protocols do not extend to other versions of the data element.

[0062] To resolve the consistency issue, and to maintain data consistency of the versions, the host 205 may immediately flush the modified cache line (or may configure the data object address space as non-cacheable), making the write to the data element visible to the memory device 220. Here, the memory device 220 immediately invalidates all other cached copies of all versions of the data element. This may be accomplished using memory protocol consistency commands available in, for example, CXL or Gen-Z. In an example, a mapping function may be used to calculate the byte address of the data element on all versions of the data object. Once the cache is invalidated, active or delayed version updates may continue as usual.

[0063] Another approach may enable the modified version to remain in the cache. In this example, the memory device hosting the data element participates in a consistency protocol to receive notification of a "read exclusive" or BusReadX consistency probe from the cache agent that writes the data element. This approach is similar to the above in that upon receiving a BusReadX, an invalidation message is sent to all other cache devices that may have a copy of any version of the data element. In order to maintain data consistency, the memory device 220 may delay the response to the BusReadX until all invalidations have occurred. In some protocols, this behavior may result in deadlock.

[0064] Hardware consistency may result in a slowdown, depending on the amount of additional consistency traffic generated by each write in the system and the type of consistency protocol. Software consistency techniques may be used as an alternative. Here, a function call in the program may signal the memory device 220 whenever data is modified and flushed to memory or when data is recalled by the memory device 220. This signal may then trigger the memory device 220 to update the data object version and send an invalidation for the entire data object in a batch operation, for example. In an example, the software may invalidate its own cached copies of other versions. The software may wait (e.g., a gate function or spin lock) for the hardware to set a flag indicating that the update is complete before continuing.

[0065] Multi-format data objects may also affect memory management. In some examples described above, the host 205 allocates memory (e.g., requests memory allocation) for all versions of the data object at the same time (e.g., in advance). In an example, by adding a "reconfigure object" command, the host 205 can allocate different amounts of space or move one or more of the data object versions in memory. Here, the host 110 can indicate a new starting address or size for each new version to the memory device 220, essentially reinitializing the new version of the data object. In an example, the memory device 220 can manage the memory management of the data object similar to the host-based memory management just mentioned. However, here, any changes made by the memory device 220 will generally be communicated back to the host 205.

[0066] In an example, data objects may be shared between multiple hosts or other memory devices. For example, a structured attached memory software API and library is used, such as OpenFAM: a library for programming structured attached memory. In OpenFAM, data objects may be named when allocated for access by any host. In an example, data objects may be interleaved across memory devices to, for example, exploit proportionality or parallelism. For example, software may be used to allocate an entire data object across memory devices, such as in a round-robin allocation. In an example, software may be used to split a data object into multiple smaller objects (e.g., subsets of data elements), each data object being allocated to a different memory device. In an example, hardware may be used to interleave data objects across multiple memory devices, such as through a host-side controller 210 or a switch 215 between a host and a memory device. In general, when objects are interleaved, element IDs are adjusted according to the interleaving. For example, the most significant bit may be removed before the data object ID is passed to the target memory device.

[0067] Figure 3 An example of host 305 and memory device 310 interaction to write a multi-format object is depicted in accordance with an embodiment. In general, when accessing a multi-format object, the interaction can be on-demand (e.g., delayed) or proactive (e.g., pre-allocated). Again, an on-demand interaction is one in which the conversion of data elements from one version by version control engine 315 does not occur until a read is performed. The proactive approach differs in that all versions of a data object are updated when any version of a data object or a specific version of a data object is written. In an example, these updates can be performed as a background task (e.g., facilitated by version control engine 315) when memory device 310 is idle or bandwidth is underutilized.

[0068] In an example, a directory 320 in a reserved memory space (e.g., for each allocated data object) tracks the state of the data elements. In an example, the state may be tracked with a VALID or INVALID state bit for each version of each data element. In an example, as a space-saving simplification, a larger group of data elements may be tracked such that a single INVALID data element in the group causes all data elements in the group to be considered INVALID. The state data in the directory 320 may be used to maintain consistency between versions of the data elements, and therefore between versions of the data objects.

[0069] In an example, all data elements of all versions begin with INVALID. After being written by the host 305 or updated by the version engine 315, the data element is marked as VALID. When using an on-demand implementation scheme (e.g., mode), after writing to the data element, the data elements in all other versions of the data object are marked as INVALID. Here, during the update of various versions of the data element, the reading of any version of the data element is blocked. This can be implemented by delaying the read response. Because the update is for fine-grained data elements rather than the entire data object, this practice will generally not cause significant performance loss.

[0070] When in the active implementation scheme, after writing to a data element, all other versions of the data element are updated by calling one or more conversion function sequences. Once completed, the directory 320 entries for the data element across these versions are marked as VALID.

[0071] Figure 3 The scenario depicted in illustra ts how a write replaces the data value D0 in version 0 of object 1. This can be requested by the host 305 using a flat physical or virtual address, a version ID with a byte offset (e.g., a number), or a version ID with a data element index. As mentioned above, depending on the mode, a write causes the data items in other versions to be invalidated or updated.

[0072] Figure 4 An example of host and memory device interaction to read a multi-format object is depicted according to an embodiment. Here, data element D2 is read for target version 1 of object 0. In an active implementation, host 305 can directly reference the memory address to obtain data element D2. Host 305 can use an alternative identification mechanism that identifies the version (version 1) and identifies the offset or data element ID in an on-demand or active implementation. In these cases, version control engine 315 locates the data element via a mapping function, or converts the data element via a conversion function as needed.

[0073] Figure 5 An example of a host connected to a CXL device is depicted according to an embodiment. Figure 5 Generally depicted is an example of a CXL system 500 that uses a CXL link 506 to connect a host device 502 and a CXL device 504 via a host physical layer PCIE interface 508 and a CXL client physical layer PCIE interface 510, respectively. In the example, the host device 502 includes or corresponds to the first host 110 (or the second host 160), and the CXL device 504 includes or corresponds to a CXL client physical layer PCIE interface 510. Figure 1504. The memory system command manager may include a portion of a host device 502 or a CXL device 504. In an example, a CXL link 506 may support communications using a multiplexing protocol for cache (e.g., CXL.cache), memory access (e.g., CXL.mem), and data input / output transactions (e.g., CXL.io). CXL.io may include a PCIe-based protocol for functions such as device discovery, configuration, initialization, I / O virtualization, and direct memory access (DMA) using non-uniform load-store, producer-consumer semantics. CXL.cache may enable a device to cache data from a host memory (e.g., from host memory 512) using a request and response protocol. CXL.memory may enable a host device 502 to use memory attached to a CXL device 504, for example, in or using a virtualized memory space. In an example, a CXL.memory transaction may be a memory load and store operation that is executed downstream or external to the host device 502.

[0074] exist Figure 5 In an example of , host device 502 includes a host processor 514 (e.g., including one or more CPUs or cores) and one or more IO devices 528. Host device 502 may include or may be coupled to host memory 512. Host device 502 may include various circuitry (e.g., logic) configured to facilitate CXL-based communications and transactions with CXL device 504. For example, host device 502 may include coherence and memory circuitry 518 configured to implement transactions according to CXL.cache and CXL.mem semantics, and host device 502 may include PCIe circuitry 520 configured to implement transactions according to CXL.io semantics. In an example, host device 502 may be configured to manage the coherence of data cached at CXL device 504 using, for example, its coherence and memory circuitry 518.

[0075] Host device 502 may further include a host multiplexer 516 configured to modulate communications over CXL link 506 (e.g., using a PCIe PHY layer). Multiplexing of protocols ensures that latency-sensitive protocols (e.g., CXL.cache and CXL.memory) have the same or similar latency as the native inter-processor link. In an example, CXL defines an upper bound on the response time of latency-sensitive protocols to help ensure that device performance is not adversely affected by latency variations between different devices implementing coherency and memory semantics.

[0076] In an example, a symmetric cache coherence protocol may be difficult to implement between host processors because different architectures may use different solutions, which in turn may compromise backward compatibility. CXL may address this issue by merging coherence functions at host device 502, such as using coherence and memory circuitry 518.

[0077] The CXL device 504 may include an accelerator device that includes various accelerator circuitry 522. In an example, the CXL device 504 may include or may be coupled to a CXL device memory 526. The CXL device 504 may include various circuitry configured to facilitate CXL-based communications and transactions with the host device 502 using the CXL link 506. For example, the accelerator circuitry 522 may be configured to implement transactions according to CXL.cache, CXL.mem, and CXL.io semantics. The CXL device 504 may include a CXL device multiplexer 524 configured to control communications over the CXL link 506. The accelerator circuitry 522 may be one or more processors that may perform one or more tasks. The accelerator circuitry 522 may be a general purpose processor or a processor designed to accelerate one or more specific workloads.

[0078] Figure 6 Example components of a memory device according to an embodiment are shown. The components shown are part of a memory controller, such as those described above that implement a memory side cache (MSC) (e.g., Figure 1 The illustrated components include elements to resolve differences in internal (e.g., from a near memory accelerator) and external (e.g., received from a host via a CXL link) requests for maintaining CXL protocol requirements, such as maintaining forward progress of CXL memory (CM) requests.

[0079] As shown, CM refers to CXL memory or other external requests, and NI refers to requests from the NOC interface or other internal requests. Requests from CXL.mem are written to the CM request information table 605. The entries in the CM request information table 605 to which the request is written are obtained from the CM request information table pool 610. The CM request information table pool 610 maintains a list of indexes pointing to available CM request information table entries (e.g., free, or unused). Requests from accelerators within the device are written to the NI request information table 615 using the NI request information table pool 620 indexed by the available entries. The two pools, the CM request information table pool 610 and the NI request information table pool 620, are configured so that accelerator requests (e.g., internal requests) cannot consume all table entries. Therefore, for example, if additional NI requests arrive and there are no free entries indicated in the NI request information table pool 620, the request is suspended until an entry is available. Here, the request can be kept in the inbound queue until an entry is available.

[0080] CXL.mem requests from CM queue 625 are selected with a higher priority than NI requests in NI queue 630 to ensure forward progress of CM requests. In the example, as shown, when a request is selected from CM queue 625 or NI queue 630, the request information is written to NI+CM request information table 631. Hereinafter, each request is represented in various queues by an identifier (e.g., index) to an entry of NI+CM request information table 631. This arrangement can reduce storage requirements and bandwidth when request information is transferred between various queues at different processing points in the controller. When a processing point needs a certain aspect of a request (e.g., an address for reading), the identifier is used to reference the entry in NI+CM request information table 631 and retrieve the fields of the request corresponding to the required aspect. As with CM request information table 605 and NI request information table 615, a free list or pool of entries can be used to quickly determine which entries are available to store request information in NI+CM request information table 631.

[0081] When a request is selected, the cache tag 635 of the cache line (e.g., cache way) corresponding to the address in the request may be checked to determine whether the request is to be delayed (e.g., processed later). A request is typically delayed when there is no available (e.g., free) way entry in the cache set for the address in the request. If no delay occurs, the cache data may be read 640 or modified 645 (e.g., for writing), and the way tag may be modified 650. The modified tag 650 or cache data 645 may be written to the backing store, such as when the tag data 655 and cache way data 660 are written, respectively.

[0082] When a request is deferred, a request entry identifier (e.g., from the NI+CM request information table 631) is pushed to a CM or NI deferral queue 665. A way deferral queue 665 is used when there is a way corresponding to the address in the request but the way is busy (e.g., waiting for another command to complete). A set deferral queue 665 is used when there is no way corresponding to the address. The request remains queued until the way is available (e.g., not busy). In an example, there are separate CM and NI deferral queues 665 for each cache set within a cache.

[0083] The external control queue 670 manages external responses to the cache, such as responses to reads or writes to backing memory, memory controller (MC) requests, or CXL recalls. A CXL recall is a request made by the memory device to regain control of a cache way from the host. A recall is a request made to the host, and the host communicates control of the cache way to the memory controller, for example, in a CXL metastate. This procedure may be referred to as a bias flip because the control bias for the cache way flips from the host to the controller and vice versa. This technique is used to achieve cache coherency between any host cache and the memory device.

[0084] The command queue 675 tracks requests through various processing points, such as whether a request is pushed or popped from the deferred queue 665, whether a CXL recall is initiated, a memory controller request, an execution command, or an atomic memory operation (AMO) is performed. A reference to a long AMO is an AMO that cannot be completed within a single execution cycle (e.g., a clock cycle). An AMO is a near memory operation that is completed by an accelerator of a memory controller.

[0085] The control and data paths described are configured so that separate storage, queuing, and request prioritization enable advancement on CM requests while executing in the presence of NI requests. Thus, CM requests will not be delayed by NI requests.

[0086] Figure 6An example of an associative cache according to an embodiment is depicted. Here, the associative cache includes four cache sets, namely cache set zero 605, cache set one 610, cache set two 615, and cache set three 620. It should be noted that each cache set corresponds to a memory address range. Therefore, cache set one corresponds to all memory elements with addresses having a prefix of 00, while cache set three 615 corresponds to all memory elements with addresses having a prefix of 10. The cache lines within each cache set represent storage elements (e.g., registers) sized for elements in the memory. Each cache line may also be referred to as a "way". Therefore, as depicted, the associative cache is a four-way associative cache because four ways are available for each cache set. In general, a memory request with an address in one cache set will load one way until all ways are used. In the event that another memory request arrives, a process of evicting one way to load new data may be performed to free up the way for the new memory request.

[0087] The associative cache may maintain metadata for the ways. Thus, as illustrated, the associative cache includes tags (e.g., metadata) in addition to the way data, resulting in way zero tag and data 625, way one tag and data 630, way two tag and data 635, and way three tag and data 640. Examples of tag data may include a dirty bit to indicate whether the way is out of sync with backing memory, whether there is an operation to synchronize the way with host memory (e.g., a host recall is in progress), or CXL meta-state, request status, etc. In an example, when the source of the request (e.g., internal or external) affects the operation of the memory controller, the tag data may include a designation of whether the request is internal or external and, for example, whether the request is internal and deferred or external and deferred.

[0088] Figure 7 A flow chart is shown of an example of a method 700 for multi-format data objects in memory according to an embodiment. The operations of method 700 are performed by a device and implemented in hardware (eg, computing hardware) (eg, processing circuitry) such as described above or below.

[0089] At operation 705, a request for allocation of a data object is received (e.g., at a device interface, such as those compliant with the Compute Express Link (CXL) family of standards). In this example, the data object includes a set of data elements, and the request includes details of a set of formats for the data object. In an example, the details of a first format in the set of formats may include: a base memory address; a size; a mapping between a first data element of the data object in the first format and a second data element in a second format in the set of formats (the first data element and the second data element representing the same data element); or an identification of a conversion function configured to convert the first data element to the second data element.

[0090] At operation 710, a memory device (eg, circuitry therein) allocates space in memory for a first version of a data object in a first format. In an example, the allocation is based on a base memory address and size in an allocation request.

[0091] At operation 715, the mapping is stored in a mapping data structure corresponding to the data object.

[0092] At operation 720, an identification of the conversion function is stored in a conversion data structure corresponding to the data object. In an example, the memory device includes a processor, and the conversion function is software executed on the processor. In an example, the identification of the conversion function is an address of the code (e.g., instructions) of the conversion function in the memory. In an example, the identification of the conversion function is the code of the conversion function.

[0093] At operation 725, access to a data object in a second format is provided from a data object in a first format in a memory based on a mapping data structure or a conversion data structure. In an example, providing access to the data object in the second format includes receiving (e.g., on an interface) a write request for the same data element of the data object. In an example, the write request includes an identifier of the first data element, an identifier of the second data element or the second format. The device (e.g., the circuit system therein) then converts the second data element to the first data element using a conversion function in the conversion data structure. In an example, the conversion function is located (e.g., retrieved, indexed, etc.) in the conversion data structure based on the identifier of the second format and the identifier of the same data element in the write request.

[0094] In an example, the identifier of the first data element comprises a memory address of the first data element. In an example, the identifier of the first data element comprises a base memory address of a data object in a first format in memory and an offset relative to the base memory address of the first data element.

[0095] In an example, providing access to the data object in the second format includes receiving a read request including an identification of the second data element. The first data element from the memory may then be converted to the second data element using a conversion function identified in the conversion data structure. A response to the read request including the second data element may be communicated (e.g., by the device circuitry on the device interface).

[0096] The operation of method 700 can be extended to include allocating a second space in memory for a second version of the data object in a second format based on a second base memory address and a second size provided in an allocation request or in a second allocation request. In this example, a conversion between a data element in the first version of the data object and a corresponding data element in the second version of the data object can be performed using a conversion function identified in a conversion data structure. In an example, providing access to the data object in the second format includes receiving a read request that identifies the first data element and specifies a response in the second format. The second data element can be retrieved from the second version of the data object in the memory based on a mapping in a mapping data structure. In this example, the mapping provides a location in the memory from the first data element to the second data element. Subsequently, a response can be made to the read request that includes the second data element.

[0097] In an example, a cache coherence data structure of a data object includes an entry corresponding to a first data element. In this example, the entry for the first data element is marked as valid after a write request is completed. In an example, the entry for the first data element is marked as invalid when exclusive access to the first data element is granted to another device.

[0098] Figure 8A block diagram of an example machine 800 on which any one or more of the techniques (e.g., methods) discussed herein may be performed is illustrated. As described herein, an example may include logic or multiple components or mechanisms in the machine 800, or may be operated by it. A circuit system (e.g., a processing circuit system) is a collection of circuits implemented in a tangible entity of the machine 800, which includes hardware (e.g., simple circuits, gates, logic, etc.). The membership of the circuit system may be flexible over time. The circuit system includes components that can perform specified operations individually or in combination when operating. In an example, the hardware of the circuit system may be immutably designed to perform specific operations (e.g., hard wiring). In an example, the hardware of the circuit system may include variably connected physical components (e.g., execution units, transistors, simple circuits, etc.), which include machine-readable media that are physically modified (e.g., magnetic properties of fixed centralized particles, electrically movable placement, etc.) to encode instructions for specific operations. When connecting physical components, the fundamental electrical properties of the hardware components are changed, such as from insulators to conductors, or vice versa. Instructions enable embedded hardware (e.g., an execution unit or a loading mechanism) to create components of a circuit system in hardware via variable connections to perform a portion of a specific operation when in operation. Therefore, in an example, a machine-readable media element is a part of a circuit system or is communicatively coupled to other components of the circuit system when the device is in operation. In an example, any of the physical components can be used in more than one component in more than one circuit. For example, under operation, an execution unit can be used in a first circuit of a first circuit system at one point in time and reused by a second circuit in the first circuit system at a different time, or reused by a third circuit in the second circuit system. Additional examples of these components relative to machine 800 are as follows.

[0099] In some embodiments, the machine 800 may be connected (e.g., using a network) to other machines. In a networked deployment, the machine 800 may operate as a server machine, a client machine, or both in a server-client network environment. In one example, the machine 800 may operate as a peer machine in a peer-to-peer (P2P) (or other distributed) network environment. The machine 800 may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a mobile phone, a network appliance, a network router, a switch or a bridge, or any machine capable of executing (sequentially or otherwise) instructions that specify actions to be taken by the machine. Further, while a single machine is illustrated, the term “machine” shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein (e.g., cloud computing, software as a service (SaaS), other computer cluster configurations).

[0100] The machine (e.g., computer system) 800 may include a hardware processor 802 (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a hardware processor core, or any combination thereof), a main memory 804, a static memory (e.g., memory or storage for firmware, microcode, basic input output (BIOS), unified extensible firmware interface (UEFI), etc.) 806, and a mass storage device 808 (e.g., a hard drive, a tape drive, a flash storage device, or other block device), some or all of which may communicate with each other via an interconnect (e.g., a bus) 830. The machine 800 may further include a display unit 810, an alphanumeric input device 812 (e.g., a keyboard), and a user interface (UI) navigation device 814 (e.g., a mouse). In an example, the display unit 810, the input device 812, and the UI navigation device 814 may be a touch screen display. The machine 800 may additionally include a storage device (e.g., a drive unit) 808, a signal generating device 818 (e.g., a speaker), a network interface device 830, and one or more sensors 816, such as a global positioning system (GPS) sensor, a compass, an accelerometer, or another sensor. The machine 800 may include an output controller 838, such as a serial (e.g., universal serial bus (USB)), parallel or other wired or wireless (e.g., infrared (IR), near field communication (NFC), etc.) connection to communicate with or control one or more peripheral devices (e.g., a printer, a card reader, etc.).

[0101] The processor 802, main memory 804, static memory 806, or a register of a mass storage device 808 may be or include a machine-readable medium 832 on which is stored one or more sets of data structures or instructions 834 (e.g., software) embodying or utilized by any one or more of the techniques or functions described herein. The instructions 834 may also reside, completely or at least partially, within any of the registers of the processor 802, main memory 804, static memory 806, or mass storage device 808 during execution thereof by the machine 800. In an example, one or any combination of the hardware processor 802, main memory 804, static memory 806, or mass storage device 808 may constitute the machine-readable medium 832. Although the machine-readable medium 832 is depicted as a single medium, the term "machine-readable medium" may include a single medium or multiple media (e.g., a centralized or distributed database, and / or associated caches and servers) configured to store one or more instructions 834.

[0102] The term "machine-readable medium" may include any medium capable of storing, encoding, or carrying instructions for execution by the machine 800 and causing the machine 800 to perform any one or more of the techniques of the present disclosure, or capable of storing, encoding, or carrying data structures used by or associated with such instructions. Non-limiting machine-readable medium examples may include solid-state memory, optical media, magnetic media, and signals (e.g., radio frequency signals, other photon-based signals, sound signals, etc.). In an example, a non-transitory machine-readable medium includes a machine-readable medium having a plurality of particles that have a constant (e.g., stationary) mass and are therefore composed of matter. Thus, a non-transitory machine-readable medium is a machine-readable medium that does not include a transient propagating signal. Specific examples of non-transitory machine-readable media may include: non-volatile memory, such as semiconductor memory devices (e.g., electrically programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM)) and flash memory devices; magnetic disks, such as internal hard disks and removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks.

[0103] In an example, the information stored or otherwise provided on the machine-readable medium 832 may represent instructions 834, such as the instructions 834 themselves or a format from which the instructions 834 may be derived. Such a format from which the instructions 834 may be derived may include source code, encoded instructions (e.g., in compressed or encrypted form), packaged instructions (e.g., split into multiple data packets), etc. The information representing the instructions 834 in the machine-readable medium 832 may be processed by the processing circuitry into instructions to implement any of the operations discussed herein. For example, deriving the instructions 834 from the information (e.g., processed by the processing circuitry) may include: compiling (e.g., from source code, object code, etc.), interpreting, loading, organizing (e.g., dynamically or statically linking), encoding, decoding, encrypting, decrypting, packaging, unpacking, or otherwise manipulating the information into instructions 834.

[0104] In an example, the export of instructions 834 may include the assembly, compilation, or interpretation of information (e.g., by processing circuitry) to create instructions 834 from some intermediate or pre-processed format provided by machine-readable media 832. When the information is provided in multiple parts, the information may be combined, unpacked, and modified to create instructions 834. For example, the information may be in multiple compressed source code data packets (or object code, or binary executable code, etc.) on one or more remote servers. The source code data packets may be encrypted when transmitted over the network, and, if necessary, decrypted, decompressed, assembled (e.g., linked), and compiled or interpreted at the local machine (e.g., into a library, a stand-alone executable file, etc.), and executed by the local machine.

[0105] The instructions 834 may further be transmitted or received over a communication network 836 using a transmission medium via the network interface device 830 using any of a number of transmission protocols (e.g., frame relay, Internet Protocol (IP), transmission control protocol (TCP), user datagram protocol (UDP), hypertext transfer protocol (HTTP), etc.). Example communication networks may include a local area network (LAN), a wide area network (WAN), a packet data network (e.g., the Internet), a LoRa / LoRaWAN or satellite communication network, a mobile phone network (e.g., a cellular network, such as a cellular network compliant with 3G, 4G LTE / LTE-A, or 5G standards), a plain old telephone (POTS) network, and a wireless data network (e.g., the Institute of Electrical and Electronics Engineers (IEEE) 802.11 series of standards (known as ), IEEE 802.15.4 family of standards), peer-to-peer (P2P) networks, etc. In an example, the network interface device 830 may include one or more physical jacks (e.g., Ethernet, coaxial, or telephone jacks) or one or more antennas to connect to the communication network 836. In an example, the network interface device 830 may include multiple antennas to communicate wirelessly using at least one of single-input multiple-output (SIMO), multiple-input multiple-output (MIMO), or multiple-input single-output (MISO) technology. The term "transmission media" should be taken to include any intangible media capable of storing, encoding, or carrying instructions for execution by the machine 800, and includes digital or analog communication signals or other intangible media used to facilitate the communication of such software. Transmission media is machine-readable media.

[0106] Additional Notes and Examples

[0107] Example 1 is a device for implementing multi-format data objects in a memory, the device comprising: an interface configured to communicate with an external entity; and a processing circuit system configured to: receive an allocation request for a data object at the interface, the data object comprising a set of data elements, the allocation request comprising corresponding details of a set of formats of the data object, the details of a first format in the set of formats comprising: a basic memory address; a size; a mapping between a first data element of the data object in the first format and a second data element in a second format in the set of formats, the first data element and the second data element representing the same data element; and an identification of a conversion function configured to convert the first data element to the second data element; allocate space for a first version of the data object in the first format in a memory managed by the device based on the basic memory address and size in the allocation request; store the mapping in a mapping data structure corresponding to the data object; store the identification of the conversion function in a conversion data structure corresponding to the data object; and provide access to a data object in a second format from the data object in the first format in the memory based on the mapping data structure or the conversion data structure, the second format comprising the second data element.

[0108] In Example 2, according to the subject matter described in Example 1, to provide access to a data object in a second format, the processing circuit system is configured to: receive a write request for the same data element of the data object on an interface, the write request including an identifier of the first data element, a second data element, and an identifier of the second format; and convert the second data element to the first data element for storage in a memory using a conversion function in a conversion data structure, the conversion function being located based on the identifier of the second format and the identifier of the same data element in the write request.

[0109] In example 3, according to the subject matter of example 2, wherein the identifier of the first data element comprises a memory address of the first data element.

[0110] In example 4, according to the subject matter of any of examples 2-3, the identifier of the first data element comprises a base memory address of the data object of the first format in the memory and an offset relative to the base memory address of the first data element.

[0111] In Example 5, the subject matter of any of Examples 2 to 4, wherein the cache coherence data structure of the data object includes an entry corresponding to the first data element, and wherein the entry for the first data element is marked as valid after the write request is completed.

[0112] In example 6, according to the subject matter of example 5, wherein the entry for the first data element is marked as invalid when exclusive access to the first data element is granted to another device.

[0113] In Example 7, according to the subject matter described in any of Examples 1 to 6, to provide access to a data object in a second format, the processing circuit system is configured to: receive a read request on an interface, the read request including an identification of a second data element; convert a first data element from a memory into a second data element using a conversion function identified in a conversion data structure; and communicate a response to the read request on the interface, the response including the second data element.

[0114] In Example 8, according to the subject matter described in any of Examples 1 to 7, the processing circuit system is configured to: allocate second space in the memory for a second version of the data object in a second format based on a second base memory address and a second size provided in an allocation request or in a second allocation request; and convert data elements in the first version of the data object into corresponding data elements in the second version of the data object using a conversion function identified in a conversion data structure.

[0115] In Example 9, according to the subject matter described in Example 8, to provide access to a data object in a second format, the processing circuit system is configured to: receive a read request on an interface, the read request including an identification of a first data element and specifying a response in a second format; retrieve a second data element from a second version of the data object in a memory based on a mapping in a mapping data structure, the mapping providing a location in the memory from the first data element to the second data element; and communicate a response to the read request on the interface, the response including the second data element.

[0116] In example 10, the subject matter of any of examples 1-9, wherein the processing circuitry is a processor, and wherein the conversion function is software executing on the processor.

[0117] In example 11, according to the subject matter of example 10, the identification of the conversion function is an address of the code of the conversion function in memory.

[0118] In Example 12, according to the subject matter of any of Examples 10-11, the identification of the conversion function is a code of the conversion function.

[0119] In Example 13, according to the subject matter of any of Examples 1 to 12, wherein the interface complies with the Compute Express Link (CXL) family of standards.

[0120] Example 14 is a method for multi-format data objects in a memory, the method comprising: receiving an allocation request for a data object at an interface of a memory device, the data object comprising a set of data elements, the allocation request comprising corresponding details of a set of formats of the data object, the details of a first format in the set of formats comprising: a basic memory address; a size; a mapping between a first data element of the data object in the first format and a second data element in a second format in the set of formats, the first data element and the second data element representing the same data element; and an identifier of a conversion function configured to convert the first data element to the second data element; allocating space for a first version of the data object in the first format in a memory of the memory device based on the basic memory address and size in the allocation request by a circuit system of the memory device; storing the mapping in a mapping data structure corresponding to the data object; storing the identifier of the conversion function in a conversion data structure corresponding to the data object; and providing access to a data object in a second format from the data object in the first format in the memory based on the mapping data structure or the conversion data structure, the second format comprising the second data element.

[0121] In Example 15, according to the subject matter described in Example 14, providing access to a data object in a second format includes: receiving a write request for the same data element of the data object on an interface, the write request including an identifier of the first data element, a second data element, and an identifier of the second format; and converting the second data element to the first data element for storage in a memory using a conversion function in a conversion data structure by a circuit system, the conversion function being located based on the identifier of the second format and the identifier of the same data element in the write request.

[0122] In Example 16, according to the subject matter of Example 15, wherein the identifier of the first data element comprises a memory address of the first data element.

[0123] In Example 17, according to the subject matter of any of Examples 15-16, the identifier of the first data element comprises a base memory address of a data object of the first format in the memory and an offset relative to the base memory address of the first data element.

[0124] In Example 18, the subject matter of any of Examples 15 to 17, wherein the cache coherence data structure of the data object includes an entry corresponding to the first data element, and wherein the entry for the first data element is marked as valid after the write request is completed.

[0125] In Example 19, according to the subject matter of Example 18, wherein the entry for the first data element is marked as invalid when exclusive access to the first data element is granted to another device.

[0126] In Example 20, the subject matter of any of Examples 14 to 19, wherein providing access to a data object in a second format comprises: receiving a read request on an interface, the read request comprising an identification of a second data element; converting a first data element from a memory to a second data element using a conversion function identified in a conversion data structure; and communicating a response to the read request on the interface by a circuit system, the response comprising the second data element.

[0127] In Example 21, the subject matter described in any one of Examples 14 to 20 includes: allocating a second space in a memory for a second version of a data object in a second format based on a second base memory address and a second size provided in an allocation request or in a second allocation request; and converting data elements in a first version of the data object into corresponding data elements in a second version of the data object using a conversion function identified in a conversion data structure.

[0128] In Example 22, the subject matter of Example 21, wherein providing access to a data object in a second format comprises: receiving a read request on an interface, the read request including an identification of a first data element and specifying a response in a second format; retrieving a second data element from a second version of the data object in a memory based on a mapping in a mapping data structure, the mapping providing a location in the memory from the first data element to the second data element; and communicating a response to the read request on the interface through a circuit system, the response including the second data element.

[0129] In Example 23, the subject matter of any of Examples 14-22, wherein the memory device includes a processor, and wherein the conversion function is software executed on the processor.

[0130] In example 24, according to the subject matter of example 23, the identification of the conversion function is an address of the code of the conversion function in memory.

[0131] In Example 25, according to the subject matter of any of Examples 23-24, the identification of the conversion function is a code of the conversion function.

[0132] In Example 26, the subject matter of any of Examples 14-25, wherein the interface complies with the Compute Express Link (CXL) family of standards.

[0133] Example 27 is a machine-readable medium comprising instructions for implementing a multi-format data object in a memory, which instructions, when executed by a processing circuit system of a device, cause the device to perform operations including the following: receiving an allocation request for a data object at an interface of the device, the data object comprising a set of data elements, the allocation request comprising corresponding details of a set of formats of the data object, the details of a first format in the set of formats comprising: a base memory address; a size; a mapping between a first data element of the data object in the first format and a second data element in a second format in the set of formats, the first data element and the second data element representing the same data element; and an identification of a conversion function configured to convert the first data element to the second data element; allocating space in the memory of the device for a first version of the data object in the first format based on the base memory address and size in the allocation request; storing the mapping in a mapping data structure corresponding to the data object; storing the identification of the conversion function in a conversion data structure corresponding to the data object; and providing access to a data object in a second format from the data object in the first format in the memory based on the mapping data structure or the conversion data structure, the second format comprising the second data element.

[0134] In Example 28, according to the subject matter of Example 27, providing access to a data object in a second format includes: receiving a write request for the same data element of the data object on an interface, the write request including an identifier of the first data element, a second data element, and an identifier of the second format; and converting the second data element to the first data element for storage in a memory using a conversion function in a conversion data structure, the conversion function being located based on the identifier of the second format and the identifier of the same data element in the write request.

[0135] In Example 29, the subject matter of Example 28, wherein the identifier of the first data element comprises a memory address of the first data element.

[0136] In Example 30, according to the subject matter of any of Examples 28-29, the identifier of the first data element comprises a base memory address of a data object of the first format in the memory and an offset relative to the base memory address of the first data element.

[0137] In Example 31, the subject matter of any of Examples 28-30, wherein the cache coherence data structure of the data object includes an entry corresponding to the first data element, and wherein the entry for the first data element is marked as valid after the write request is completed.

[0138] In example 32, according to the subject matter of example 31, wherein the entry for the first data element is marked as invalid when exclusive access to the first data element is granted to another device.

[0139] In Example 33, the subject matter of any of Examples 27 to 32, wherein providing access to a data object in a second format comprises: receiving a read request on an interface, the read request comprising an identification of a second data element; converting a first data element from a memory to a second data element using a conversion function identified in a conversion data structure; and communicating a response to the read request on the interface, the response comprising the second data element.

[0140] In Example 34, according to the subject matter described in any of Examples 27 to 33, operations include: allocating second space in the memory for a second version of the data object in a second format based on a second base memory address and a second size provided in an allocation request or in a second allocation request; and converting data elements in the first version of the data object into corresponding data elements in the second version of the data object using a conversion function identified in a conversion data structure.

[0141] In Example 35, according to the subject matter of Example 34, providing access to a data object in a second format includes: receiving a read request on an interface, the read request including an identification of a first data element and specifying a response in a second format; retrieving a second data element from a second version of the data object in a memory based on a mapping in a mapping data structure, the mapping providing a location in the memory from the first data element to the second data element; and communicating a response to the read request on the interface, the response including the second data element.

[0142] In Example 36, the subject matter of any of Examples 27-35, wherein the processing circuitry is a processor, and wherein the conversion function is software executing on the processor.

[0143] In Example 37, according to the subject matter of Example 36, the identification of the conversion function is an address of the code of the conversion function in memory.

[0144] In Example 38, according to the subject matter of any of Examples 36-37, the identification of the conversion function is a code of the conversion function.

[0145] In Example 39, the subject matter of any of Examples 27-38, wherein the interface complies with the Compute Express Link (CXL) family of standards.

[0146] Example 40 is a system for multi-format data objects in a memory, the system comprising: a component for receiving an allocation request for a data object at an interface of a memory device, the data object comprising a set of data elements, the allocation request comprising corresponding details of a set of formats of the data object, the details of a first format in the set of formats comprising: a basic memory address; a size; a mapping between a first data element of the data object in the first format and a second data element in a second format in the set of formats, the first data element and the second data element representing the same data element; and an identifier of a conversion function configured to convert the first data element to the second data element; a component for allocating space in a memory of the memory device for a first version of the data object in the first format based on the basic memory address and size in the allocation request; a component for storing the mapping in a mapping data structure corresponding to the data object; a component for storing the identifier of the conversion function in a conversion data structure corresponding to the data object; and a component for providing access to a data object in a second format from a data object in the first format in the memory based on the mapping data structure or the conversion data structure, the second format comprising the second data element.

[0147] In Example 41, according to the subject matter of Example 40, the means for providing access to a data object in a second format includes: means for receiving a write request for the same data element of the data object on an interface, the write request including an identifier of the first data element, a second data element, and an identifier of the second format; and means for converting the second data element to the first data element for storage in a memory using a conversion function in a conversion data structure, the conversion function being located based on the identifier of the second format and the identifier of the same data element in the write request.

[0148] In Example 42, the subject matter of Example 41, wherein the identifier of the first data element comprises a memory address of the first data element.

[0149] In Example 43, according to the subject matter of any of Examples 41-42, the identifier of the first data element comprises a base memory address of a data object of the first format in the memory and an offset relative to the base memory address of the first data element.

[0150] In Example 44, the subject matter of any of Examples 41 to 43, wherein a cache coherent data structure of the data object includes an entry corresponding to the first data element, and wherein the entry for the first data element is marked as valid after the write request is completed.

[0151] In Example 45, according to the subject matter of Example 44, wherein the entry for the first data element is marked as invalid when exclusive access to the first data element is granted to another device.

[0152] In Example 46, the subject matter of any of Examples 40 to 45, wherein the means for providing access to a data object in a second format comprises: means for receiving a read request on an interface, the read request comprising an identification of a second data element; means for converting a first data element from a memory to a second data element using a conversion function identified in a conversion data structure; and means for communicating a response to the read request on the interface, the response comprising the second data element.

[0153] In Example 47, the subject matter described in any one of Examples 40 to 46 includes: a component for allocating a second space in a memory for a second version of a data object in a second format based on a second base memory address and a second size provided in an allocation request or in a second allocation request; and a component for converting data elements in a first version of the data object into corresponding data elements in a second version of the data object using a conversion function identified in a conversion data structure.

[0154] In Example 48, according to the subject matter of Example 47, the means for providing access to a data object in a second format includes: means for receiving a read request on an interface, the read request including an identification of a first data element and specifying a response in a second format; means for retrieving the second data element from a second version of the data object in a memory based on a mapping in a mapping data structure, the mapping providing a location in the memory from the first data element to the second data element; and means for communicating a response to the read request on the interface, the response including the second data element.

[0155] In Example 49, the subject matter of any of Examples 40 to 48, wherein the memory device includes a processor, and wherein the conversion function is software executed on the processor.

[0156] In example 50, according to the subject matter of example 49, the identification of the conversion function is an address of the code of the conversion function in memory.

[0157] In Example 51, according to the subject matter of any of Examples 49 to 50, the identifier of the conversion function is a code of the conversion function.

[0158] In example 52, the subject matter of any of examples 40 to 51, wherein the interface complies with the Compute Express Link (CXL) family of standards.

[0159] Example 53 is at least one machine-readable medium comprising instructions that, when executed by processing circuitry, cause the processing circuitry to perform operations to implement any of Examples 1-52.

[0160] Example 54 is an apparatus comprising means for implementing any of Examples 1-52.

[0161] Example 55 is a system for implementing any one of Examples 1 to 52.

[0162] Example 56 is a method for implementing any one of Examples 1-52.

[0163] The above detailed description includes reference to the accompanying drawings, which form a part of the detailed description. The drawings illustrate specific embodiments that can be put into practice by means of illustration. These embodiments are also referred to as "examples" in this article. Such examples may include elements other than those shown or described. However, the inventors also consider examples in which only those elements shown or described are provided. In addition, the inventors also consider examples (or one or more aspects thereof) of any combination or arrangement of those elements shown or described with respect to a specific example (or one or more aspects thereof) or with respect to other examples (or one or more aspects thereof) shown or described herein.

[0164] All publications, patents, and patent documents referenced in this document are incorporated herein by reference in their entirety, as if individually incorporated by reference. In the event of inconsistent usages between this document and those documents incorporated by reference, the usage in the incorporated reference(s) should be considered supplementary to that of this document; for irreconcilable inconsistencies, the usage in this document controls.

[0165] In this document, as is common in patent documents, the term "a" or "an" is used to include one or more than one, which is independent of any other examples or usages of "at least one" or "one or more". In this document, the term "or" is used to refer to a non-exclusive or, so that unless otherwise indicated, "A or B" includes "A but not B", "B but not A" and "A and B". In the appended claims, the terms "including" and "in which" are used as concise English equivalents of the corresponding terms "comprising" and "wherein". In addition, in the following claims, the terms "including" and "comprising" are open-ended, that is, systems, devices, articles or processes that include elements other than those listed after such terms in the claims are still considered to be within the scope of the claims. In addition, in the following claims, the terms "first", "second", and "third", etc. are used only as labels and are not intended to impose numerical requirements on their objects.

[0166] The above description is intended to be illustrative and not restrictive. For example, the examples described above (or one or more aspects thereof) may be used in combination with each other. For example, a person of ordinary skill in the art may use other embodiments after consulting the above description. The abstract is to allow the reader to quickly determine the nature of the technical disclosure, and is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the above specific embodiments, various features may be grouped together to simplify the present disclosure. This situation should not be interpreted as an expectation that unclaimed public features are necessary for any claim. On the contrary, the subject matter of the present invention may be less than all the features of a specific disclosed embodiment. Therefore, the attached claims are hereby incorporated into the specific embodiments, wherein each claim is taken as a separate embodiment in itself. The scope of the embodiment should be determined by reference to the attached claims and the full scope of equivalents granted by such claims.

Claims

1. An apparatus for implementing a multi-format data object in a memory, the apparatus comprising: an interface configured to communicate with an external entity; and A processing circuit system configured to: receiving at the interface a request for allocation of a data object, the data object comprising a set of data elements, the allocation request comprising respective details of a set of formats of the data object; allocating space for a first version of the data object in the first format in a memory managed by the device based on details of the first format in the allocation request; storing a mapping of the details from the first format in a mapping data structure corresponding to the data object; storing an identification of a conversion function of the detail from the first format in a conversion data structure corresponding to the data object; as well as Access to the data object in a second format is provided from the data object in the first format in the memory based on the mapping data structure or the translation data structure.

2. The apparatus of claim 1 , wherein to provide access to the data object in the second format, the processing circuitry is configured to: receiving, on the interface, a write request for the same data element of the data object, the write request comprising: an identifier of a first data element in said first version of said data object; The second data element; and an identifier in the second format; and The second data element is converted to the first data element for storage in the memory using the conversion function in the conversion data structure, the conversion function being located based on the identification of the second format in the write request and the identifier of the same data element.

3. The apparatus of claim 2, wherein a cache coherence data structure of the data object includes an entry corresponding to the first data element, and wherein the entry for the first data element is marked as valid after the write request is completed. 4 . The apparatus of claim 3 , wherein the entry for the first data element is marked as invalid when exclusive access to the first data element is granted to another apparatus.

5. The apparatus of claim 1 , wherein to provide access to the data object in the second format, the processing circuitry is configured to: receiving a read request on the interface, the read request including an identification of a second data element; converting a first data element in the first version of the data object from the memory to the second data element using the conversion function identified in the conversion data structure; as well as A response to the read request is communicated over the interface, the response including the second data element.

6. The apparatus of claim 1 , wherein the processing circuitry is configured to: allocating second space in memory for a second version of the data object in the second format based on a second base memory address and a second size provided in the allocation request or in a second allocation request; and Data elements in the first version of the data object are converted to corresponding data elements in the second version of the data object using the conversion function identified in the conversion data structure.

7. The apparatus of claim 6, wherein to provide access to the data object in the second format, the processing circuitry is configured to: receiving, on the interface, a read request including an identification of a first data element in the first version of the data object and specifying a response in the second format; retrieving a second data element from the second version of the data object in the memory based on a mapping in the mapping data structure, the mapping providing a location in memory from the first data element to the second data element; as well as A response to the read request is communicated over the interface, the response including the second data element.

8. The apparatus of claim 1, wherein the interface complies with the Compute Express Link (CXL) series standard.

9. A method for storing multi-format data objects in a memory, the method comprising: receiving, at an interface of a memory device, an allocation request for a data object, the data object comprising a set of data elements, the allocation request comprising respective details of a set of formats for the data object; allocating, by circuitry of the memory device, space in a memory of the memory device for a first version of the data object in the first format based on details of the first format in the allocation request; storing a mapping of the details from the first format in a mapping data structure corresponding to the data object; storing an identification of a conversion function of the detail from the first format in a conversion data structure corresponding to the data object; as well as Access to the data object in a second format is provided from the data object in the first format in the memory based on the mapping data structure or the translation data structure.

10. The method of claim 9, wherein providing access to the data object in the second format comprises: receiving, on the interface, a write request for the same data element of the data object, the write request comprising: an identifier of a first data element in said first version of said data object; The second data element; and an identifier in the second format; and The second data element is converted, by the circuitry, to the first data element for storage in the memory using the conversion function in the conversion data structure, the conversion function being located based on the identification of the second format in the write request and the identifier of the same data element.

11. The method of claim 10, wherein a cache coherence data structure of the data object includes an entry corresponding to the first data element, and wherein the entry for the first data element is marked as valid after the write request is completed.

12. The method of claim 11, wherein the entry for the first data element is marked as invalid when exclusive access to the first data element is granted to another device.

13. A machine-readable medium comprising instructions to implement a multi-format data object in a memory, the instructions, when executed by processing circuitry of a device, causing the device to perform operations comprising: receiving, at an interface of a memory device, an allocation request for a data object, the data object comprising a set of data elements, the allocation request comprising respective details of a set of formats for the data object; allocating, by circuitry of the memory device, space in a memory of the memory device for a first version of the data object in the first format based on details of the first format in the allocation request; storing a mapping of the details from the first format in a mapping data structure corresponding to the data object; storing an identification of a conversion function of the detail from the first format in a conversion data structure corresponding to the data object; as well as Access to the data object in a second format is provided from the data object in the first format in the memory based on the mapping data structure or the translation data structure.

14. The machine-readable medium of claim 13, wherein providing access to the data object in the second format comprises: receiving, on the interface, a write request for the same data element of the data object, the write request comprising: an identifier of a first data element in said first version of said data object; The second data element; and an identifier in the second format; and The second data element is converted, by the circuitry, to the first data element for storage in the memory using the conversion function in the conversion data structure, the conversion function being located based on the identification of the second format in the write request and the identifier of the same data element.

15. The machine-readable medium of claim 14, wherein a cache coherence data structure of the data object includes an entry corresponding to the first data element, and wherein the entry for the first data element is marked valid after the write request is completed.

16. The machine-readable medium of claim 15, wherein the entry for the first data element is marked as invalid when exclusive access to the first data element is granted to another device.

17. The machine-readable medium of claim 13, wherein providing access to the data object in the second format comprises: receiving a read request on the interface, the read request including an identification of a second data element; converting a first data element in the first version of the data object from the memory to the second data element using the conversion function identified in the conversion data structure; and A response to the read request is communicated over the interface, the response including the second data element.

18. The machine-readable medium of claim 13, wherein the operations comprise: allocating second space in memory for a second version of the data object in the second format based on a second base memory address and a second size provided in the allocation request or in a second allocation request; as well as Data elements in the first version of the data object are converted to corresponding data elements in the second version of the data object using the conversion function identified in the conversion data structure.

19. The machine-readable medium of claim 18, wherein providing access to the data object in the second format comprises: receiving, on the interface, a read request including an identification of a first data element in the first version of the data object and specifying a response in the second format; retrieving a second data element from the second version of the data object in the memory based on a mapping in the mapping data structure, the mapping providing a location in memory from the first data element to the second data element; as well as A response to the read request is communicated over the interface, the response including the second data element.

20. The machine-readable medium of claim 13, wherein the interface complies with the Compute Express Link (CXL) family of standards.

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