Truncation resolution for time slice calculations using array of memory cells for multiplication and accumulation

Abstract

The disclosure relates to a memory subsystem configured to perform multiplication and accumulation operations using truncated output. For example, a voltage may be applied to a memory cell storing a weight according to a bit slice having a slice weight in an input. Resolution control may be applied to an analog-to-digital converter coupled to a line having a current derived by the memory cell in response to the voltage according to the slice weights. The analog-to-digital converter may measure at least one first bit of a quantity representing a magnitude of the current in the line to provide a truncated output, and control measurement of at least one second bit skipping the quantity according to the resolution. Summing truncated outputs resulting from the bit slices from the input may provide an approximation result of a sum of elements in the input weighted by the weights.

Description

[0001] Related Applications

[0002] This application claims priority to provisional U.S. patent application serial number 63 / 519,529, filed on August 14, 2023, the entire disclosure of which is hereby incorporated by reference herein. Technical Field

[0003] At least some embodiments disclosed herein relate generally to computations of multiply and accumulate, and more particularly, but not limited to, computations of multiply and accumulate implemented in a memory array. Background Art

[0004] Many techniques have been developed to speed up the calculation of multiplication and accumulation. For example, multiple sets of logic circuits can be configured into an array to perform multiplication and accumulation in parallel to speed up the multiplication and accumulation operations. For example, a memory subsystem can use a memristor crossbar switch or array to speed up the multiplication and accumulation operations in the electrical domain.

[0005] The memory subsystem may include one or more memory devices that store data. For example, the memory devices may be non-volatile memory devices and volatile memory devices. In general, the host system may utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the invention BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings in which like reference numerals indicate similar elements.

[0007] Figure 1 A technique for time-sliced ​​computation with truncated resolution for multiply-and-accumulate operations is shown according to one embodiment.

[0008] Figure 2 Truncation of slices of results of a multiply-and-accumulate operation according to one embodiment is illustrated.

[0009] Figure 3 A computation is shown in which a column of weight bits is multiplied by a column of input bits to provide an accumulated result according to one embodiment.

[0010] Figure 4 The computation of a column of multi-bit weights multiplied by a column of input bits to provide an accumulated result is shown according to one embodiment.

[0011] Figure 5 A computation is shown in which a list of multi-bit weights is multiplied by a list of multi-bit inputs to provide an accumulated result, according to one embodiment.

[0012] Figure 6An example computing system is shown having a memory subsystem configured to perform multiply and accumulate operations according to one embodiment.

[0013] Figure 7 A method of performing a multiplication and accumulation operation according to one embodiment is shown. DETAILED DESCRIPTION

[0014] Multiplication and accumulation operations that apply weights to inputs can be implemented by programming memory cells in the array to have states that represent the weights. When a voltage representing the input is applied to a word line of the array, the programmed memory cell can output a current that represents the result of multiplying the input by the corresponding weight. The bit lines of the array can collect and sum the output currents. An analog-to-digital converter can be used to measure the magnitude of the current in the bit line and produce a digital output that represents the result of the multiplication and accumulation operation.

[0015] The sum of products between the weight list and the corresponding input list can be configured as the sum of results from the time slice calculation. Each result from the time slice calculation can provide a partial sum of products between the weight list and the corresponding input list. Adding the partial sums can provide the sum of products between the weight list and the corresponding input list.

[0016] For example, the bits of the input may be divided into slices according to the bit significance. Each slice may include one or more bits from the input with a predetermined significance level. Instead of applying the input to the weight, a slice of the significant bits from the input may be applied to the weight as an input slice. The bit slices may be applied one at a time to the memory cells storing the weights to generate partial sums, each partial sum corresponding to the sum of the products between the weight list and the corresponding bit slices shifted according to the significance of the slice. The sum of the products between the weight list and the corresponding input list may be obtained by adding the partial sums using a digital circuit.

[0017] For example, the input pattern may be presented as a digital bit stream in a serial-parallel manner to a memory array storing weights, where one bit from each input is applied sequentially at a time, and bits from multiple inputs are applied to the memory array in parallel. At each such time slice, the same significant bit level of each input pattern is presented. Also, at each such slice, a multiplication and accumulation operation of applying the weights is performed to produce a partial sum of products. After all slices are presented, all partial sums are calculated, which can then be combined by considering the significance of each slice to produce a sum of products.

[0018] Each time slice calculation may be configured to be completed with a constant slice duration; and the analog-to-digital converter may be configured to have a constant conversion resolution when generating its digital output for a slice.

[0019] For example, an 8-bit input vector may be applied as 8 time slices, each time slice being configured to have a duration sufficient to support multiplication with weights, analog-to-digital conversion, and the like.

[0020] At least some embodiments disclosed herein are configured to reduce the time used to perform time slice calculations.The conversion resolution of different time slices can be reduced to produce truncated partial sums according to the effectiveness of the time slices.

[0021] For example, the resolution of the slices may be chosen such that high-significance partial sums are captured at a high resolution, while low-significance partial sums are captured at a lower resolution.

[0022] The reduced or truncated resolution in the analog-to-digital conversion allows the corresponding slice period to be shortened. Additionally, the array settling time allotted for the less significant slices can be shorter than for the more significant slices. Thus, reducing the resolution of the less significant portion of the sum can not only shorten the time required to perform the analog-to-digital conversion, but also shorten the time it takes for the current in the array to settle for accurate measurement.

[0023] When combining the results from the time slices after digitization, the carry components from the slices can be ignored. The overall effect is to produce a combination of truncated partial sums of the products.

[0024] In applications such as computations of artificial neural networks, the magnitude of the error produced by the reduction in resolution of at least some time slices may be negligible relative to other sources of error. The benefits of the approximation may be significant in terms of total computation time, energy expended to perform the computation, and / or area and complexity of circuits configured to implement the computation, while still achieving a desired level of accuracy.

[0025] Figure 1 A technique for time-sliced ​​computation with truncated resolution for multiply-and-accumulate operations is shown according to one embodiment.

[0026] exist Figure 1 , a list of weights 111, 113, ..., 115 may be used to weight a corresponding list of elements of input 130; and the weighted elements of input 130 may be summed to provide a result of a multiplication and accumulation operation applied to the weights 111, 113, ..., 115 and the corresponding elements in input 130. The result of the multiplication and accumulation operation is equal to the sum of the elements in input 130 weighted according to the corresponding weights 111, 113, ..., 115.

[0027] In time-slicing computation, the significant bits of the input elements are divided into bit slices 131, 133, ..., 135. Each bit slice has a list of bit segments of the same significance as each of the elements from the input 103.

[0028] For example, input bit slice 133 has a list of inputs 101, 103, ..., 105. Input 101 is a bit segment of a corresponding element from input 130 to be weighted by weight 111; input 103 is a bit segment of the same significance from a corresponding element from input 103 to be weighted by weight 113; and input 105 is a bit segment of the same significance from a corresponding element from the input to be weighted by weight 115.

[0029] The input bit slices 131, 133, ..., 135 have corresponding slice weights 141, 143, ..., 145 according to the significance level of the slices 131, 133, ..., 135 in the input 130. The slice weights 141, 143, ..., 145 correspond to the number of bitwise shifts that can be applied to move the corresponding bit slice (e.g., 131, 133, ...) to the significance level of the least significant input bit slice 135.

[0030] The input bit slices 131, 133, ..., 135 can be applied to the weights 111, 113, ..., 115 one slice at a time in the same manner as the least significant input bit slice 135 is applied. Each of the input bit slices 131, 133, ..., 135 has a resolution (or count of significant bits) less than the input 130.

[0031] Time-sliced ​​computation allows the input 130 to be applied one slice at a time at a reduced resolution of slices 131, 133, ..., 135 to obtain partial sums 161, 163, ..., 165 over a period of time. The partial sums 161, 163, ..., 165 can then be combined when summing to produce a sum in which the elements of the input 130 are weighted by the corresponding weights 111, 113, ..., 115.

[0032] When input slice 133 is applied to weights 111, 113, ..., 115, inputs 101, 103, ..., 105 are multiplied by weights 111, 113, ..., 115, respectively, to produce multiplication results 121, 123, ..., 125.

[0033] In some implementations, weights 111, 113, ..., 115 are implemented using a column of memory cells programmed to have states representing weights 111, 113, ..., 115; inputs 101, 103, ..., 105 are applied as voltages driven onto word lines connected to the memory cells; and multiplication results 121, 123, ..., 125 are represented by currents through the memory cells and collected in the bit lines for accumulation operations. An analog-to-digital converter may be connected to the bit lines to measure the magnitude of the bit line current corresponding to the sum of the multiplication results 121, 123, ..., 125.

[0034] The resolution of the operation of accumulating 151 the multiplication results 121, 123, ..., 125 and generating a digital result (e.g., via an analog-to-digital converter) may be controlled by the slice weights 143 of the input bit slices 133. When the resolution is reduced according to the input bit weights 143, the digital result generated by the analog-to-digital converter represents a truncated output 153 having a reduced number of significant bits. Reducing the resolution may reduce the duration allotted for generating the output 153. For example, reducing the resolution may allow a shortened period of time for the bit line current to stabilize or become stable for measurement by the analog-to-digital converter, and allow the analog-to-digital converter to complete the measurement in a shorter period of time.

[0035] For example, when a larger level of significance of the input bit slice (e.g., 133) is applied, the truncated output 153 may truncate fewer bits to reduce the loss of accuracy; and when a smaller level of significance of the input bit slice is applied, the truncated output may truncate more bits to shorten the duration of the computation without causing a significant loss of accuracy. Examples of resolution truncation are shown in Figure 2 For example, the bits discarded from the sum of the multiplication results 121, 123, ..., 125 may be the corresponding least significant bits to be ignored in the result of the sum of the elements in the input 130 weighted by the corresponding weights 111, 113, ..., 115.

[0036] Shift 155 operation may be applied to truncated output 153 according to slice weights 143 to produce partial sum 163 corresponding to the sum of input bit slices 133 weighted by weights 111, 113, ..., 115. Shift 155 operation replaces discarded bits in truncated output 153 without bits having value 0.

[0037] The operation of adding 157 the partial sums 161, 163, ..., 165 obtained by the input bit slices 131, 133, ..., 135, respectively, can provide an approximation result 160 of the sum of the elements in the input 130 weighted by the weights 111, 113, ..., 115, respectively. When a predetermined number of least significant bits in the approximation result 160 are to be ignored (or discarded to retain the remaining most significant bits), the truncated output 153 can be configured to discard the bits corresponding to the same predetermined number of least significant bits in the partial sum 163. Therefore, the significant bits of the truncated output (e.g., 153) are aligned by truncation according to the slice weights (e.g., 143) and are therefore ready for summation without the need for a shift 155 operation. The truncated output (e.g., 153) generated by the input bit slices 131, 133, ..., 135 can reduce the resolution summation without applying the shift 155 operation, which arrangement can reduce the size and / or complexity of the circuit used to calculate the sum of the partial sums 161, 163, ..., 165.

[0038] Since the partial sums 161, 163, ..., 165 are calculated using truncation, the approximation result 160 calculated according to the operation of adding 157 the partial sums 161, 163, ..., 165 may differ from the exact sum of the elements of the input 130 weighted by the corresponding weights 111, 113, ..., 115. The difference (and therefore the approximation error in the approximation result 160) is typically a small fraction of the exact sum of the elements of the input 130 weighted by the weights 111, 113, ..., 115, respectively. In many applications, such as in the calculation of artificial neural networks, the difference (and therefore the approximation error) may be negligible.

[0039] Figure 2 Truncation of slices of results of a multiply-and-accumulate operation according to one embodiment is illustrated.

[0040] exist Figure 2 , the sum of the elements of the input 130 weighted by the corresponding weights 110 is configured to be truncated by discarding a predetermined number of least significant bits 185, ..., 187 to retain bits 181, ..., 183 as a truncated result 180. Therefore, the approximation result 160 of the sum can be represented using bits 181, ..., 183 of the truncated result 180 (without the discarded bits 195). The approximation result 160 is equal to the truncated result 180 shifted left according to the scaling factor 190 to fill the discarded bits 195 with 0. The scaling factor 190 corresponds to the predetermined number of least significant bits 185, ..., 187 that are discarded.

[0041] like Figure 1 , a sum of elements of input 130 weighted by corresponding weights 110 may be calculated based on partial sums (e.g., 161, 163, ..., 165) obtained by applying weights 110 to input bit slices (e.g., 131, 133, ..., 135).

[0042] For example, a typical input bit slice 191 with a slice weight 193 (corresponding to the significance level of the input bit slice 191 in the input 130 ) may be applied to the weight 110 to produce the accumulated result 140 .

[0043] Input bit slice 191 (eg, Figure 1 133) in the elements according to the corresponding weights 110 (for example, Figure 1 , 111, 113, ..., 115) in the multiplication result 121, 123, ..., 125) are weighted and provide the accumulation result 140. The full resolution accumulation result 140 (e.g., as the exact sum of the multiplication results 121, 123, ..., 125) has bits 171, ..., 173, 175, ..., 177, including the most significant bit 171 and the least significant bit 177.

[0044] The operation of shifting 155 according to the slice weight 193 of the input bit slice 191 can be applied to the accumulated result 140 to produce a partial sum 120 having bits 171, ..., 173, 175, ..., 177 followed by a number of bits 179 having the value zero.

[0045] exist Figure 2 193, the same predetermined number of least significant bits that are discarded from the sum of the elements of the input 130 weighted by the corresponding weights 110 are also discarded from the partial sum 120. Therefore, bits 175, ..., 177 can be discarded from the accumulated result 140 to obtain the truncated output 150 produced by the input bit slice 191 without applying the shift 155 operation. The count of bits 175, ..., 177 discarded from the accumulated result corresponds to the difference between the predetermined number of discarded bits 195 and the number of bit-by-bit shifts 155 to be applied according to the slice weight 193.

[0046] The truncated outputs (eg, 150 ) generated by the input bit slices (eg, 191 ) of the input 130 may be summed to compute the truncated result 180 without the discarded bits 195 .

[0047] In general, the sum of the truncated output (e.g., 150) of the input bit slice (e.g., 191) of the input 130 may be different from the truncated result 180 of the sum of the elements from the input 130 weighted by the corresponding weights 110. In some examples, the sum of the discarded bits of the partial sum (e.g., 120, such as bits 175, ..., 177) may produce a carry component, which will be carried into one or more least significant bits (e.g., 183) of the truncated result 180. By discarding the bits (e.g., 175, ..., 177) from the partial sum 120, the carry component is also discarded. Therefore, by truncating the bits (e.g., 175, ..., 177) before summing the partial sum (e.g., 120) of the input bit slice (e.g., 191), there may be an error of missing the carry component.

[0048] The maximum magnitude of the carry component corresponds to bits (e.g., 175, ..., 177) discarded from the partial sum (e.g., 120) that each have a value of 1. The carry component is typically small when compared to the magnitude of the truncated result 180. Therefore, the accumulation 151 operation can be configured to measure bits 171, ..., 173 of the truncated output 150 without measuring the discarded bits (e.g., 175, ..., 177) of the partial sum 120.

[0049] Using a truncated output (eg, 150) has advantages.

[0050] For example, when implementing application of weight 110 via memory cells in an array, skipping the measurement of bits 175, ..., 177 may allow a shortened period to be used to stabilize the bit line current.

[0051] Additionally, skipping the measurement of bits 175 , . . . , 177 may reduce the time the analog-to-digital converter uses in generating the truncated output 150 .

[0052] Additionally, reducing the resolution of computing the truncated result 180 by skipping operations on a predetermined number of least significant bits (e.g., corresponding to discarded bits 195) can reduce the size and complexity of the circuitry configured to add the partial sums (e.g., 120). Since no operations are performed on the discarded bits (e.g., 175, ..., 177), the circuitry can be configured to skip the shift 155 operation and sum the truncated outputs (e.g., 150) to obtain an approximation corresponding to the truncated result 180 minus the carry component.

[0053] Figure 3 A calculation of a column of weight bits multiplied by a column of input bits to provide an accumulated result is shown according to one embodiment. For example, Figure 1 The weights 111, 113, ..., 115 in can be Figure 3 The manner described in is configured to perform multiplication and accumulation operations applied to input 130 and weights 111, 113, ..., 115.

[0054] exist Figure 3 , a column of synaptic memory cells 207, 217, ..., 227 (eg, in a memory cell array of an analog computing module) may be programmed in a synaptic mode to have threshold voltages at levels representing a weight value indicative of each memory cell storing one bit.

[0055] The column of memory cells 207, 217, ..., 227 programmed in synaptic mode can be read in synaptic mode, during which the voltage drivers 203, 213, ..., 223 are configured to concurrently apply voltages 205, 215, ..., 225 to the memory cells 207, 217, ..., 227, respectively, based on the input bits 201, 211, ..., 221 they receive.

[0056] For example, when the input bit 201 has a value of 1, the voltage driver 203 applies a predetermined read voltage as the voltage 205, thereby causing: if the memory cell 207 has a threshold voltage programmed at a lower level below the predetermined read voltage, then the memory cell 207 outputs a predetermined amount of current as its output current 209 to represent a stored weight of 1, or if the memory cell 207 has a threshold voltage programmed at a higher level above the predetermined read voltage, then the memory cell 207 outputs a negligible amount of current as its output current 209 to represent a stored weight of 0. However, when the input bit 201 has a value of 0, the voltage driver 203 applies a voltage of a lower level (e.g., 0) below the threshold voltage as the voltage 205 (e.g., no predetermined read voltage is applied), thereby causing the memory cell 207 to output a negligible amount of current at its output current 209, regardless of the weight stored in the memory cell 207. Therefore, the output current 209, which is a multiple of the predetermined amount of current, represents the result of multiplying the weight bit stored in the memory cell 207 by the input bit 201.

[0057] Similarly, current 219 passing through memory cell 217 as a multiple of a predetermined amount of current represents the result of multiplying the weight bit stored in memory cell 217 by input bit 211; and current 229 passing through memory cell 227 as a multiple of a predetermined amount of current represents the result of multiplying the weight bit stored in memory cell 227 by input bit 221.

[0058] The output currents 209, 219, ..., and 229 of the memory cells 207, 217, ..., 227 are connected to a common line 241 (e.g., a bit line) for summing. The summed current 231 is compared with a unit current 232 (which is equal to a predetermined amount of current) by a digitizer 233 of an analog-to-digital converter 245 to determine a digital result 237 of the sum of the columns of weight bits respectively stored in the memory cells 207, 217, ..., 227 multiplied by the columns of input bits 201, 211, ..., 221 and the multiplication results.

[0059] The sum of the negligible amounts of current from the memory cells connected to line 241 is less than the unit current 232 (e.g., a predetermined amount of current). Therefore, the presence of the negligible amounts of current from the memory cells does not alter the result 237 and is negligible in the operation of the analog-to-digital converter 245.

[0060] exist Figure 3, voltages 205, 215, ..., 225 applied to memory cells 207, 217, ..., 227 represent digitized input bits 201, 211, ..., 221; memory cells 207, 217, ..., 227 are programmed to store digitized weight bits; and currents 209, 219, ..., 229 represent digitized results. Thus, memory cells 207, 217, ..., 227 do not act as memristors that convert analog voltages into analog currents based on their linear resistance over a voltage range; and the operating principles of the memory cells when calculating multiplications are fundamentally different from the operating principles of a memristor crossbar. When a memristor crossbar is used, a conventional digital-to-analog converter is used to generate an input voltage proportional to the input to the rows of the memristor crossbar. When using Figure 3 When the technology is used, such a digital-to-analog converter can be eliminated; and the operation of the digitizer 233 to produce the result 237 can be greatly simplified. The result 237 is an integer not greater than the count of the memory cells 207, 217, ..., 227 connected to the line 241. The digitized form of the output current 209, 219, ..., 229 can improve the accuracy and reliability of the calculations performed using the memory cells 207, 217, ..., 227.

[0061] exist Figure 3 2, analog-to-digital converter 245 has an input configured to receive a resolution control 239. Resolution control 239 may be used to control the truncation of bits in the digital representation of the current magnitude in line 241.

[0062] For example, the resolution control 239 may be generated based on the slice weights 143 of the bit slices represented by the input bits 201 , 211 , . . . , 221 .

[0063] For example, when according to Figure 2 When resolution control 239 is applied to slice weights 193 in , the measurement of accumulated result 140 represented by the magnitude of the current in line 241 can be configured to skip the measurement of bits 175 , . . . , 177 and produce a truncated output 150 as result 237 .

[0064] Generally speaking, the weights involved in the multiplication and accumulation operations may be more than one bit. Multiple columns of memory cells may be used to store different significant bits of the weights (e.g. Figure 4 ) to perform multiplication and accumulation operations.

[0065] Figure 3 The circuit described in can be viewed as a multiplier-accumulator unit configured to operate on a column of 1-bit weights and a column of 1-bit inputs. Multiple such circuits can be connected in parallel to implement a multiplier-accumulator unit to operate on a column of multi-bit weights and a column of 1-bit inputs, such as Figure 4 As described in .

[0066] Figure 3 The circuits described in can also be used to read data stored in memory cells 207, 217, ..., 227. For example, to read data or weights stored in memory cell 207, input bits 211, ..., 221 can be set to 0 to cause memory cells 217, ..., 227 to output a negligible amount of current into line 241 (e.g., as a bit line). Input bit 201 is set to 1 to cause voltage driver 203 to apply a predetermined read voltage. Thus, result 237 from digitizer 233 provides the data or weights stored in memory cell 207. Similarly, data or weights stored in memory cell 217 can be read by applying 1 as input bit 211 and applying 0 as the remaining input bits in the column; and data or weights stored in memory cell 227 can be read by applying 1 as input bit 221 and applying 0 as the other input bits in the column.

[0067] Generally speaking, Figure 3 The circuits illustrated in can be used to select any of the memory cells 207, 217, ..., 227 for reading or writing. A voltage driver (e.g., 203) can apply a programming voltage pulse to adjust the threshold voltage of the corresponding memory cell (e.g., 207) to erase data, store data or weights, etc.

[0068] Figure 4 The computation of a column of multi-bit weights multiplied by a column of input bits to provide an accumulated result is shown according to one embodiment.

[0069] For example, a row of memory cells 207, 206, ..., 208 may be used to implement the weight 250 having bits 257, 258, ..., 259. Figure 1 The weight in is 111 (or 113, or 115).

[0070] exist Figure 4 , the weight 250 in binary form has a most significant bit 257, a second most significant bit 258, ..., and a least significant bit 259. The significant bits 257, 258, ..., 259 may be stored in a number of rows of memory cells 207, 206, ..., 208 across a number of columns in an array 273 (e.g., in a memory cell array of an analog computing module). The significant bits 257, 258, ..., 259 of the weight 250 will be multiplied by the voltage driver 203 (e.g., as in Figure 3 ) An input bit 201 represented by a voltage 205 applied to a line 281 (eg, a word line).

[0071] Similarly, memory cells 217, 216, ..., 218 may be used to store the voltage to be multiplied by voltage driver 213 (e.g., as in Figure 3) is applied to line 282 (e.g., word line) The corresponding valid bit of the next weight (e.g., 113) of the next input bit 211 represented by the voltage 215 applied to line 282 (e.g., word line); and the memory cells 227, 226, ..., 228 can be used to store the corresponding valid bit to be multiplied by the voltage driver 223 (e.g., as in Figure 3 ) corresponds to the weight (e.g., 115) of the input bit 221 represented by the voltage 225 applied to the line 283 (e.g., the word line).

[0072] The most significant bit (e.g., 257) of the weight (e.g., 250) stored in the memory cell of the corresponding row in array 273 is multiplied by the input bits 201, 211, ..., 221 represented by voltages 205, 215, ..., 225 and then summed as current 231 in line 241 and digitized using digitizer 233 (as in Figure 3 ), to produce result 237 corresponding to the most significant bit of the weight.

[0073] Similarly, the second most significant bit (e.g., 258) of the weight (e.g., 250) stored in the memory cell of the corresponding row in array 273 is multiplied by the input bits 201, 211, ..., 221 represented by voltages 205, 215, ..., 225 and then summed as the current in line 242 and digitized to produce a result 236 corresponding to the second most significant bit.

[0074] Similarly, the least significant bit (e.g., 259) of the weight (e.g., 250) stored in the memory cell of the corresponding row in array 273 is multiplied by the input bits 201, 211, ..., 221 represented by voltages 205, 215, ..., 225 and then summed as the current in line 243 and digitized to produce a result 238 corresponding to the least significant bit.

[0075] The most significant bit may be left shifted by 1 bit to have the same weight as the second significant bit, and the second significant bit may be further left shifted by 1 bit to have the same weight as the next significant bit. Thus, the operation of left shift 247 by one bit may be applied to the result 237 generated by the multiplication and summation of the most significant bit (e.g., 257) of the weight (e.g., 250); and the addition operation 246 may be applied to the result of the operation of left shift 247 and the result 236 generated by the multiplication and summation of the second most significant bit (e.g., 258) of the weight (e.g., 250). The operation of left shift (e.g., 247, 249) may be used to apply the weights of the bits (e.g., 257, 258, ...) to sum using the addition (e.g., 246, ..., 248) operation to generate the result 251. Thus, the result 251 is equal to the weight column in the memory cell array 273 multiplied by the column of input bits 201, 211, ..., 221 and accumulating the multiplication results.

[0076] In some implementations, the memory cell can be programmed to output a multiple of the unit current 232 when a predetermined voltage is applied, and to output a negligible amount of current when the applied voltage is less than the predetermined voltage. Thus, a memory cell (e.g., 207) can be programmed to represent the value of a bit of a weight (e.g., 250) and its weight to another memory cell (e.g., 206).

[0077] For example, when the most significant bit 257 has a value of 1, the memory cell 207 is programmed to have a state such that when a predetermined voltage representing an input bit 201 having a value of 1 is applied to the memory cell 207, the memory cell 207 outputs a unit current of 2 times, so that the current magnitude of the bit line 241 has a bit weight built into the current generated by the memory cells 207, 217, ..., 227. Therefore, the currents in the bit lines 241 and 242 can be connected to a common line to be measured using the same analog-to-digital converter 245. This arrangement can reduce the number of analog-to-digital converters 245 configured to produce a digitized result (e.g., the truncated output 153).

[0078] In some implementations, a memory cell (e.g., 207) may be programmed to generate 4 times the unit current when a predetermined voltage representing an input bit 201 having a value of 1 is applied; and another memory cell (e.g., 206) may be programmed to generate 2 times the unit current when a predetermined voltage representing an input bit 201 having a value of 1 is applied. Thus, memory cells 207 and 206 may be programmed to store the most significant bit 257 and the second most significant bit 258 and the bit weight relative to another memory cell programmed to store the third most significant bit. Since the currents in the bit lines 241, 242 connected to memory cells 207 and 206 have built-in bit weights relative to the bit lines connected to the other memory cells, the three bit lines may be connected to a common line for accumulation and for measurement using the same analog-to-digital converter 245. Thus, the number of analog-to-digital converters 245 configured to produce a digitized result (e.g., truncated output 153) may be further reduced. Additionally, circuits configured to perform operations of left shift (eg, 247) and addition (eg, 246) may be reduced.

[0079] In some implementations, a memory cell (e.g., 207) can be programmed to output an amount of current that is a multiple of the unit current 232 for the value of a bit segment (e.g., 257 and 258) corresponding to a weight value (e.g., 250). Thus, a memory cell (e.g., 207) can be programmed to store a bit segment and thus reduce the number of memory cells configured to store a weight value (e.g., 250).

[0080] In general, the inputs involved in the multiplication and accumulation operations may be more than one bit. Several columns of input bits may be applied one column at a time to the weights stored in the memory cell array 273 to obtain a column of weights multiplied by a column of inputs and the results accumulated, such as Figure 5 As described in .

[0081] Figure 4 The circuit illustrated in can be used to read data stored in the memory cell array 273. For example, to read the data or weights 250 stored in the memory cells 207, 206, ..., 208, the input bits 211, ..., 221 can be set to 0 to cause the memory cells 217, 216, ..., 218, ..., 227, 226, ..., 228 to output a negligible amount of current into the lines 241, 242, ..., 243 (e.g., as bit lines). The input bit 201 is set to 1 to cause the voltage driver 203 to apply a predetermined read voltage as the voltage 205. Thus, the results 237, 236, ..., 238 from the digitizer (e.g., 233) connected to the lines 241, 242, ..., 243 provide the bits 257, 258, ..., 259 of the data or weights 250 stored in the row of the memory cells 207, 206, ..., 208. In addition, the result 251 calculated by the shift operations 247, 249, ... and the addition operations 246, ..., 248 provides a weight value 250 in binary form.

[0082] Generally speaking, Figure 4 The circuits described in can be used to select any row of the memory cell array 273 for reading. Optionally, different columns of the memory cell array 273 can be driven by different voltage drivers. Thus, the memory cells in a row (e.g., 207, 206, ..., 208) can be programmed to write data of weight 250 in parallel (e.g., for storing bits 257, 258, ..., 259).

[0083] Figure 5 A computation is shown in which a list of multi-bit weights is multiplied by a list of multi-bit inputs to provide an accumulated result, according to one embodiment.

[0084] exist Figure 5 , the valid bits of the input (eg, 280) are applied to the multiplier-accumulator unit 270 at multiple times T, T1, . . . , T2.

[0085] For example, the multi-bit input 280 may have a most significant bit 201 , a second most significant bit 202 , . . . , a least significant bit 204 .

[0086] At time T, an input bit slice 291 having the most significant bits 201, 211, ..., 221 of an input (e.g., 280) may be applied to a multiplier-accumulator unit 270 to obtain a result 251 of multiplying a weight (e.g., 250) stored in a memory cell array 273 by a column of bits 201, 211, ..., 221 and summing the multiplication results.

[0087] The result 251 may be a truncated output controlled using a resolution control 239 applied based on the slice weights of the most significant bits 201 , 211 , . . . , 221 .

[0088] For example, you can Figure 4 The multiplier-accumulator unit 270 is implemented in the manner described in . The multiplier-accumulator unit 270 has a voltage driver 271 connected to apply voltages 205, 215, ..., 225 representing input bits 201, 211, ..., 221. The multiplier-accumulator unit 270 has a voltage driver 271 connected to apply voltages 205, 215, ..., 225 representing input bits 201, 211, ..., 221. Figure 4 The multiplier-accumulator unit 270 has a digitizer 275 for converting the currents summed on lines 241, 242, ..., 243 for the columns of memory cells in the array 273 to output results 237, 236, ..., 238. The multiplier-accumulator unit 270 has a digitizer 275 connected to combine the column results 237, 236, ..., 238 to provide Figure 4 Shifter 277 and adder 279 of result 251 in. In some implementations, the logic circuits of multiplier-accumulator unit 270 (eg, shifter 277 and adder 279) are implemented as part of the inference logic circuitry of an analog computation module.

[0089] Similarly, at time T1, an input bit slice 293 having the second most significant bits 202, 212, ..., 222 of the input (e.g., 280) may be applied to the multiplier-accumulator unit 270 to obtain a result 253 of multiplying the weights (e.g., 250) stored in the memory cell array 273 by the vector of bits 202, 212, ..., 222 and summing the multiplication results.

[0090] Similarly, at time T2, an input bit slice 295 having the least significant bits 204, 214, ..., 224 of the input (e.g., 280) may be applied to the multiplier-accumulator unit 270 to obtain a result 255 of multiplying the weight (e.g., 250) stored in the memory cell array 273 by the vector of bits 202, 212, ..., 222 and summing the multiplication results.

[0091] For example, through Figure 5 The bit slices 291, 293, ..., 295 are implemented Figure 1Input bit slices 131, 133, ..., 135 in.

[0092] The operation of left shift 261 by one bit may be applied to the result 251 produced by the multiplication and summation of the most significant bits 201, 211, ..., 221 of the input (e.g., 280); and the addition operation 262 may be applied to the result of the left shift 261 operation and the result 253 produced by the multiplication and summation of the second most significant bits 202, 212, ..., 222 of the input (e.g., 280). The left shift (e.g., 261, 263) operation may be used to apply the weights of the bits (e.g., 201, 202, ...) to be summed using the addition (e.g., 262, ..., 264) operation to produce the result 267. Therefore, the result 267 is equal to the weights (e.g., 250) in the memory cell array 273 multiplied by the columns of the input (e.g., 280) respectively and then summed.

[0093] Alternatively, the results 251, 253, ..., 255 may be configured to truncate the output (e.g., 153) to have the same level of weight corresponding to the scaling factor 190 of the truncated result 180. Thus, the circuitry for performing the left shift 261, 263 may be eliminated; and the results 251, 253, ..., 255 may be summed to obtain the value corresponding to Figure 2 The truncated result in 180 is 267.

[0094] In some implementations, a current accumulator (e.g., a capacitor) is configured on a bit line (e.g., 241) to generate a parameter that is an integral of the bit line current over a period of time. The period of time may be configured according to the bit weight of the significant bit (e.g., 201). An analog-to-digital converter may be configured to measure the parameter generated using the current accumulator.

[0095] Optionally, the current generated in the bit line (e.g., 241) for consecutive bit slices (e.g., 291 and 293) can be accumulated in the current accumulator to be measured in one operation. Thus, consecutive bit slices (e.g., 291 and 293) can be combined and considered as one bit slice.

[0096] A plurality of multiplier-accumulator units 270 may be connected in parallel to operate on a matrix of weights multiplied by a column of multi-bit inputs at a series of time instants T, T1, ..., T2.

[0097] Optionally, the memory cells (e.g., 207, ..., 227) may be implemented using memristors, each having a substantially constant resistance value in a range of applied voltages. Thus, the resistance values ​​of the memristors may be programmed to represent weights 111, 113, ..., 115. An input slice (e.g., 191) having one or more valid bits for each element from input 130 may be applied as a voltage having a magnitude corresponding to the input in the slice (e.g., 191). An analog-to-digital converter 245 with a resolution control 239 may be used to measure the current through the memristors in the bit lines to produce a truncated output 153. Thus, the input slice (e.g., 191) may have one or more bits with the same level of significance for each element from input 130.

[0098] Figure 6 An example computing system is shown having a memory subsystem configured to perform multiply and accumulate operations according to one embodiment.

[0099] Figure 6 The example computing system of includes a host system 310 and a memory subsystem 301. An analog computing module (e.g., having memory units 207, 217, ..., 227 and an analog / digital converter 245 controlled via a resolution control 239, as in Figure 3 ) may be configured in the memory subsystem 301 or in the host system 310.

[0100] Memory subsystem 301 may include media such as one or more volatile memory devices (eg, memory device 321), one or more non-volatile memory devices (eg, memory device 323), or a combination of the like.

[0101] For example, the memory device 323 may include a memory unit 327 configured to store the weights 111, 113, ..., 115 (e.g., as Figure 4 273 in the array). The memory device 323 may include a voltage driver 333 configured to apply an input bit slice as Figure 3 The voltage drivers 203, 213, ..., 223 in the embodiment of the present invention, or Figure 5 271 in the memory cell 327. The memory device 323 may include an analog-to-digital converter (e.g., 245) having a resolution control 239. The local media controller 325 of the memory device 323 may include a time slice truncation manager 331 configured to adjust the resolution control 239 of the analog-to-digital converter (e.g., 245) according to the slice weights (e.g., 141, 143, ..., or 145) of the input bit slices (e.g., 131, 133, ..., or 135) applied to the memory cell 327 via the voltage driver 333.

[0102] The memory subsystem 301 may be a storage device, a memory module, or a mixture of storage devices and memory modules. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage devices (UFS) drives, secure digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0103] The computing system may be a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, drone, train, car, or other transportation vehicle), a device with Internet of Things (IoT) capabilities, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or a networked commercial device), or such a computing device that includes a memory and a processing device.

[0104] The computing system may include a host system 310 coupled to one or more memory subsystems 301 . Figure 6 An example of a host system 310 coupled to a memory subsystem 301 is illustrated. As used herein, "coupled to" or "coupled with" generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical connections, optical connections, magnetic connections, etc.

[0105] The host system 310 may include a processor chipset (e.g., processing device 311) and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., controller 313) (e.g., NVDIMM controller) and a storage protocol controller (e.g., PCIe controller, SATA controller). The host system 310 uses the memory subsystem 301 to, for example, write data to the memory subsystem 301 and read data from the memory subsystem 301.

[0106] The host system 310 may be coupled to the memory subsystem 301 via a physical host interface 309. Examples of the physical host interface 309 include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, a Fibre Channel, a Serial Attached SCSI (SAS) interface, a Double Data Rate (DDR) memory bus interface, a Small Computer System Interface (SCSI), a Dual In-line Memory Module (DIMM) interface (e.g., a DIMM slot interface supporting Double Data Rate (DDR)), an Open NAND Flash Interface (ONFI), a Double Data Rate (DDR) interface, a Low Power Double Data Rate (LPDDR) interface, or any other interface. The physical host interface 309 may be used to transfer data between the host system 310 and the memory subsystem 301. When the memory subsystem 301 is coupled to the host system 310 through a PCIe interface, the host system 310 may further utilize an NVM Express (NVMe) interface to access components (e.g., memory device 323). The physical host interface 309 may provide an interface for passing control, address, data, and other signals between the memory subsystem 301 and the host system 310 . Figure 6 Memory subsystem 301 is illustrated as an example. In general, host system 310 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0107] For example, the processing device 311 of the host system 310 may be a microprocessor, a central processing unit (CPU), a processing core of a processor, an execution unit, etc. In some examples, the controller 313 may be referred to as a memory controller, a memory management unit, and / or an initiator. In one example, the controller 313 controls communication via a bus coupled between the host system 310 and the memory subsystem 301. In general, the controller 313 may send commands or requests to the memory subsystem 301 for desired access to the memory devices 323, 321. The controller 313 may further include an interface circuit system for communicating with the memory subsystem 301. The interface circuit system may convert a response received from the memory subsystem 301 into information for the host system 310.

[0108] The controller 313 of the host system 310 may communicate with the controller 303 of the memory subsystem 301 to perform operations such as reading data, writing data, or erasing data at the memory devices 323, 321, and other such operations. In some examples, the controller 313 is integrated into the same package of the processing device 311. In other examples, the controller 313 is separate from the package of the processing device 311. The controller 313 and / or the processing device 311 may include hardware, such as one or more integrated circuits (ICs) and / or discrete components, buffer memory, cache memory, or a combination thereof. The controller 313 and / or the processing device 311 may be a microcontroller, a dedicated logic circuit system (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or another suitable processor.

[0109] The memory devices 323, 321 may include any combination of different types of non-volatile memory components and / or volatile memory components. Volatile memory devices (e.g., memory device 321) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0110] Some examples of non-volatile memory components include NAND (or NOT AND) type flash memory and write-in-place memory, such as three-dimensional cross-point ("3D cross-point") memory. A cross-point array of non-volatile memory can perform bit storage based on changes in bulk resistance in conjunction with a stackable cross-gate data access array. In addition, in contrast to many flash-based memories, cross-point non-volatile memory can perform write-in-place operations, where non-volatile memory cells can be programmed without the need to previously erase the non-volatile memory cells. NAND type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0111] Each of the memory devices 323 may include one or more arrays of memory cells 327. One type of memory cell, for example, a single level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cells (MLC), three-level cells (TLC), four-level cells (QLC), and five-level cells (PLC), may store multiple bits per cell. In some embodiments, each of the memory devices 323 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, PLC, or any combination of such. In some embodiments, a particular memory device may include an SLC portion, an MLC portion, a TLC portion, a QLC portion, and / or a PLC portion of memory cells. The memory cells of the memory devices 323 may be grouped into pages, which may refer to a logical unit of a memory device for storing data. For some types of memory, such as NAND, pages may be grouped to form blocks.

[0112] Although non-volatile memory devices such as 3D cross-point type and NAND type memory (e.g., 2D NAND, 3D NAND) are described, the memory device 323 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase change memory (PCM), self-select memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), non-OR (NOR) flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0113] The memory subsystem controller 303 (or simply controller 303) can communicate with the memory device 323 to perform operations such as reading data, writing data, or erasing data at the memory device 323 and other such operations (e.g., in response to commands dispatched by the controller 313 on the command bus). The controller 303 may include hardware, such as one or more integrated circuits (ICs) and / or discrete components, buffer memory, or a combination thereof. The hardware may include digital circuitry with dedicated (i.e., hard-coded) logic for performing the operations described herein. The controller 303 may be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or another suitable processor.

[0114] The controller 303 may include a processing device 307 (processor) configured to execute instructions stored in the local memory 305. In the illustrated example, the local memory 305 of the controller 303 includes an embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 301, including handling communications between the memory subsystem 301 and the host system 310.

[0115] In some embodiments, local memory 305 may include memory registers that store memory pointers, fetched data, etc. Local memory 305 may also include read-only memory (ROM) for storing microcode. Figure 6 The example memory subsystem 301 in FIG. 3 is illustrated as including a controller 303, but in another embodiment of the present disclosure, the memory subsystem 301 does not include the controller 303, but may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0116] In general, the controller 303 may receive commands or operations from the host system 310 and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 323. The controller 303 may be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation between logical addresses (e.g., logical block addresses (LBA), namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 323. The controller 303 may further include a host interface circuit system to communicate with the host system 310 via a physical host interface. The host interface circuit system may convert commands received from the host system into command instructions to access the memory device 323 and convert responses associated with the memory device 323 into information for the host system 310.

[0117] The memory subsystem 301 may also include additional circuitry or components not illustrated. In some embodiments, the memory subsystem 301 may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that may receive addresses from the controller 303 and decode the addresses to access the memory device 323.

[0118] In some embodiments, the memory device 323 includes a local media controller 325 that operates in conjunction with the memory subsystem controller 303 to perform operations on one or more memory cells of the memory device 323. An external controller (e.g., the memory subsystem controller 303) can manage the memory device 323 externally (e.g., perform media management operations on the memory device 323). In some embodiments, the memory device 323 is a managed memory device, which is a raw memory device combined with a local controller (e.g., the local media controller 325) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0119] Figure 7 A method for performing a multiplication and accumulation operation according to one embodiment is shown. For example, the method may be Figure 6 The invention is implemented in a computing system or device.

[0120] At box 401, the method includes applying multiple voltages (e.g., 203, 213, ..., 223) to multiple memory cells (e.g., 207, 217, ..., 227) programmed to represent multiple weights (e.g., one or more bits of weights 111, 113, ..., 115) based on a bit slice (e.g., 191 or 133) having a slice weight (e.g., 193 or 143) in an input (e.g., 130).

[0121] For example, in a computing system or device (e.g., as in Figure 6 ), memory cells (e.g., 207, 217, ..., 227) are connected to a plurality of word lines (e.g., 281, 282, ..., 283) to receive a plurality of voltages (e.g., 203, 213, ..., 223). In response to the applied voltages (e.g., 203, 213, ..., 223), the memory cells (e.g., 207, 217, ..., 227) allow a certain amount of current to pass through and enter the bit line (e.g., 241) connected to the memory cells (e.g., 207, 217, ..., 227). The amount of current passing through each of the memory cells (e.g., 207, 217, ..., 227) represents a multiplication result (e.g., 121, 123, ..., 125) generated by the corresponding input (e.g., 101, 103, ..., 105) and the corresponding weight (e.g., 111, 113, ..., 115) in the bit slice (e.g., 133).

[0122] For example, the logic circuitry of a computing system or device (eg, controller 325 or 303, or processing device 307) may be configured (eg, via instructions, firmware, and / or software) to perform Figure 7 The method includes the functionality of the time slice truncation manager 331.

[0123] For example, a computing system or device may have a voltage driver 271 (e.g., 203, 213, ..., 223) operable to apply a voltage according to an instruction or control signal from a logic circuit. The logic circuit may use the voltage driver to apply a programming voltage to program the state of a memory cell (e.g., 207, 217, ..., 227) to represent a weight (e.g., 111, 113, ..., 115) to apply an input voltage (e.g., 205, 215, ..., 225) representing an input bit (e.g., 201, 211, ..., 221) or input (e.g., 101, 103, ..., 105) of an input bit slice (e.g., 133) so that the memory cell (e.g., 207, 217, ..., 227) outputs a current into a bit line (e.g., 241) corresponding to a multiplication result (e.g., 121, 123, ..., 125).

[0124] For example, input 130 has multiple elements weighted by multiple weights (e.g., 111, 113, ..., 115), respectively; and a bit slice (e.g., 133) includes one bit with the same significance level from each of the multiple elements (e.g., input 101, 103, ..., or 105; or input bit 201, 211, ..., or 221).

[0125] For example, each of the plurality of weights (e.g., 111, 113, ..., 115) may be a 1-bit value stored in a corresponding memory cell (e.g., 207, 217, ..., or 227). Alternatively, more than one memory cell connected to the same bit line (e.g., 241) may be combined to store weights (e.g., 111, 113, ..., 115) having multi-bit values. Alternatively, the memory cells may be programmed to store weights having multi-bit values.

[0126] In some implementations, the memory cells (eg, 207, 217, ..., 227) are memristors that are programmed to have conductances representing weights (eg, 111, 113, ..., 115).

[0127] In some implementations, the memory cells (e.g., 207, 217, ..., 227) have a nonlinear current-voltage curve; and each of the memory cells (e.g., 207, 217, ..., 227) can be programmed to output a current at a level representing a weight stored in the memory cell in response to a predetermined voltage applied to the memory cell representing an input bit having a value of 1 (e.g., 201, 211, ..., or 221).

[0128] At box 403, the method includes generating a current in a line (e.g., bit line 241) connected to the plurality of memory cells (e.g., 207, 217, ..., 227) in response to a plurality of voltages (e.g., 203, 213, ..., 223).

[0129] For example, the current in the bit line 241 is the sum of the currents entering the bit line 241 through the memory cells 205 , 215 , . . . , 225 .

[0130] At block 405 , the method includes applying a resolution control (eg, 239 ) to an analog-to-digital converter 245 coupled to a line (eg, bit line 241 ) according to a slice weight (eg, 193 or 143 ).

[0131] At box 407, the method includes using analog-to-digital converter 245 to measure at least one first bit (e.g., 171, ..., 173) representing the magnitude of current in a line (e.g., bit line 241) in response to multiple voltages (e.g., 203, 213, ..., 223).

[0132] At block 409 , the method includes skipping measurement of at least one second bit (eg, 175 , . . . , 177 ) of the quantity according to a resolution control (eg, 239 ).

[0133] At block 411, the method includes summing a plurality of truncated outputs (e.g., 153, 150) obtained from a plurality of bit slices (e.g., 131, 133, ..., 135) respectively having a plurality of slice weights (e.g., 141, 143, ..., 145) in the input 130. The plurality of truncated outputs includes a truncated output (e.g., 153 or 150) having at least one first bit (e.g., 171, ..., 173) but not having at least one second bit (e.g., 175, ..., 177).

[0134] Optionally, the method may further include controlling the length of a time period allocated to allow current to stabilize in a line (e.g., bit line 241) before measuring at least one first bit (e.g., 171, ..., 173) based on resolution control 239 or a slice weight (e.g., 193 or 143).

[0135] For example, multiple truncated outputs (eg, 153 or 150) from the analog-to-digital converter 245 are summed without requiring a shift operation (eg, corresponding to left shift 261) to align the significant bits of the multiple truncated outputs (eg, 153 or 150).

[0136] For example, multiple truncated outputs (eg, 153 or 150 ) are truncated by the A / D converter 245 according to the resolution control 239 to have the same level of weight (eg, the same weight as the scaling factor 190 of the truncated result 180 ).

[0137] For example, the method may further include: based on summing the plurality of truncated outputs (eg, 153 or 150 ), providing an approximation result 160 of a sum of truncated elements weighted by a plurality of weights (eg, 111 , 113 , . . . , 115 ), respectively.

[0138] For example, the approximation result 160 may include a truncated result 180 and a scaling factor 190 to discard a predetermined number of least significant bits (e.g., 185, ..., 187); each of the multiple truncated outputs (e.g., 150) corresponds to a partial sum (e.g., 120) that has been truncated to discard the same predetermined number of least significant bits (e.g., 175, ..., 177 and zero 179); and the partial sum (e.g., 120) is equal to a sum of corresponding bit slices (e.g., 191) in a plurality of bit slices (e.g., 131, 133, ..., 135) having corresponding slice weights (e.g., 193) and weighted according to multiple weights (e.g., 111, 113, ..., 115) shifted according to corresponding slice weights (e.g., 193).

[0139] In one embodiment, an example machine of a computer system may execute within the computer system a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein. In some embodiments, the computer system may correspond to a host system that includes, is coupled to, or utilizes a memory subsystem or may be used to perform the operations described above. In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, an intranet, an extranet, or the Internet, or any combination thereof. The machine may operate as a server or a client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

[0140] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, a network-attached storage facility, or any machine capable of executing (sequentially or otherwise) a set of instructions that specify actions to be taken by the machine. In addition, while a single machine is described, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0141] An example computer system includes a processing device, a main memory (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) (e.g., synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), static random access memory (SRAM), etc.), and a data storage system, which communicate with each other via a bus (which may include multiple buses).

[0142] The processing device represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, or the like. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor implementing other instruction sets or multiple processors implementing a combination of instruction sets. The processing device may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. The processing device is configured to execute instructions for performing the operations and steps discussed herein. The computer system may further include a network interface device for communicating via a network.

[0143] The data storage system may include a machine-readable medium (also referred to as a computer-readable medium) on which is stored one or more sets of instructions or software embodying any one or more of the methodologies or functions described herein. The instructions may also reside completely or at least partially within the main memory and the processing device during their execution by the computer system, the main memory and the processing device also constituting machine-readable storage media. The machine-readable medium, data storage system, or main memory may correspond to a memory subsystem.

[0144] In one embodiment, the instructions include instructions that implement functionality corresponding to the operations described above. Although the machine-readable medium is shown as a single medium in the example embodiments, the term "machine-readable storage medium" should be taken to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be taken to include any medium capable of storing or encoding a set of instructions for execution by a machine and causing the machine to perform any one or more of the methodologies of the present disclosure. Therefore, the term "machine-readable storage medium" should be taken to include (but not limited to) solid-state memory, optical media, and magnetic media.

[0145] Some portions of the foregoing detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively convey the substance of their work to others skilled in the art. Algorithms herein are generally conceived of as self-consistent sequences of operations leading to desired results. Operations are operations requiring physical manipulation of physical quantities. Typically, although not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, primarily for common sense reasons, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0146] It should be remembered, however, that all of these and similar terms should be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may involve actions and processes of computer systems or similar electronic computing devices that manipulate and transform data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0147] The present disclosure also relates to an apparatus for performing the operations herein. This apparatus may be specially constructed for the intended purpose, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. This computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of magnetic disk (including floppy disks, optical disks, CD-ROMs, and magneto-optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0148] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general purpose systems may be used in conjunction with programs according to the teachings herein, or it may prove convenient to construct more specialized equipment to perform the methods. The structures of a variety of these systems will appear as set forth in the description below. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages ​​may be used to implement the teachings of the present disclosure as described herein.

[0149] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, which can be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form that can be read by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory component, etc.

[0150] In this description, various functions and operations are described as being performed or caused by computer instructions to simplify the description. However, those skilled in the art will recognize that the meaning of such expressions is that the functions are derived from one or more controllers or processors such as microprocessors executing computer instructions. Alternatively or in combination, the functions and operations can be implemented using dedicated circuit systems with or without software instructions, such as using application specific integrated circuits (ASICs) or field programmable gate arrays (FPGAs). Embodiments can be implemented using hard-wired circuit systems without or in combination with software instructions. Therefore, the technology is neither limited to any specific combination of hardware circuit systems and software, nor to any specific source of instructions executed by a data processing system.

[0151] In the foregoing description, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be appreciated that various modifications may be made to the present disclosure without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. Accordingly, the description and drawings should be viewed in an illustrative rather than a restrictive sense.

Claims

1. A method comprising: applying a plurality of voltages to a plurality of memory cells programmed to represent a plurality of weights according to a bit slice having a slice weight in an input; generating, in lines connected to the plurality of memory cells, currents derived by the plurality of memory cells in response to the plurality of voltages; applying resolution control to an analog-to-digital converter coupled to the line based on the slice weights; measuring, using the analog-to-digital converter, at least one first bit of a quantity representative of a magnitude of the current in the line in response to the plurality of voltages; and A plurality of truncated outputs obtained from a plurality of bit slices in the input respectively having a plurality of slice weights are summed, the plurality of truncated outputs including a truncated output having the at least one first bit.

2. The method according to claim 1, further comprising: controlling, based on the resolution control, a length of a time period allotted to allow the current to settle in the line prior to the measuring of the at least one first bit; wherein the measurement of at least one second bit of the quantity is skipped according to the resolution control; and wherein the plurality of truncated outputs exclude the at least one second bit.

3. The method according to claim 2, wherein the input has a plurality of elements to be weighted by the plurality of weights respectively; wherein the bit slice comprises one bit from each of the plurality of elements having the same significance level; wherein the plurality of truncated outputs from the analog-to-digital converter are summed without requiring a shift operation to align significant bits of the plurality of truncated outputs; and The plurality of truncated outputs are truncated to have the same level of weight.

4. The method according to claim 3, further comprising: Based on summing the plurality of truncated outputs, providing an approximation result of truncating a sum of the plurality of elements weighted by the plurality of weights respectively; wherein each of the plurality of weights has a 1-bit value; and wherein the approximation result has a scaling factor to discard a predetermined number of least significant bits; each of the multiple truncated outputs corresponds to a partial sum that has been truncated to discard the same predetermined number of least significant bits; and the partial sum is equal to shifting the sum of corresponding bit slices in the multiple bit slices having the corresponding slice weights and weighted according to the multiple weights according to the corresponding slice weights.

5. A device comprising: a plurality of memory cells programmable to represent a plurality of weights; a plurality of word lines connected to the plurality of memory cells; a bit line connected to collect current flowing through the plurality of memory cells; a voltage driver operable to apply a plurality of voltages to the plurality of memory cells via the plurality of word lines according to a bit slice having a slice weight in an input; an analog-to-digital converter coupled to the bit line and configured with a resolution control; and a logic circuit configured to apply the resolution control according to the slice weight when measuring, using the analog-to-digital converter, at least one first bit representing an amount of magnitude of current in the bit line in response to the plurality of voltages applied to the plurality of memory cells; and The logic circuit is configured to sum a plurality of truncated outputs obtained from a plurality of bit slices in the input respectively having a plurality of slice weights, the plurality of truncated outputs including a truncated output having the at least one first bit.

6. The apparatus of claim 5, wherein the logic circuit is configured to control the length of a time period allotted to allow the current to stabilize in the bit line before the measurement begins; wherein the analog-to-digital converter is configured to skip measurement of at least one second bit of the quantity according to the resolution control; wherein the truncated output excludes the at least one second bit; and wherein the input has a plurality of elements to be weighted by the plurality of weight values, respectively; and the bit slice includes one bit with a same significance level from each of the plurality of elements.

7. The apparatus of claim 6, wherein the plurality of truncated outputs are truncated to have the same level of weight; wherein the logic circuit is configured to provide the sum of the plurality of truncated outputs as an approximation result of truncating the sum of the plurality of elements weighted by the plurality of weights respectively; and wherein the approximation result has a scaling factor to discard a predetermined number of least significant bits; each of the multiple truncated outputs corresponds to a partial sum that has been truncated to discard the same predetermined number of least significant bits; and the partial sum is equal to shifting the sum of corresponding bit slices in the multiple bit slices having the corresponding slice weights and weighted according to the multiple weights according to the corresponding slice weights.

8. The apparatus of claim 6, wherein the plurality of truncated outputs from the analog-to-digital converter are summed without applying a shift operation to align significant bits of the plurality of truncated outputs.

9. A system comprising: a memory cell array having a plurality of memory cells connected to a plurality of word lines and bit lines; Voltage driver; and at least one analog-to-digital converter; A processor configured to: programming the plurality of memory cells to store a plurality of weight values; identifying bit slices in the input having slice weights; instructing the voltage driver to apply a plurality of voltages via the word line according to the bit slice; and instructing the analog-to-digital converter to generate a truncated output based on measuring a current in the bit line drawn by the plurality of memory cells in response to the plurality of voltages, wherein the analog-to-digital converter measures at least one first bit of a quantity representative of a magnitude of the current in the line in response to the plurality of voltages; The system is configured to sum a plurality of truncated outputs obtained from a plurality of bit slices in the input respectively having a plurality of slice weights to provide an approximation of a sum of a plurality of elements of the input weighted by the plurality of weights respectively.

10. The system of claim 9, further configured to control, based on the slice weight, a length of a time period allocated to allow the current to stabilize in the bit line prior to the measurement of the at least one first bit; wherein the analog-to-digital converter is configured to skip measurement of at least one second bit of the quantity; wherein the plurality of truncated outputs are truncated to have the same level of weight; wherein each of the plurality of weights has a 1-bit value; and wherein the approximation result has a scaling factor to discard a predetermined number of least significant bits; each of the multiple truncated outputs corresponds to a partial sum that has been truncated to discard the same predetermined number of least significant bits; and the partial sum is equal to shifting the sum of corresponding bit slices in the multiple bit slices having the corresponding slice weights and weighted according to the multiple weights according to the corresponding slice weights.

Images