Method, system, apparatus and device for real-time bidirectional data transmission between chips

Abstract

Embodiments of the present application provide a real-time bidirectional data transmission method, system, device and equipment between chips. In the embodiments of the present application, the system comprises a first data sending module, a first data receiving module, a first signal selection module, a second data sending module, a second data receiving module and a second signal selection module. The first data sending module comprises a first output end for sending data to the first signal selection module, and a second output end for sending data to the second data sending module. The second output end of the first data sending module is also used for receiving data from the second data sending module when sending data to the second data sending module. The first signal selection module comprises a first input end for receiving data output by the first output end of the first data sending module, and a second data end for receiving data output by the second output end of the first data sending module.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a method, system, apparatus and device for real-time bidirectional data transmission between chips. Background Technology

[0002] D2D (Die-to-Die) communication technology typically refers to a communication method where two chips communicate directly. Currently, when chip A sends data to chip B through the same chip interface (simplex mode), chip B often cannot send data back to chip A. This limits the amount of data transmitted between chip A and chip B within a given time period, thus affecting the data transmission rate between them. Therefore, improving the existing data transmission method between chips to increase the data transmission rate still requires further solutions. Summary of the Invention

[0003] This application provides a method, system, apparatus, and device for real-time bidirectional data transmission between chips, aimed at improving data transmission rates.

[0004] This application provides a real-time bidirectional data transmission system between chips, comprising: a first data transmission module, a first data receiving module, a first signal selection module, a second data transmission module, a second data receiving module, and a second signal selection module, wherein: the first data transmission module includes a first output terminal for transmitting data to the second data selection module, and a second output terminal for transmitting data to the second data transmission module; the second output terminal of the first data transmission module, when transmitting data to the second data transmission module, is also used to receive data from the second data transmission module; the first signal selection module includes a first input terminal for receiving data output from the first output terminal of the first data transmission module, and a second input terminal for receiving data from the first data transmission module. The second data sending module includes a second input terminal for data output from the second output terminal of the sending module, and an output terminal for outputting data to the first data receiving module; the second data sending module includes a first output terminal for sending data to the first signal selection module, and a second output terminal for sending data to the first data sending module. When sending data to the first data sending module, the second output terminal of the second data sending module is also used to receive data from the first data sending module; the second signal selection module includes a first input terminal for receiving data output from the first output terminal of the second data sending module, a second input terminal for receiving data output from the second output terminal of the second data sending module, and an output terminal for outputting data to the second data receiving module.

[0005] This application also provides an electronic device, the memory of which includes a real-time bidirectional data transmission system.

[0006] This application also provides a data transmission device, which includes a real-time bidirectional data transmission system.

[0007] This application also provides a chip that includes a real-time bidirectional data transmission system.

[0008] This application also provides an integrated circuit that includes a real-time bidirectional data transmission system.

[0009] This application also provides a method for real-time bidirectional data transmission between chips. The method is applied to a real-time bidirectional data transmission system. The method includes: determining data sent by a first data transmission module through a first selector; when the data sent by the first data transmission module is determined to be a first specified value through the first selector, selecting a first comparator to judge the output data from the first transmitting end to obtain data sent by a second transmitting end; and when the data sent by the first data transmission module is determined to be a second specified value through the first selector, selecting a second comparator to judge the output data from the first transmitting end to obtain data sent by the second transmitting end.

[0010] This application embodiment also provides a real-time bidirectional data transmission device for inter-chip communication, comprising: a determining module, configured to determine data sent by a first data sending module through a first selector; a selecting module, configured to, when the data sent by the first data sending module is determined to be a first specified value through the first selector, select a first comparator to judge the output data from the first sending end to obtain data sent by a second sending end; and, when the data sent by the first data sending module is determined to be a second specified value through the first selector, select a second comparator to judge the output data from the first sending end to obtain data sent by the second sending end.

[0011] The real-time bidirectional data transmission system for inter-chip communication provided in this application includes a first data transmission module, a first data receiving module, a first signal selection module, a second data transmission module, a second data receiving module, and a second signal selection module. Since the first data transmission module includes a first output terminal for transmitting data to the second signal selection module and a second output terminal for transmitting data to the second data transmission module, and the second output terminal of the first data transmission module is used to receive data from the second data transmission module while transmitting data to the second data transmission module, it is possible for the first and second data transmission modules to simultaneously transmit data to each other, thereby effectively improving the data transmission rate. Furthermore, the data transmitted by the first data transmission module can be acquired by the first signal selection module, which also includes a second input terminal for receiving data output from the second output terminal of the first data transmission module. That is, the first signal selection module can simultaneously acquire the data transmitted by the first data transmission module and the composite data transmitted by the first and second data transmission modules, thereby accurately acquiring the data transmitted by the first data transmission module based on the data transmitted by the first data transmission module and the composite data transmitted by the first and second data transmission modules. Similarly, the second signal selection module can simultaneously acquire data from the second data transmission module, as well as composite data from the first and second data transmission modules. This allows it to accurately retrieve the data sent by the second data transmission module based on this composite data. Thus, it achieves the goal of accurately retrieving data sent by the other party when both the first and second data transmission modules are simultaneously sending data to each other. Attached Figure Description

[0012] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings: Figure 1 A schematic diagram of a real-time bidirectional data transmission system between chips is provided as an exemplary embodiment of this application; Figure 2 A schematic diagram of two data transmission links in a real-time bidirectional data transmission system between chips, provided as an exemplary embodiment of this application; Figure 3 Synchronization in the real-time bidirectional data transmission system between chips provided in the embodiments of this application Figure 2 The diagram shows the structure of the bit delay unit for the signals transmitted through the two data transmission links. Figure 4The diagram shows the waveforms of data transmitted by TX1 and TX2 and the waveforms of composite data transmitted by TX1 and TX2 in a real-time bidirectional data transmission system between chips provided in the embodiments of this application. Figure 5 A schematic diagram illustrating the extraction of the data waveform sent by TX2 from the waveform of composite data sent by TX1 and TX2 in a real-time bidirectional data transmission system between chips provided in an embodiment of this application. Figure 6 A schematic diagram of the structure of an electronic device / chip / integrated circuit provided in this application embodiment; Figure 7 A schematic diagram illustrating the implementation process of a real-time bidirectional data transmission method between chips, provided as an exemplary embodiment of this application; Figure 8 This is a schematic diagram of a device for real-time bidirectional data transmission between chips, provided as an exemplary embodiment of this application. Detailed Implementation

[0013] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below in conjunction with specific embodiments and corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0014] First, the terms and concepts involved in one or more embodiments of this application will be explained.

[0015] D2D: Short for Die-to-Die, it's a chip-to-die interface used to provide a data interface between two chips assembled in the same package. Chip-to-chip interfaces utilize very short channels to connect two chips within the package, achieving higher power efficiency and bandwidth efficiency than traditional chip-to-chip interfaces.

[0016] Comparator: A comparison is the process of comparing two or more data items to determine whether they are equal, or to determine their relative magnitudes and order. A circuit or device capable of performing this comparison is called a comparator. A comparator is a circuit that compares an analog voltage signal with a reference voltage. The two inputs of a comparator are analog signals, and the output is a binary signal of 0 or 1. When the difference in the input voltages increases or decreases while the sign remains unchanged, the output remains constant.

[0017] Full-duplex: A term in communications transmission, full-duplex allows data to be transmitted simultaneously in both directions. It's essentially a combination of two simplex communication methods. Full-duplex refers to the ability to transmit signals bidirectionally (A→B and B→A) simultaneously (instantaneously). It means that A→B and B→A are simultaneous, exhibiting instantaneous synchronization.

[0018] Simplex: In simplex communication, data transmission is unidirectional. One party is always the sender, and the other is always the receiver. Information can only be transmitted in one direction, using a single transmission line.

[0019] Network bandwidth: Network bandwidth refers to the amount of data that can be transmitted per unit of time (usually 1 second). A network is similar to a highway; the larger the bandwidth, the more lanes a highway has, and the greater its throughput.

[0020] Bandwidth rate: Broadband rate refers to the maximum theoretical speed that can be achieved technically. It is generally the upload and download speed. The higher the rate, the faster the upload and download speeds.

[0021] Buffers: In the computer field, a buffer refers to a buffer register, which is divided into two types: input buffers and output buffers. The former temporarily stores data sent from peripherals so that the processor can retrieve it; the latter temporarily stores data sent by the processor to peripherals. With buffers, the high-speed CPU and the slow-speed peripherals can coordinate and buffer each other, achieving synchronization of data transmission.

[0022] As described in the background section, to improve the data transmission efficiency of existing simplex mode in D2D, related technologies have proposed a bidirectional data transmission method. Specifically, this method involves two data transmitters on the same data transmission link: a first data transmitter and a second data transmitter. The first data transmitter normally sends data to the second data transmitter, while the second data transmitter sends data to the first data transmitter with the opposite code pattern. Clearly, while this data transmission method achieves real-time bidirectional data transmission, it means that only one data transmitter's data is useful at any given time. Furthermore, the simultaneous data transmission by the second data transmitter and the first data transmitter incurs additional power consumption.

[0023] To address this, embodiments of this application provide a real-time bidirectional data transmission system between chips. The system includes a first data transmission module, a first data receiving module, a first signal selection module, a second data transmission module, a second data receiving module, and a second signal selection module. The first data transmission module includes a first output terminal for transmitting data to the second signal selection module and a second output terminal for transmitting data to the second data transmission module. Furthermore, when transmitting data to the second data transmission module, the second output terminal of the first data transmission module is also used to receive data from the second data transmission module.

[0024] Because the second output terminal of the first data transmission module is used to receive data from the second data transmission module while sending data to it, the first and second data transmission modules can simultaneously send data to each other, thereby effectively improving the data transmission rate. Furthermore, the data sent by the first data transmission module can be acquired by the first signal selection module. This first signal selection module also includes a second input terminal for receiving data output from the second output terminal of the first data transmission module. That is, the first signal selection module can simultaneously acquire the data sent by the first data transmission module and the composite data sent by the first and second data transmission modules, thus accurately obtaining the data sent by the first data transmission module based on this composite data. Similarly, the second signal selection module can also simultaneously acquire the data sent by the second data transmission module and the composite data sent by the first and second data transmission modules, thus accurately obtaining the data sent by the second data transmission module based on this composite data. This achieves the goal of accurately obtaining the data sent by the other party when the first data sending module and the second data sending module send data to each other simultaneously.

[0025] The technical solutions provided by the various embodiments of this application are described in detail below with reference to the accompanying drawings.

[0026] Figure 1 This is a schematic diagram of a real-time bidirectional data transmission system 100 between chips, provided as an exemplary embodiment of this application. Figure 1 As shown, the system may include a first data transmission module 110, a first data receiving module 130, a first signal selection module 120, a second data transmission module 210, a second data receiving module 230, and a second signal selection module 220, wherein: The first data transmission module 110 includes a first output terminal for transmitting data to the first signal selection module 120 and a second output terminal for transmitting data to the second data transmission module 210. When transmitting data to the second data transmission module 210, the second output terminal of the first data transmission module 110 is also used to receive data from the second data transmission module 210. The first signal selection module 120 includes a first input terminal for receiving data output from a first output terminal of the first data transmission module 110, a second input terminal for receiving data output from a second output terminal of the first data transmission module 110, and an output terminal for outputting data to the first data receiving module 130. The second data transmission module 210 includes a first output terminal for transmitting data to the second signal selection module 220 and a second output terminal for transmitting data to the first data transmission module 110. When transmitting data to the first data transmission module 110, the second output terminal of the second data transmission module 210 is also used to receive data from the first data transmission module 110. The second signal selection module 220 includes a first input terminal for receiving data output from the first output terminal of the second data transmission module 210, a second input terminal for receiving data output from the second output terminal of the second data transmission module 210, and an output terminal for outputting data to the second data receiving module 230.

[0027] In some exemplary embodiments, the system for real-time bidirectional data transmission between chips further includes a first data control module C1 and a second data control module C2; The first data transmission module 110 includes a first data receiving end T1 for receiving data from the first data control module C1, and a first transmitting end TX1 for transmitting data from the first data control module C1; The second data transmission module 210 includes a second data receiving end T2 for receiving data from the second data control module C2, and a second transmitting end TX2 for transmitting data from the second data control module C2.

[0028] In this system, the data sent from the first data sending module 110 to the second data sending module 210 originates from the first data control module C1, and the data sent from the second data sending module 210 to the first data sending module 110 originates from the second data control module C2. After receiving data from the first data control module C1, the first data receiving end T1 sends the data to the first sending end TX1, which then forwards it to the second sending end TX2. Similarly, after receiving data from the second data control module C2, the second data receiving end T2 sends the data to the second sending end TX2, which then forwards it to the first sending end TX1.

[0029] In some exemplary embodiments, the first signal selection module 120 includes a first comparator 11, a second comparator 12, and a first selector 1, and the second signal selection module 220 includes a third comparator 21, a fourth comparator 22, and a second selector 2, wherein: The first selector 1 includes a first input terminal for receiving data output from the first data receiving terminal T1, a second input terminal for receiving output data from the first comparator 11, a third input terminal for receiving output data from the second comparator 12, and an output terminal for outputting data to the first data receiving module 130. The first comparator 11 includes an input terminal for receiving data output from the first transmitter TX1 and an output terminal for outputting a comparison result to the first selector 1. The second comparator 12 includes an input terminal for receiving data output from the first transmitter TX1 and an output terminal for outputting a comparison result to the first selector 1. The second selector 2 includes a first input terminal for receiving data output from the second data receiving terminal T2, a second input terminal for receiving output data from the third comparator 21, a third input terminal for receiving output data from the fourth comparator 22, and an output terminal for outputting data to the second data receiving module 230. The third comparator 21 includes an input for receiving data output from the second transmitter TX2 and an output for outputting a comparison result to the second selector 2. The fourth comparator 22 includes an input for receiving data output from the second transmitter TX2 and an output for outputting a comparison result to the second selector 2.

[0030] Among them, the reference comparison values ​​of the first comparator and the second comparator are different, with the reference comparison value of the first comparator being 1 and the reference comparison value of the second comparator being 0. The reference comparison values ​​of the third comparator and the fourth comparator are also different, with the reference comparison value of the third comparator being 1 and the reference comparison value of the fourth comparator being 0.

[0031] It should be understood that since the data sent by the first transmitting end TX1 and the data sent by the second transmitting end TX2 are both transmitted using a single transmission link between TX1 and TX2, when the first transmitting end TX1 and the second transmitting end TX2 simultaneously send data to the other end, superimposed data will be generated on this transmission link between TX1 and TX2. To accurately obtain the data sent by the other end from the first data receiving module 130 and the second data receiving module 230, this embodiment of the application can select a matching comparator based on the data sent by the first data sending module 110 and the second data sending module 210 respectively, and eliminate the local data from the superimposed data generated on this transmission link between TX1 and TX2, thereby obtaining the data sent by the other end.

[0032] The data transmitted by the first data transmission module 110 and the second data transmission module 210 can be obtained through the first input terminal of the first selector 1 for receiving data output from the first data receiving terminal T1, and through the first input terminal of the second selector 2 for receiving data output from the second data receiving terminal T2, respectively.

[0033] Specifically, the first selector can select a comparator from the first comparator and the second comparator that matches the data output by the first data receiver T1 based on the data received at its first input terminal. This will eliminate the data sent by the first transmitter TX1 from the data output by the first transmitter TX1 (i.e., the superimposed data of the data sent by the first transmitter TX1 and the data sent by the second transmitter TX2 on the transmission link between TX1 and TX2), thereby enabling the first data receiving module 130 to obtain the data sent by the second transmitter TX2.

[0034] The second selector can select a comparator from the third and fourth comparators that matches the data output by the second data receiver T2 based on the data received at its first input terminal. This will eliminate the data sent by the second transmitter TX2 from the data output by the second transmitter TX2 (i.e., the superimposed data of the data sent by the first transmitter TX1 and the data sent by the second transmitter TX2 on the transmission link between TX1 and TX2), thereby enabling the second data receiving module 230 to obtain the data sent by the first transmitter TX1.

[0035] In some exemplary embodiments, in order to achieve synchronization of the signals received by the first input terminal and the second input terminal of the first selector 1, and the signals received by the first input terminal and the second data terminal of the second selector 2, thereby avoiding the problem of glitches in the signals received by the first selector 1 and the second selector 2 affecting the eye diagram quality, the real-time bidirectional data transmission system for inter-chip further includes a first delay module BDL1 and a second delay module BDL2. The output terminal of the first delay module BDL1 is connected to the first input terminal of the first selector 1 and is used to synchronize the signals received by the first input terminal and the second input terminal of the first selector 1. The output of the second delay module BDL2 is connected to the second input of the second selector 2 to synchronize the signals received by the first input and the second data terminal of the second selector 2.

[0036] Figure 2 This is a schematic diagram of two data transmission links in a real-time bidirectional data transmission system between chips, provided as an exemplary embodiment of this application. Data transmission link ① transmits the data received by the first data receiver T1 to selector 1, allowing selector 1 to determine the data content to be sent by its own end, i.e., the first data transmitting module 110. Data transmission link ② transmits the data received by the first data receiver T1 sequentially to the first transmitter TX1, the first comparator 11, or the second comparator 12, and finally to selector 1. Since the first transmitting end TX1 receives data from the first data receiving end T1 and the second transmitting end TX2 simultaneously, the data transmitted to comparator 11 or comparator 12 in data transmission link ② is the superposition of the data transmitted by the first transmitting end TX1 and the second transmitting end TX2. To ensure that the first selector 1 can accurately obtain the data transmitted by the other end, i.e., the second transmitting end TX2, from the superposition of the data transmitted by the first transmitting end TX1 and the second transmitting end TX2 while receiving its own data, this embodiment adds a first-bit delay module BDL1 to the data transmission link ①, which has a shorter data transmission distance, so that the data transmitted on data transmission link ① and data transmission link ② arrive at the selector 1 at the same time. Similarly, a second-bit delay module BDL2 is also added between the second selector 2 and the second data receiving end T2 to synchronize the signals received by the first input end and the second data end of the second selector 2.

[0037] Figure 3 Synchronization in the real-time bidirectional data transmission system between chips provided in the embodiments of this application Figure 2The diagram shows the structure of the bit delay devices for the signals transmitted through the two data transmission links. D1 to D4 are four bit delay devices. As an example, the delay time of each bit delay device can be the same, for example, 1 ps. The signal can be output from any one of ① to ④ as needed. When the signal is output from ①, the delay time is 1 ps; when the signal is output from ②, the delay time is 2 ps; when the signal is output from ③, the delay time is 3 ps; and when the signal is output from ④, the delay time is 4 ps. The specific output path selected by the first bit delay module BDL1 and the second bit delay module BDL2 can be determined through simulation, as long as the signals received by the first and second input terminals of the first selector 1 are synchronized, and the signals received by the first input terminal and the second data terminal of the second selector 2 are synchronized.

[0038] As another example Figure 3 The number of the four bit delay devices D1~D4 shown and the delay time period of each bit delay device can be set according to the requirements of delay adjustment accuracy and delay adjustment range. For example, if the delay adjustment range is 100ps and the delay adjustment accuracy is 1ps, and if bit delay devices with a delay time period of 1ps are used to construct the bit delay module, then 100 1ps bit delay devices need to be connected in series, which makes the bit delay module quite complex. In this embodiment of the application, bit delay devices with different delay time periods can be selected to construct the bit delay module. As an example, the number of D1~D4 can be expanded to 10, that is, expanded to D1~D10. The delay time periods of these bit delay devices can not be exactly the same. For example, the delay time period of D1~D4 is 1ps, the delay time period of D5 is 5ps, the delay time period of D6 and D7 is 10ps, the delay time period of D8 and D9 is 20ps, and the delay time period of D10 is 30ps. Thus, D1+D2+D3+…+D10=100ps, satisfying an adjustment range of 100ps, with a minimum adjustment unit of 1ps, while also meeting a delay adjustment accuracy of 1ps. Compared to a bit delay module composed of 100 1ps bit delayers connected in series, the number of delay devices in this bit delay module is greatly reduced, facilitating adjustment and simplifying the structure of the bit delay module.

[0039] In some exemplary embodiments, when the first selector 1 determines that the input data at the first input terminal of the first selector 1 is a first specified value, the first comparator 11 is selected to judge the data output from the second output terminal of the first data transmission module 110; and when the first selector 1 determines that the input data at the first input terminal of the first selector 1 is a second specified value, the second comparator is selected to judge the data output from the second output terminal of the first data transmission module 110. When the input data at the first input terminal of the second selector 2 is determined to be the first specified value, the third comparator 21 judges the data output from the second output terminal of the second data transmission module 210. When the input data at the first input terminal of the second selector 2 is determined to be the second specified value, the fourth comparator 22 judges the data output from the second output terminal of the second data transmission module 210.

[0040] Figure 4 The diagram illustrates the data waveforms transmitted by TX1 and TX2, and the waveforms of composite data transmitted by TX1 and TX2, in a real-time bidirectional data transmission system between chips provided in this application embodiment. Figure 4 It can be seen that the data sent by the first transmitter TX1 is 10100, the data sent by the second transmitter TX2 is 01101, and the data after the data sent by the first transmitter TX1 and the second transmitter TX2 are superimposed is 10100. Figure 5 This is a schematic diagram illustrating the extraction of the data waveform transmitted by TX2 from the composite data transmitted by TX1 and TX2 in the real-time bidirectional data transmission system provided in this application embodiment. For the first selector 1, the data 10100 transmitted by the first transmitting end TX1 can be obtained through the first input terminal of the first selector 1, and the data after superimposing the data transmitted by the first transmitting end TX1 and the second transmitting end TX2 can be obtained through the second input terminal of the first signal selection module 120.

[0041] In some exemplary embodiments, the first specified value is 1, and the second specified value is 0. When the first selector 1 determines that the input data at its first input terminal is the first specified value 1, it selects a first comparator 11 with a comparison reference value of 1 to judge the data output from the second output terminal of the first data transmission module 110, and obtains a first bit value of 0. When the first selector 1 determines that the input data at its first input terminal is the second specified value 0, it selects a second comparator 12 with a comparison reference value of 0 to judge the data output from the second output terminal of the first data transmission module 110, and obtains a second bit value of 1. This process continues until the data sent by the second transmission terminal TX2 is 01101.

[0042] When the second selector 2 determines that the input data at its first input terminal is the second specified value 0, it selects a fourth comparator 22 with a comparison reference value of 0 to judge the data output from the second output terminal of the second data transmission module, and obtains the first bit value 1. When the second selector 2 determines that the input data at its first input terminal is the first specified value 1, it selects a third comparator 21 with a comparison reference value of 1 to judge the data output from the second output terminal of the second data transmission module 210, and obtains the second bit value 0. This process continues until the data transmitted by the first transmitter TX1 is 10100.

[0043] In some exemplary embodiments, to compensate for the difference in data processing rates between different data processing modules, data buffer modules for data buffering are added between the first data receiving end T1 and the first transmitting end TX1, between the second data receiving end T2 and the second transmitting end TX2, between the first receiving end R1 and the first signal selection module 120, and between the second receiving end R2 and the second signal selection module 220. Specifically, the first data transmitting module 110 further includes a first data buffer module Ca1, the output of which is connected to the input of the first data transmitting end TX1, for buffering the data to be sent to the first data transmitting end TX1. The first data receiving module 130 also includes a second data buffer module Ca2 and a first receiving terminal R1. The input terminal of the second data buffer module Ca2 is connected to the output terminal of the first signal selection module 120 and is used to buffer the output data of the first signal selection module 120. The output terminal of the second data buffer module Ca2 is connected to the first receiving terminal R1 and the first receiving terminal R1 is used to send the output data of the second data buffer module Ca2 to the first data control module C1. The second data transmission module 210 also includes a third data buffer module Ca3. The output of the third data buffer module Ca3 is connected to the input of the second data transmission terminal TX2 and is used to buffer the data to be sent to the first data transmission terminal TX2. The second data receiving module 230 also includes a fourth data buffer module Ca4 and a second receiving terminal R2. The input terminal of the fourth data buffer module Ca4 is connected to the output terminal of the second signal selector 220 and is used to buffer the output data of the second signal selector 220. The output terminal of the fourth data buffer module Ca4 is connected to the second receiving terminal R2 and is used to send the output data of the fourth data buffer module Ca4 to the second data control module C2.

[0044] The first data buffer module Ca1 and the third data buffer module Ca3 are input buffers used to temporarily buffer data sent from the first data control module C1 or the second data control module C2, so that the first transmitting end TX1 and the second transmitting end TX2 can retrieve the data sent from the first data control module C1 or the second data control module C2. The second data buffer module Ca2 and the fourth data buffer module Ca4 are output buffers used to temporarily store data sent to the first data control module C1 or the second data control module C2.

[0045] Obviously, the real-time bidirectional data transmission system for inter-chip communication provided in this application differs from the full-duplex mode. This system, based on the simplex mode, only adds a module to eliminate the influence of data transmitted from the local end. Figure 1 The first signal selection module 120 and the second signal selection module 220 shown do not require an additional transmission link between the first transmitting end TX1 and the second transmitting end TX2. This not only enables real-time bidirectional data transmission but also reduces the power consumption and winding area of ​​the entire system.

[0046] The real-time bidirectional data transmission system for inter-chip communication provided in this application includes a first data transmission module, a first data receiving module, a first signal selection module, a second data transmission module, a second data receiving module, and a second signal selection module. Since the first data transmission module includes a first output terminal for transmitting data to the second signal selection module and a second output terminal for transmitting data to the second data transmission module, and the second output terminal of the first data transmission module is used to receive data from the second data transmission module while transmitting data to the second data transmission module, it is possible for the first and second data transmission modules to simultaneously transmit data to each other, thereby effectively improving the data transmission rate. Furthermore, the data transmitted by the first data transmission module can be acquired by the first signal selection module, which also includes a second input terminal for receiving data output from the second output terminal of the first data transmission module. That is, the first signal selection module can simultaneously acquire the data transmitted by the first data transmission module and the composite data transmitted by the first and second data transmission modules, thereby accurately acquiring the data transmitted by the first data transmission module based on the data transmitted by the first data transmission module and the composite data transmitted by the first and second data transmission modules. Similarly, the second signal selection module can simultaneously acquire data from the second data transmission module, as well as composite data from the first and second data transmission modules. This allows it to accurately retrieve the data sent by the second data transmission module based on this composite data. Thus, it achieves the goal of accurately retrieving data sent by the other party when both the first and second data transmission modules are simultaneously sending data to each other.

[0047] Figure 6 A schematic diagram of the structure of an electronic device / chip / integrated circuit 600 provided for an exemplary embodiment of this application. The electronic device / chip / integrated circuit includes... Figure 1 The system shown is a real-time bidirectional data transmission system 100 for inter-chip communication.

[0048] The English name for chip is Chiplet, which refers to a pre-manufactured, functional, and combinable die. Specifically, it involves breaking down the functionality of a single SoC chip into numerous smaller chips (Chiplet dies), and then using advanced packaging technologies (2.5D / 3D / Fanout, etc.) to reassemble them into a large and complex system within a single package, thereby reducing the overall cost of the chip.

[0049] Figure 6The electronic device shown can be a device containing a chip for a real-time bidirectional data transmission system between chips, such as a server, high-performance terminal device, or autonomous driving device used in data center networks.

[0050] about Figure 6 The specific implementation of the electronic device / chip / integrated circuit shown has been described in detail in the embodiments of the clock phase adjustment system, and will not be elaborated here.

[0051] Figure 7 A flowchart illustrating a real-time bidirectional data transmission method between chips is provided as an exemplary embodiment of this application. This real-time bidirectional data transmission method is applied to... Figures 1-5 The diagram shows a real-time bidirectional data transmission system between chips. (Example:) Figure 7 As shown, the method may include: Step 710: Determine the data to be sent by the first data sending module through the first selector.

[0052] Step 720: When the data sent by the first data sending module is determined to be a first specified value by the first selector, the first comparator is selected to judge the output data from the first sending end to obtain the data sent by the second sending end; and when the data sent by the first data sending module is determined to be a second specified value by the first selector, the second comparator is selected to judge the output data from the first sending end to obtain the data sent by the second sending end.

[0053] Optionally, when the data sent by the first data sending module is determined to be a first specified value by the first selector, the first comparator is selected to judge the output data from the first sending end to obtain the data sent by the second sending end, including: When the data sent by the first data sending module is determined to be a first specified value by the first selector, a first comparator that matches the first specified value is selected; The first comparator judges the output data from the first transmitter to obtain the data sent by the second transmitter.

[0054] Optionally, when the first selector determines that the data sent by the first data sending module is the second specified value, a second comparator is selected to judge the output data from the first sending end to obtain the data sent by the second sending end, including: When the first selector determines that the data sent by the first data sending module is the second specified value, a second comparator that matches the second specified value is selected. The second comparator judges the output data from the first transmitter to obtain the data sent by the second transmitter.

[0055] Figure 7 For a detailed implementation of the method for real-time bidirectional data transmission between chips, please refer to [link / reference]. Figures 1-5 The specific implementation of the real-time bidirectional data transmission system between chips in the illustrated embodiment will not be described in detail.

[0056] The real-time bidirectional data transmission method for inter-chip communication provided in this application is applied to a real-time bidirectional data transmission system for inter-chip communication. Since the first data transmission module includes a first output terminal for sending data to a second signal selection module and a second output terminal for sending data to the second data transmission module, and the second output terminal of the first data transmission module is also used to receive data from the second data transmission module while sending data to the second data transmission module, it is possible for the first and second data transmission modules to simultaneously send data to each other, thereby effectively improving the data transmission rate. Furthermore, the data sent by the first data transmission module can be acquired by the first signal selection module, which also includes a second input terminal for receiving data output from the second output terminal of the first data transmission module. That is, the first signal selection module can simultaneously acquire the data sent by the first data transmission module and the composite data sent by the first and second data transmission modules, thereby accurately acquiring the data sent by the first data transmission module based on the data sent by the first data transmission module and the composite data sent by the first and second data transmission modules. Similarly, the second signal selection module can simultaneously acquire data from the second data transmission module, as well as composite data from the first and second data transmission modules. This allows it to accurately retrieve the data sent by the second data transmission module based on this composite data. Thus, it achieves the goal of accurately retrieving data sent by the other party when both the first and second data transmission modules are simultaneously sending data to each other.

[0057] It should be noted that the execution subject of each step of the method provided in the above embodiments can be the same device, or the method can be executed by different devices. For example, the execution subject of steps 710 to 720 can be device A; or the execution subject of step 710 can be device A, and the execution subject of step 720 can be device B; and so on.

[0058] Furthermore, in some processes described in the above embodiments and accompanying drawings, multiple operations appear in a specific order. However, it should be clearly understood that these operations may not be executed in the order they appear herein, or they may be executed in parallel. The operation numbers, such as 710, 720, etc., are merely used to distinguish different operations and do not represent any execution order. Additionally, these processes may include more or fewer operations, and these operations may be executed sequentially or in parallel. It should be noted that the descriptions such as "first" and "second" in this document are used to distinguish different messages, devices, modules, etc., and do not represent a sequential order, nor do they limit "first" and "second" to different types.

[0059] Figure 8 A schematic diagram of a real-time bidirectional data transmission device 800 for inter-chip communication is provided as an exemplary embodiment of this application. This real-time bidirectional data transmission device is applied to… Figures 1-5 The diagram shows a real-time bidirectional data transmission system between chips. (Example:) Figure 8 As shown, the device includes: a determining module 810 and a selecting module 820, wherein: The determining module 810 is used to determine the data sent by the first data sending module through the first selector; Selection module 820 is configured to, when the data sent by the first data sending module is determined to be a first specified value by the first selector, select the first comparator to judge the output data from the first sending end to obtain the data sent by the second sending end; and, when the data sent by the first data sending module is determined to be a second specified value by the first selector, select the second comparator to judge the output data from the first sending end to obtain the data sent by the second sending end.

[0060] For details regarding the structure, signal flow and data processing of the device for real-time bidirectional data transmission between chips, as well as the achieved technical effects, please refer to [reference needed]. Figures 1-5 The implementation methods and technical effects of the real-time bidirectional data transmission system between chips shown in the embodiments will not be described in detail.

[0061] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0062] The above description is merely an embodiment of this application and is not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. A real-time bidirectional data transmission system between chips, characterized in that, The system includes a first data transmission module, a first data reception module, a first signal selection module, a second data transmission module, a second data reception module, a second signal selection module, a first data control module, and a second data control module. The first signal selection module includes a first comparator, a second comparator, and a first selector. The second signal selection module includes a third comparator, a fourth comparator, and a second selector, wherein: The first data transmission module includes a first output terminal for transmitting data to the first signal selection module and a second output terminal for transmitting data to the second data transmission module. When transmitting data to the second data transmission module, the second output terminal of the first data transmission module is also used to receive data from the second data transmission module. The second data transmission module includes a first output terminal for transmitting data to the second signal selection module and a second output terminal for transmitting data to the first data transmission module. When transmitting data to the first data transmission module, the second output terminal of the second data transmission module is also used to receive data from the first data transmission module. The first data transmission module further includes a first data receiving end for receiving data from the first data control module, and a first transmitting end for transmitting data from the first data control module; The second data transmission module further includes a second data receiving end for receiving data from the second data control module, and a second transmitting end for transmitting data from the second data control module; wherein, the first transmitting end and the second transmitting end simultaneously transmit data to the other end; The first selector includes a first input terminal for receiving data output from the first data receiving terminal, a second input terminal for receiving output data from the first comparator, a third input terminal for receiving output data from the second comparator, and an output terminal for outputting data to the first data receiving module. The first comparator includes an input terminal for receiving data output from the first transmitting end, and an output terminal for outputting a comparison result to the first selector; the second comparator includes an input terminal for receiving data output from the first transmitting end, and an output terminal for outputting a comparison result to the first selector. When the first selector determines that the input data at the first input terminal of the first selector is a first specified value, it selects the first comparator to judge the data output from the second output terminal of the first data transmission module; and when it determines that the input data at the first input terminal of the first selector is a second specified value, it selects the second comparator to judge the data output from the second output terminal of the first data transmission module. The second selector includes a first input terminal for receiving data output from the second data receiving terminal, a second input terminal for receiving output data from the third comparator, a third input terminal for receiving output data from the fourth comparator, and an output terminal for outputting data to the second data receiving module. The third comparator includes an input for receiving data output from the second transmitting end and an output for outputting a comparison result to the second selector. The fourth comparator includes an input for receiving data output from the second transmitting end and an output for outputting a comparison result to the second selector.

2. The system as described in claim 1, characterized in that, When the second selector determines that the input data at the first input terminal of the second selector is a first specified value, it uses the third comparator to judge the data output from the second output terminal of the second data transmission module; and when the second selector determines that the input data at the first input terminal of the second selector is a second specified value, it uses the fourth comparator to judge the data output from the second output terminal of the second data transmission module.

3. The system as described in claim 1 or 2, characterized in that, The system also includes a first delay module and a second delay module. The output of the first delay module is connected to the first input of the first selector and is used to synchronize the signals received by the first input and the second input of the first selector. The output of the second delay module is connected to the second input of the second selector to synchronize the signals received by the first input and the second data terminal of the second selector.

4. The system as described in claim 2, characterized in that, The first data sending module further includes a first data buffer module, the output of which is connected to the input of the first sending end, and is used to buffer the data to be sent to the first sending end; The first data receiving module further includes a second data buffer module and a first receiving end. The input end of the second data buffer module is connected to the output end of the first signal selection module and is used to buffer the output data of the first signal selection module. The output end of the second data buffer module is connected to the first receiving end of the first data receiving module. The first receiving end of the first data receiving module is used to send the output data of the second data buffer module to the first data control module. The second data sending module further includes a third data buffer module, the output of which is connected to the input of the second sending end, and is used to buffer the data to be sent to the second sending end; The second data receiving module further includes a fourth data buffer module and a second receiving end. The input end of the fourth data buffer module is connected to the output end of the second signal selection module and is used to buffer the output data of the second signal selection module. The output end of the fourth data buffer module is connected to the second receiving end of the second data receiving module and the second receiving end of the second data receiving module is used to send the output data of the fourth data buffer module to the second data control module.

5. An electronic device, characterized in that, The electronic device includes the real-time bidirectional data transmission system for inter-chip communication as described in any one of claims 1 to 4.

6. A core element, characterized in that, The chip includes the real-time bidirectional data transmission system for inter-chip communication as described in any one of claims 1 to 4.

7. A chip, characterized in that, The chip includes the real-time bidirectional data transmission system for inter-chip communication as described in any one of claims 1 to 4.

8. An integrated circuit, characterized in that, The integrated circuit includes the real-time bidirectional data transmission system for inter-chip communication as described in any one of claims 1 to 4.

9. A method for real-time bidirectional data transmission between chips, characterized in that, The method is applied to the real-time bidirectional data transmission system between chips according to claim 1, and the method includes: The data sent by the first data sending module is determined by the first selector; When the first selector determines that the data sent by the first data sending module is a first specified value, a first comparator is selected to eliminate the data sent by the first sending end from the superimposed data output from the first sending end, thereby obtaining the data sent by the second sending end; and when the first selector determines that the data sent by the first data sending module is a second specified value, a second comparator is selected to eliminate the data sent by the first sending end from the superimposed data output from the first sending end, thereby obtaining the data sent by the second sending end, wherein the superimposed data is the superimposed data of the data sent by the first sending end and the data sent by the second sending end on the transmission link between the first sending end and the second sending end.

10. A device for real-time bidirectional data transmission between chips, characterized in that, The device is applied to the real-time bidirectional data transmission system between chips as described in claim 1, comprising: A determining module is used to determine the data sent by the first data sending module through a first selector; The selection module is configured to, when the data sent by the first data sending module is determined to be a first specified value by the first selector, select a first comparator to eliminate the data sent by the first sending end from the superimposed data output from the first sending end, thereby obtaining the data sent by the second sending end; and, when the data sent by the first data sending module is determined to be a second specified value by the first selector, select a second comparator to eliminate the data sent by the first sending end from the superimposed data output from the first sending end, thereby obtaining the data sent by the second sending end, wherein the superimposed data is the superimposed data of the data sent by the first sending end and the data sent by the second sending end on the transmission link between the first sending end and the second sending end.

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