A Boundary Scan-Based Test Method for 659 Bus Input Boards

Abstract

This invention relates to the field of internal circuit testing technology for airborne equipment, specifically a boundary scan-based testing method for 659 bus input boards. The method includes: Step 1, designing the 659 bus main control board and test resource boards, designing the timing and control logic, and the industrial computer test control program; Step 2, connecting the 659 bus main control board, test resource boards, boundary scan controller, and industrial computer, and connecting the 659 bus main control board, test resource boards, and boundary scan controller to the board under test; Step 3, performing 659 bus testing; Step 4, performing input acquisition testing, including AD conversion testing and discrete input testing; Step 5, performing self-test functionality testing. This invention enables rapid fault location of 659 bus input boards, significantly reducing waste in the production process, saving resources, and lowering costs; it also features a simple structure, reliable operation, and strong applicability; and improves the testing and maintenance capabilities of airborne products.

Description

Technical Field

[0001] This invention relates to the field of airborne equipment internal circuit testing technology, specifically a 659 bus input board testing method based on boundary scan. Background Technology

[0002] With the increasing integration and modularity of airborne systems in new aircraft, a large number of highly reliable baseboard buses are used for communication between modules. The Arinc659 bus, as a new type of baseboard bus in new aircraft, is widely used in airborne products due to its high transmission rate and strong error correction capability.

[0003] Current airborne equipment is becoming increasingly complex and integrated, leading to higher maintenance costs. Since each airborne module is a fundamental component of electronic products, its functions are complex, its usage characteristics vary, and its failure modes are highly uncertain. A prominent problem is that performance-based testing and diagnostic methods struggle to quickly and accurately test module performance and diagnose module faults. Analog signals cannot yet be completely replaced by digital signals in electronic circuits, and mixed-signal technology combining digital and analog circuits is rapidly developing and being widely applied. Statistical analysis of module failures shows that analog circuits have a relatively higher failure rate.

[0004] The Arinc659 bus board has a complex architecture, typical of 659 bus boards. It includes multiple analog inputs, multiple discrete input types, an Arinc659 baseboard bus, an Actel encrypted FPGA (APA600), no FPGA control logic, various internal self-tests, and the HK659 does not support boundary scan, making it impossible to conduct tests based on a single technology.

[0005] For the reasons mentioned above, this invention proposes a 659 bus input board testing method based on boundary scan, which can be tested independently of the entire airborne equipment. Summary of the Invention

[0006] To address the aforementioned technical problems, this invention proposes a boundary scan-based testing method for 659 bus input boards. Based on boundary scan testing technology, a basic 659 bus main control board is designed, along with related hardware resource circuits and software programs, to implement self-testing and functional testing of the input board. This invention is applicable to fault location and performance testing of functional board circuits based on boundary scan testing technology and the Arinc659 baseboard bus, effectively reducing costs and simplifying operation.

[0007] The technical problem to be solved by this invention is achieved by the following technical solution:

[0008] A boundary scan-based testing method for a 659 bus input board includes the following steps:

[0009] Step 1: Design the 659 bus main control board and test resource board, design the timing and control logic and the industrial computer test control program;

[0010] Step 2: Connect the 659 bus main control board, test resource board, and boundary scan controller to the industrial computer, and connect the 659 bus main control board, test resource board, and boundary scan controller to the board under test respectively.

[0011] Step 3: After powering on, keep the boundary scan controller in its default state. The FPGA in the board under test will work normally. The industrial computer and the 659 bus main control board will communicate via Ethernet to perform 659 bus testing.

[0012] Step 4: The industrial control computer communicates with the test resource board via USB. The analog signal to be sent and the connection channel on the programmable test resource board are sent to the input port of the board under test, and the output self-test voltage is set to 0V. Input acquisition test is performed, which includes AD conversion test and discrete input test.

[0013] Step 5: The industrial control computer communicates with the test resource board via USB, the analog signals of all channels are programmed to be 0V, and the self-test output voltage is set to a fixed value and sent to the self-test voltage input port of the board under test to perform self-test function test.

[0014] As a further improvement of the present invention, the 659 bus main control board described in step one is based on the GJB289BRM controller, has a built-in SOC chip, is a PCI bus main controller, and runs the VXWORKS operating system.

[0015] As a further improvement of the present invention, the test resource board described in step one is based on an STM32F407 controller, which controls the FPGA chip to process data.

[0016] As a further improvement of the present invention, the timing and control logic described in step one includes the internal control program of the STM32F407 controller on the test resource board, the FPGA control logic on the test resource board, and the 659 bus main control board program.

[0017] As a further improvement to the present invention, the 659 bus test in step three is as follows:

[0018] Step 1: Under the control of the industrial control computer, the 659 bus main control board is connected to the 659 bus of the board under test;

[0019] Step 2: Read register data to determine the working status of the HK659 bus and perform tests on the HK659 bus controller and transceiver.

[0020] As a further improvement to the present invention, the AD conversion test in step four is as follows:

[0021] Step 1: Use the boundary scan controller to select the analog signal channel to be tested using the FPGA;

[0022] Step 2: Call the boundary scan controller to start the AD conversion control using the FPGA, and after a delay, read the output data of the AD conversion and analyze the results;

[0023] Step 3: Test all 32 AD conversion channels sequentially using the above testing methods.

[0024] As a further improvement to the present invention, the discrete input test in step four is specifically as follows:

[0025] Step 1: The industrial control computer controls the discrete quantities and connection channels to be sent by the test resource board and sends them to the input port of the board under test;

[0026] The second step is to use the FPGA to control the self-test control to be turned off by calling the boundary scan controller. At the same time, the FPGA is used to select the discrete input channels to be tested. There are six groups of discrete input channels, with 16 discrete input channels in each group.

[0027] Step 3: Next, call the boundary scan controller to read the digital signal of the corresponding port and analyze the results;

[0028] Step 4: Follow the above test steps to complete the test of six groups of discrete inputs, totaling 96 channels.

[0029] As a further improvement to the present invention, the self-test function test in step five is as follows:

[0030] Step 1: Use the FPGA to select any channel of the analog quantity group A to be tested by calling the boundary scan controller;

[0031] Step 2: Next, the boundary scan controller is invoked to start the AD conversion control using the FPGA, and after a delay, the output data of the AD conversion is read and the result is analyzed.

[0032] Step 3: Complete the test of the A / D conversion channel of Group B according to the above test method and analyze the results;

[0033] Step 4: The discrete outputs of all test resource boards controlled by the industrial control computer are disconnected;

[0034] Step 5: Then, by calling the boundary scan controller, the FPGA is used to control the self-test to start. The FPGA is used to select the discrete input channels to be tested, 16 at a time.

[0035] Step 6: Next, call the boundary scan controller to read the six sets of discrete input digital signals in sequence and analyze the results.

[0036] The beneficial effects of this invention are:

[0037] This invention provides a boundary scan-based testing method for 659 bus input boards, which can quickly locate faults in 659 bus input boards, greatly reducing waste in the production process, saving resources, and lowering costs. It also features a simple structure, reliable operation, strong applicability, and excellent practicality. Furthermore, it reduces the workload of personnel and improves the testing and maintenance capabilities of airborne products. Attached Figure Description

[0038] The present invention will be further described below with reference to the accompanying drawings and embodiments:

[0039] Figure 1 This is a schematic diagram of the test equipment connection during the testing of this invention;

[0040] In the diagram: 1. Industrial computer; 2. 659 bus main control board; 3. Test resource board; 4. Boundary scan controller; 5. Board under test. Detailed Implementation

[0041] To make the technical means, creative features, objectives and effects of this invention easier to understand, the invention will be further described below in conjunction with the accompanying drawings and embodiments.

[0042] A boundary scan-based testing method for a 659 bus input board includes the following steps:

[0043] Step 1: Design the 659 bus main control board 2 and test resource board 3, and design the timing and control logic and industrial computer test control program.

[0044] The 659 bus main control board 2 is based on the GJB289BRM controller, with a built-in SOC chip, PCI bus main control, running the VXWORKS operating system, and communicating with an external industrial control computer via Ethernet. The GJB289BRM interacts with the HK659 chip through the PCI bus to control the 659 baseboard bus and provide control of the 659 baseboard bus for the board under test.

[0045] The test resource board 3 is based on an STM32F407 controller and communicates with the industrial computer via USB 2.0. The STM32F407 controls the FPGA chip to process data, using optocouplers to implement 84 low-voltage outputs and 12 27V open-circuit outputs; using DA converters and analog switches to implement 36 analog outputs; and using a 74LS245 to implement 16 digital I / O channels, among other test resources. Simultaneously, the test resources are connected to the 659 bus input board under test and the 659 baseboard bus control motherboard connection socket (only providing the 659 baseboard bus transmission channel, without level processing) via connectors. This is used to provide various input signals to the board under test.

[0046] The main components of timing and control logic are:

[0047] Test the internal control program of the STM32F407 controller on the resource board: parse and test the USB control commands of the industrial control computer, exchange data with the FPGA, USB interface driver, DA conversion and channel switching, etc.

[0048] Test resource board FPGA control logic: interface with STM32F407 controller, data exchange, control output relay, optocoupler output, digital I / O, etc.

[0049] HK659 baseboard bus control motherboard program: This program runs on the VxWorks operating system and includes Ethernet driver, PCI driver, HK659 driver, baseboard bus control, Ethernet command processing, etc.

[0050] The industrial control computer test control program mainly communicates with the 659 baseboard bus control motherboard and test resource board to realize program control, calls the boundary scan controller API interface control program to control the FPGA board under test, and forms the entire automated test program according to the test method.

[0051] Step 2: Connect the 659 bus main control board 2, test resource board 3, and boundary scan controller 4 to the industrial computer 1. Then connect the 659 bus main control board 2, test resource board 3, and boundary scan controller 4 to the board under test 5. See the connection diagram below. Figure 1 As shown, the industrial computer 1 serves as the core control unit, communicating with the 659 bus main control board 2 via host computer software; controlling the boundary scan controller 4; and connecting to and programmably controlling the test resource board 3. Simultaneously, the industrial computer 1 comprehensively controls and collects various data, gathers test results, and generates test reports, etc.

[0052] Boundary scan controller 4 controls the FPGA chip on the main control board based on the IEEE 1149.1 protocol, and controls the analog quantity section based on the internal resources of the board under test 5. Boundary scan controller 4 communicates with industrial computer 1 via USB 2.0.

[0053] Step 3: After powering on, maintain the default state of the boundary scan controller 4. The FPGA in the board under test 5 is working normally. The industrial computer 1 and the 659 bus main control board 2 communicate via Ethernet to perform 659 bus testing. Under the control of the industrial computer 1, the 659 bus main control board 2 is connected to the 659 bus of the board under test 5. Read the register data to determine the working status of the 659 bus and realize the testing of the HK659 bus controller and transceiver.

[0054] Step 4: The industrial control computer 1 communicates with the test resource board 3 via USB. The analog signal to be sent and the connection channel on the programmable test resource board 3 are sent to the input port of the board under test 5, and the output self-test voltage is set to 0V. Input acquisition test is performed, which includes AD conversion test and discrete input test.

[0055] AD conversion test;

[0056] Call the boundary scan controller 4 to select the analog channel to be tested using the FPGA; call the boundary scan controller 4 to start the AD conversion control using the FPGA, and read the output data of the AD conversion after a delay and analyze the results; complete the test of 32 AD conversion channels in sequence according to the above test method.

[0057] Discrete input testing;

[0058] The industrial control computer 1 controls the discrete quantities and connection channels to be sent by the test resource board 3 and sends them to the input ports of the board under test 5. Then, by calling the boundary scan controller 4, the self-test control is turned off by the FPGA. At the same time, the FPGA selects the discrete input channels to be tested. There are six groups of discrete input channels, with 16 discrete input channels in each group. Then, the boundary scan controller 4 reads the digital signals of the corresponding ports and analyzes the results. The test of the six groups of 96 discrete inputs is completed in sequence according to the above test steps.

[0059] Step 5: The industrial control computer 1 communicates with the test resource board 3 via USB. The analog signals of all channels are programmed to be 0V, and the self-test output voltage is set to a fixed value, which is then sent to the self-test voltage input port of the board under test 5 to perform a self-test function test. The boundary scan controller 4 is invoked to use the FPGA to select any channel of the analog quantity group A to be tested. Then, the boundary scan controller 4 is invoked to use the FPGA to start the AD conversion control, and after a delay, the AD conversion output data is read and the results are analyzed. The test of the AD conversion channels of group B is completed according to the above test method, and the results are analyzed.

[0060] The industrial control computer 1 controls the discrete output of all components 3 of the test resource board to be disconnected; then, by calling the boundary scan controller 4, the self-test control is enabled by the FPGA. The FPGA selects the discrete input channels to be tested, 16 at a time; then the boundary scan controller 4 reads the digital signals of the six discrete inputs in sequence and analyzes the results.

[0061] The control commands of the 659 baseboard bus control motherboard, the boundary scan API interface, and the programming methods of the test resource board are integrated to form an automatic test program, realizing fully automatic testing of 659 bus input boards.

[0062] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely prisms of the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the present invention as claimed. The scope of protection of this invention is defined by the appended claims and their equivalents.

Claims

1. A test method for a 659 bus input board based on boundary scan, characterized in that: Includes the following steps: Step 1: Design the 659 bus main control board (2) and test resource board (3), and design the timing and control logic and industrial computer test control program; The 659 bus main control board (2) communicates with an external industrial computer via Ethernet, interacts with the HK659 chip via PCI bus, controls the 659 baseboard bus, and provides control of the 659 baseboard bus of the board under test; The test resource board (3) communicates with the industrial control computer based on USB2.0, controls the FPGA chip to process data, uses optocouplers to realize 84 low-voltage outputs and 12 27V open outputs, uses DA converters and analog switches to realize 36 analog outputs, and connects the test resources to the 659 bus input board under test and the 659 baseboard bus control motherboard connection socket through connectors. Step 2: Connect the 659 bus main control board (2), test resource board (3), boundary scan controller (4) to the industrial computer (1), and connect the 659 bus main control board (2), test resource board (3), boundary scan controller (4) to the board under test (5) respectively. Step 3: After powering on, keep the boundary scan controller (4) in its default state. The FPGA in the board under test (5) works normally. The industrial computer (1) and the 659 bus main control board (2) communicate via Ethernet to perform 659 bus testing. Step 4: The industrial control computer (1) communicates with the test resource board (3) via USB. The analog signal to be sent and the connection channel on the programmable test resource board (3) are sent to the input port of the board under test (5), and the output self-test voltage is set to 0V. Input acquisition test is performed. Input acquisition test includes AD conversion test and discrete input test. Step 5: The industrial control computer (1) communicates with the test resource board (3) via USB. The analog signals of all channels are programmed to be 0V, and the self-test output voltage is set to a fixed value and sent to the self-test voltage input port of the board under test (5) to perform self-test mode function test.

2. The 659 bus input board testing method based on boundary scan according to claim 1, characterized in that: The 659 bus main control board (2) mentioned in step one is based on the GJB289BRM controller, with a built-in SOC chip, PCI bus main control, and running the VXWORKS operating system.

3. The 659 bus input board testing method based on boundary scan according to claim 1, characterized in that: The test resource board (3) mentioned in step one is based on the STM32F407 controller, which controls the FPGA chip to process data.

4. The 659 bus input board testing method based on boundary scan according to claim 1, characterized in that: The timing and control logic described in step one includes the internal control program of the STM32F407 controller on the test resource board, the FPGA control logic on the test resource board, and the 659 bus main control board program.

5. The 659 bus input board testing method based on boundary scan according to claim 1, characterized in that: The specific steps for the 659 bus test in step three are as follows: Step 1: Under the control of the industrial computer (1), the 659 bus main control board (2) is connected to the 659 bus of the board under test (5); Step 2: Read register data to determine the working status of the HK659 bus and perform tests on the HK659 bus controller and transceiver.

6. The 659 bus input board testing method based on boundary scan according to claim 1, characterized in that: The AD conversion test in step four is as follows: Step 1: Call the boundary scan controller (4) to select the analog signal channel to be tested using the FPGA; Step 2: Call the boundary scan controller (4) to start the AD conversion control using the FPGA, and after a delay, read the output data of the AD conversion and analyze the results; Step 3: Test all 32 AD conversion channels sequentially using the above testing methods.

7. The 659 bus input board testing method based on boundary scan according to claim 1, characterized in that: The discrete input test in step four is as follows: Step 1: The industrial control computer (1) controls the discrete quantity and connection channel to be sent by the test resource board (3) and sends it to the input port of the board under test (5); Step 2: Then, by calling the boundary scan controller (4), the FPGA is used to control the self-test control to be in the off state. At the same time, the FPGA is used to select the discrete input channels to be tested. There are six groups of discrete input channels, with 16 discrete input channels in each group. Step 3: Next, call the boundary scan controller (4) to read the digital signal of the corresponding port and analyze the results; Step 4: Follow the above test steps to complete the test of six groups of discrete inputs, totaling 96 channels.

8. The 659 bus input board testing method based on boundary scan according to claim 1, characterized in that: The self-test function test in step five is as follows: Step 1: By calling the boundary scan controller (4), the FPGA is used to select any channel of the analog quantity A group to be tested; Step 2: Next, call the boundary scan controller (4) to start the AD conversion control using the FPGA, and after a delay, read the output data of the AD conversion and analyze the results; Step 3: Complete the test of the A / D conversion channel of Group B according to the above test method and analyze the results; Step 4: Industrial computer (1) controls test resource board (3) all output discrete quantities are disconnected; Step 5: Then, by calling the boundary scan controller (4), the FPGA is used to control the self-test control to the start state, and the FPGA is used to select the discrete input channels to be tested, 16 at a time; Step 6: Next, call the boundary scan controller (4) to read the six sets of discrete input digital signals in sequence and analyze the results.

Images