Configuring PCI high-speed modules using hardware in memory subsystem

Abstract

The invention relates to configuring PCI high-speed modules using hardware in a memory subsystem. The first set of parameter values is programmed to a first set of sequencer registers. A second set of parameter values is programmed to a second set of sequencer registers. In response to detecting a trigger event, a hardware sequencer performs the following: transferring the first set of parameter values from the first set of sequencer registers to a first set of link training registers; transferring the second set of parameter values from the second set of sequencer registers to a second set of link training registers; and initiating, by the host, one end of the communication link training.

Description

Technical Field

[0001] Embodiments of the present disclosure relate generally to memory subsystems, and more specifically, to configuring Peripheral Component Interconnect Express (PCI Express or "PCIe") using hardware in a memory subsystem. Background Art

[0002] The memory subsystem may include one or more memory devices that store data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. In general, the host system may utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the invention

[0003] One aspect of the present disclosure relates to a memory subsystem, comprising: a memory device; a hardware sequencer comprising a plurality of sequencer registers; a processing device operatively coupled to the memory device to perform operations comprising: programming a first set of parameter values ​​to a first set of sequencer registers among the plurality of sequencer registers, and programming a second set of parameter values ​​to a second set of sequencer registers among the plurality of sequencer registers; and in response to detecting a trigger event, the hardware sequencer performs operations comprising: transferring the first set of parameter values ​​from the first set of sequencer registers to a first set of link training registers among a plurality of link training registers of the memory subsystem; transferring the second set of parameter values ​​from the second set of sequencer registers to a second set of link training registers among the plurality of link training registers of the memory subsystem; and initiating one end of communication link training by a host.

[0004] Another aspect of the present disclosure relates to a method, comprising: programming, by a processing device, a first set of parameter values ​​to a first set of sequencer registers among a plurality of sequencer registers of a memory subsystem, and programming a second set of parameter values ​​to a second set of sequencer registers among a plurality of sequencer registers; and in response to detecting a trigger event, performing, by a hardware sequencer, operations including: transferring the first set of parameter values ​​from the first set of sequencer registers to a first set of link training registers among a plurality of link training registers of the memory subsystem; transferring the second set of parameter values ​​from the second set of sequencer registers to a second set of link training registers among a plurality of link training registers of the memory subsystem; and initiating, by a host, one end of communication link training.

[0005] Yet another aspect of the present disclosure relates to a computer-readable, non-transitory storage medium comprising executable instructions which, when executed by a controller managing a memory device comprising a plurality of memory cells, cause the controller to: program a first set of parameter values ​​to a first set of sequencer registers among a plurality of sequencer registers of a memory subsystem, and program a second set of parameter values ​​to a second set of sequencer registers among a plurality of sequencer registers; and in response to detecting a trigger event, perform operations by a hardware sequencer comprising: transferring the first set of parameter values ​​from the first set of sequencer registers to a first set of link training registers among a plurality of link training registers of the memory subsystem; transferring the second set of parameter values ​​from the second set of sequencer registers to a second set of link training registers among a plurality of link training registers of the memory subsystem; enabling a configuration mode of the memory subsystem, wherein the configuration mode permits a host to obtain values ​​from the plurality of link training registers; and initiating, by the host, one end of communication link training. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments of the present disclosure. However, the drawings should not be considered to limit the present disclosure to specific embodiments, but are only for explanation and understanding.

[0007] Figure 1 An example computing system including a memory subsystem according to some embodiments of the present disclosure is described.

[0008] Figure 2 An example of a hardware implementation of a memory subsystem and a hardware sequencer is described.

[0009] Figure 3 is a flowchart of an example method according to some embodiments of the present disclosure.

[0010] Figure 4 is a flowchart of an example method according to some embodiments of the present disclosure.

[0011] Figure 5 is a block diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0012] Various aspects of the present disclosure relate to configuring a Peripheral Component Interconnect Express (PCI Express or "PCIe") using hardware in a memory subsystem. The memory subsystem may be a storage device, a memory module, or a combination of a storage device and a memory module. Figure 1 Examples of storage devices and memory modules are described. In general, a host system may utilize a memory subsystem that includes one or more components, such as a memory device, that stores data. The host system may provide data to be stored at the memory subsystem and may request retrieval of data from the memory subsystem.

[0013] The memory subsystem may include a high-density non-volatile memory device where data needs to be retained when power is not supplied to the memory device. An example of a non-volatile memory device is a NAND memory device. Figure 1 Other examples of nonvolatile memory devices are described. A nonvolatile memory device is a package of one or more dies. Each die may include one or more planes. For some types of nonvolatile memory devices (e.g., NAND devices), each plane includes a set of physical blocks. Each block includes a set of pages. Each page includes a set of memory cells ("cells"). A cell is an electronic circuit that stores information. Depending on the cell type, a cell may store one or more binary bits of information and have various logical states associated with the number of bits stored. The logical state may be represented by a binary value such as "0" and "1" or a combination of such values.

[0014] A memory device may be composed of bits arranged in a two-dimensional or three-dimensional grid. Memory cells are formed on a silicon wafer in an array of columns (hereinafter also referred to as bit lines) and rows (hereinafter also referred to as word lines). A word line may have an associated row of memory cells in a memory device, which is used together with one or more bit lines to generate an address for each of the memory cells. The intersection of a bit line and a word line constitutes the address of a memory cell. Hereinafter, a block refers to a unit of a memory device for storing data, and may include a group of memory cells, a group of word lines, a word line, or an individual memory cell. One or more blocks may be grouped together to form a separate partition (e.g., a plane) of a memory device so as to allow parallel operations on each plane. A memory device may include a circuit system that performs parallel memory page accesses of two or more memory planes. For example, a memory device may include a plurality of access line driver circuits and power circuits that may be shared by planes of a memory device to facilitate parallel access of two or more memory planes (including pages of different page types). For ease of description, these circuits may generally be referred to as independent plane driver circuits. Depending on the storage architecture employed, data may be stored across memory planes (i.e., in stripes). Thus, one request to read a segment of data (e.g., corresponding to one or more data addresses) may result in read operations being performed on two or more of the memory planes of the memory device.

[0015] The Compute Express Link (CXL) protocol is a high-speed interconnect standard that enables communication between various components and / or systems. CXL can provide a low-latency, high-bandwidth interface that allows connected systems to share memory and perform common memory-mapped input / output (I / O) operations. When implemented in a memory subsystem, the CXL protocol can improve performance and reduce latency in the system. The CXL protocol supports multiple topologies, including point-to-point topologies, switch-based topologies, daisy-chain topologies, etc. The CXL protocol can be implemented using various physical layer technologies, such as PCI Express ("PCIe") and advanced chip-to-chip signaling. Implementing the CXL protocol on a PCI-E connection can introduce additional complexity associated with PCIe communication requirements. PCIe-based CXL can utilize the physical layer and electrical signaling of the PCIe specification while adding a CXL-specific protocol layer to achieve higher levels of functionality.

[0016] At the protocol layer, CXL adds a set of commands. The CXL protocol is highly sensitive to latency, and components or systems that do not properly implement the CXL protocol may incur latency penalties that reduce or even prohibit the use of the CXL protocol. For example, CXL may allow devices to perform memory access operations (such as read or write operations) on memory areas owned by other systems. In this way, connected systems can share data, reduce expensive data copies between systems, and improve the allocation of physical memory. CXL may include additional features for connected systems, such as memory expansion (which may allow systems to expand memory capacity by accessing memory from connected systems), cache hints (which may allow systems to communicate cache status information to each other), data consistency (which may allow systems accessing shared memory areas to have a consistent view of memory), and various system controls (which may allow systems to control and configure each other).

[0017] At the physical layer, the CXL protocol uses the PCIe physical layer to provide a high-speed, low-latency communication link between systems. For example, the PCIe 5.0 specification may allow the system to support data rates of up to 32GT / s per channel, which means that the total bandwidth of the ×16 link reaches 128GB / s. In some embodiments, the CXL protocol may support link widths of ×2, ×4, and ×8, thereby providing flexibility for different use cases. The PCIe specification defines a set of electrical characteristics (e.g., communication link configuration parameters) that are critical to communication between devices. These communication link configuration parameters may include, for example, requirements for signal levels, timing, jitter, etc., and are designed to facilitate accurate transmission and reception of signals across the PCIe interface. Signal level requirements include, for example, the minimum and maximum voltages of the signal when it is transmitted and received. Signal level requirements may cover transmission and receiver equalization, thereby compensating for signal level attenuation and / or distortion that may occur due to the characteristics of the communication medium. Timing requirements may be strict and may include, for example, maximum rise and fall times, setup and hold times, clock-data skew, etc. Timing requirements may vary based on the application and version of the PCIe specification. Jitter may refer to variations in the timing of a signal (eg, clock signal, data signal) caused by noise and other interference. The PCIe specification includes provisions for jitter testing and mitigation, including specifying maximum jitter values ​​for signals and requiring jitter tolerance testing of devices.

[0018] Communication between two systems based on the PCIe specification can be achieved using a communication link across the PCIe interface. "Communication link training" may refer to the process that two systems (e.g., a host and a client) undergo to establish a communication link on the PCIe physical layer. Communication link training can establish a reliable high-speed communication link between the systems, and can take into account the characteristics of each system, the characteristics of the communication medium, and other factors that may affect the quality of the link. Communication link training may include initialization, idle detection, idle insertion, equalization, negotiation, and verification. During initialization, the systems exchange a predetermined sequence to start a basic communication link. This basic communication link allows the systems to exchange data at a low data rate, and can allow the systems to establish a common reference point for further communication (e.g., by allowing the systems to synchronize their respective clocks, etc.). During idle detection, the system can detect when the communication link is in an idle state (i.e., when no data is transmitted on the link). Detecting the idle state allows the system to synchronize its respective timing and clocks. During idle insertion, each system can insert an idle mode onto the basic communication link. Each system can use the corresponding received idle mode to detect problems with the communication link, such as impedance mismatch or other electrical problems. During equalization, the system can compensate for signal attenuation or distortion that may occur due to the operating conditions and / or characteristics of the communication medium. Equalization can include adjusting the voltage level and timing of the signal to improve the accuracy of the transmitted signal. During negotiation, the system can negotiate various communication link parameters, such as data rate, channel count, encoding scheme, etc., to maximize the speed and efficiency of the communication link. Once the negotiation is complete, the system can perform a final check to verify that the link is operating correctly. During verification, the system can exchange test patterns to confirm that each system is correctly receiving the test pattern at the other end of the link.

[0019] After the communication link training is completed, the client may enable the configuration request retry state (CRS) handling mode. The CRS handling mode allows the client to notify the host that the client is not ready to provide configuration values. When the CRS handling mode is enabled, the client may instruct the host to try the configuration request again. In some embodiments, when the CRS handling mode is enabled, the client may also provide updated parameter values ​​to the host, and the host may retry the configuration request using the updated parameter values. The CRS handling mode may be enabled for the client (e.g., a memory subsystem) until the configuration is successful, until a certain amount of time has passed to reach a certain number of updated requests, etc., or until the client is otherwise disabled. In some embodiments, when a configuration request fails or is not successfully completed, the client may enable the configuration request retry state (CRS) handling mode.

[0020] As discussed above, the PCIe specification includes strict timing requirements for signals, such as maximum rise and fall times, setup and hold times, clock-data skew, etc. These requirements are designed to ensure that the signals are sampled correctly, and data is transmitted and received correctly. In the PCIe 5.0 specification, one timing requirement is that the PCIe system should begin participating in communication link training within 20 milliseconds after receiving a PCIe reset signal. In some cases (e.g., during a cold start), the PCIe 5.0 specification allows a maximum clock stability time (e.g., a waiting period to reduce jitter) of 100 milliseconds, but in some embodiments, even with additional clock stability time, the PCIe system may be difficult or unable to respond within the set period. For example, in some embodiments participating in communication link training, the system may be required to reset and program its corresponding PCIe parameter values, which may be difficult to achieve within the required 20ms or even 120ms. Participating in communication link training requires configuration parameter values ​​for the communication link. For PCIe, these configuration parameters may include physical layer (PHY) parameters and equalization settings (EQ) parameters. The PHY parameter values ​​of the corresponding system may be compensation for physical aspects of the system. These physical aspects may include trace length, electrical component type, manufacturing process / defects, electrical characteristics, etc. The EQ parameter values ​​of the corresponding system may be compensation for the communication link media between the PCIe systems, including compensation for the characteristics of the components (e.g., electrical connectors, sockets, transceivers, etc.) that enable the communication link. The EQ parameter values ​​may be based on the characteristics of the signal received on the communication link, including the strength of the signal (e.g., power), the phase of the signal, the distortion of the signal, the voltage of the signal, the frequency of the signal, etc. The EQ parameter values ​​may also be based on the physical layer that connects the communication medium (e.g., electrical connector) to the corresponding system. The configuration parameter values ​​(i.e., PHY parameter values ​​and EQ parameter values) of the memory subsystem may be adjusted based on the characteristics of the memory subsystem and the characteristics of the corresponding communication system. In some embodiments, these configuration values ​​may be adjusted during the production of the memory subsystem. In some embodiments, these configuration values ​​may be adjusted by the controller of the memory subsystem. In some embodiments, using firmware, PCIe parameter values ​​can be customized for each system connected to the memory subsystem. However, as described above, both CXL and PCIe protocols have strict timing / latency requirements, and in some embodiments, the memory subsystem controller and corresponding firmware may not be able to comply with the strict timing requirements.

[0021] Aspects of the present disclosure address the above and other deficiencies by providing a memory subsystem that uses a hardware sequencer to start a portion of a PCIe link training process. A controller may program parameter values ​​to registers of a hardware sequencer. When a trigger event is detected (e.g., when an automatic release mode is enabled), the hardware sequencer may transfer the parameter values ​​from the registers to link training registers. Subsequently, the hardware sequencer may participate in communication link training with an external device (e.g., a host device). In some embodiments, a configuration mode may be enabled that allows the hardware sequencer to provide parameter values ​​to an external device. In some embodiments, the configuration mode may permit an external device to read values ​​from a link training register. The hardware sequencer may then participate in one end of communication link training. In some embodiments, the hardware sequencer may start configuration of a PCIe communication link in response to an event such as a PCIe reset. In response to a request to start link training, the controller may enable the automatic release mode of the hardware sequencer. The hardware sequencer may then set the PHY parameter values ​​and EQ parameter values ​​required for link training independently of the controller, and then perform one side of link training.

[0022] In some embodiments, the controller may initialize the hardware sequencer with PHY parameter values ​​and EQ parameter values, which is faster than the controller can perform link training. After initializing the hardware sequencer, the controller may perform other operations for the memory subsystem, such as startup operations, firmware operations, memory access operations, etc. In this way, the number of time-sensitive operations that the controller must perform or prepare to perform (sometimes during critical performance periods of the memory subsystem, such as during startup, or during firmware upgrades) can be reduced. In addition, by starting the hardware sequencer and then relying on the hardware sequencer to perform link training, the controller does not have to wait for a link training request, and once the request is received, it interrupts other processes to participate in link training. This allows the controller timing flexibility to perform the preparatory portion of the communication link training (i.e., initialize the hardware sequencer with corresponding values) at any time before receiving a communication link training request. Further details about the hardware sequencer are described below.

[0023] Figure 1 An example computing system 100 is illustrated that includes a memory subsystem 110 in accordance with some embodiments of the present disclosure. Memory subsystem 110 may include media such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of such devices.

[0024] The memory subsystem 110 may be a storage device, a memory module, or a combination of a storage device and a memory module. Examples of storage devices include solid state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage (UFS) drives, secure digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual inline memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual inline memory modules (NVDIMMs).

[0025] The computing system 100 may be a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, drone, train, car, or other transportation vehicle), an Internet of Things (IoT) enabled device, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or a networked commercial device), or such a computing device that includes a memory and a processing device.

[0026] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to multiple memory subsystems 110 of different types. Figure 1 An example of a host system 120 coupled to a memory subsystem 110 is illustrated. As used herein, "coupled to" or "coupled with..." generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without intermediate components), whether wired or wireless, including connections such as electrical connections, optical connections, magnetic connections, etc.

[0027] The host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more cache memories, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 120 uses the memory subsystem 110, for example, to write data to the memory subsystem 110 and read data from the memory subsystem 110.

[0028] The host system 120 may be coupled to the memory subsystem 110 via a physical host interface. Examples of the physical host interface include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, a Fibre Channel, a Serial Attached SCSI (SAS), a Double Data Rate (DDR) memory bus, a Small Computer System Interface (SCSI), a Dual In-line Memory Module (DIMM) interface (e.g., a DIMM socket interface supporting Double Data Rate (DDR)), etc. The physical host interface may be used to transfer data between the host system 120 and the memory subsystem 110. When the memory subsystem 110 is coupled to the host system 120 through a physical host interface (e.g., a PCIe bus), the host system 120 may further utilize an NVM Express (NVMe) interface to access components (e.g., the memory device 130). The physical host interface may provide an interface for passing control, address, data, and other signals between the memory subsystem 110 and the host system 120. Figure 1 Memory subsystem 110 is illustrated as an example. In general, host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0029] The memory devices 130, 140 may include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM) such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0030] Some examples of non-volatile memory devices (e.g., memory device 130) include "NAND" type flash memory and write-in-place memory, such as a three-dimensional cross-point ("3D cross-point") memory device, which is a cross-point array of non-volatile memory cells. The cross-point array of non-volatile memory can perform bit storage based on changes in body resistance in combination with a stackable cross-grid data access array. In addition, in contrast to many flash-based memories, cross-point non-volatile memory can perform write-in-place operations, where non-volatile memory cells can be programmed without pre-erasing the non-volatile memory cells. NAND-type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0031] Each of the memory devices 130 may include one or more memory cell arrays (e.g., memory array 104). One type of memory cell, for example, a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cells (MLC), triple-level cells (TLC), quad-level cells (QLC), and penta-level cells (PLC) may store multiple bits per cell. In some embodiments, each memory device 130 may include one or more memory cell arrays, such as SLC, MLC, TLC, QLC, PLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion and an MLC portion, a TLC portion, a QLC portion, or a PLC portion of memory cells. The memory cells of the memory devices 130 may be grouped into pages, which may refer to a logical unit of a memory device for storing data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0032] Although nonvolatile memory components such as a 3D cross-point nonvolatile memory cell array and NAND-type flash memory (e.g., 2D NAND, 3D NAND) are described, the memory device 130 may be based on any other type of nonvolatile memory, such as read-only memory (ROM), phase change memory (PCM), self-selected memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), "NOR" (NOR) flash memory, or electrically erasable programmable read-only memory (EEPROM).

[0033] The memory subsystem controller 115 (for simplicity, controller 115) can communicate with the memory device 130 to perform operations, such as reading data, writing data, or erasing data and other such operations at the memory device 130. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The hardware may include digital circuitry with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor.

[0034] The memory subsystem controller 115 may include a processing device including one or more processors (e.g., processor 117) configured to execute instructions stored in a local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes an embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120.

[0035] In some embodiments, local memory 119 may include memory registers that store memory pointers, fetched data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Figure 1 The example memory subsystem 110 in FIG. 1 has been illustrated as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115 and may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0036] In general, the memory subsystem controller 115 may receive commands or operations from the host system 120, and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. The memory subsystem controller 115 may be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address conversion between logical addresses (e.g., logical block addresses (LBA), name space) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuit system to communicate with the host system 120 via a physical host interface. The host interface circuit system may convert commands received from the host system into command instructions to access the memory device 130, and convert responses associated with the memory device 130 into information for the host system 120.

[0037] The memory subsystem 110 may also include additional circuitry or components not illustrated. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that may receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0038] In some embodiments, the memory device 130 includes a local media controller 135 that operates in conjunction with the memory subsystem controller 115 to perform operations on one or more memory cells of the memory device 130. An external controller (e.g., the memory subsystem controller 115) can manage the memory device 130 externally (e.g., perform media management operations on the memory device 130). In some embodiments, the memory subsystem 110 is a managed memory device, which is a raw memory device 130 with control logic (e.g., the local media controller 135) located on the die and a controller (e.g., the memory subsystem controller 115) for memory management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0039] The memory subsystem 110 includes a hardware sequencer component 113 that can perform at least a portion of client-side communication link training between the memory subsystem 110 and an external system, such as a host system 120. In some embodiments, the memory subsystem 110 can be connected to an external system, such as a host system 120, to provide additional resources and / or capabilities to the host system 120. As described above, in order for the host system 120 to utilize the resources of the memory subsystem 110, the host system 120 and the memory subsystem need to establish a communication link. As used herein, "client" communication link training can refer to the portion of communication link training that is performed by a system, such as the memory subsystem 110. Conversely, "host-side" communication link training can refer to the portion of communication link training that is performed by an external system, such as a host. For each system (e.g., the host system 120, the memory subsystem 110, etc.), the parameters of the communication link can be different and can depend on the physical structure of the system, the operating conditions, and / or the manufacturing process of one or more corresponding systems. Establishing a communication link through communication link training can be achieved using communication link parameters corresponding to the corresponding system. In some embodiments, the memory subsystem controller 115 may initialize the hardware sequencer component 113 in preparation for client-side communication link training. In some embodiments, a portion of the memory subsystem controller 115 may be dedicated to causing the hardware sequencer component 113 to perform at least a portion of client-side communication link training.

[0040] The hardware sequencer component 113 may include an auto-release register 112 and a link setup register 114. The auto-release register 112 may be initialized by the hardware sequencer component 113 with various values. In some embodiments, a controller (such as a memory subsystem controller 115 or a local media controller 135) may cause the hardware sequencer component 113 to fill the auto-release register 112 with a specific value. The link setup register 114 may be filled with a value from the auto-release register 112. The auto-release register 112 may be designed to release a stored value based on a triggering event (such as a threshold being met, a value of a stored indicator, etc.). When the auto-release register 112 is released, the hardware sequencer component 113 may cause the stored value to be transferred from the auto-release register 112 to the link setup register 114. The value of the link setup register 114 may be made available to an external system (such as a host system 120). In this way, the link setup register 114 may facilitate client-side communication link training (i.e., the portion of communication link training that is the responsibility of the memory subsystem 110). In some embodiments, the memory subsystem controller 115 may include a portion of the hardware sequencer component 113. In some embodiments, the local media controller 135 may cause the hardware sequencer component 113 to perform at least a portion of the client-side communication link training. In some embodiments, the local media controller 135 may include a portion of the hardware sequencer component 113.

[0041] After initialization, the hardware sequencer component 113 may operate independently of the memory subsystem controller 115. In some embodiments, the memory subsystem controller 115 may initialize the hardware sequencer component 113. In some embodiments, the hardware sequencer component 113 may be initialized in response to the memory subsystem being powered on. In some embodiments, the hardware sequencer component 113 may be initialized in response to the memory subsystem 110 being connected to an external system, such as a host system 120. For example, if the memory subsystem 110 is connected to the host system 120 via a PCIe interface (e.g., PCIe 5.0), the hardware sequencer component 113 may be initialized in response to the memory subsystem 110 being properly seated in the PCIe interface connector. The hardware sequencer component 113 and the memory subsystem controller may perform operations in parallel. The hardware sequencer component 113 and the memory subsystem controller may each facilitate client-side communication link training of the memory subsystem 110. The hardware sequencer component 113 may initiate a process for communication link training on the memory subsystem side. The memory subsystem controller 115 may continue the client-side communication link training operation of the memory subsystem 110 initiated by the hardware sequencer component 113. In some embodiments, the memory subsystem controller 115 may control the client-side communication link training operation of the memory subsystem 110 at any time. In some embodiments, the memory subsystem controller 115 and the hardware sequencer component 113 may simultaneously facilitate the client-side communication link training.

[0042] Figure 2 Describe the hardware sequencer 201 and the memory subsystem (such as Figure 1 1. In some embodiments, the hardware sequencer 201 may be a hardware sequencer component (such as, for example, Figure 1 1. The hardware implementation 200 includes a controller 210, a sequencer instruction memory 220, an auto-release register 230, a link training register 240, and a sequencer circuit 250. In this illustrative example, the output from the hardware implementation 200 is represented as a communication link parameter value 260. The hardware implementation 200 can illustrate the connection and function of the illustrative component blocks without regard to the physical or logical location of each illustrative component block. For example, in some embodiments, the hardware sequencer 201 does not include the link training register 240. Whether part of the hardware sequencer 201, part of another component, or a separate component of the memory subsystem, the link training register 240 will operate as described below. Regardless of the physical location of one or more of the illustrative block components, the hardware sequencer 201 and the hardware implementation 200 of the memory subsystem can generate or help generate the communication link parameter value 260.

[0043] The hardware sequencer 201 may perform at least a portion of the client-side communication link training. The hardware sequencer 201 may include an auto-release register 230, a link training register 240, and a sequencer circuit 250. In some embodiments, the hardware sequencer 201 may include a Figure 2 illustratively shown are fewer block components. For example, hardware sequencer 201 may include auto-release register 230 and sequencer circuit 250, but not link training register 240. In some embodiments, hardware sequencer 201 may include fewer block components than those provided by Figure 2 Block components illustratively shown are more block components. For example, hardware sequencer 201 may include auto-release register 230, link training register 240, sequencer circuit 250, and sequencer instruction memory 220. In some embodiments, hardware sequencer 201 may generate communication link parameter value 260.

[0044] The controller 210 may cause the hardware sequencer 201 to perform certain actions. In some embodiments, the controller may cause Figure 2 Controller 210 may initialize hardware sequencer 201. In some embodiments, controller 210 may initialize sequencer circuit 250. In some embodiments, controller 210 may initialize auto-release register 230 and / or link training register 240. In some embodiments, controller 210 may configure sequencer circuit 250. In some embodiments, controller 210 may be a controller, such as, for example, Figure 1 The memory subsystem controller 115 or local media controller 135 is depicted.

[0045] The sequencer instruction memory 220 may provide initialization values ​​for the hardware sequencer 201 for communication link training. The sequencer instruction memory 220 may be used in conjunction with the controller 210 to initialize the hardware sequencer 201. In some embodiments, the sequencer instruction memory 220 may be a portion of the controller 210 as a local memory (e.g., such as the local memory 119 of the memory subsystem controller 115). The values ​​for the sequencer instruction memory 220 may be stored as metadata in a corresponding data structure. The sequencer instruction memory 220 may include initialization settings for the hardware sequencer 201. In some embodiments, the sequencer instruction memory 220 may include initialization settings for the auto-release register 230, the link training register 240, and / or the sequencer circuit 250. In some embodiments, the sequencer instruction memory 220 may include parameter values ​​corresponding to client (e.g., memory subsystem 110) communication link training. In some embodiments, the sequencer instruction memory 220 may include a set of instructions to be executed by a controller (e.g., controller 210) in response to an action performed by the sequencer circuit 250. For example, in response to detecting a triggering event that causes the auto-release register 230 to release a corresponding stored value, the sequencer instruction memory 220 may include an instruction set that causes the controller 210 and / or the hardware sequencer 201 to enable a configuration mode that permits an external system (e.g., a host system, such as a controller 210) to access the auto-release register 230. Figure 1 The host system 120 is depicted reading a communication link parameter value 260 from a memory subsystem (eg, memory subsystem 110).

[0046] The automatic release register 230 may be initialized with a parameter value corresponding to the system (e.g., memory subsystem 110). In response to a triggering event, the automatic release register may release the stored parameter value. In some embodiments, the sequencer circuit 250 may determine the location to release the stored parameter value. In some embodiments, the stored parameter value is released to the link training register 240. The automatic release register 230 may include registers corresponding to various link training parameters. In some embodiments, the automatic release register 230 may include registers to store PHY parameter values. In some embodiments, the automatic release register 230 may include registers to store EQ parameter values.

[0047] The link training registers 240 may include multiple sets of link training registers. In some embodiments, the link training registers 240 may be initialized before receiving values ​​from the auto release registers 230. In some embodiments, the sequencer circuit 250 may determine the location where the link training registers 240 receive stored parameter values. In some embodiments, the link training registers 240 may include registers for receiving PHY parameter values. In some embodiments, the link training registers 240 may include registers for receiving EQ parameter values. In some embodiments, the communication link parameter values ​​260 may be values ​​received by the link training registers 240 and subsequently stored by the link training registers 240.

[0048] The sequencer circuit 250 may include AND gates, OR gates, etc., flip-flops, registers, etc., and various combinations of such hardware components. In some embodiments, the sequencer circuit 250 may include configurable circuit logic, such as, for example, a field programmable gate array (FPGA). In some embodiments, the sequencer circuit 250 may initialize the auto-release register 230 or cause the auto-release register 230 to be initialized. In some embodiments, the sequencer circuit 250 may include a trace connecting the auto-release register 230 to the link training register 240. In some embodiments, before allowing the values ​​released from the auto-release register 230 to be received (e.g., stored) in the link training register 240, the sequencer circuit 250 may perform a hardware-based conversion on those values. In some embodiments, the sequencer circuit 250 may perform a hardware-based conversion on the values ​​stored in the link training register 240.

[0049] The communication link parameter values ​​260 may include client-based parameter values ​​for initiating and establishing a communication link between two systems (e.g., between the memory subsystem 110 and the host system 120). In some embodiments, the value received and subsequently stored in the link training register 240 may be a communication link parameter value. In some embodiments, the communication link parameter value 260 may be a hardware-based translation of the value stored in the link training register 240. The communication link parameter value 260 may be stored in a data structure of the memory subsystem 110. The communication link parameter value 260 may be read by the host system when a specific mode is enabled for the memory subsystem 110. In some embodiments, the specific mode permits the host system 120 to read the value stored in the link training register 240.

[0050] Figure 3300 according to some embodiments of the present disclosure. The method 300 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 300 is performed by Figure 1 The hardware sequencer component 113 of the embodiment of the present invention is executed. Although shown in a specific order or sequence, unless otherwise specified, the order of the process can be modified. Therefore, it should be understood that the illustrated embodiments are only examples, and the illustrated processes can be performed in a different order, and some processes can be performed in parallel. In addition, one or more processes can be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0051] In operation 310, the memory subsystem begins booting, and the controller implementing method 300 loads a boot loader. As described above, the PCIe 5.0 specification may require the PCIe system to begin engaging in communication link training within 20 milliseconds after receiving a PCIe reset signal. The PCIe specification allows a maximum clock stabilization time of 100 milliseconds, and the desired signal may be sent from the PCIe system after the clock has stabilized. In some embodiments, the controller may load the boot loader and then start the firmware (as in operation 320) while adhering to the PCIe 5.0 specification timing for communication link training.

[0052] At operation 320 , the controller starts the firmware. The firmware may allow the controller to manage resources of the memory subsystem and interface with external systems. In some embodiments, operation 320 may be performed after operation 330 .

[0053] At operation 330, the controller initializes a hardware sequencer (such as, for example, Figure 2 The controller may offload certain aspects of PCIe communication link training to the hardware sequencer. In this way, the controller may load the boot loader and boot firmware with minimal interruption while the hardware sequencer manages certain aspects of the communication link training process. The controller may initialize the hardware sequencer with client parameter values ​​(e.g., PHY values, EQ parameter values, etc.) that affect the communication link training process. The hardware sequencer may be configured to respond to a link training trigger. In response to the link training trigger, the hardware sequencer may perform various hardware operations, which are further described below with respect to operation 350. In some embodiments, when operating in a specific mode, the hardware sequencer may respond to the link training trigger. In some embodiments, when a reset signal is detected, the hardware sequencer may be ready to respond to the link training trigger.

[0054] As part of operation 330, at operation 332, the controller programs the PHY parameter values ​​into the auto-release PHY registers. In some embodiments, multiple PHY parameter values ​​may be programmed into the PHY registers. As described above, the PHY parameter values ​​may be affected by physical aspects of the corresponding system (e.g., memory subsystem), including trace lengths, electrical component types, manufacturing processes / defects, other electrical characteristics of the corresponding system, etc. Although PHY parameter values ​​are shown in this illustrative example, these notations are for exemplary purposes only, and it should be understood that the PHY parameter values ​​used for the memory subsystem (e.g., as described with respect to FIG. 1 ) may be used in conjunction with the PHY registers. Figure 1 Any communication link training parameter values ​​described in the memory subsystem 110) are programmed into corresponding registers.

[0055] As part of operation 330, at operation 334, the controller programs the EQ parameter values ​​into the auto-release EQ register. In some embodiments, multiple EQ parameter values ​​may be programmed into the EQ register. As described above, the EQ parameter values ​​are affected by the characteristics of the signal received over the communication link, including the power, phase, distortion, frequency, voltage, etc. of the signal. The EQ parameter values ​​may also be affected by the physical interface between the communication medium (e.g., an electrical connector) and the rest of the corresponding system (e.g., a memory subsystem). Although EQ parameter values ​​are shown in this illustrative example, these labels are for exemplary purposes only, and it should be understood that the EQ parameter values ​​used for the memory subsystem (e.g., as described with respect to FIG. 1 ) may be used in conjunction with the controller. Figure 1 Any communication link training parameter values ​​of the memory subsystem 110 described herein are programmed into corresponding registers. In some embodiments, additional communication link training parameter values ​​may be programmed into additional corresponding registers.

[0056] In some embodiments, the initialization parameter values ​​(e.g., PHY parameter values, EQ parameter values, etc.) may be approximate values. During communication link training, the two systems perform various operations to optimize the communication link between the systems. As part of these operations, the parameter values ​​of each system may be updated to improve the quality of the link. For example, the link may be initiated, but the quality of the communication link may be poor (e.g., may be slow, have high latency, low bandwidth, etc.) due to inaccurate or unoptimized parameter values ​​of either of the two systems. Although the poor quality communication link may degrade the operation between the systems if it is not improved, the poor quality communication link is sufficient for the respective systems to perform communication link training. Communication link training may improve the quality of the communication link so that the communication link may then reach a specified level (e.g., the communication link may comply with various industry standards or protocols, such as PCIe 5.0, CXL, etc.). Therefore, in some embodiments, the parameter values ​​stored in the hardware sequencer and accessed by the external system to initiate communication link training may be sufficient to initiate communication link training. After the communication link training has been initiated, the controller may re-engage in the communication link training and optimize or correct the memory subsystem parameter values ​​as needed to improve the communication link.

[0057] As part of operation 330, in operation 336, in response to completing both operation 332 and operation 334, the controller enables an automatic release mode. In some embodiments, the automatic release mode may be triggered by a port reset of the memory subsystem. A port reset may occur when the memory subsystem is powered off and then powered back on. For example, in order to upgrade the firmware on the memory subsystem, various components of the memory subsystem controller may be power cycled. This process may trigger a port reset. In some embodiments, the automatic release mode may be triggered by other events. For example, during a cold start, the memory subsystem controller may perform multiple functions as quickly as possible to minimize the downtime or latency that the host system may experience. The memory subsystem may require the functions so that the memory subsystem can perform memory access operations without relying on the ability of the memory subsystem to communicate with the host system. As described above, because various industry specifications and protocols (e.g., PCIe 5.0, CXL, etc.) may have strict communication link training timing requirements, in some embodiments, a cold start may trigger a hardware sequencer to perform its operations. In some embodiments, the controller may configure the content that will trigger the automatic release mode. In some embodiments, the automatic release mode may be triggered in response to the controller (or hardware sequencer) detecting a specific value of a stored flag (e.g., a port reset flag, a cold start flag, etc.). In some embodiments, the automatic release mode may be triggered in response to the controller (or hardware sequencer) detecting a change in the value of a stored flag.

[0058] At operation 340, the controller detects a link training trigger. In some embodiments, detecting a link training trigger is performed by a hardware sequencer. In some embodiments, the hardware sequencer may be triggered by the controller. In some embodiments, the hardware sequencer may be triggered by an external system (e.g., such as, for example, Figure 1 In some embodiments, the link training trigger may be a request from an external system (eg, the host system 120) to start link training.

[0059] At operation 350, the hardware sequencer executes the hardware sequencer circuit logic. Figure 1 and Figure 2 As described, the hardware sequencer may release the initialization value from the auto-release register to the link training register. In some embodiments, the hardware sequencer may include additional hardware logic that may perform hardware-based conversions on the values ​​initially stored in the auto-release register and / or the values ​​received and subsequently stored in the link training register. In some embodiments, the hardware sequencer may perform conversions on the values ​​between the time when the values ​​are released from the auto-release register and the time when the values ​​are received by the link training register. In some embodiments, the hardware sequencer may include hardware data structures (e.g., additional registers, latches, flip-flops, etc.) in addition to the auto-release register and the link training register.

[0060] As part of operation 350, at operation 352, the hardware sequencer performs PHY configuration from the PHY repeat register. In some embodiments, performing PHY configuration may include releasing stored values ​​of the PHY registers to corresponding link training registers, such as with respect to Figure 2 Although a PHY configuration with PHY parameter values ​​is shown in this illustrative example, these labels are for exemplary purposes only, and it should be understood that the PHY configuration with PHY parameter values ​​is not used for memory subsystems (e.g., as described with respect to Figure 1 Any communication link training parameter configuration of the memory subsystem 110 described herein may be performed using corresponding registers. In some embodiments, the PHY register of operation 352 may be an auto-release PHY register (eg, a register released in response to a trigger event, value, etc.).

[0061] As part of operation 350, at operation 354, the hardware sequencer performs EQ configuration from the EQ register. In some embodiments, performing EQ configuration may include causing the stored value of the auto-release EQ register to be released to the corresponding EQ link training register, such as with respect to Figure 2 Although an EQ configuration with EQ parameter values ​​is shown in this illustrative example, these labels are for exemplary purposes only, and it should be understood that the EQ configuration used in the memory subsystem (e.g., as described with respect to Figure 1Any communication link training parameter configuration of the memory subsystem 110 described herein may be performed using corresponding registers. In some embodiments, the EQ register of operation 354 may be an automatically released EQ register (e.g., a register released in response to a trigger event, value, etc.). In some embodiments, additional communication link training parameter configurations may be performed using additional corresponding registers.

[0062] As part of operation 350, at operation 356, in response to completing both operation 352 and operation 354, the hardware sequencer enables a configuration request retry state (CRS) handling mode for the memory subsystem. As described above, when enabled, the CRS handling mode allows a client (i.e., a memory subsystem) to initiate a configuration request through a host using a different set of parameter values. The hardware sequencer may be configured to initiate a configuration request through the host using values ​​stored in PHY and EQ link training registers. In some embodiments, with the CRS handling mode enabled, the hardware sequencer may provide parameter values ​​to the host. In some embodiments, the host may be permitted to obtain parameter values ​​by reading values ​​from a designated area of ​​the memory subsystem. In some embodiments, once the host has the parameter values ​​from the link training registers, the host may retry the configuration request using the parameter values ​​from the link training registers. In some embodiments, this designated area may include PHY and EQ link training registers, as described above with respect to Figure 2 As described, the PHY and EQ link training registers have received PHY and EQ parameter values ​​from the auto-release PHY and EQ registers, respectively.

[0063] As part of operation 350, the hardware sequencer facilitates communication link training at operation 358. The hardware sequencer may perform client operations in response to receiving a request from a host system (eg, such as host system 120) to perform communication link training.

[0064] At operation 360, the hardware sequencer configures link training. In some embodiments, the hardware sequencer initiates client-side communication link training. In some embodiments, the controller configures link training. In some embodiments, after the hardware sequencer initiates link training, the controller continues to perform link training. The hardware sequencer can trigger the memory subsystem to enter a specific mode that permits an external system (e.g., host system 120) to read values ​​from specific areas of the memory subsystem (e.g., link training registers of the hardware sequencer). Client link training requires parameter values ​​corresponding to physical aspects of the system (e.g., memory subsystem), and these parameter values ​​are values ​​that can be stored in link training registers. In some embodiments, the hardware sequencer can initiate client operations for communication link training by making the corresponding parameter values ​​available to the external system.

[0065] Figure 4 4 is a flowchart of an example method 400 according to some embodiments of the present disclosure. The method 400 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 400 is performed by Figure 1 The hardware sequencer component 113 of the embodiment of the present invention is executed. Although shown in a specific order or sequence, unless otherwise specified, the order of the process can be modified. Therefore, it should be understood that the illustrated embodiments are only examples, and the illustrated processes can be performed in a different order, and some processes can be performed in parallel. In addition, one or more processes can be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0066] At operation 410, a controller implementing method 400 programs a first set of parameter values ​​into a first set of sequencer registers in a plurality of sequencer registers and a second set of parameter values ​​into a second set of sequencer registers in a plurality of sequencer registers. Figure 2 The described hardware sequencer 201) may include a plurality of sequencer registers.

[0067] In operation 420, in response to detecting a triggering event, the hardware sequencer performs the following operations. The triggering event may include a request from the host to start link training. In some embodiments, the controller may trigger an automatic trigger mode of the hardware sequencer. In some embodiments, detecting the triggering event may include enabling an automatic release mode of the hardware sequencer. The automatic release mode may cause the hardware sequencer to perform operations in response to the link training request. In some embodiments, receiving the link training request may trigger the automatic release mode.

[0068] At operation 430, the hardware sequencer transfers the first set of parameter values ​​from the first set of sequencer registers to a first set of link training registers of a plurality of link training registers of the memory subsystem. In some embodiments, the first set of parameter values ​​may include values ​​of PHY parameters.

[0069] At operation 440, the hardware sequencer transfers the second set of parameter values ​​from the second set of sequencer registers to a second set of link training registers in the plurality of link training registers of the memory subsystem. In some embodiments, the second set of parameter values ​​may include values ​​for EQ parameters.

[0070] In some embodiments, the initialization parameter values ​​(e.g., PHY parameter values, EQ parameter values, etc.) may be approximate values. During communication link training, the two systems perform various operations to optimize the communication link between the systems. As part of these operations, the parameter values ​​for each operation may be updated to improve the quality of the link. For example, a link may be initiated, but the quality of the communication link may be poor (e.g., may be slow, have high latency, low bandwidth, etc.) due to inaccurate or unoptimized parameter values ​​in either of the two systems. Although a poor quality communication link may degrade the operation between the systems if not improved, a poor quality communication link is sufficient for the respective systems to perform communication link training. Communication link training may improve the quality of the communication link so that the communication link may then reach a specified level (e.g., the communication link may comply with various industry standards or protocols, such as PCIe 5.0, CXL, etc.). Therefore, in some embodiments, the parameter values ​​stored in the hardware sequencer and accessed by the external system to initiate communication link training may be sufficient to initiate communication link training. After communication link training has been initiated, the controller may re-engage in communication link training and optimize or correct memory subsystem parameter values ​​as needed to improve the communication link.

[0071] In some embodiments, the hardware sequencer may enable a configuration mode of the memory subsystem. The configuration mode may allow the host to obtain data from multiple link training registers. The configuration mode may enable another configuration of the communication link that was initially established. In some embodiments, the configuration mode of the memory subsystem may include a configuration request retry state (CRS) handling mode. As described above, when enabled, the CRS handling mode may allow the client (i.e., the memory subsystem) to notify the host that the client is not ready to provide configuration values. The client may indicate that the host should try the configuration request again. In some embodiments, the client may indicate that the host should start the configuration request using a different set of parameter values. The hardware sequencer may be configured to provide parameter values ​​to the host using the PHY link training register and the EQ link training register. In some embodiments, the host may be allowed to obtain parameter values ​​by reading values ​​from a specified area of ​​the memory subsystem. In some embodiments, once the host has parameter values ​​from the link training registers, the host can retry the configuration request using the parameter values ​​from the link training registers.

[0072] At operation 450, the hardware sequencer initiates one end of the communication link training. The link training operation may be controlled by an external system, such as a host system. In some embodiments, enabling a configuration mode of the memory subsystem may allow the hardware sequencer to initiate the client side (e.g., portion of the memory subsystem) of the communication link training. In some embodiments, the host system may obtain parameter values ​​from the memory subsystem and perform communication link training using the read parameter values. The values ​​provided by the hardware sequencer to the host system for communication link training may be preliminary values ​​sufficient to establish a basic communication link. In some embodiments, these preliminary values ​​may not be optimized for optimal performance of the communication link. After the hardware sequencer initiates the communication link training (e.g., the memory subsystem side), the controller may re-engage in the communication link training.

[0073] In some embodiments, after communication link training has been initiated, the controller may disable a configuration mode of the memory subsystem. In some embodiments, after communication link training has been initiated, the controller may receive a link training interrupt. In response to receiving the training link interrupt, the controller may perform a peripheral component interconnect express (PCIe) configuration update. In response to receiving the training link interrupt, the controller may perform a compute express link (CXL) configuration update. In some embodiments, the PCIe configuration update and the CXL configuration update are performed simultaneously. In some embodiments, after communication link training has been completed, the controller may enable an operating mode of the memory subsystem. The operating mode of the memory subsystem may allow the host to enumerate the memory subsystem.

[0074] Figure 5 An example machine of a computer system 500 is illustrated within which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In some embodiments, the computer system 500 may correspond to a computer system that includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 A host system (eg, a memory subsystem 110) of Figure 1 host system 120), or can be used to perform operations of the controller (e.g., execute an operating system to perform operations corresponding to Figure 1 In some embodiments, the machine may be connected (e.g., using a network) to other machines in a peer-to-peer (or distributed) network environment, or in the capacity of a server or a client machine in a client-server network environment.

[0075] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions that specify actions to be taken by the machine. Further, while a single machine is described, the term "machine" shall also be construed to include any collection of machines that individually or collectively execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0076] The example computer system 500 includes a processing device 502, a main memory 504 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or RDRAM, etc.), a static memory 506 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 518 that communicate with each other via a bus 530.

[0077] Processing device 502 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, etc. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets, or a processor that implements a combination of instruction sets. Processing device 502 may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, etc. Processing device 502 is configured to execute instructions 526 for performing the operations and steps discussed herein. Computer system 500 may further include a network interface device 508 to communicate over a network 520.

[0078] The data storage system 518 may include a machine-readable storage medium 524 (also referred to as a computer-readable medium) on which is stored one or more sets of instructions 526 or software embodying any one or more of the methods or functions described herein. The instructions 526 may also reside, completely or at least partially, within the main memory 504 and / or within the processing device 502 during execution by the computer system 500, with the main memory 504 and the processing device 502 also constituting machine-readable storage media. The machine-readable storage medium 524, the data storage system 518, and / or the main memory 504 may correspond to Figure 1 Memory subsystem 110.

[0079] In one embodiment, the instructions 526 include instructions for implementing a sequence corresponding to the hardware sequencer component 113 (e.g., Figure 1The term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions for execution by a machine and causing the machine to perform any one or more of the methods of the present disclosure. The term "machine-readable storage medium" should therefore be considered to include, but not be limited to, solid-state memory, optical media, and magnetic media.

[0080] Some portions of the previous detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively convey the substance of their work to others skilled in the art. In this document, and generally, an algorithm is conceived to be a self-consistent sequence of operations that produces a desired result. An operation is one that requires physical manipulation of physical quantities. Typically (but not necessarily), these quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. It has proven convenient at times, primarily for common reasons, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, and the like.

[0081] It should be borne in mind, however, that all of these and similar terms will be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may refer to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0082] The present disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specially constructed for the desired purpose, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. This computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magnetic optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0083] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general purpose systems may be used with programs according to the teachings herein, or it may prove convenient to construct more specialized devices to perform the methods. The structures of various such systems will be presented as set forth in the description below. In addition, the present disclosure is not described with reference to any particular programming language. It should be appreciated that the teachings of the present disclosure as described herein may be implemented using various programming languages.

[0084] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having stored thereon instructions that can be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. The machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, the machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory component, etc.

[0085] In the foregoing description, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made to the present disclosure without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative sense rather than a restrictive sense.

Claims

1. A memory subsystem comprising: Memory device; a hardware sequencer comprising a plurality of sequencer registers; A processing device operatively coupled to the memory device to perform operations comprising: programming a first set of parameter values ​​to a first set of sequencer registers of the plurality of sequencer registers and programming a second set of parameter values ​​to a second set of sequencer registers of the plurality of sequencer registers; and In response to detecting a trigger event, the hardware sequencer performs operations including: transferring the first set of parameter values ​​from the first set of sequencer registers to a first set of link training registers of a plurality of link training registers of the memory subsystem; transferring the second set of parameter values ​​from the second set of sequencer registers to a second set of link training registers of the plurality of link training registers of the memory subsystem; and The host initiates one end of the communication link training.

2. The memory subsystem of claim 1 , wherein detecting the trigger event comprises: enabling an auto-release mode of the hardware sequencer, wherein the auto-release mode causes the hardware sequencer to perform an operation in response to a link training request; and The link training request is received. 3 . The memory subsystem of claim 1 , wherein the first set of parameter values ​​comprises values ​​of physical layer (PHY) parameters, wherein the second set of parameter values ​​comprises values ​​of equalization setting (EQ) parameters. 4 . The memory subsystem of claim 1 , wherein the triggering event comprises a request from the host to start link training.

5. The memory subsystem of claim 1, wherein the plurality of link training registers are included by the hardware sequencer.

6. The memory subsystem of claim 1 , wherein the operations further comprise: A configuration mode of the memory subsystem is enabled, wherein the configuration mode permits the host to obtain values ​​from the plurality of link training registers.

7. The memory subsystem of claim 6, wherein the operations further comprise: deactivating the configuration mode of the memory subsystem; and An operating mode of the memory subsystem is enabled, wherein the operating mode permits the host to enumerate the memory subsystem.

8. The memory subsystem of claim 6, wherein the configuration mode of the memory subsystem comprises a configuration request retry state (CRS) handling mode.

9. The memory subsystem of claim 1 , wherein the operations further comprise: Link training interrupt received; Performing Peripheral Component Interconnect Express (PCIe) configuration updates; and Performs computation of high-speed link CXL configuration updates.

10. A method comprising: programming, by a processing device, a first set of parameter values ​​to a first set of sequencer registers of a plurality of sequencer registers of a memory subsystem and a second set of parameter values ​​to a second set of sequencer registers of the plurality of sequencer registers; and In response to detecting a trigger event, operations performed by the hardware sequencer include: transferring the first set of parameter values ​​from the first set of sequencer registers to a first set of link training registers of a plurality of link training registers of the memory subsystem; transferring the second set of parameter values ​​from the second set of sequencer registers to a second set of link training registers of the plurality of link training registers of the memory subsystem; and The host initiates one end of the communication link training.

11. The method of claim 10, wherein detecting the triggering event comprises: enabling an auto-release mode of the hardware sequencer, wherein the auto-release mode causes the hardware sequencer to perform an operation in response to a link training request; and The link training request is received.

12. The method of claim 10, wherein the first set of parameter values ​​comprises values ​​of physical layer (PHY) parameters, and wherein the second set of parameter values ​​comprises values ​​of equalization setting (EQ) parameters.

13. The method of claim 10, wherein the triggering event comprises a request from the host to start link training.

14. The method of claim 10, wherein the plurality of link training registers are included by the hardware sequencer.

15. The method according to claim 10, comprising: A configuration mode of the memory subsystem is enabled, wherein the configuration mode permits a host to obtain values ​​from the plurality of link training registers.

16. The method according to claim 15, comprising: deactivating the configuration mode of the memory subsystem; and An operating mode of the memory subsystem is enabled, wherein the operating mode permits the host to enumerate the memory subsystem. 17 . The method of claim 15 , wherein the configuration mode of the memory subsystem comprises a configuration request retry state (CRS) handling mode.

18. The method according to claim 10, further comprising: Link training interrupt received; Performing Peripheral Component Interconnect Express (PCIe) configuration updates; and Performs computation of high-speed link CXL configuration updates.

19. A computer-readable non-transitory storage medium comprising executable instructions that, when executed by a controller managing a memory device comprising a plurality of memory units, cause the controller to: programming a first set of parameter values ​​to a first set of sequencer registers of a plurality of sequencer registers of a memory subsystem and programming a second set of parameter values ​​to a second set of sequencer registers of the plurality of sequencer registers; and In response to detecting a trigger event, operations performed by the hardware sequencer include: transferring the first set of parameter values ​​from the first set of sequencer registers to a first set of link training registers of a plurality of link training registers of the memory subsystem; transferring the second set of parameter values ​​from the second set of sequencer registers to a second set of link training registers of the plurality of link training registers of the memory subsystem; enabling a configuration mode of the memory subsystem, wherein the configuration mode permits a host to obtain values ​​from the plurality of link training registers; and One end of the communication link training is initiated by the host.

20. The computer-readable non-transitory storage medium of claim 19, wherein the operations further comprise: enabling an auto-release mode of the hardware sequencer, wherein the auto-release mode causes the hardware sequencer to perform an operation in response to a link training request; and The link training request is received.

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