Data processing method and device, electronic equipment, storage medium and program product

Abstract

The embodiment of the invention provides a data processing method and device, electronic equipment, a storage medium and a program product, and relates to the technical field of chips. The method comprises the following steps: receiving a read-write request sent by a processor; if it is detected that the read-write request carries a refresh synchronization indication, target countdown information is determined based on obtained countdown information corresponding to each DDR channel; and controlling each DDRC to perform synchronous refreshing based on the target countdown information. According to the embodiment of the invention, the refresh synchronization indication is generated based on the type of the data stream corresponding to the read-write request through the refresh synchronization indication generation module of the processor, and when the refresh synchronization module detects that the read-write request carries the refresh synchronization indication, each DDRC is controlled to synchronously refresh based on the target countdown information. Therefore, the refreshing synchronization of the plurality of DDR channels is realized, the prolonging of data loading time caused by the asynchronous refreshing of the plurality of DDR channels is avoided, the data loading time is shortened, and the overall data processing performance of the chip is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of chip technology, and in particular to a data processing method, device, electronic device, storage medium and program product. Background Art

[0002] A SOC chip (System on Chip) is a chip that integrates multiple functional modules. When a SOC chip contains processors with large bandwidth requirements such as NPU (Neural Processing Unit) and GPU (Graphics Processing Unit), these processors often use multiple interleaved paths to increase the design bandwidth when accessing memory. SOC chips also often contain multiple interleaved DDR (Double Data Rate) channels. DDR channels use DRAM (Dynamic Random-Access Memory), which needs to be refreshed regularly to ensure the stability and integrity of memory data.

[0003] When the processor accesses the data stream of multiple DDR channels to load data processing tasks, the refresh of the DDR channels will interrupt the loading of the data stream. Moreover, each DDR channel is an independent state machine. When the refresh of multiple DDR channels does not occur at the same time, the loading time of the entire data stream will be lengthened, reducing the performance of data processing. Summary of the invention

[0004] The embodiments of the present disclosure provide a data processing method, device, electronic device, storage medium and program product, which can solve the problem of long data loading time in the prior art. The technical solutions provided by the present disclosure are as follows: According to one aspect of an embodiment of the present disclosure, a data processing method is provided, which is applied to a refresh synchronization module, wherein the refresh synchronization module is respectively connected to a double data rate controller DDRC corresponding to a plurality of double data rate DDR channels respectively; the method comprises: Receive read and write requests sent by the processor; If it is detected that the read / write request carries a refresh synchronization indication, the target countdown information is determined based on the countdown information corresponding to each DDR channel obtained; wherein the refresh synchronization indication is generated by a refresh synchronization indication generation module in the processor based on the type of data stream corresponding to the read / write request; and the refresh synchronization indication is used to indicate the start of a refresh operation; Based on the target countdown information, each DDRC is controlled to perform synchronous refresh.

[0005] Optionally, the refresh synchronization indication is generated based on the following method: Receiving the read / write request to be transmitted through the refresh synchronization indication generating module, and if it is detected that the read / write request meets the preset condition, adding the refresh synchronization indication to the read / write request; The preset conditions include that the refresh synchronization indication adding operation is not performed within the processing task time period, and the bandwidth of the data stream corresponding to the read and write request is greater than a preset bandwidth threshold within the preset time period.

[0006] Optionally, controlling each DDRC to perform synchronous refresh based on the target countdown information includes: Starting a countdown based on the target countdown information; When the countdown is completed, the DDRCs corresponding to each DDR channel are configured to turn off the automatic refresh function, and each DDRC is configured to perform a refresh operation simultaneously.

[0007] Optionally, the method further comprises: Adding the target countdown information to the read / write request, and sending the read / write request carrying the target countdown information to the DDRCs corresponding to the respective DDR channels; The step of controlling each DDRC to perform synchronous refresh based on the target countdown information includes: For each DDRC, if the DDRC detects that the received read / write request carries the target countdown information and the refresh synchronization indication, the DDRC starts the countdown based on the target countdown information, and performs a refresh operation when the countdown is completed.

[0008] Optionally, if it is detected that the read / write request carries a refresh synchronization indication, determining the target countdown information based on the acquired countdown information corresponding to each DDR channel includes: At every preset period, the countdown information corresponding to each DDR channel is obtained; If it is detected that the read / write request carries a refresh synchronization indication, the target countdown information is determined from the countdown information corresponding to each DDR channel that is acquired most recently.

[0009] Optionally, determining the target countdown information from the countdown information corresponding to each DDR channel obtained most recently includes: The maximum value of the countdown information corresponding to each DDR channel obtained most recently is used as the first countdown information; Based on the first countdown information, the target countdown information is determined; the target countdown information is not less than the first countdown information.

[0010] Optionally, the countdown information corresponding to each DDR channel is obtained based on at least one of the following methods: Sending countdown information of the corresponding DDR channels to the refresh synchronization module through each DDRC; The DDR physical layer interfaces corresponding to the respective DDR channels are connected through the refresh synchronization module to collect countdown information corresponding to the respective DDR channels.

[0011] According to another aspect of an embodiment of the present disclosure, a data processing method is provided, which is applied to a refresh synchronization indication generating module in a processor, wherein the processor is connected to the refresh synchronization module, and the refresh synchronization module is respectively connected to double data rate controllers DDRC corresponding to a plurality of double data rate DDR channels, wherein the method comprises: Receive read and write requests to be transmitted; If it is detected that the read / write request meets the preset conditions, the refresh synchronization indication is added to the read / write request; wherein the preset conditions include that the refresh synchronization indication adding operation is not performed within the processing task time period, and the bandwidth of the data stream corresponding to the read / write request is greater than the preset bandwidth threshold within the preset time period; The read / write request is sent to the refresh synchronization module, so that if the refresh synchronization module detects that the read / write request carries a refresh synchronization indication, the target countdown information is determined based on the countdown information corresponding to each DDR channel obtained, and each DDRC is controlled to perform synchronous refresh based on the target countdown information.

[0012] According to another aspect of the embodiments of the present disclosure, a chip is provided, the chip comprising a processor, a chip network, a refresh synchronization module and a double data rate controller DDRC corresponding to a plurality of double data rate DDR channels respectively; the processor comprises a refresh synchronization indication generation module; The refresh synchronization module is connected to each DDRC respectively; the refresh synchronization module is connected to the processor through the chip network; The refresh synchronization module is used to execute the data processing method provided based on any optional embodiment of the present disclosure.

[0013] According to another aspect of an embodiment of the present disclosure, there is provided a data processing device, the device comprising: A first receiving module, used for receiving a read / write request sent by a processor; a countdown determination module, configured to determine target countdown information based on the countdown information corresponding to each DDR channel obtained if it is detected that the read / write request carries a refresh synchronization indication; wherein the refresh synchronization indication is generated by the refresh synchronization indication generation module in the processor based on the type of data stream corresponding to the read / write request; and the refresh synchronization indication is used to indicate the start of a refresh operation; The synchronous refresh control module is used to control each DDRC to perform synchronous refresh based on the target countdown information.

[0014] According to another aspect of an embodiment of the present disclosure, there is provided a data processing device, the device comprising: A second receiving module, used for receiving a read / write request to be transmitted; A refresh synchronization indication adding module, used for adding the refresh synchronization indication to the read / write request if it is detected that the read / write request meets a preset condition; wherein the preset condition includes that the refresh synchronization indication adding operation is not performed within the processing task time period, and the bandwidth of the data stream corresponding to the read / write request is greater than a preset bandwidth threshold within the preset time period; The sending module is used to send the read / write request to the refresh synchronization module, so that if the refresh synchronization module detects that the read / write request carries a refresh synchronization indication, the target countdown information is determined based on the countdown information corresponding to each DDR channel obtained, and each DDRC is controlled to perform synchronous refresh based on the target countdown information.

[0015] According to another aspect of an embodiment of the present disclosure, an electronic device is provided, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor, and the processor implements the steps of any one of the above-mentioned data processing methods when executing the program.

[0016] According to another aspect of the embodiments of the present disclosure, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above-mentioned data processing methods are implemented.

[0017] According to one aspect of an embodiment of the present disclosure, a computer program product is provided, which includes a computer program, and when the computer program is executed by a processor, the steps of any of the above-mentioned data processing methods are implemented.

[0018] The technical solution provided by the embodiments of the present disclosure has the following beneficial effects: By generating a refresh synchronization indication based on the type of data stream corresponding to the read / write request in the refresh synchronization indication generation module of the processor, and controlling each DDRC to refresh synchronously based on the target countdown information when detecting that the read / write request carries a refresh synchronization indication through the refresh synchronization module, refresh synchronization of multiple DDR channels is achieved, thereby avoiding the extension of data loading time caused by the asynchronous refresh of multiple DDR channels, shortening the data loading time, and improving the overall data processing performance of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for describing the embodiments of the present disclosure are briefly introduced below.

[0020] Figure 1 A schematic diagram of the time axis of multi-channel data loading in the case of refresh synchronization; Figure 2 A schematic diagram of the timeline of multi-channel data loading when the refresh is not synchronized; Figure 3 A schematic diagram of the structure of a chip provided in an embodiment of the present application; Figure 4 A flowchart of a data processing method provided by an embodiment of the present disclosure; Figure 5 A schematic diagram of another data processing method provided by an embodiment of the present disclosure; Figure 6 A schematic diagram of a chip state when adding a refresh synchronization indication provided by an embodiment of the present disclosure; Figure 7 A schematic diagram of the state of a chip when transmitting a read or write request provided by an embodiment of the present disclosure; Figure 8 A schematic diagram of the state of a chip when processing a read or write request provided by an embodiment of the present disclosure; Fig. 9 A schematic diagram of a chip state during synchronous refresh provided by an embodiment of the present disclosure; Fig.10 A flowchart of a synchronous refresh method provided by an embodiment of the present disclosure; Fig.11 A schematic diagram of another chip state during synchronous refresh provided by an embodiment of the present disclosure; Fig.12 A flowchart of another synchronous refresh method provided by an embodiment of the present disclosure; Fig.13 A schematic diagram of the structure of a data processing device provided in an embodiment of the present disclosure; Fig.14 A schematic diagram of the structure of another data processing device provided by an embodiment of the present disclosure; Fig.15 A schematic diagram of the structure of an electronic device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0021] The embodiments of the present disclosure are described below in conjunction with the drawings in the present disclosure. It should be understood that the implementation methods described below in conjunction with the drawings are exemplary descriptions for explaining the technical solutions of the embodiments of the present disclosure and do not constitute a limitation on the technical solutions of the embodiments of the present disclosure.

[0022] It will be understood by those skilled in the art that, unless specifically stated, the singular forms "one", "said", and "the" used herein may also include plural forms. It should be further understood that the terms "including" and "comprising" used in the embodiments of the present disclosure refer to that the corresponding features can be implemented as the presented features, information, data, steps, operations, elements and / or components, but do not exclude the implementation as other features, information, data, steps, operations, elements, components and / or combinations thereof supported by the technical field. It should be understood that when we say that an element is "connected" or "coupled" to another element, the one element may be directly connected or coupled to the other element, or it may refer to that the one element and the other element establish a connection relationship through an intermediate element. In addition, the "connection" or "coupling" used herein may include wireless connection or wireless coupling. The term "and / or" used herein indicates at least one of the items defined by the term, for example, "A and / or B" or "A, B" indicates that it is implemented as "A", or implemented as "B", or implemented as "A and B".

[0023] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0024] When the NPU, GPU or other processors (hereinafter referred to as XPU) in the SOC chip have a large bandwidth requirement when processing the parameter loading task of the large AI model, these processors often use multiple interleaved paths to increase the design bandwidth when accessing memory. SOC chips also often contain multiple interleaved DDR channels. DDR channels use DRAM, which needs to be refreshed regularly to ensure the stability and integrity of memory data.

[0025] Figure 1 It is a schematic diagram of the time axis of multi-channel loading data in the case of refresh synchronization, such as Figure 1 As shown, for 4 DDR channels (Channel 1, Channel 2, Channel 3 and Channel 4), Figure 1A rectangle in the diagram corresponds to the timeline corresponding to a DDR channel. Green indicates the time for executing data loading tasks (such as loading parameters of a large AI model), orange indicates the time for refreshing in the DDR channel, and gray indicates that the DDR channel is unavailable during this time. When an XPU accesses four DDR channels to perform data loading tasks, the refreshing of the DDR will interrupt the loading of the data stream. In reality, each DDR channel is an independent state machine, so it is likely that multiple DDR channel refreshes will not occur at the same time. Figure 2 It is a schematic diagram of the time axis of multi-channel loading data when the refresh is not synchronized, such as Figure 2 As shown in the figure, since XPU interleaves the same data stream to access multiple channels, when multiple DDR channels are refreshed asynchronously, the data loading of one channel will be interrupted, causing the entire data stream to stagnate, resulting in a head blocking problem. Figure 2 When the orange blocks in multiple DDR channels are not aligned (i.e., the refresh is not synchronized), the number of gray blocks in the DDR channels will increase, resulting in a longer data loading time ( Figure 2 The data loading time is significantly longer than Figure 1 data loading time), thereby reducing the chip data processing performance.

[0026] The data processing method, device, electronic device, storage medium and program product provided by the present disclosure are intended to solve the above technical problems in the prior art.

[0027] The following describes several exemplary embodiments to illustrate the technical solutions of the embodiments of the present disclosure and the technical effects produced by the technical solutions of the present disclosure. It should be noted that the following embodiments can refer to, draw on or combine with each other, and the same terms, similar features and similar implementation steps in different embodiments will not be described repeatedly.

[0028] Figure 3 A schematic diagram of the structure of a chip provided in an embodiment of the present application is shown in FIG. Figure 3 As shown, the chip includes a processor, a chip network (Network on Chip, NoC), a refresh synchronization module, and a double data rate controller DDRC corresponding to a plurality of double data rate DDR channels, the refresh synchronization module is respectively connected to the DDRC corresponding to each DDR channel, and the refresh synchronization module is connected to the processor through the chip network. Among them, the refresh synchronization module can be used to execute the data processing method provided by any embodiment of the present disclosure.

[0029] Optionally, when the number of DDR channels is 4, the 4 DDR channels correspond to 4 DDRCs, namely DDRC0, DDRC1, DDRC2 and DDRC3. For each DDR channel, the DDRC is connected to a DDR physical layer (DDR Physical Layer), and the DDR physical layer is connected to a DDR DRAM.

[0030] It should be noted that Figure 3 The number of DDR channels is 4, but Figure 3 The example given does not constitute a limitation on the number of DDR channels in a chip.

[0031] It should be noted that Figure 3 The colors corresponding to the modules are used to indicate the clock frequencies of the corresponding modules, that is, the clock frequencies of modules with the same colors are consistent. When the color of a module is gray, it indicates that there is no restriction on the clock frequency of the module.

[0032] Figure 4 A flowchart of a data processing method provided by an embodiment of the present disclosure is shown in FIG. Figure 4 As shown, the method is applied to refresh the synchronization module, and the method includes: Step S110, receiving a read / write request sent by a processor.

[0033] Specifically, the execution body of the data processing method provided by the embodiment of the present disclosure is a refresh synchronization module. The refresh synchronization module may be a hardware module in a SOC chip. The refresh synchronization module may be used to control the refresh synchronization between multiple DDR channels.

[0034] The processor may be a neural network processor (NPU), a graphics processing unit (GPU), or another type of processor (XPU). The type of processor may be specifically set according to the actual application scenario, and the embodiments of the present disclosure are not limited to this.

[0035] When the processor is executing a data processing task, the processor can divide the corresponding data stream into multiple paths, and continuously transmit the read and write requests of each path to the refresh synchronization module through the chip network. The refresh synchronization module can receive the read and write requests sent by the processor.

[0036] Step S120, if it is detected that the read / write request carries a refresh synchronization indication, the target countdown information is determined based on the countdown information corresponding to each DDR channel obtained; wherein the refresh synchronization indication is generated by a refresh synchronization indication generation module in the processor based on the type of data stream corresponding to the read / write request; the refresh synchronization indication is used to indicate the start of a refresh synchronization operation; Step S130: Control each DDRC to perform synchronous refresh based on the target countdown information.

[0037] Specifically, a refresh synchronization indication generation module may be provided in the processor, and the refresh synchronization indication generation module may be a hardware module, which is used to generate a refresh synchronization indication based on the type of data stream corresponding to the received read / write request, and the refresh synchronization indication is used to indicate the start of a refresh synchronization operation. The generation process of the refresh synchronization indication will be described in detail below.

[0038] The processor can continuously transmit the read / write request to the refresh synchronization module. After receiving the read / write request sent by the processor, the refresh synchronization module can detect whether the read / write request carries a refresh synchronization indication. If it is detected that the read / write request carries a refresh synchronization indication, it means that the data stream corresponding to the read / write request meets the specific type, and the refresh synchronization operation can be started, and the target countdown information is determined according to the countdown information corresponding to each DDR channel obtained, and each DDRC is controlled to perform the refresh operation at the same time based on the target countdown information. Otherwise, the refresh synchronization operation is not started, and the read / write request sent by the processor continues to be received.

[0039] Among them, the countdown information corresponding to the DDR channel can be used to represent the remaining time information from the next DDR refresh to the current time. The countdown information corresponding to different DDR channels may be different. The target countdown information can be understood as a unified countdown information for each DDR channel. The method for obtaining the countdown information and the method for determining the target countdown information will be described in detail below.

[0040] In the disclosed embodiment, a refresh synchronization indication is generated in a refresh synchronization indication generation module of a processor based on the type of data stream corresponding to a read or write request, and when the refresh synchronization module detects that a read or write request carries a refresh synchronization indication, each DDRC is controlled to be refreshed synchronously based on target countdown information, thereby achieving refresh synchronization of multiple DDR channels, thereby avoiding the extension of data loading time caused by the asynchronous refresh of multiple DDR channels, shortening the data loading time, and improving the overall data processing performance of the chip.

[0041] As an optional embodiment, the refresh synchronization indication is generated based on the following method: Receiving the read / write request to be transmitted through the refresh synchronization indication generating module, and if it is detected that the read / write request meets the preset condition, adding the refresh synchronization indication to the read / write request; The preset conditions include that the refresh synchronization indication adding operation is not performed within the processing task time period, and the bandwidth of the data stream corresponding to the read and write requests is greater than a preset bandwidth threshold within the preset time period.

[0042] Specifically, the refresh synchronization indication generation module can be set in the processor, which can receive the read and write requests to be transmitted and determine whether the read and write requests meet the preset conditions. If it is detected that the received read and write requests meet the preset conditions, the refresh synchronization indication is added to the read and write requests.

[0043] The preset condition may include that the bandwidth of the data stream corresponding to the read / write request is greater than the preset bandwidth threshold value within the preset time period, that is, the data stream corresponding to the read / write request may be a continuous data stream with a large bandwidth. At the same time, the preset condition may also include that the refresh synchronization indication adding operation is not performed within the processing task time period, that is, the refresh synchronization is not performed within the processing task time period.

[0044] It should be noted that the processing task time period refers to the time period for the processor to perform data processing tasks, such as the time period for the processor to perform AI large model parameter loading tasks, and the preset time period is the duration for the data flow to maintain a large bandwidth. The two can be the same or different in time length.

[0045] It can be understood that the read and write request that meets the preset conditions can be the first read and write request in a continuous data stream with a large bandwidth. That is to say, when the refresh synchronization indication generation module detects a specific continuous data stream with a large bandwidth, it will add a refresh synchronization indication to the first read and write request in the data stream, and will not continue to add refresh synchronization indications to subsequent read and write requests in the data stream; and during the task processing time period, refresh synchronization indications will not be added to read and write requests in other continuous data streams with a large bandwidth.

[0046] Optionally, the refresh synchronization indication generation module can save target data stream identifiers (data stream IDs) corresponding to multiple specific large-bandwidth continuous data streams. If a read / write request to be transmitted is received, the data stream identifier corresponding to the read / write request can be obtained based on the read / write request. If the data stream identifier corresponding to the read / write request is the target data stream identifier, indicating that the data stream corresponding to the read / write request is a large-bandwidth continuous data stream, a refresh synchronization indication can be added to the read / write request.

[0047] For example, the target data stream identifiers stored in the refresh synchronization indication generation module include 1, 3, 5 and 7. When the refresh synchronization indication generation module detects that the data stream identifier corresponding to the read-write request is 3, and the refresh synchronization indication generation module has not added refresh synchronization indications to other read-write requests during the task processing time period, a refresh synchronization indication can be added for the read-write request.

[0048] Optionally, a refresh synchronization flag may be added to the read / write request. When the read / write request meets a preset condition, the refresh synchronization flag in the read / write request is set to 1; otherwise, the refresh synchronization flag is set to 0.

[0049] In addition, after a certain period of time, a clear operation (ie, clear) may be performed by software to clear the refresh synchronization indication in the read / write request carrying the refresh synchronization indication.

[0050] In the disclosed embodiment, a refresh synchronization indication generating module is used to determine whether a read or write request meets preset conditions, thereby screening out specific large-bandwidth continuous data streams, and adding refresh synchronization indications to qualified read and write requests, so that the refresh synchronization module can start a refresh synchronization operation based on the refresh synchronization indication, thereby triggering a refresh synchronization operation when the processor accesses multiple DDR channels to load large-bandwidth data streams, thereby avoiding the extension of data loading time caused by the asynchronous refresh of multiple DDR channels, shortening the data loading time, and improving the performance when executing large-bandwidth demand tasks such as AI parameter loading.

[0051] As an optional embodiment, controlling each DDRC to perform synchronous refresh based on the target countdown information includes: Start countdown based on target countdown information; When the countdown is completed, the DDRCs corresponding to each DDR channel are configured to turn off the automatic refresh function, and each DDRC is configured to perform a refresh operation simultaneously.

[0052] Specifically, after determining the target countdown information, the refresh synchronization module can start the countdown according to the target countdown information. When the countdown is completed, the refresh synchronization module connects to the configuration interfaces corresponding to each DDRC and sends a configuration command to the configuration interface of each DDRC at the same time to configure each DDRC to turn off the automatic refresh function, and periodically configure each DDRC to issue a refresh operation based on the relevant DDR protocol.

[0053] It should be noted that after each DDRC is refreshed synchronously for the first time, it can be refreshed synchronously at each refresh cycle.

[0054] In the disclosed embodiment, each DDRC is controlled to perform synchronous refresh through a refresh synchronization module without modifying the internal logic of the DDRC. When the technician does not know or cannot change the internal logic of the DDRC, the synchronous refresh of multiple DDR channels can be effectively achieved, and the application scope is wider.

[0055] As an optional embodiment, the method further includes: Add the target countdown information to the read / write request, and send the read / write request carrying the target countdown information to the DDRC corresponding to each DDR channel; Based on the target countdown information, each DDRC is controlled to refresh synchronously, including: For each DDRC, if the DDRC detects that the received read / write request carries the target countdown information and the refresh synchronization indication, the DDRC starts the countdown based on the target countdown information, and performs the refresh operation when the countdown is completed.

[0056] Specifically, after determining the target countdown information, the refresh synchronization module may add the target countdown information to the read / write request that meets the preset condition, and send the read / write request carrying the target countdown information and the refresh synchronization indication to each DDRC.

[0057] For each DDRC, when the DDRC receives the read / write request sent by the refresh synchronization module, it can detect the read / write request. If it is detected that the read / write request carries both the refresh synchronization indication and the target countdown information, the countdown can be started based on the target countdown information, and the refresh operation can be performed based on the relevant DDR protocol cycle when the countdown is completed.

[0058] Since the target countdown information received by each DDRC is unified, each DDRC can simultaneously issue a refresh operation when the countdown of the target countdown information is completed, that is, synchronous refresh is achieved.

[0059] In the disclosed embodiment, when the technicians are able to modify the internal logic of the DDRC, by modifying the automatic refresh logic inside the DDRC, each DDRC cooperates with the refresh synchronization module to achieve synchronous refresh of each DDR channel, which can adapt to different application scenarios.

[0060] As an optional embodiment, if it is detected that the read / write request carries a refresh synchronization indication, the target countdown information is determined based on the countdown information corresponding to each DDR channel obtained, including: At every preset period, the countdown information corresponding to each DDR channel is obtained; If it is detected that the read / write request carries a refresh synchronization indication, the target countdown information is determined from the countdown information corresponding to each DDR channel that is acquired most recently.

[0061] Specifically, the countdown information corresponding to each DDR channel changes dynamically, and a preset period can be set. At intervals of the preset period, the refresh synchronization module obtains the countdown information corresponding to each DDR channel. At the same time, the refresh synchronization module can also receive read and write requests continuously transmitted by the processor. When it is detected that the received read and write requests carry a refresh synchronization indication, the countdown information corresponding to each DDR channel obtained in the preset period closest to the current moment can be used as the latest countdown information corresponding to each DDR channel, and the target countdown information can be determined from the latest countdown information corresponding to each DDR channel.

[0062] As an optional embodiment, determining the target countdown information from the countdown information corresponding to each DDR channel obtained most recently includes: The maximum value of the countdown information corresponding to each DDR channel obtained most recently is used as the first countdown information; Based on the first countdown information, target countdown information is determined; the target countdown information is not less than the first countdown information.

[0063] Specifically, after obtaining the countdown information corresponding to each DDR channel that is newly acquired, the refresh synchronization module may select the maximum value of the countdown information corresponding to each DDR channel as the first countdown information.

[0064] For example, when the number of DDR channels is 4, the countdown information corresponding to each DDR channel obtained recently includes: DDR channel 0 is 50ns (nanoseconds), DDR channel 1 is 150ns, DDR channel 2 is 250ns, and DDR channel 3 is 200ns, and the first countdown information determined therefrom is 250ns.

[0065] After obtaining the first countdown information, the refresh synchronization module may determine the target countdown information based on the first countdown information, wherein the target countdown information is not less than the first countdown information.

[0066] Optionally, the first countdown information may be directly used as the target countdown information; or a preset increment may be set, and the value of the preset increment is greater than 0, and the sum of the first countdown information and the preset increment is used as the target countdown information.

[0067] Optionally, when the value of the target countdown information is small, it may be frequently refreshed in a short period of time. To avoid the above situation, a preset increment can be calculated based on the current countdown information of each channel to avoid the refresh execution time period of all channels. If it is detected that the value of the first countdown information is less than the preset countdown information, the sum of the preset increment and the first countdown information is used as the target countdown information.

[0068] In the disclosed embodiment, the target countdown information is always not less than the maximum value (i.e., the first countdown information) in the countdown information corresponding to each DDR channel. When the countdown of the target countdown information is completed, each DDRC is controlled to perform a refresh operation simultaneously, thereby achieving refresh synchronization.

[0069] As an optional embodiment, the countdown information corresponding to each DDR channel is obtained based on at least one of the following methods: Send countdown information corresponding to the DDR channels to the refresh synchronization module through each DDRC; The DDR physical layer interfaces corresponding to the respective DDR channels are connected through the refresh synchronization module to collect countdown information corresponding to the respective DDR channels.

[0070] Specifically, the refresh synchronization module can obtain the countdown information corresponding to each DDR channel in at least one of the following ways: The countdown information corresponding to each DDR channel can be provided by each DDRC, that is, each DDRC can send the countdown information of the corresponding DDR channel to the refresh synchronization module at every preset period, so that the refresh synchronization module can determine the target countdown information based on the countdown information corresponding to each DDR channel.

[0071] The countdown information corresponding to each DDR channel can also be actively obtained through the refresh synchronization module, that is, at every preset period, the refresh synchronization module collects the countdown information corresponding to each DDR channel by connecting to the DDR physical layer interface (DDR PHYInterface, DFI) corresponding to each DDR channel.

[0072] Figure 5 A schematic diagram of a data processing method provided in an embodiment of the present disclosure is provided, wherein the method is applied to a refresh synchronization indication generating module in a processor, wherein the processor is connected to the refresh synchronization module, and the refresh synchronization module is respectively connected to double data rate controllers DDRC corresponding to a plurality of double data rate DDR channels.

[0073] like Figure 5 As shown, the method includes: Step S210, receiving a read / write request to be transmitted; Step S220, if it is detected that the read / write request meets the preset conditions, a refresh synchronization indication is added to the read / write request; wherein the preset conditions include that the refresh synchronization indication adding operation is not performed within the processing task time period, and the bandwidth of the data flow corresponding to the read / write request is greater than the preset bandwidth threshold within the preset time period; Step S230, sending the read / write request to the refresh synchronization module, so that if the refresh synchronization module detects that the read / write request carries a refresh synchronization indication, it determines the target countdown information based on the countdown information corresponding to each DDR channel obtained, and controls each DDRC to perform synchronous refresh based on the target countdown information.

[0074] Specifically, the refresh synchronization indication generation module can be set in the processor, which can receive the read and write requests to be transmitted and determine whether the read and write requests meet the preset conditions. If it is detected that the received read and write requests meet the preset conditions, the refresh synchronization indication is added to the read and write requests.

[0075] The preset condition may include that the bandwidth of the data stream corresponding to the read / write request is greater than the preset bandwidth threshold value within the preset time period, that is, the data stream corresponding to the read / write request may be a continuous data stream with a large bandwidth. At the same time, the preset condition may also include that the refresh synchronization indication adding operation is not performed within the processing task time period, that is, the refresh synchronization is not performed within the processing task time period.

[0076] After receiving the read / write request sent by the processor, the refresh synchronization module can detect whether the read / write request carries a refresh synchronization indication. If it is detected that the read / write request carries a refresh synchronization indication, it means that the data stream corresponding to the read / write request meets the specific type, and the refresh synchronization operation can be started, and the target countdown information corresponding to each DDR channel is determined according to the countdown information obtained, and each DDRC is controlled to perform the refresh operation at the same time based on the target countdown information. Otherwise, the refresh synchronization operation is not started, and the read / write request sent by the processor continues to be received.

[0077] In the disclosed embodiment, a refresh synchronization indication is generated in a refresh synchronization indication generation module of a processor based on the type of data stream corresponding to a read or write request, and when the refresh synchronization module detects that a read or write request carries a refresh synchronization indication, each DDRC is controlled to be refreshed synchronously based on target countdown information, thereby achieving refresh synchronization of multiple DDR channels, thereby avoiding the extension of data loading time caused by the asynchronous refresh of multiple DDR channels, shortening the data loading time, and improving the overall data processing performance of the chip.

[0078] The data processing method provided by the embodiment of the present disclosure is described below with reference to a specific example. Figure 6 A schematic diagram of a chip state when adding a refresh synchronization indication provided by an embodiment of the present disclosure, Figure 6 The middle circle represents a read / write request, and the green circle represents a read / write request without a refresh synchronization indication, such as Figure 6 As shown, the processor divides the data stream into four paths and transmits them through four DDR channels respectively. The refresh synchronization indication generation module receives the read and write requests to be transmitted. If it is detected that the read and write requests meet the preset conditions, a refresh synchronization indication is added to the read and write requests. Figure 6 The colored circles in the figure represent read and write requests to which a refresh synchronization indication is being added.

[0079] Figure 7 A schematic diagram of a chip state when transmitting a read / write request provided by an embodiment of the present disclosure, Figure 7 The red circle in the middle represents the read and write request with refresh synchronization indication, such as Figure 7As shown, after the refresh synchronization indication generation module adds the refresh synchronization indication to the read / write request (i.e., the circle changes from green to red), the read / write request continues to be transmitted to the chip network, and then transmitted to the refresh synchronization module through the chip network. Moreover, after the refresh synchronization indication generation module has performed the refresh synchronization indication adding operation, it will not continue to add refresh synchronization indications for subsequent read / write requests during the task processing time period.

[0080] Figure 8 A schematic diagram of a chip state when processing a read / write request provided by an embodiment of the present disclosure, such as Figure 8 As shown, the refresh synchronization module receives the read / write request sent from the processor. If it is detected that the read / write request carries a refresh synchronization indication (i.e., the red circle), the target countdown information is determined based on the countdown information corresponding to each DDR channel obtained, and each DDRC is controlled to perform synchronous refresh based on the target countdown information. Among them, the refresh synchronization module can actively collect the countdown information corresponding to each DDR channel by connecting the DFI corresponding to each DDRC (i.e., the purple dotted line in the figure).

[0081] Fig. 9 A schematic diagram of a chip state during synchronous refresh provided by an embodiment of the present disclosure, Fig.10 A flow chart of a synchronous refresh method provided by an embodiment of the present disclosure is shown in FIG. Fig. 9 and Fig.10 As shown, the synchronous refresh provided by the embodiment of the present disclosure is implemented solely through a refresh synchronization module. After determining the target countdown information, the refresh synchronization module starts to start the target countdown information. When the countdown is completed, each DDRC is configured to turn off automatic refresh according to the relevant DDR protocol, and the DDRC is periodically configured to issue a refresh operation. Fig. 9 The orange squares represent refresh operations initiated by the DDRC on the DRAM, and the green squares represent read operations initiated by the DDRC on the DRAM. In addition, the operations initiated by the DDRC on the DRAM may also include write operations, activate operations, and precharge operations.

[0082] Fig. 9 The red arrows between the refresh synchronization module and each DDRC represent the refresh control flow. This control flow and the existing data flow have different physical paths and information transmission. Fig. 9 In the example provided, each DDRC is configured to issue a refresh operation through software, and the automatic refresh logic inside the DDRC will not be modified. The control of the synchronous refresh process is all implemented by the refresh synchronization module, so each DDRC does not need to process the refresh synchronization indication in the read / write request carrying the refresh synchronization indication, and can be regarded as a general read / write request. Fig. 9The read and write requests processed by each DDRC are represented by green circles.

[0083] Fig.11 A schematic diagram of a chip state during synchronous refresh provided by an embodiment of the present disclosure, Fig.12 A flow chart of a synchronous refresh method provided by an embodiment of the present disclosure is shown in FIG. Fig.11 and Fig.12 As shown, the synchronous refresh provided by the embodiment of the present disclosure is realized by the cooperation of the refresh synchronization module and each DDRC, and the automatic refresh logic inside the DDRC needs to be modified. After determining the target countdown information, the refresh synchronization module adds the target countdown information to the read and write requests that meet the preset conditions, and transmits the processed read and write requests to each DDRC. For each DDRC, the DDRC receives the read and write requests sent by the refresh synchronization module. If it is detected that the read and write requests carry both the refresh synchronization indication and the target countdown information (i.e. Fig.11 ), the countdown is started based on the target countdown, and a refresh operation is periodically issued according to the relevant DDR protocol when the countdown is completed.

[0084] The data processing method provided by the embodiment of the present disclosure completes refresh synchronization between DDR channels through upstream and downstream cooperation, and is suitable for scenarios where the XPU module accesses DDR with large bandwidth. For example, for the currently popular AI large model scenarios and parameter loading tasks in the scenarios, the memory access performance of the XPU module in the data stream is improved, thereby improving the overall latency of the data stream and the overall performance of the scenario.

[0085] Fig.13 A structural diagram of a data processing device provided in an embodiment of the present disclosure is shown in FIG. Fig.13 As shown, the device of this embodiment may include: A first receiving module 310, configured to receive a read / write request sent by a processor; A countdown determination module 320 is used to determine target countdown information based on the countdown information corresponding to each DDR channel obtained if it is detected that the read / write request carries a refresh synchronization indication; wherein the refresh synchronization indication is generated by the refresh synchronization indication generation module in the processor based on the type of data stream corresponding to the read / write request; and the refresh synchronization indication is used to indicate the start of a refresh operation; The synchronous refresh control module 330 is used to control each DDRC to perform synchronous refresh based on the target countdown information.

[0086] As an optional embodiment, the refresh synchronization indication is generated based on the following method: Receiving the read / write request to be transmitted through the refresh synchronization indication generating module, and if it is detected that the read / write request meets the preset condition, adding the refresh synchronization indication to the read / write request; The preset conditions include that the refresh synchronization indication adding operation is not performed within the processing task time period, and the bandwidth of the data stream corresponding to the read and write request is greater than a preset bandwidth threshold within the preset time period.

[0087] As an optional embodiment, when the synchronous refresh control module controls each DDRC to perform synchronous refresh based on the target countdown information, it is specifically used to: Starting a countdown based on the target countdown information; When the countdown is completed, the DDRCs corresponding to each DDR channel are configured to turn off the automatic refresh function, and each DDRC is configured to perform a refresh operation simultaneously.

[0088] As an optional embodiment, the device further includes a target countdown information adding module, which is used to: Adding the target countdown information to the read / write request, and sending the read / write request carrying the target countdown information to the DDRCs corresponding to the respective DDR channels; When the synchronous refresh control module controls each DDRC to perform synchronous refresh based on the target countdown information, it is specifically used to: For each DDRC, if the DDRC detects that the received read / write request carries the target countdown information and the refresh synchronization indication, the DDRC starts the countdown based on the target countdown information, and performs a refresh operation when the countdown is completed.

[0089] As an optional embodiment, if the read / write request is detected to carry a refresh synchronization indication, the countdown determination module determines the target countdown information based on the countdown information corresponding to each DDR channel obtained, specifically for: At every preset period, the countdown information corresponding to each DDR channel is obtained; If it is detected that the read / write request carries a refresh synchronization indication, the target countdown information is determined from the countdown information corresponding to each DDR channel that is acquired most recently.

[0090] As an optional embodiment, when the countdown determination module determines the target countdown information from the countdown information corresponding to each DDR channel obtained most recently, it is specifically used to: The maximum value of the countdown information corresponding to each DDR channel obtained most recently is used as the first countdown information; Based on the first countdown information, the target countdown information is determined; the target countdown information is not less than the first countdown information.

[0091] As an optional embodiment, the countdown information corresponding to each DDR channel is obtained based on at least one of the following methods: Sending countdown information of the corresponding DDR channels to the refresh synchronization module through each DDRC; The DDR physical layer interfaces corresponding to the respective DDR channels are connected through the refresh synchronization module to collect countdown information corresponding to the respective DDR channels.

[0092] Fig.14 A structural diagram of a data processing device provided in an embodiment of the present disclosure is shown in FIG. Fig.14 As shown, the device of this embodiment may include: A second receiving module 410, configured to receive a read / write request to be transmitted; A refresh synchronization indication adding module 420 is used to add the refresh synchronization indication to the read / write request if it is detected that the read / write request meets a preset condition; wherein the preset condition includes that the refresh synchronization indication adding operation is not performed within the processing task time period, and the bandwidth of the data stream corresponding to the read / write request is greater than a preset bandwidth threshold within the preset time period; The sending module 430 is used to send the read / write request to the refresh synchronization module, so that if the refresh synchronization module detects that the read / write request carries a refresh synchronization indication, the target countdown information is determined based on the countdown information corresponding to each DDR channel obtained, and each DDRC is controlled to perform synchronous refresh based on the target countdown information.

[0093] The device of the embodiment of the present disclosure can execute the method provided by the embodiment of the present disclosure, and its implementation principle is similar and has corresponding technical effects. The actions performed by each module in the device of each embodiment of the present disclosure correspond to the steps in the method of each embodiment of the present disclosure. For the detailed functional description of each module of the device, please refer to the description of the corresponding method shown in the previous text, which will not be repeated here.

[0094] In the embodiments of the present disclosure, the term "module" or "unit" refers to a computer program or a part of a computer program that has a predetermined function and works together with other related parts to achieve a predetermined goal, and can be implemented in whole or in part by using software, hardware (such as processing circuits or memories), or a combination thereof. Similarly, a processor (or multiple processors or memories) can be used to implement one or more modules or units. In addition, each module or unit can be part of an overall module or unit that includes the function of the module or unit.

[0095] In an embodiment of the present disclosure, an electronic device is provided, including a memory, a processor, and a computer program stored in the memory, and the processor executes the above computer program to implement the steps of the method provided by any optional embodiment of the present disclosure. Compared with the prior art, it can be achieved that: by generating a refresh synchronization indication based on the type of data stream corresponding to the read / write request in the refresh synchronization indication generation module of the processor, the refresh synchronization module controls each DDRC to refresh synchronously based on the target countdown information when detecting that the read / write request carries a refresh synchronization indication, thereby realizing the refresh synchronization of multiple DDR channels, thereby avoiding the extension of data loading time caused by the asynchronous refresh of multiple DDR channels, shortening the data loading time, and improving the overall data processing performance of the chip.

[0096] In an alternative embodiment, an electronic device is provided, such as Fig.15 As shown, Fig.15 The electronic device 4000 shown includes: a processor 4001 and a memory 4003. The processor 4001 and the memory 4003 are connected, such as through a bus 4002. Optionally, the electronic device 4000 may also include a transceiver 4004, which may be used for data interaction between the electronic device and other electronic devices, such as data transmission and / or data reception. It should be noted that in actual applications, the transceiver 4004 is not limited to one, and the structure of the electronic device 4000 does not constitute a limitation on the embodiments of the present disclosure.

[0097] Processor 4001 may be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array) or other programmable logic devices, transistor logic devices, hardware components or any combination thereof. It may implement or execute various exemplary logic blocks, modules and circuits described in conjunction with the disclosure of the present invention. Processor 4001 may also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, etc.

[0098] The bus 4002 may include a path to transmit information between the above components. The bus 4002 may be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus. The bus 4002 may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Fig.15 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0099] The memory 4003 may be a ROM (Read Only Memory) or other types of static storage devices that can store static information and instructions, a RAM (Random Access Memory) or other types of dynamic storage devices that can store information and instructions, or an EEPROM (Electrically Erasable Programmable Read Only Memory), a CD-ROM (Compact Disc Read Only Memory) or other optical disk storage, optical disk storage (including compressed optical disk, laser disk, optical disk, digital versatile disk, Blu-ray disk, etc.), magnetic disk storage media, other magnetic storage devices, or any other medium that can be used to carry or store computer programs and can be read by a computer, without limitation herein.

[0100] The memory 4003 is used to store the computer program for executing the embodiment of the present disclosure, and the execution is controlled by the processor 4001. The processor 4001 is used to execute the computer program stored in the memory 4003 to implement the steps shown in the above method embodiment.

[0101] Among them, electronic devices include but are not limited to: mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), vehicle-mounted terminals (such as vehicle-mounted navigation terminals), wearable devices, etc., and fixed terminals such as digital TVs, desktop computers, etc.

[0102] An embodiment of the present disclosure provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps and corresponding contents of the aforementioned method embodiment can be implemented.

[0103] The embodiments of the present disclosure also provide a computer program product, including a computer program, which can implement the steps and corresponding contents of the aforementioned method embodiments when executed by a processor.

[0104] It should be understood that, although the flowchart of the embodiment of the present disclosure indicates each operation step by arrows, the implementation order of these steps is not limited to the order indicated by the arrows. Unless clearly stated herein, in some implementation scenarios of the embodiment of the present disclosure, the implementation steps in each flowchart can be executed in other orders according to demand. In addition, some or all of the steps in each flowchart may include multiple sub-steps or multiple stages based on the actual implementation scenario. Some or all of these sub-steps or stages can be executed at the same time, and each sub-step or stage in these sub-steps or stages can also be executed at different times. In scenarios with different execution times, the execution order of these sub-steps or stages can be flexibly configured according to demand, and the embodiment of the present disclosure does not limit this.

[0105] The above is only an optional implementation method for some implementation scenarios of the present disclosure. It should be pointed out that for ordinary technicians in this technical field, without departing from the technical concept of the scheme of the present disclosure, other similar implementation methods based on the technical ideas of the present disclosure are also within the protection scope of the embodiments of the present disclosure.

Claims

1. A data processing method, characterized in that: Applied to a refresh synchronization module, the refresh synchronization module is respectively connected to double data rate controllers DDRC corresponding to a plurality of double data rate DDR channels respectively; The method comprises: Receive read and write requests sent by the processor; If it is detected that the read / write request carries a refresh synchronization indication, the target countdown information is determined based on the countdown information corresponding to each DDR channel obtained; wherein the refresh synchronization indication is generated by a refresh synchronization indication generation module in the processor based on the type of data stream corresponding to the read / write request; and the refresh synchronization indication is used to indicate the start of a refresh operation; Based on the target countdown information, each DDRC is controlled to perform synchronous refresh.

2. The data processing method according to claim 1, characterized in that: The refresh synchronization indication is generated based on the following method: Receiving the read / write request to be transmitted through the refresh synchronization indication generating module, and if it is detected that the read / write request meets the preset condition, adding the refresh synchronization indication to the read / write request; The preset conditions include that the refresh synchronization indication adding operation is not performed within the processing task time period, and the bandwidth of the data stream corresponding to the read and write request is greater than a preset bandwidth threshold within the preset time period.

3. The data processing method according to claim 1, characterized in that: The step of controlling each DDRC to perform synchronous refresh based on the target countdown information includes: Starting a countdown based on the target countdown information; When the countdown is completed, the DDRCs corresponding to each DDR channel are configured to turn off the automatic refresh function, and each DDRC is configured to perform a refresh operation simultaneously.

4. The data processing method according to claim 1, characterized in that: The method further comprises: Adding the target countdown information to the read / write request, and sending the read / write request carrying the target countdown information to the DDRCs corresponding to the respective DDR channels; The step of controlling each DDRC to perform synchronous refresh based on the target countdown information includes: For each DDRC, if the DDRC detects that the received read / write request carries the target countdown information and the refresh synchronization indication, the DDRC starts the countdown based on the target countdown information, and performs a refresh operation when the countdown is completed.

5. The data processing method according to claim 1, characterized in that: If it is detected that the read / write request carries a refresh synchronization indication, the target countdown information is determined based on the countdown information corresponding to each DDR channel obtained, including: At every preset period, the countdown information corresponding to each DDR channel is obtained; If it is detected that the read / write request carries a refresh synchronization indication, the target countdown information is determined from the countdown information corresponding to each DDR channel that is acquired most recently.

6. The data processing method according to claim 5, characterized in that: The step of determining the target countdown information from the countdown information corresponding to each DDR channel obtained most recently includes: The maximum value of the countdown information corresponding to each DDR channel obtained most recently is used as the first countdown information; Based on the first countdown information, the target countdown information is determined; the target countdown information is not less than the first countdown information.

7. The data processing method according to claim 5, characterized in that: The countdown information corresponding to each DDR channel is obtained based on at least one of the following methods: Sending countdown information of the corresponding DDR channels to the refresh synchronization module through each DDRC; The DDR physical layer interfaces corresponding to the respective DDR channels are connected through the refresh synchronization module to collect countdown information corresponding to the respective DDR channels.

8. A data processing method, characterized in that: A refresh synchronization indication generating module is applied to a processor, the processor is connected to the refresh synchronization module, the refresh synchronization module is respectively connected to double data rate controllers DDRC corresponding to a plurality of double data rate DDR channels, the method comprising: Receive read and write requests to be transmitted; If it is detected that the read / write request meets the preset conditions, the refresh synchronization indication is added to the read / write request; wherein the preset conditions include that the refresh synchronization indication adding operation is not performed within the processing task time period, and the bandwidth of the data stream corresponding to the read / write request is greater than the preset bandwidth threshold within the preset time period; The read / write request is sent to the refresh synchronization module, so that if the refresh synchronization module detects that the read / write request carries a refresh synchronization indication, the target countdown information is determined based on the countdown information corresponding to each DDR channel obtained, and each DDRC is controlled to perform synchronous refresh based on the target countdown information.

9. A chip, characterized in that: The chip includes a processor, a chip network, a refresh synchronization module and a double data rate controller DDRC corresponding to a plurality of double data rate DDR channels respectively; the processor includes a refresh synchronization indication generation module; The refresh synchronization module is connected to each DDRC respectively; the refresh synchronization module is connected to the processor through the chip network; The refresh synchronization module is used to execute the data processing method described in any one of claims 1-7.

10. A data processing device, characterized in that: include: A first receiving module, used for receiving a read / write request sent by a processor; a countdown determination module, configured to determine target countdown information based on the countdown information corresponding to each DDR channel obtained if it is detected that the read / write request carries a refresh synchronization indication; wherein the refresh synchronization indication is generated by the refresh synchronization indication generation module in the processor based on the type of data stream corresponding to the read / write request; and the refresh synchronization indication is used to indicate the start of a refresh operation; The synchronous refresh control module is used to control each DDRC to perform synchronous refresh based on the target countdown information.

11. A data processing device, characterized in that: include: A second receiving module, used for receiving a read / write request to be transmitted; A refresh synchronization indication adding module, used for adding the refresh synchronization indication to the read / write request if it is detected that the read / write request meets a preset condition; wherein the preset condition includes that the refresh synchronization indication adding operation is not performed within the processing task time period, and the bandwidth of the data stream corresponding to the read / write request is greater than a preset bandwidth threshold within the preset time period; The sending module is used to send the read / write request to the refresh synchronization module, so that if the refresh synchronization module detects that the read / write request carries a refresh synchronization indication, the target countdown information is determined based on the countdown information corresponding to each DDR channel obtained, and each DDRC is controlled to perform synchronous refresh based on the target countdown information.

12. An electronic device comprising a memory, a processor and a computer program stored in the memory, characterized in that: The processor executes the computer program to implement the steps of the method according to any one of claims 1 to 8.

13. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 8 are implemented.

14. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 8 are implemented.

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