Real-time decimation method for high-speed sampling data based on parallel digital filter
By combining a parallel CIC filter and a cascaded parallel half-band filter, the problems of high resource consumption and spectral aliasing in high sampling rate signal analysis are solved, achieving high frequency resolution and effective aliasing suppression.
Patent Information
- Application Number
- CN202411507632.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-28
- Publication Date
- 2025-11-25
- Estimated Expiration
- 2044-10-28
AI Technical Summary
In high sampling rate signal analysis, existing technologies face challenges in decimation filter design, including high resource consumption and spectral aliasing. Traditional methods cannot effectively suppress aliasing components and have insufficient frequency response.
A combination structure of parallel CIC filter and cascaded parallel half-band filter is adopted. High-rate real-time data extraction is achieved through parallel CIC decimation and cascaded parallel half-band filter, reducing resource consumption and improving frequency resolution.
It achieves a significant improvement in frequency resolution, a reduction in resource consumption, and an effective suppression of aliasing components without increasing the FFT length, achieving a stopband attenuation of 60dB.
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Figure CN119493977B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of high-speed acquisition system technology, and more specifically, relates to a method for real-time extraction of high-speed sampling data based on parallel digital filters. Background Technology
[0002] In today's electronic measurement field, sampling rates are becoming increasingly higher. When the bandwidth of a signal is far lower than the sampling rate, decimation becomes an essential operation for signal analysis. However, because decimation alters the signal spectrum, leading to aliasing, and the extremely high speed of the original data, the design of decimation filters presents significant challenges.
[0003] A mixed-domain oscilloscope is a powerful instrument for analyzing broadband signals in both the time and frequency domains. With the continuous development of digital acquisition technology, the sampling rate of digital signals has increased to tens of GSPS, making real-time analysis of high-sampling-rate signals extremely difficult. Therefore, decimation is often used to reduce the signal sampling rate. However, since decimation causes spectral aliasing, a real-time decimation filter needs to be designed to suppress the aliasing components introduced by decimation.
[0004] Traditional decimation filtering methods can be roughly divided into two categories. One is the finite impulse response (FIR) method, which uses a polyphase FIR structure to process high sampling rate signals. The advantage of this method is that it can obtain a good frequency response. However, as the sampling rate increases, more polyphase blocks are required, which leads to a sharp increase in resource consumption. The other is the Farrow method. Although the Farrow structure has the lowest computational complexity and does not consume too many resources, its low stopband attenuation and insufficient frequency response characteristics can lead to the filtering effect not meeting the requirements. Summary of the Invention
[0005] The purpose of this invention is to overcome the shortcomings of the prior art and provide a high-speed sampling data real-time decimation method based on parallel digital filters. It effectively achieves high decimation by using parallel CIC filters and provides better frequency response by using half-band filters. Therefore, it has the advantages of low resource consumption and excellent anti-aliasing performance.
[0006] To achieve the above-mentioned objective, the present invention provides a high-speed real-time sampling data extraction method based on parallel digital filters, characterized by comprising the following steps:
[0007] (1) Data collection;
[0008] The signal under test is input to a mixed-domain oscilloscope, and the high-speed ADC at the front end acquires the signal under test to obtain serial sampling data;
[0009] (2) Input the serial sampling data to the FPGA through the high-speed interface to obtain parallel L-channel sampling data;
[0010] (3) Parallel CIC extraction;
[0011] The parallel L-channel sampled data is decimated by a factor of R using a parallel CIC filter, resulting in L / R-channel sampled data, where L / R = 2. p p = 0, 1, ...;
[0012] (4) Cascaded parallel halfband extraction;
[0013] The L / R channel sampled data is processed by a cascaded parallel half-band filter. p The data is extracted multiple times, and after extraction, serial data is obtained.
[0014] (5) Serial extraction;
[0015] The serial data is sequentially passed through a serial CIC filter and a cascaded serial half-band filter to extract the output data.
[0016] The objective of this invention is achieved as follows:
[0017] This invention discloses a high-speed sampling data real-time decimation method based on parallel digital filters. First, the test signal is acquired through the acquisition system of a mixed-domain oscilloscope to obtain parallel multi-channel signals. Then, a high-magnification real-time decimation filtering is achieved through a parallel CIC filter and a cascaded parallel half-band filter to obtain serial data. Finally, the serial data is serially decimated to obtain the output data. In this way, the frequency resolution of the oscilloscope's spectrum analysis function can be significantly improved without increasing the FFT length.
[0018] Meanwhile, the high-speed sampling data real-time extraction method based on parallel digital filters of the present invention also has the following beneficial effects:
[0019] (1) The present invention adopts a structure of parallel CIC decimation + cascaded parallel half-band decimation. Real-time decimation filtering of 20GSPS sampling rate signal can be achieved through parallel CIC decimation without consuming multipliers, which can greatly reduce the resource consumption of real-time filtering processing. The cascaded parallel half-band filter improves the filter's suppression effect on aliasing components, achieving a stopband attenuation of 60dB.
[0020] (2) This invention achieves parallel real-time decimation processing by using parallel CIC filters and cascaded parallel half-band filters, which reduces the sampling rate of the signal while ensuring the continuity of the data. It can significantly improve the frequency resolution of the oscilloscope's spectrum analysis function without increasing the FFT length. Attached Figure Description
[0021] Figure 1 This is a schematic diagram of a parallel CIC filter structure;
[0022] Figure 2 This is a schematic diagram of the structure of a parallel integrator;
[0023] Figure 3 This is a schematic diagram of the structure of a parallel dressing comb;
[0024] Figure 4 This is a schematic diagram of a parallel half-band filter.
[0025] Figure 5 This is a flowchart of a high-speed real-time sampling data extraction method based on a parallel digital filter according to the present invention. Detailed Implementation
[0026] The specific embodiments of the present invention will now be described with reference to the accompanying drawings to enable those skilled in the art to better understand the invention. It should be particularly noted that in the following description, detailed descriptions of known functions and designs that might obscure the main content of the invention will be omitted here.
[0027] Example
[0028] In this embodiment, we will first introduce the structures of the parallel CIC filter and the parallel half-band filter;
[0029] like Figure 1 As shown, the parallel CIC filter consists of a cascaded parallel integrator, a parallel down-decimator, and a cascaded parallel comb. The number of cascaded parallel integrators and parallel combs is the same, and the number of cascaded stages can be determined according to the stopband attenuation requirements of the design.
[0030] The parallel L-channel sampled data is processed by a cascaded parallel integrator to obtain the parallel integration result, then by a parallel down-decimator to obtain the L / R-channel parallel data with a downsampling rate, and finally by a cascaded parallel comb to obtain the final result of decimation filtering.
[0031] like Figure 2 As shown, the parallel integrator consists of an addition matrix unit, an integration unit, and an addition chain. The addition matrix unit accumulates the parallel L-channel sampled data row by row, and the output of each row is the accumulated result from the first row to the current row. The integration unit integrates the last element of the accumulated result of each column, and the addition chain adds the output of the integration unit to the accumulated results of each row to obtain the integration result of each row in the current column. The integration result of all rows in the current column is the parallel integration result at the time corresponding to the current column.
[0032] like Figure 3As shown, the parallel comb is implemented by L / R subtractors. For the first row, the output is the first row at the current time minus the last row at the previous time. For other rows, the output is the current row minus the previous row. The outputs of the subtractors of all rows constitute the output of the parallel comb.
[0033] In this embodiment, as Figure 4 As shown, the structure of the parallel half-band filter includes a parallel delay unit and a parallel polyphase filter; the length of the parallel half-band filter is 2N+1; the coefficients q(n) of the parallel half-band filter satisfy the following conditions:
[0034]
[0035] In this embodiment, the delay of the lower row in the parallel delay unit increases by 1 relative to the delay of the first row. For example, the delay of the second row increases by 1 relative to the first row, the delay of the third row increases by 2 relative to the first row, and so on.
[0036] Each row H(z) of the parallel polyphase filter is equivalent to an FIR filter of length N, and its filter coefficients satisfy the following condition:
[0037]
[0038] After the L / R path sampling data is input to the parallel half-band filter, the L / R path sampling data is first split into odd and even paths. All odd path data is input to the parallel delay unit, and all even path data is input to the parallel polyphase filter. The processing results of the odd and even paths are added together to obtain the output of the parallel half-band filter.
[0039] Below, we will describe in detail the high-speed real-time sampling data extraction method based on parallel digital filters of this invention, such as... Figure 5 As shown, the specific steps include:
[0040] (1) Data collection;
[0041] The signal under test is input to a mixed-domain oscilloscope, and the high-speed ADC at the front end acquires the signal under test to obtain serial sampling data;
[0042] (2) Input the serial sampling data to the FPGA through the high-speed interface to obtain parallel L-channel sampling data;
[0043] In this embodiment, let the sampling rate f of the ADC be... s With a power of 20 GSPS and an FPGA operating frequency f0 of 250 MHz, the acquired data is processed in parallel within the FPGA, with the number of parallel paths L being:
[0044] L = f s / f0=80
[0045] (3) Parallel CIC extraction;
[0046] The parallel L-channel sampled data is decimated by a factor of R using a parallel CIC filter, resulting in L / R-channel sampled data, where L / R = 2. p p = 0, 1, ... In this embodiment, L = 80, R = 10, therefore, p = 3;
[0047] (3.1) Set the number of iterations T of the parallel integrator, T = log2L = 3, and initialize the current iteration number i = 1, i ∈ [1, T];
[0048] (3.2) Input the parallel L-channel sampled data into the parallel integrator, and calculate the integral result x of each column in the L-channel sampled data through the parallel integrator. T (n,l);
[0049] (3.2.1) Calculate the integral result x after the i-th iteration of the parallel integrator. i (n,l):
[0050]
[0051] Where n represents the number of columns, l represents the number of rows, k, j, m are all integer coefficients, and l = 0, 1, 2, ..., L-1;
[0052] (3.2.2) Let x be the integral result of the parallel integrator after the Tth iteration. T (n,l);
[0053] (3.2.3) Calculate the final integration result of the parallel integrator;
[0054]
[0055] Where d represents the column number;
[0056] In this embodiment, an 8-way integration operation is taken as an example:
[0057] Let the 8 data paths be: x(n,0), x(n,1), ..., x(n,7). The inner loop runs from 1 to 8, and the outer loop runs from 1 to 3. After the inner loop completes its first execution, the result is: x1(n,0), x1(n,1), ..., x1(n,7).
[0058] x1(n,0)=x(n,0); x1(n,1)=x(n,0)+x(n,1);
[0059] x1(n,2)=x(n,2); x1(n,3)=x(n,2)+x(n,3);
[0060] x1(n,4)=x(n,4); x1(n,5)=x(n,4)+x(n,5);
[0061] x1(n,6)=x(n,6); x1(n,7)=x(n,6)+x(n,7);
[0062] The result obtained after the inner loop executes for the second time is: x2(n,0),x2(n,1),…,x2(n,7);
[0063] x2(n,0)=x1(n,0); x2(n,1)=x1(n,1);
[0064] x2(n,2)=x1(n,1)+x1(n,2); x2(n,3)=x1(n,1)+x1(n,3);
[0065] x2(n,4)=x1(n,4); x2(n,5)=x1(n,5);
[0066] x2(n,6)=x1(n,5)+x1(n,6); x2(n,7)=x1(n,5)+x1(n,7);
[0067] The result obtained after the inner loop executes for the third time is: x3(n,0),x3(n,1),…,x3(n,7), which is I(n,0),I(n,1),…,I(n,7);
[0068] I(n,0)=x2(n,0); I(n,1)=x2(n,1);
[0069] I(n,2)=x2(n,2); I(n,3)=x2(n,3);
[0070] I(n,4)=x2(n,3)+x2(n,4);x2(n,5)=x2(n,3)+x2(n,5);
[0071] I(n,6)=x2(n,3)+x2(n,6);x2(n,7)=x2(n,3)+x2(n,7);
[0072] Substituting the previous formula, we get:
[0073] I(n,0)=x(n,0); I(n,1)=x(n,0)+x(n,1);…I(n,7)=x(n,0)+x(n,1)+…+x(n,7);
[0074] Thus, the integral results of each element in each column are obtained.
[0075] In the second step of the parallel integrator stream, the integration results of each column should be accumulated. In fact, the last element of each column is the integration result of the current column. Therefore, we can accumulate the last element of the adder matrix output.
[0076] The final step is to add the sum of the previous columns to the integral results of each row in the current column to obtain the final integral result.
[0077] (3.3) Input the final integration result y(n,l) of the parallel integrator into the parallel downsampler. The parallel downsampler performs R-fold decimation on the L parallel sampled data to obtain L / R sampled data, denoted as y(n,l1). The row index retained in each column is l1=R·r, r=0,1,2,…,L / R-1, where R is the decimation factor of the parallel downsampler. For example, if there are 80 data channels and the decimation factor is 10, then the indexes of the retained elements are 0, 10, 20…70.
[0078] (3.4) The parallel comb processes the sampling results of the parallel downsampler;
[0079] (3.4.1) Let the output of the parallel downsampler be h(n,r)=y(n,l1);
[0080] (3.4.2) Delay h(n,r) through a delay unit to obtain h(n',r');
[0081]
[0082] Where M is the differential delay parameter of the CIC filter;
[0083] (3.4.3) Solve h(n,r) and h(n',r') through a subtractor to obtain the final decimation result g(n,r) = h(n,r) - h(n',r') of the parallel CIC filter.
[0084] (4) Cascaded parallel halfband extraction;
[0085] The L / R channel sampled data is processed by a cascaded parallel half-band filter. p The data is extracted multiple times, and after extraction, serial data is obtained.
[0086] (4.1) Input the L / R path sampling data into the first-stage parallel half-band filter. First, split the L / R path sampling data into odd and even paths, where all odd path sampling data is denoted as g. odd (n,f), g odd (n,f)=g(n,r / 2+1), let g be the sampled data of all even paths. even (n,f), g even(n,f)=g(n,r / 2), where n represents the number of columns and f represents the number of rows;
[0087] (4.2) Sample all odd-path data g odd (n,f) is input to the parallel delay unit, and after delay processing, the data w(n,f) is obtained;
[0088]
[0089] (4.3) Collect all even-path sampled data g even (n,f) is input to a parallel polyphase filter to obtain a parallel output r(n,f);
[0090] r(n,f)=q′(n)*G N (n,f)
[0091] Among them, G N (n,f) represents the even-path sampled data g even In (n,f), take any sampling point g * Starting from (n,f), take a vector of length N along the column direction;
[0092] (4.4) The output of the first-stage parallel half-band filter is calculated as o(n,f):
[0093] o(n,f)=w(n,f)+r(n,f)
[0094] (4.5) Use the output o(n,f) of the first-stage parallel half-band filter as the input of the second-stage parallel half-band filter, and then repeat steps (4.1) to (4.4) until p parallel half-band filters are cascaded to obtain the serial data of cascaded parallel half-band decimation.
[0095] (5) Serial extraction;
[0096] The serial data is sequentially passed through a serial CIC filter and a cascaded serial half-band filter to extract the output data.
[0097] In this embodiment, the serial CIC filter and the cascaded serial half-band filter are traditional structures, which will not be described in detail here. We can configure the decimation factor of the serial CIC filter to be in the range of 1 to 4000, while the cascaded serial half-band filter can be configured to have a decimation factor of 2 to the power of n. After the above decimation process, parallel decimation from 80 times to 2,560,000 times can be achieved. After the data changes from high-speed parallel to low-speed serial signal, it is sent to the subsequent modules of the oscilloscope for calculation.
[0098] Although the illustrative specific embodiments of the present invention have been described above to enable those skilled in the art to understand the invention, it should be understood that the invention is not limited to the scope of the specific embodiments. For those skilled in the art, various changes are obvious as long as they are within the spirit and scope of the invention as defined and determined by the appended claims, and all inventions utilizing the concept of the present invention are protected.
Claims
1. A method for real-time decimation of high-speed sampled data based on parallel digital filters, characterized in that, The method comprises the following steps: (1) data acquisition; The measured signal is input to a mixed-domain oscilloscope, the measured signal is collected by a high-speed ADC at the front end, and serial sampling data is obtained; (2) The serial sampling data is input to the FPGA through a high-speed interface to obtain parallel sampling data. road sampling data; (3) parallel CIC decimation; The parallel CIC filter is used to decimate the parallel sample data by 2 , and obtain sample data, wherein ; The parallel CIC filter is composed of a cascaded parallel integrator, a parallel down sampler and a cascaded parallel combiner. The parallel CIC filter is composed of a cascaded parallel integrator, a parallel down sampler and a cascaded parallel combiner. The parallel CIC filter is composed of a cascaded parallel integrator, a parallel down sampler and a cascaded parallel combiner. The parallel integrator is composed of an addition matrix unit, an integration unit and an addition chain; the addition matrix unit performs row-by-row accumulation on the parallel L-channel sampling data, and the output of each row is the accumulation result from the first row to the current row; the integration unit integrates the last element of each column accumulation result, and the addition chain adds the output of the integration unit to each row accumulation result to obtain the integration result of each row in the current column; the integration result of all rows in the current column is the parallel integration result corresponding to the time of the current column; The parallel combiner is realized by The parallel combiner is realized by (4) cascaded parallel half-band decimation; The sampling data is passed through a cascade parallel half-band filter The sampling data is passed through a cascade parallel half-band filter The sampling data is passed through a cascade parallel half-band filter The process of cascaded parallel half-band decimation is as follows: (4.1), the first level parallel half-band filter is inputted with the sampling data of the first channel, and the sampling data of the first channel is first split into odd and even channels representing the number of columns, (4.2), all the odd channel sampling data are input to the parallel delay unit, and the data after the delay processing is obtained ; ; (4.3) all even path sampled data is input to a parallel polyphase filter to obtain a parallel output ; ; wherein, filter coefficients of a parallel polyphase filter, denotes a vector of length in the column direction, starting at an arbitrary one of the sample points in the even channel sampled data ; (4.4) computing the output of the first stage parallel half-band filter as : ; (4.5) taking the output of the first stage parallel half-band filter as input to a second stage parallel half-band filter, then repeating steps (4.1) - (4.4) until a cascade of N parallel half-band filters is obtained, resulting in serial data cascaded parallel half-band decimated, (5) serial decimation; The serial data is sequentially decimated through the serial CIC filter and the cascaded serial half-band filter to obtain the output data after decimation.
2. The parallel digital filter based high speed sampling data real time decimation method according to claim 1, wherein, The parallel CIC filter pair is parallel The process of decimation by a factor of is: (2.1) setting the number of iterations of the integrator , , initializing the current iteration number , ; (2.2), the parallel The integral results of each column in the road sampling data are calculated by the integrator The integral results of each column in the road sampling data are calculated by the integrator The integral results of each column in the road sampling data are calculated by the integrator (2.2.1), the integrator is calculated the integral result after the second iteration : ; wherein represents the number of columns, represents the number of rows, are all integer coefficients, ; (2.2.2), the number of The integration result of the integrator after the second iteration is ; (2.2.3) calculating the final integration result of the integrator; ; wherein represents column number; (2.3), the final integration result of the integrator is input to the parallel downsampler, and the parallel downsampler performs sampling data in parallel by decimation at a decimation rate of to obtain sampling data, denoted as , , is the decimation rate of the parallel downsampler; (2.4) the parallel combiner processes the sampling result of the parallel down sampler; (2.4.1), the output of the parallel down-sampler is recorded ; (2.4.2), to The output is delayed by a delay unit ; ; wherein, is a differential delay parameter for the CIC filter; (2.4.3), and and The final decimation result of the parallel CIC filter is obtained by subtraction .
3. The parallel digital filter based high speed sampling data real time decimation method according to claim 1, wherein, The length of the parallel half-band filter is 2 +1; coefficient of the parallel half-band filter satisfies the following conditions: ; The structure of the parallel half-band filter comprises a parallel delay unit and a parallel polyphase filter; the delay of the lower row in the parallel delay unit is sequentially increased by 1 relative to the delay of the first row; each row of the parallel polyphase filter corresponds to a FIR filter with a length of , and the filter coefficients satisfy the following conditions: ; After the parallel half-band filter is input with the sampled data, all the odd-numbered channel data is input to the parallel delay unit, and all the even-numbered channel data is input to the parallel polyphase filter. The sampled data is split into odd and even channels, wherein all the odd-numbered channel data is input to the parallel delay unit, and all the even-numbered channel data is input to the parallel polyphase filter. The processing results of the odd and even channels are added to obtain the output of the parallel half-band filter.
Citation Information
Patent Citations
Optimized filter parameters design for digital IF programmable downconverter
US20040107078A1
Cascaded integrator-comb (CIC) decimation filter with integration reset to support a reduced number of differentiators
US20190379358A1