Method of compensating for pixel circuit differences and apparatus for generating compensation data

Abstract

The present disclosure provides a method of compensating for pixel circuit differences in a display device and a device for generating compensation data for a plurality of pixels. The method comprises the following steps: displaying a test image of a plurality of pixels of the display device; generating a first camera image by shooting the test image; applying a test input signal to each of the plurality of pixels and sensing a corresponding test output, where the test input signal is at least one of a test current and a test voltage; generating weights for the plurality of pixels based on the test output; generating a second camera image by applying the weight to the first camera image; and generating compensation data for the plurality of pixels based on the second camera image.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0107478 filed in the Korean Intellectual Property Office on August 17, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a display device, a method of compensating for pixel circuit differences in a display device, and a device for generating compensation data for a plurality of pixels. Background Art

[0004] With the development of information technology, the role of display devices as a connection medium between users and information has become increasingly important. Therefore, display devices (such as liquid crystal display devices and organic light emitting diode display devices) have become increasingly popular.

[0005] A display device uses a plurality of pixels to display an image. A plurality of pixels may have the same pixel circuit structure. However, as display devices become larger, even for the same pixel circuit, there may be differences in electrical characteristics.

[0006] Even if the difference in electrical characteristics between pixel circuits is compensated, color spots or discoloration may occur during the manufacturing process of the display device. Therefore, optical compensation may be performed by taking a test image of the display device using an optical system.

[0007] However, accurate optical compensation at the sub-pixel level is difficult due to limitations of the optical system, such as the moiré phenomenon. Summary of the invention

[0008] The present disclosure provides a display device capable of accurately performing optical compensation, a method of compensating for pixel circuit differences in a display device, and a device for generating compensation data for a plurality of pixels.

[0009] According to an embodiment of the present disclosure, a method for compensating for pixel circuit differences in a display device includes: displaying a test image of multiple pixels of the display device; generating a first camera image by photographing the test image; applying a test input signal to each of the multiple pixels and sensing a corresponding test output, wherein the test input signal is at least one of a test current and a test voltage; generating weights for the multiple pixels based on the test output; generating a second camera image by applying the weights to the first camera image; and generating compensation data for the multiple pixels based on the second camera image.

[0010] The test output may include at least one of a threshold voltage of a driving transistor of the plurality of pixels, a mobility of the plurality of pixels, and a threshold voltage of a light emitting element of the plurality of pixels.

[0011] A size of a color spot disposed in a first region of the first camera image may be greater than a size of a color spot disposed in a corresponding region of the second camera image, the corresponding region and the first region representing a same portion of pixels among the plurality of pixels.

[0012] The generating the second camera image may include multiplying the weight by a corresponding gray level of the first camera image.

[0013] The method may further include storing the compensation data in a memory of the display device.

[0014] The first camera image and the second camera image may not be stored in a memory of the display device.

[0015] The compensation data may include compensation gray levels for the plurality of pixels, and a size of the compensation gray level of the compensation data may be inversely proportional to a size of a gray level of the second camera image of the plurality of pixels.

[0016] Each of the plurality of pixels may include a first sub-pixel of a first color, a second sub-pixel of a second color, and a third sub-pixel of a third color, and at least one of generating the first camera image, generating the second camera image, and generating the compensation data may be independently performed for each of the first sub-pixel, the second sub-pixel, and the third sub-pixel.

[0017] Each of the plurality of pixels includes a first subpixel of a first color, a second subpixel of a second color, and a third subpixel of a third color, and at least one of generating the first camera image, generating the second camera image, and generating the compensation data can be performed for the first subpixel, the second subpixel, and the third subpixel in a coordinated order.

[0018] According to an embodiment of the present disclosure, a device for generating compensation data for multiple pixels includes: a camera, which generates a first camera image by photographing a test image displayed by the multiple pixels of a display device; and a test controller, which inputs a test input signal to each of the multiple pixels and senses a corresponding test output, wherein the test input signal is at least one of a test current and a test voltage, wherein the test controller generates weights for the multiple pixels based on the test outputs, generates a second camera image by applying the weights to the first camera image, and generates compensation data for the multiple pixels based on the second camera image.

[0019] The test output may include at least one of a threshold voltage of a driving transistor of the plurality of pixels, a mobility of the plurality of pixels, and a threshold voltage of a light emitting element of the plurality of pixels.

[0020] A size of a color spot disposed in a first region of the first camera image may be greater than a size of a color spot disposed in a corresponding region of the second camera image, the corresponding region and the first region representing a same portion of pixels among the plurality of pixels.

[0021] The second camera image may be generated by multiplying the weight by a corresponding gray level of the first camera image.

[0022] The test controller may store the compensation data in a memory of the display device.

[0023] The compensation data may be stored in a memory of the display device without the first camera image and the second camera image.

[0024] The compensation data may include compensation gray levels for the plurality of pixels, and a size of the compensation gray level of the compensation data may be inversely proportional to a size of a gray level of the second camera image of the plurality of pixels.

[0025] A display device according to an embodiment of the present disclosure includes: a plurality of pixels; a sensing unit, sensing corresponding test outputs from the plurality of pixels to which a test input signal is applied, wherein the test input signal is at least one of a test current and a test voltage; a memory, providing first compensation data as optical compensation data; and a compensation data correction unit, generating second compensation data by applying a weight based on the test output to the first compensation data.

[0026] The first compensation data may be maintained without change, and the second compensation data may be updated when the test output is updated.

[0027] The display device may further include a timing controller which generates an output grayscale by applying the second compensation data to input grayscales of the plurality of pixels.

[0028] The display device may further include a data driver generating a data voltage corresponding to the output grayscale and supplying the data voltage to the plurality of pixels.

[0029] A display device, a method of compensating for a pixel circuit difference in a display device, and a device for generating compensation data for a plurality of pixels according to the present disclosure may accurately perform optical compensation. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 2 is a diagram for illustrating a device for generating compensation data according to an embodiment of the present disclosure.

[0031] Figure 2 is a diagram for illustrating a display device according to an embodiment of the present disclosure.

[0032] Figure 3 is a diagram for illustrating pixels and sensing channels according to an embodiment of the present disclosure.

[0033] Figure 4 is a diagram for illustrating a display period according to an embodiment of the present disclosure.

[0034] Figure 5 is a diagram for illustrating a threshold voltage sensing period of a transistor according to an embodiment of the present disclosure.

[0035] Figure 6 is a diagram for illustrating a mobility sensing period according to an embodiment of the present disclosure.

[0036] Figure 7 is a diagram for illustrating a threshold voltage sensing period of a light emitting diode according to an embodiment of the present disclosure.

[0037] Figure 8 is a diagram for illustrating a first camera image according to an embodiment of the present disclosure.

[0038] Fig. 9 and Fig.10 is a diagram for illustrating a test output according to an embodiment of the present disclosure.

[0039] Fig.11 is a diagram for illustrating weights according to an embodiment of the present disclosure.

[0040] Fig.12 is a diagram for illustrating a second camera image according to an embodiment of the present disclosure.

[0041] Fig.13is a diagram for illustrating compensation data according to an embodiment of the present disclosure.

[0042] Fig.14 is a diagram for illustrating a display device according to another embodiment of the present disclosure.

[0043] Fig.15 is a diagram for illustrating first compensation data according to an embodiment of the present disclosure.

[0044] Fig.16 is a diagram for illustrating weights according to an embodiment of the present disclosure.

[0045] Fig.17 is a diagram for illustrating second compensation data according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0046] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the present disclosure. The present disclosure can be embodied in many different forms and is not limited to the embodiments described herein.

[0047] In order to clearly illustrate the present disclosure, parts not related to the description are omitted, and the same or similar constituent elements are given the same reference numerals throughout the specification. Therefore, the aforementioned reference numerals may be used in other drawings.

[0048] In addition, since the size and thickness of each configuration shown in the drawings are selected for better understanding and clear description, the present disclosure is not necessarily limited to the depicted relative dimensions. In the drawings, the sizes of layers and regions are exaggerated for clarity of illustration.

[0049] The expression "same" in the specification may mean "substantially the same" so that those skilled in the art will understand that the multiple elements achieve the same purpose intended.

[0050] Figure 1 2 is a diagram for illustrating a device for generating compensation data according to an embodiment of the present disclosure.

[0051] refer to Figure 1 The compensation data generating device (also referred to as a device for generating compensation data for a plurality of pixels) ED according to an embodiment of the present disclosure may include a camera 110 and a test controller 120 .

[0052] The camera 110 may generate a camera image by photographing a test image displayed by pixels of the display device DD. The camera 110 may be configured by various brightness meters, optical systems, and the like.

[0053] The test controller 120 may input a test current or a test voltage to each of the pixels of the display device DD and sense a corresponding test output. The test controller 120 may be composed of a general or dedicated computing device. The computing device may include a recording medium and a processor. The recording medium and the processor may be physically included in the same device, but may also be physically included in different devices using cloud technology, etc.

[0054] Recording media include all types of recording devices that can store data or programs that can be read by a processor. Examples of recording media that can be read by a processor may include read-only memory (ROM), random access memory (RAM), compact disc read-only memory (CD-ROM), magnetic tape, floppy disk, optical data storage device, hard disk, external hard disk, solid state drive (SSD), universal serial bus (USB) storage device, digital video disc (DVD) and blue disc. In addition, the recording medium that can be read by the processor can be a combination of multiple devices or can be distributed in a computer system connected to a network. The recording medium can be a non-transitory computer-readable medium. Non-transitory computer-readable medium can refer to a medium that can store data or programs semi-permanently and can be read by a processor, rather than a medium (such as a register, cache and memory) that stores data or programs for a short time.

[0055] Figure 2 is a diagram for illustrating a display device according to an embodiment of the present disclosure.

[0056] refer to Figure 2 , the display device DD according to an embodiment of the present disclosure includes a timing controller 11 , a data driver 12 , a scan driver 13 , a pixel unit 14 , a sensing unit 15 , and a memory 16 .

[0057] The memory 16 includes all types of recording devices capable of writing or reading data. The memory 16 may be an external memory or an internal memory of the timing controller 11. In addition, the memory 16 may be an internal memory of another device. The memory 16 may include compensation data CDATA. The compensation data CDATA may be optical compensation data and may be pre-created and stored in the memory 16 before product shipment. During the use of the display device DD, the compensation data CDATA may remain unchanged.

[0058] The timing controller 11 may receive an input grayscale and a control signal for each frame (eg, image frame) from a processor. Here, the processor may correspond to at least one of a graphics processing unit (GPU), a central processing unit (CPU), and an application processor (AP).

[0059] The timing controller 11 may convert an input gray level to generate an output gray level. At least one of the sensing data provided by the sensing unit 15 and the compensation data CDATA provided by the memory 16 may be used to generate the output gray level.

[0060] For example, the timing controller 11 may generate an output gray level by converting an input gray level using sensing data provided by the sensing unit 15. For example, the timing controller 11 may generate an output gray level by converting an input gray level using compensation data CDATA provided by the memory 16. For example, the timing controller 11 may generate an intermediate gray level by converting an input gray level using sensing data, and may generate an output gray level by converting the intermediate gray level using compensation data CDATA. Compensation using sensing data may compensate for discreteness of electrical characteristics of a pixel circuit. Compensation using compensation data CDATA may compensate for color spots, discoloration, etc. that occur during the manufacturing process of the display device DD. The selection of application data or the order of application may vary according to the embodiment.

[0061] The timing controller 11 may provide an output grayscale to the data driver 12. In addition, the timing controller 11 may provide a control signal suitable for the specification of each of the data driver 12, the scan driver 13, and the sensing unit 15.

[0062] In the display period, the data driver 12 can use the output grayscale and control signal received from the timing controller 11 to generate the data voltage to be provided to the data lines D1, D2, D3, ... and Dm. For example, the data driver 12 can sample the output grayscale using a clock signal and convert the sampled output grayscale into a data voltage. The data driver 12 can apply data voltages to the data lines D1 to Dm in units of pixel rows. m can be an integer greater than zero. Here, a pixel row refers to a pixel (or sub-pixel) connected to the same scan line. During the sensing period, the data driver 12 can supply a reference voltage to the data lines D1 to Dm.

[0063] The scan driver 13 may receive a clock signal, a scan start signal, etc. from the timing controller 11 to generate a first scan signal to be provided to the first scan lines S11, S12, ... and S1n and a second scan signal to be provided to the second scan lines S21, S22, ... and S2n. n may be an integer greater than zero.

[0064] The scan driver 13 may sequentially supply a first scan signal having a pulse at an on-level to the first scan lines S11 to S1n. In addition, the scan driver 13 may sequentially supply a second scan signal having a pulse at an on-level to the second scan lines S21 to S2n. The scan driver 13 may include a first scan driver connected to the first scan lines S11, S12, ..., and S1n and a second scan driver connected to the second scan lines S21, S22, ..., and S2n. Each of the first scan driver and the second scan driver may include a scan stage formed in the form of a shift register. Each of the first scan driver and the second scan driver may generate a scan signal by sequentially transmitting a scan start signal in the form of a pulse as an on-level to a next scan stage under the control of a clock signal.

[0065] In the display period, the sensing unit 15 may supply an initialization voltage to the sensing lines I1, I2, I3, ... and Ip. p may be an integer greater than 0. In the sensing period, the sensing unit 15 may receive a sensing voltage from the sensing lines I1 to Ip connected to the pixels (or sub-pixels).

[0066] The sensing unit 15 may include sensing channels connected to the sensing lines I1 to Ip. For example, the sensing lines I1 to Ip and the sensing channels may correspond one to one. For example, the number of sensing lines I1 to Ip and the number of sensing channels may be the same. In another embodiment, the number of sensing channels may be less than the number of sensing lines I1 to Ip. At this time, the sensing unit 15 may further include a demultiplexer to perform sensing of pixels (or sub-pixels) in a time-division manner.

[0067] The pixel unit 14 includes a plurality of pixels. Each pixel may include a first sub-pixel emitting light of a first color, a second sub-pixel emitting light of a second color, and a third sub-pixel emitting light of a third color. The first color, the second color, and the third color may be different colors.

[0068] Each sub-pixel SPij can be connected to a corresponding data line, a scan line, and a sensing line. i can be an integer greater than zero and less than or equal to n, and j can be an integer greater than zero and less than or equal to m. The pixel (or sub-pixel) can be connected to a common first power line ELVDD and a common second power line ELVSS. For example, during a display period, the voltage of the first power line ELVDD can be greater than the voltage of the second power line ELVSS.

[0069] According to an embodiment, at least two of the timing controller 11, the data driver 12, the scan driver 13, the pixel unit 14, the sensing unit 15, and the memory 16 may be formed of an integrated chip (IC). Figure 1Each functional unit shown in the figure falls within the scope that can be easily changed by those skilled in the art, and descriptions of all possibilities will be omitted.

[0070] Figure 3 is a diagram for illustrating pixels and sensing channels according to an embodiment of the present disclosure.

[0071] The sub-pixel SPij may include transistors T1 , T2 , and T3 , a storage capacitor Cst, and a light emitting diode LD.

[0072] Transistors T1, T2 and T3 may be composed of N-type transistors. In another embodiment, transistors T1, T2 and T3 may be composed of P-type transistors. In another embodiment, transistors T1, T2 and T3 may be composed of a combination of N-type transistors and P-type transistors. P-type transistors are a general term for transistors in which the amount of current to be conducted increases when the voltage difference between the gate electrode and the source electrode increases in the negative direction. N-type transistors are a general term for transistors in which the amount of current to be conducted increases when the voltage difference between the gate electrode and the source electrode increases in the positive direction. Transistors may be composed of various forms, such as thin film transistors (TFTs), field effect transistors (FETs), and bipolar junction transistors (BJTs).

[0073] The first transistor T1 may have a gate electrode connected to the first node N1, a first electrode connected to the first power line ELVDD, and a second electrode connected to the second node N2. The first transistor T1 may be referred to as a driving transistor.

[0074] The second transistor T2 may have a gate electrode connected to the first scan line S1i, a first electrode connected to the data line Dj, and a second electrode connected to the first node N1. The second transistor T2 may be referred to as a scan transistor.

[0075] The third transistor T3 may have a gate electrode connected to the second scan line S2i, a first electrode connected to the second node N2, and a second electrode connected to the sensing line Ik. The third transistor T3 may be referred to as a sensing transistor.

[0076] The storage capacitor Cst may have a first electrode connected to the first node N1 and a second electrode connected to the second node N2 .

[0077] The light emitting diode LD may have an anode connected to the second node N2 and a cathode connected to the second power line ELVSS. The light emitting diode LD may emit light of one of the first color, the second color, and the third color.

[0078] Generally, the voltage of the first power line ELVDD may be greater than the voltage of the second power line ELVSS. However, in special cases, such as preventing the light emitting diode LD from emitting light, the voltage of the second power line ELVSS may be set to be greater than the voltage of the first power line ELVDD.

[0079] The sensing channel 151 may include a first switch SW1 , a second switch SW2 , and a sensing capacitor Css.

[0080] The first electrode of the first switch SW1 may be connected to the third node N3. For example, the third node N3 may correspond to the sensing line Ik. The second electrode of the first switch SW1 may receive the initialization voltage Vint. For example, the second electrode of the first switch SW1 may be connected to an initialization power supply supplying the initialization voltage Vint.

[0081] A first electrode of the second switch SW2 may be connected to the third node N3 , and a second electrode of the second switch SW2 may be connected to the fourth node N4 .

[0082] The sensing capacitor Css may have a first electrode connected to the fourth node N4 and a second electrode connected to a reference power source (eg, ground).

[0083] Although not shown, the sensing unit 15 (see Figure 2 ) may include an analog-to-digital converter. For example, the sensing unit 15 may include an analog-to-digital converter corresponding to the number of sensing channels. The analog-to-digital converter may convert the sensing voltage stored in the sensing capacitor Css into a digital value. The converted digital value may be provided as sensing data to the timing controller 11 (see Figure 2 In another example, the sensing unit 15 may include analog-to-digital converters whose number is less than the number of sensing channels, and may convert the sensing signals stored in the sensing channels in a time-division manner.

[0084] Figure 4 is a diagram for illustrating a display period according to an embodiment of the present disclosure.

[0085] refer to Figure 4 , also refer to Figure 3 , the sensing line Ik (ie, the third node N3) may receive the initialization voltage Vint during the display period. During the display period, the first switch SW1 may be in the on state and the second switch SW2 may be in the off state.

[0086] During the display period, data voltages DS(i-1)j, DSij, and DS(i+1)j may be sequentially applied to the data line Dj in units of horizontal periods. A first scan signal at an on level (e.g., a logic high level) may be applied to the first scan line S1i in the horizontal period. In addition, a second scan signal at an on level may be applied to the second scan line S2i in synchronization with the first scan line S1i. In another embodiment, during the display period, the second scan line S2i may always be in a state of applying a second scan signal at an on level.

[0087] For example, when a scan signal at a turn-on level is applied to the first scan line S1i and the second scan line S2i, the second transistor T2 and the third transistor T3 may be in a turn-on state. Accordingly, a voltage corresponding to the difference between the data voltage DSij and the initialization voltage Vint is written into the storage capacitor Cst of the subpixel SPij.

[0088] In the subpixel SPij, the amount of driving current flowing in the driving path connecting the first power line ELVDD, the first transistor T1, the light emitting diode LD, and the second power line ELVSS is determined depending on the voltage difference between the gate electrode and the source electrode of the first transistor T1. The light emitting brightness of the light emitting diode LD can be determined according to the level of the driving current.

[0089] Thereafter, when a scan signal at a cut-off level (e.g., a logic low level) is applied to the first scan line S1i and the second scan line S2i, the second transistor T2 and the third transistor T3 may be in a cut-off state. Therefore, regardless of the voltage change of the data line Dj, the voltage difference between the gate electrode and the source electrode of the first transistor T1 may be maintained by the storage capacitor Cst, and the light emitting brightness of the light emitting diode LD may be maintained.

[0090] Figure 5 is a diagram for illustrating a threshold voltage sensing period of a transistor according to an embodiment of the present disclosure.

[0091] refer to Figure 5 , also refer to Figure 2 and Figure 3 , before time t1a, the first switch SW1 may be in the on state, and the second switch SW2 may be in the off state. Therefore, the initialization voltage Vint may be applied to the third node N3. In addition, the data driver 12 may supply the reference voltage Vref1 to the data line Dj.

[0092] At time t1a, a first scan signal at an on level may be supplied to the first scan line S1i, and a second scan signal at an on level may be supplied to the second scan line S2i. Therefore, a reference voltage Vref1 may be applied to the first node N1, and an initialization voltage Vint may be applied to the second node N2. Therefore, the first transistor T1 may be turned on depending on the difference between the gate voltage and the source voltage.

[0093] At time t2a, the second switch SW2 may be turned on. Therefore, the first electrode of the sensing capacitor Css may be initialized to the initialization voltage Vint.

[0094] At time t3a, the first switch SW1 may be turned off. Therefore, as current is supplied from the first power line ELVDD, the voltages of the second node N2 and the third node N3 may increase. In response to the voltages at the second node N2 and the third node N3 increasing to the sensing voltage (Vref1-Vth), the first transistor T1 is turned off. In the case where the first transistor T1 is turned off, the voltages of the second node N2 and the third node N3 no longer increase. Since the fourth node N4 is connected to the third node N3 through the second switch SW2 in the on state, the sensing voltage (Vref1-Vth) is stored in the first electrode of the sensing capacitor Css.

[0095] At time t4a, the second switch SW2 is turned off, so the sensing voltage (Vref1-Vth) of the first electrode of the sensing capacitor Css can be maintained. The sensing unit 15 can perform analog-to-digital conversion of the sensing voltage (Vref1-Vth) and thus can determine the threshold voltage Vth of the first transistor T1 of the subpixel SPij.

[0096] At time t5a, the first scan signal at the off level may be supplied to the first scan line S1i, and the second scan signal at the off level may be supplied to the second scan line S2i. In addition, the first switch SW1 may be turned on. Therefore, the initialization voltage Vint may be applied to the third node N3.

[0097] Figure 6 is a diagram for illustrating a mobility sensing period according to an embodiment of the present disclosure. Figure 6 , also refer to Figure 3 , the mobility sensing period allows the mobility of the first transistor T1 to be determined.

[0098] At time t1b, a first scan signal at an on level may be applied to the first scan line S1i, and a second scan signal at an on level may be applied to the second scan line S2i. At this time, since the reference voltage Vref2 is applied to the data line Dj, the reference voltage Vref2 may be applied to the first node N1. In addition, since the first switch SW1 is in an on state, the initialization voltage Vint may be applied to the second node N2 and the third node N3. Therefore, the first transistor T1 may be turned on depending on the difference between the gate voltage and the source voltage.

[0099] At time t2b, when the first scan signal at the off level is applied to the first scan line S1i, the first node N1 may be in a floating state. In addition, when the second switch SW2 is turned on, the initialization voltage Vint may be applied to the fourth node N4.

[0100] At time t3b, the first switch SW1 may be turned off. Therefore, when current is supplied from the first power line ELVDD through the first transistor T1, the voltages of the second node N2, the third node N3, and the fourth node N4 increase. At this time, since the first node N1 is in a floating state, the gate-source voltage difference of the first transistor T1 may be maintained.

[0101] At time t4b, the second switch SW2 may be turned off. Therefore, the sensing voltage is stored in the first electrode of the sensing capacitor Css. The sensing current of the first transistor T1 may be obtained as shown in Equation 1 below.

[0102] [Equation 1]

[0103] I=C×(Vp2-Vp1) / (tp2-tp1)

[0104] At this time, I is a sensing current of the first transistor T1, C is a capacitance of the sensing capacitor Css, Vp2 is a sensing voltage at time tp2, and Vp1 is a sensing voltage at time tp1.

[0105] Assuming that the voltage slope of the fourth node N4 between time t3b and time t4b is linear, the sensing voltage at time t3b and the sensing voltage at time t4b can be determined, and the sensing current of the first transistor T1 can be calculated. In addition, the mobility of the first transistor T1 can be calculated using the calculated sensing current. For example, the larger the sensing current, the larger the mobility. For example, the size of the mobility can be proportional to the size of the sensing current.

[0106] Figure 7 is a diagram for illustrating a threshold voltage sensing period of a light emitting diode according to an embodiment of the present disclosure.

[0107] refer to Figure 7, also refer to Figure 3 , at time t1c, a first scan signal at an on level may be applied to the first scan line S1i, and a second scan signal at an on level may be applied to the second scan line S2i. At this time, since the reference voltage Vref3 is applied to the data line Dj, the reference voltage Vref3 may be applied to the first node N1. At the same time, since the first switch SW1 is in an on state, the initialization voltage Vint may be applied to the second node N2 and the third node N3. Therefore, the first transistor T1 may be turned on depending on the gate-source voltage Vgs1.

[0108] At time t2c, a second scan signal at a cut-off level may be applied to the second scan line S2i. In addition, a first scan signal at a cut-off level may be applied to the first scan line S1i at time t2c or immediately thereafter. At this time, the voltage of the second node N2 increases due to the current supplied from the first power line ELVDD. In addition, the voltage of the first node N1 coupled to the second node N2 and in a floating state also increases. At this time, the voltage of the second node N2 is saturated to a voltage corresponding to the threshold voltage of the light emitting diode LD. As the degree of degradation of the light emitting diode LD increases, the voltage of the saturated second node N2 may increase. The gate-source voltage Vgs2 of the first transistor T1 may be reset by the voltage of the saturated second node N2. For example, the reset gate-source voltage Vgs2 may be less than the preset gate-source voltage Vgs1.

[0109] At time t3c, the second scan signal at the on level may be applied to the second scan line S2i. Therefore, the initialization voltage Vint may be applied to the second node N2. At this time, the reset gate-source voltage Vgs2 may be maintained by the storage capacitor Cst.

[0110] At time t4c, the first switch SW1 may be turned off. At this time, since the second switch SW2 is in the on state, the voltages of the second node N2, the third node N3, and the fourth node N4 may increase. The greater the degree of degradation of the light emitting diode LD (or the threshold voltage of the light emitting diode LD), the smaller the slope of the voltage increase.

[0111] At time t5c, the second scan signal at the turn-off level may be applied to the second scan line S2i, and the second switch SW2 may be turned off. Accordingly, the threshold voltage of the light emitting diode LD may be calculated using the sensing voltage stored in the sensing capacitor Css.

[0112] Figure 8 is a diagram for illustrating a first camera image according to an embodiment of the present disclosure.

[0113] In reference Figure 1 , Figures 8 to 17When illustrating the present disclosure, each process may be performed in pixel units or in sub-pixel units. For example, a process of generating at least one of the first camera image CIMG1, the second camera image CIMG2, the compensation data CDATA, the sensing data, the first compensation data CDATA1, the weight SWT, and the second compensation data CDATA2 may be performed for each of the first sub-pixel, the second sub-pixel, and the third sub-pixel (sub-pixel unit). A process of generating at least one of the first camera image CIMG1, the second camera image CIMG2, the compensation data CDATA, the sensing data, the first compensation data CDATA1, the weight SWT, and the second compensation data CDATA2 may be performed for the first sub-pixel, the second sub-pixel, and the third sub-pixel (pixel unit) in a coordinated manner (or coordinated order) (e.g., simultaneously or in a predetermined order). In some embodiments, a process of generating at least one of the first camera image CIMG1, the second camera image CIMG2, the compensation data CDATA, the sensing data, the first compensation data CDATA1, the weight SWT, and the second compensation data CDATA2 may be performed independently for the first sub-pixel, the second sub-pixel, and the third sub-pixel, regardless of whether the process is performed for other sub-pixels. Since it is impossible to describe the possibilities, the following description will be made based on a pixel unit, but each embodiment is not limited thereto.

[0114] The camera 110 may generate a first camera image CIMG1 by photographing a test image displayed by pixels of the display device DD. It is assumed that the first camera image CIMG1 includes fine color spots in the first area AR1. The first camera image CIMG1 may be photographed in units of pixels, but may be in a blurred state due to limitations of the optical system (e.g., interference of light emitted from adjacent pixels, etc.). Therefore, the gray level of each pixel in the first camera image CIMG1 cannot be fully trusted.

[0115] Fig. 9 and Fig.10 is a diagram for illustrating a test output according to an embodiment of the present disclosure.

[0116] Test controller 120 (see Figure 1 ) can input the test current or test voltage to the display device DD (see Figure 1 ) and sense the corresponding test output. The test output may be the threshold voltage of the driving transistor of the pixel (see Figure 5 ), pixel mobility (see Figure 6 ) and the threshold voltage of the pixel's light-emitting element (see Figure 7 The test output may refer to the above-mentioned sensing data.

[0117] For example, the test controller 120 may be configured to control the data driver 12 (see Figure 2 ) and the sensing unit 15 (see Figure 2 ) before being mounted on the display device DD, a test current or a test voltage is input to each pixel of the display device DD, and a corresponding test output can be sensed. In this case, the test controller 120 can replace the functions of the data driver 12 and the sensing unit 15.

[0118] For example, after the data driver 12 and the sensing unit 15 are mounted on the display device DD, the test controller 120 may input a test current or a test voltage to the data driver 12 and the sensing unit 15 , and may also receive a test output sensed by the sensing unit 15 .

[0119] The magnitude of the test output may indicate the electrical characteristics of each pixel. For example, as the threshold voltage of the driving transistor increases, the magnitude of the test output may decrease. For example, the test output may decrease as the transistor mobility decreases. For example, the test output may decrease as the threshold voltage of the light emitting element increases. Fig.10 Table STAB1 in FIG. 1 shows the test outputs of some pixels as an example. Fig. 9 , as the test output becomes smaller, the sensed image SIMG represented becomes darker.

[0120] Fig.11 is a diagram for illustrating weights according to an embodiment of the present disclosure.

[0121] refer to Fig.11 Table STAB2 in , shows the weights for some pixels as an example.

[0122] Test controller 120 (see Figure 1 ) can generate weights for pixels based on the test output. The size of the weight can be set proportionally to the size of the test output. For example, the smaller the size of the test output, the smaller the size of the corresponding weight.

[0123] Fig.12 is a diagram for illustrating a second camera image according to an embodiment of the present disclosure.

[0124] Test controller 120 (see Figure 1 ) can be obtained by applying the weights to the first camera image CIMG1 (see Figure 8 ) to generate the second camera image CIMG2. For example, the second camera image CIMG2 may be generated by multiplying the gray levels of the first camera image CIMG1 by the weights corresponding to them. After this process, the second camera image CIMG2 may be a normalized image. The second camera image CIMG2 may be a less blurred version of the first camera image CIMG1.

[0125] Compare Figure 8 and Fig.12 , the size of the color spot set in the first area AR1 of the first camera image CIMG1 can be larger than the size of the color spot set in the first area AR1 of the second camera image CIMG2. That is, with reference to the second camera image CIMG2, light interference caused by adjacent pixels or limitations of the optical system can be overcome, and pixels where fine color spots occur can be accurately identified.

[0126] Fig.13 is a diagram for illustrating compensation data according to an embodiment of the present disclosure.

[0127] Test controller 120 (see Figure 1 ) can use the second camera image CIMG2 (see Fig.12 ) generates compensation data CDATA for the pixel. The compensation data CDATA may include a compensated grayscale for the pixel. In some embodiments, the size of the compensation data CDATA may be inversely proportional to the size of the grayscale data for the second camera image CIMG2. For example, the lower the grayscale of the second camera image CIMG2 of the pixel, the higher the compensated grayscale of the compensation data CDATA.

[0128] refer to Figure 1 and Figure 2 , the test controller 120 may store the compensation data CDATA in the memory 16 of the display device DD. However, the test controller 120 may not store the first camera image CIMG1 and the second camera image CIMG2 in the memory 16. As a result, the storage capacity required for the memory 16 may be reduced. For example, the timing controller 11 may generate an output gray level by adding the compensated gray level of the compensation data CDATA to the input gray level.

[0129] Fig.14 is a diagram for illustrating a display device according to another embodiment of the present disclosure. Fig.15 is a diagram for illustrating first compensation data according to an embodiment of the present disclosure. Fig.16 is a diagram for illustrating weights according to an embodiment of the present disclosure. Fig.17 is a diagram for illustrating second compensation data according to an embodiment of the present disclosure.

[0130] refer to Fig.14 , the display device DD' and Figure 2 The display device DD' is different from the display device DD in that the display device DD' further includes a compensation data correction unit 17. Hereinafter, descriptions of components overlapping with those of the display device DD will be omitted.

[0131] The memory 16 may provide the first compensation data CDATA1 as optical compensation data. At this time, the first compensation data CDATA1 may be optical compensation data that does not reflect the above-mentioned test output.

[0132] The compensation data correction unit 17 may generate the second compensation data CDATA2 by applying the weight SWT based on the test output to the first compensation data CDATA1 . Figures 9 to 11 The weights described in can be applied to the first camera image CIMG1 (see Figure 8 ),and Fig.16 The weight SWT described in the above may be applied to the first compensation data CDATA1. That is, even if Figures 9 to 11 The test output of the weights described in Fig.16 The test output of the weighted SWT described in is the same, and the data can also be modified to suit individual purposes. For example, as the test output becomes smaller, Figures 9 to 11 The weights described in can be reduced. However, as the test output becomes smaller, Fig.16 The weights described in SWT can be increased.

[0133] The first compensation data CDATA1 of the memory 16 may remain unchanged. However, since the weight SWT is updated when the test output is updated, the second compensation data CDATA2 may be updated.

[0134] Here, the test output is not generated by the compensation data generating device ED (see Figure 1 ). The test output may be a value generated by the sensing unit 15 of the display device DD in real time during use of the display device DD. Therefore, the test output may be updated in real time.

[0135] The timing controller 11 may generate an output gray level by applying the second compensation data CDATA2 to an input gray level of a pixel.

[0136] The data driver 12 may generate data voltages corresponding to output gray levels and supply them to pixels.

[0137] According to one embodiment, unlike in the display device DD, the second compensation data CDATA2 may be updated depending on a change in the electrical characteristics of the pixel unit 14 .

[0138] The drawings and descriptions of the present disclosure are intended to be illustrative, and they are not intended to limit the meaning or scope of the present disclosure described in the claims, but are only intended to explain the present disclosure. Therefore, it will be understood by those skilled in the art that various modifications and other equivalent embodiments may be made therefrom. Therefore, the actual protection scope of the present disclosure should be determined by the technical scope of the attached claims.

Claims

1. A method for compensating for pixel circuit differences in a display device, wherein: The method comprises: displaying a test image of a plurality of pixels of the display device; Generate a first camera image by photographing the test image; applying a test input signal to each of the plurality of pixels and sensing a corresponding test output, wherein the test input signal is at least one of a test current and a test voltage; generating weights for the plurality of pixels based on the test output; generating a second camera image by applying the weights to the first camera image; and Compensation data for the plurality of pixels is generated based on the second camera image.

2. The method according to claim 1, wherein: The test output includes at least one of a threshold voltage of a driving transistor of the plurality of pixels, a mobility of the plurality of pixels, and a threshold voltage of a light emitting element of the plurality of pixels.

3. The method according to claim 1, wherein: A size of a color spot disposed in a first region of the first camera image is greater than a size of a color spot disposed in a corresponding region of the second camera image, the corresponding region and the first region representing a same portion of pixels among the plurality of pixels.

4. The method according to claim 1, wherein: The generating the second camera image includes multiplying the weight by a corresponding grayscale level of the first camera image.

5. The method according to claim 1, wherein: The method further comprises: The compensation data is stored in a memory of the display device.

6. The method according to claim 1, wherein: The method also includes not storing the first camera image and the second camera image in a memory of the display device.

7. The method according to claim 1, wherein: The compensation data includes compensated gray levels for the plurality of pixels, The size of the compensation grayscale of the compensation data is inversely proportional to the size of the grayscale of the second camera image of the plurality of pixels.

8. The method according to claim 1, wherein: Each of the plurality of pixels includes a first sub-pixel of a first color, a second sub-pixel of a second color, and a third sub-pixel of a third color, and At least one of the generating the first camera image, the generating the second camera image, and the generating the compensation data is independently performed for each of the first sub-pixel, the second sub-pixel, and the third sub-pixel.

9. The method according to claim 1, wherein: Each of the plurality of pixels includes a first sub-pixel of a first color, a second sub-pixel of a second color, and a third sub-pixel of a third color, and At least one of the generating the first camera image, the generating the second camera image, and the generating the compensation data is performed for the first sub-pixel, the second sub-pixel, and the third sub-pixel in a coordinated sequence.

10. An apparatus for generating compensation data for a plurality of pixels, wherein: The device comprises: a camera that generates a first camera image by photographing a test image displayed by the plurality of pixels of the display device; and a test controller that inputs a test input signal to each of the plurality of pixels and senses a corresponding test output, the test input signal being at least one of a test current and a test voltage, The test controller generates weights for the plurality of pixels based on the test output, generates a second camera image by applying the weights to the first camera image, and generates compensation data for the plurality of pixels based on the second camera image.

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