Pixel and display device including same

Abstract

A pixel and a display device including the same are provided. The pixel includes: a first transistor including a gate terminal connected to a first node, a second terminal, and a first terminal connected to a second node; a second transistor including a gate terminal receiving a first gate signal, a first terminal receiving a data voltage, and a second terminal connected to the first node; a third transistor including a gate terminal receiving a second gate signal, a first terminal receiving the first power voltage, and a second terminal connected to the second terminal of the first transistor; a first capacitor including a first terminal and a second terminal connected to the first node and the second node, respectively; a second capacitor including a first terminal receiving the first power voltage and a second terminal connected to the second node; and a light emitting element connected to the second node and receiving the second power voltage. Therefore, the data swing range can be relatively reduced, and the pixel can be applied to small and medium-sized high-resolution display devices.

Description

Technical Field

[0001] Embodiments generally provide a pixel. More specifically, embodiments relate to a pixel and a display device including the pixel. Background Art

[0002] With the development of information technology, the importance of display devices as a communication medium between users and information has become increasingly prominent. Therefore, display devices such as liquid crystal display devices, organic light emitting display devices, plasma display devices, etc. are widely used in various fields.

[0003] The display device may include a display portion including a plurality of pixels capable of displaying an image. Each pixel may include a light emitting element, at least one transistor, and at least one capacitor. In addition, a signal line for applying a signal and / or voltage to a pixel may be provided in the display portion.

[0004] Meanwhile, the higher the resolution of the display device, the clearer and more vivid images can be provided. In order to increase the resolution of the display device, more pixels can be arranged in a limited area. Summary of the invention

[0005] The embodiment provides a pixel that can be applied to a high-resolution display device.

[0006] The embodiment provides a display device including the pixel.

[0007] In a disclosed embodiment, a pixel that sequentially performs an initialization operation, a threshold voltage compensation operation, a data writing operation, and a light-emitting operation during one frame includes: a first transistor, including a gate terminal connected to a first node, a second terminal, and a first terminal connected to the second node; a second transistor, including a gate terminal to which a first gate signal is applied, a first terminal to which a data voltage is applied, and a second terminal connected to the first node; a third transistor, including a gate terminal to which a second gate signal is applied, a first terminal to which a first power voltage is applied, and a second terminal connected to the second terminal of the first transistor; a first capacitor, including a first terminal connected to the first node and a second terminal connected to the second node; a second capacitor, including a first terminal to which a first power voltage is applied, and a second terminal connected to the second node; and a light-emitting element, including a first terminal connected to the second node and a second terminal to which a second power voltage is applied.

[0008] In an embodiment, the first power voltage may have a low level during an initialization period in which an initialization operation is performed. In such an embodiment, the first power voltage may have a high level after the initialization period.

[0009] In an embodiment, the second power voltage may have a low level in a light emitting period in which a light emitting operation is performed. In such an embodiment, the second power voltage may have a high level in the remaining periods except the light emitting period in one frame, and the initialization operation, the threshold voltage compensation operation, and the data writing operation are performed in the remaining periods.

[0010] In an embodiment, each of the first transistor, the second transistor, and the third transistor may be an n-channel metal oxide semiconductor (NMOS) transistor.

[0011] In an embodiment, the first gate signal may be a global clock signal for simultaneous light emission.

[0012] In an embodiment, the second gate signal may have a high level in an initialization period in which an initialization operation is performed and a light emission period in which a light emission operation is performed. In such an embodiment, the second gate signal may have a low level in a threshold voltage compensation period in which a threshold voltage compensation operation is performed and a data write period in which a data write operation is performed.

[0013] In the disclosed embodiment, the display device according to the disclosed embodiment includes a display part and a driving circuit, the display part includes a plurality of pixels, wherein each of the pixels sequentially performs an initialization operation, a threshold voltage compensation operation, a data writing operation and a light emitting operation during one frame, and the driving circuit drives the display part by providing a data voltage, a first gate signal, a second gate signal, a first power voltage and a second power voltage to the pixel. In such an embodiment, each of the pixels includes: a first transistor, including a gate terminal connected to a first node, a second terminal and a first terminal connected to a second node; a second transistor, including a gate terminal to which a first gate signal is applied, a first terminal to which a data voltage is applied and a second terminal connected to the first node; a third transistor, including a gate terminal to which a second gate signal is applied, a first terminal to which a first power voltage is applied and a second terminal connected to the second terminal of the first transistor; a first capacitor, including a first terminal connected to a first node and a second terminal connected to a second node; a second capacitor, including a first terminal to which a first power voltage is applied and a second terminal connected to a second node; and a light emitting element, including a first terminal connected to a second node and a second terminal to which a second power voltage is applied.

[0014] In an embodiment, the first power voltage may have a low level during an initialization period in which an initialization operation is performed. In such an embodiment, the first power voltage may have a high level after the initialization period.

[0015] In an embodiment, the second power voltage may have a low level in a light emitting period in which a light emitting operation is performed. In such an embodiment, the second power voltage may have a high level in the remaining periods except the light emitting period in one frame, and the initialization operation, the threshold voltage compensation operation, and the data writing operation are performed in the remaining periods.

[0016] In an embodiment, the pixels may simultaneously emit light during a light emission period in which a light emission operation is performed.

[0017] In an embodiment, the second gate signal may have a high level in an initialization period in which an initialization operation is performed and a light emission period in which a light emission operation is performed. In such an embodiment, the second gate signal may have a low level in a threshold voltage compensation period in which a threshold voltage compensation operation is performed and a data write period in which a data write operation is performed.

[0018] In the disclosed embodiment, the display device according to the disclosed embodiment includes a display portion that displays an image and a driving circuit that drives the display portion by providing a driving signal to the display portion. In such an embodiment, the display portion includes: an active layer, which is arranged on a substrate; a first gate layer, which is arranged on the active layer and includes a first gate electrode; a second gate layer, which is arranged on the first gate layer and includes a capacitor electrode, wherein the capacitor electrode overlaps with the first gate electrode in a plan view and constitutes a first capacitor together with a portion of the first gate electrode overlapping with the capacitor electrode; a first upper conductive layer, which is arranged on the second gate layer and includes an additional power line to which a first power voltage is applied; a second upper conductive layer, which is arranged on the first upper conductive layer and includes a power line to which a second power voltage is applied and a connection pattern connected to the capacitor electrode through a contact hole, wherein the connection pattern partially overlaps with the additional power line in a plan view and constitutes a second capacitor together with a portion of the additional power line overlapping with the connection pattern; and a pixel electrode, which is arranged on the second upper conductive layer and connected to the connection pattern through a contact hole.

[0019] In an embodiment, the substrate may include a display area corresponding to the display portion and a peripheral area located around the display area, wherein the driving circuit is disposed in the peripheral area, and the additional power line may be connected to the portion of the power line in the peripheral area through the contact hole.

[0020] In an embodiment, the first power voltage and the second power voltage may be the same voltage.

[0021] In an embodiment, the first power voltage may be different from the second power voltage, and the first power voltage may be a direct current power voltage.

[0022] In an embodiment, the substrate may include a display area corresponding to the display portion and a peripheral area located around the display area, wherein the driving circuit is disposed in the peripheral area, and the additional power line may be connected to the portion of the power line in the display area through the contact hole.

[0023] In an embodiment, the power line may at least partially overlap with the additional power line in plan view.

[0024] In an embodiment, the active layer may include a first active pattern and a second active pattern spaced apart from each other. In such an embodiment, the first gate layer may further include a second gate electrode overlapping the second active pattern in a plan view and a third gate electrode overlapping the first active pattern in a plan view. In such an embodiment, the first active pattern may constitute a first transistor together with a portion of the first gate electrode overlapping the first active pattern. In such an embodiment, the second active pattern may constitute a second transistor together with a portion of the second gate electrode overlapping the second active pattern. In such an embodiment, the first active pattern may constitute a third transistor together with a portion of the third gate electrode overlapping the first active pattern.

[0025] In an embodiment, the first upper conductive layer may further include a data line at least partially overlapping the connection pattern in a plan view, wherein the data voltage is applied to the data line.

[0026] In an embodiment, each of the power line, the additional power line, and the data line may extend in a first direction, and the power line, the additional power line, and the data line may be spaced apart from each other in a second direction crossing the first direction in a plan view.

[0027] In a pixel and a display device according to a disclosed embodiment, the pixel may include a pixel circuit and a light-emitting element, the pixel circuit includes three transistors and two capacitors, and the light-emitting element is electrically connected to the pixel circuit. In such an embodiment, a first capacitor among the capacitors may be connected between a gate terminal of the first transistor and a first terminal of the first transistor, and a second capacitor among the capacitors may be connected between the first terminal of the first transistor and a first power voltage. In such an embodiment, a plurality of pixels may emit light simultaneously during a light-emitting period.

[0028] In such an embodiment, the first power voltage may have a low level in the initialization period and may have a high level after the initialization period, and the second power voltage may have a low level in the light emitting period and may have a high level in the remaining periods except the light emitting period.

[0029] In such an embodiment, a portion of the connection pattern connected to the pixel electrode and a portion of the additional power line overlapping the portion of the connection pattern may constitute a second capacitor.In such an embodiment, the first power voltage or the DC power voltage may be applied to the additional power line.

[0030] Therefore, in such an embodiment, the data swing range can be relatively reduced, so that the pixel can be applied to small and medium-sized high-resolution display devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Illustrative, non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0032] Figure 1 is a plan view showing a display device according to a disclosed embodiment.

[0033] Figure 2 It is shown that the Figure 1 Circuit diagram of a pixel in the display section of FIG.

[0034] Figure 3 It is shown Figure 2 Waveform diagram of the operation period of a pixel.

[0035] Figure 4 It is schematically shown Figure 1 A cross-sectional view of the display portion.

[0036] Figures 5 to 15 It is shown Figure 1 and Figure 2 A floor plan showing part of the floors.

[0037] Fig.16 It is along Fig.15 A cross-sectional view taken along line II'.

[0038] Fig.17 It is along Fig.15 A cross-sectional view taken along line II-II'.

[0039] Fig.18 It shows that Fig.15 A plan view of an example of a power line with additional power line connections.

[0040] Fig.19 It shows that Fig.15 A plan view of another example of a power line connected to an additional power line. DETAILED DESCRIPTION

[0041] The invention will now be more fully described below with reference to the accompanying drawings in which various embodiments are shown. However, the invention may be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the invention to those skilled in the art. The same reference numerals represent the same elements throughout.

[0042] It will be understood that when an element is referred to as being “on” another element, the element can be directly on the other element or intervening elements may be present between the element and the other element. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements.

[0043] It will be understood that, although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings herein, the "first element", "first component", "first region", "first layer" or "first part" discussed below may be referred to as a second element, second component, second region, second layer or second part.

[0044] The terms used here are only for the purpose of describing specific embodiments and are not intended to be limiting. As used herein, unless the context clearly indicates otherwise, "one", "one (kind / person)" and "said / the" and "at least one (kind / person)" do not represent a limit to quantity, but are intended to include both the singular and the plural. Therefore, the reference to the "the" element after the reference to the element in the claim includes one element and multiple elements. For example, unless the context clearly indicates otherwise, "element" has the same meaning as "at least one element". "At least one (kind / person)" should not be interpreted as being limited to "one" or "one (kind / person)". "Or" means "and / or". As used herein, the term "and / or" includes any combination and all combinations of one or more of the relevant listed items. It will also be understood that when the term "includes" and / or its variations or "comprising" and / or its variations are used in this specification, it indicates the presence of the stated features, regions, wholes, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, regions, wholes, steps, operations, elements, components and / or groups thereof.

[0045] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used here to describe the relationship of one element to another element as shown in the figures. It will be understood that relative terms are intended to include different orientations of the device in addition to the orientation depicted in the figures. For example, if the device in one of the figures in the figures is turned over, the element described as being on the "lower" side of the other elements will then be oriented to be on the "upper" side of the other elements. Therefore, depending on the specific orientation of the figure, the term "lower" may include both "lower" and "upper" orientations. Similarly, if the device in one of the figures in the figures is turned over, the element described as being "below" or "under" the other elements will then be oriented to be "above" the other elements. Therefore, the term "below..." or "under..." may include both upper and lower orientations.

[0046] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. It will also be understood that terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense, unless explicitly defined as such herein.

[0047] Here, embodiments are described with reference to the cross-sectional views as schematic diagrams of idealized embodiments. In this way, variations in the shapes of the diagrams caused by, for example, manufacturing techniques and / or tolerances will be expected. Therefore, the embodiments described herein should not be interpreted as being limited to the specific shapes of the regions as shown here, but will include deviations in shapes caused by, for example, manufacturing. For example, a region shown or described as flat may generally have rough and / or nonlinear features. In addition, the sharp angles shown may be rounded. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shapes of the regions, and are not intended to limit the scope of the claims presented.

[0048] Hereinafter, a pixel and a display device including the same according to the disclosed embodiments will be described in detail with reference to the accompanying drawings. The same reference numerals are used for the same components in the drawings, and any repetitive detailed description of the same components will be omitted.

[0049] Figure 1 is a plan view showing a display device according to a disclosed embodiment.

[0050] Reference Figure 1 , a display device DD according to a disclosed embodiment may include a display part DP and a driving circuit PDV.

[0051] The display device DD can display an image through the display part DP. For example, the display part DP may include a plurality of pixels PX. Each of the plurality of pixels PX may include a transistor and a light emitting element electrically connected to the transistor. The light emitting element may emit light by receiving a driving signal from the transistor. In this way, the display device DD can display an image through a plurality of pixels PX that emit light.

[0052] Each pixel PX can display a predetermined basic color. In other words, one pixel PX can be the smallest unit that can display a color independently of other pixels PX. For example, each pixel PX can display a corresponding color among red, green and blue.

[0053] The pixels PX may be arranged in a matrix along a first direction DR1 and a second direction DR2 crossing the first direction DR1. For example, the first direction DR1 and the second direction DR2 may be perpendicular.

[0054] The driving circuit PDV can convert various driving signals (for example, Figure 2 The data voltage DATA, the first gate signal GW, the second gate signal GC, the first power voltage (or referred to as the first power supply voltage) ELVDD and the second power voltage (or referred to as the second power supply voltage) ELVSS) are provided to the plurality of pixels PX. Therefore, the driving circuit PDV can drive the display part DP. The driving circuit PDV may include a gate driver GDV, a data driver DDV, a timing controller CON, a first power driver PD1 and a second power driver PD2.

[0055] The timing controller CON can generate a gate control signal GCTRL, a data control signal DCTRL, and an output image data ODAT based on a control signal CTRL and input image data IDAT provided from the outside. For example, the control signal CTRL may include a vertical synchronization signal, a horizontal synchronization signal, an input data enable signal, a main clock signal, etc. For example, the input image data IDAT may be RGB data including red image data, green image data, and blue image data. Alternatively, the input image data IDAT may include magenta image data, cyan image data, and yellow image data.

[0056] The gate driver GDV may generate a gate signal based on a gate control signal GCTRL provided from a timing controller CON. For example, the gate control signal GCTRL may include a vertical start signal, a clock signal, etc. For example, the gate driver GDV may be manufactured as a separate panel and connected to the display part DP. The gate driver GDV may be electrically connected to the display part DP and sequentially output a gate signal. Each of the plurality of pixels PX may receive a data voltage from the data driver DDV based on the control of each of the gate signals.

[0057] The data driver DDV may generate a data voltage based on a data control signal DCTRL and output image data ODAT provided from a timing controller CON. For example, the data control signal DCTRL may include an output data enable signal, a horizontal start signal, a load signal, etc. For example, the data driver DDV may be manufactured as a separate panel and electrically connected to the display portion DP. Each of the plurality of pixels PX may provide a signal for brightness corresponding to each of the data voltages to the light emitting element.

[0058] The first power driver PD1 may be controlled by the timing controller CON. The first power driver PD1 may be configured to generate a first power voltage (eg, Figure 2 The first power driver PD1 supplies a first power voltage ELVDD to the plurality of pixels PX. In an embodiment, the first power driver PD1 may change a voltage level of the first power voltage at a predetermined time during each frame period.

[0059] The second power driver PD2 may be controlled by the timing controller CON. The second power driver PD2 may be configured to provide a second power voltage (eg, Figure 2 The second power driver PD2 supplies the second power voltage ELVSS to the plurality of pixels PX. In an embodiment, the second power driver PD2 may change the voltage level of the second power voltage at a predetermined time during each frame period.

[0060] In an embodiment, the driving circuit PDV may drive the display part DP in a simultaneous emission driving method including a simultaneous emission period in which all pixels PX simultaneously emit light in one frame. That is, the display device DD may be driven in a simultaneous emission driving method.

[0061] Figure 2 It is shown that the Figure 1 Circuit diagram of a pixel in the display section of FIG.

[0062] Reference Figure 2 , each pixel PX may include a pixel circuit PC and a light emitting element LED electrically connected to the pixel circuit PC. The pixel circuit PC may provide a driving current to the light emitting element LED, and the light emitting element LED may emit light based on the driving current. In an embodiment, for example, the pixel circuit PC may include a first transistor T1, a second transistor T2, and a third transistor T3, a first capacitor C1, and a second capacitor C2, as shown in FIG. Figure 2 as shown in .

[0063] The first transistor T1 may include a gate terminal, a first terminal, and a second terminal. The gate terminal of the first transistor T1 may be connected to a first node N1. The first terminal of the first transistor T1 may be connected to a second node N2. The second terminal of the first transistor T1 may be connected to a second terminal of the third transistor T3. The first transistor T1 may receive a first power voltage ELVDD corresponding to a voltage of the first node N1, and supply a driving current to the light emitting element LED. For example, the first transistor T1 may be a driving transistor for driving the light emitting element LED.

[0064] The second transistor T2 may include a gate terminal, a first terminal, and a second terminal. The first gate signal GW may be applied to the gate terminal of the second transistor T2. The data voltage DATA may be applied to the first terminal of the second transistor T2. The second terminal of the second transistor T2 may be connected to the first node N1. The second transistor T2 may be turned on by the first gate signal GW to electrically connect the data line providing the data voltage DATA to the first node N1.

[0065] In an embodiment, the first gate signal GW may be a global clock signal for simultaneous light emission. In an embodiment, for example, in the case where a display device DD including a plurality of pixels PX operates in a simultaneous light emission driving method, the first gate signal GW may be commonly applied to the plurality of pixels PX. In this case, the first gate signal GW and the second gate signal GC may be generated by separate gate drivers, respectively.

[0066] The third transistor T3 may include a gate terminal, a first terminal, and a second terminal. The second gate signal GC may be applied to the gate terminal of the third transistor T3. The first power voltage ELVDD may be applied to the first terminal of the third transistor T3. The second terminal of the third transistor T3 may be connected to the second terminal of the first transistor T1. The third transistor T3 may be turned on by the second gate signal GC to electrically connect the power line providing the first power voltage ELVDD to the second terminal of the first transistor T1.

[0067] The first capacitor C1 may include a first terminal and a second terminal. The first terminal of the first capacitor C1 may be connected to the first node N1. The second terminal of the first capacitor C1 may be connected to the second node N2. The first capacitor C1 may store a difference voltage between a gate voltage and a source voltage of the first transistor T1.

[0068] The second capacitor C2 may include a first terminal and a second terminal. In an embodiment, the first power voltage ELVDD may be applied to the first terminal of the second capacitor C2, and the second terminal of the second capacitor C2 may be connected to the second node N2. The second capacitor C2 may maintain a voltage between the first power voltage ELVDD and the second node N2.

[0069] In another embodiment, a DC power voltage (eg, a gate high voltage or a gate low voltage) different from the first power voltage ELVDD may be applied to the first terminal of the second capacitor C2, and a second terminal of the second capacitor C2 may be connected to the second node N2.

[0070] In an embodiment, each of the first transistor T1, the second transistor T2, and the third transistor T3 may be an n-channel metal oxide semiconductor (NMOS) transistor. However, the disclosed embodiments are not limited thereto. In an embodiment, for example, each of the first transistor T1, the second transistor T2, and the third transistor T3 may be a p-channel metal oxide semiconductor (PMOS) transistor.

[0071] The light emitting element LED may include a first terminal (eg, an anode terminal) and a second terminal (eg, a cathode terminal). The first terminal of the light emitting element LED may be connected to the second node N2. The second power voltage ELVSS may be applied to the second terminal of the light emitting element LED.

[0072] exist Figure 2 , an embodiment in which the pixel circuit PC includes three transistors and two capacitors is shown, but the disclosed embodiments are not limited thereto.

[0073] exist Figure 2 In the embodiment, the pixel PX includes a single light emitting element LED, but the disclosed embodiments are not limited thereto. In the embodiment, for example, one pixel PX may include two or more light emitting elements.

[0074] Figure 3 It is shown Figure 2 Waveform diagram of the operation period of a pixel.

[0075] Reference Figure 2 and Figure 3 The operation period of the pixel PX may include an initialization period P1 in which an initialization operation is performed, a threshold voltage compensation period P2 in which a threshold voltage compensation operation is performed, a data writing period P3 in which a data writing operation is performed, and a light emitting period P4 in which a light emitting operation is performed.

[0076] The pixel PX may sequentially perform an initialization operation, a threshold voltage compensation operation, a data writing operation, and a light emitting operation during one frame 1FRAME. When the pixel PX sequentially performs an initialization operation, a threshold voltage compensation operation, a data writing operation, and a light emitting operation during one frame 1FRAME, the operation period of the pixel PX may also sequentially include an initialization period P1, a threshold voltage compensation period P2, a data writing period P3, and a light emitting period P4.

[0077] In the initialization period P1, the first power voltage ELVDD may have a low level, the second power voltage ELVSS may have a high level, and each of the first gate signal GW and the second gate signal GC may have a high level, and the data voltage DATA may have a high level. Therefore, during the initialization period P1, in all pixels PX, the first terminal (e.g., anode terminal) of the light emitting element LED may be initialized. That is, the initialization period P1 may be performed simultaneously in all pixels PX.

[0078] In the threshold voltage compensation period P2, the first power voltage ELVDD may have a high level, the second power voltage ELVSS may have a high level, and each of the first gate signal GW and the second gate signal GC may have a low level, and the data voltage DATA may have a low level. Therefore, the threshold voltage of the first transistor T1 may be compensated during the threshold voltage compensation period P2. That is, the threshold voltage compensation period P2 may be performed simultaneously in all pixels PX.

[0079] In the data writing period P3, the first power supply voltage ELVDD may have a high level, the second power supply voltage ELVSS may have a high level, the first gate signal GW may be changed from a low level to a high level, and may be changed from a high level to a low level after a data writing operation time has passed, the second gate signal GC may have a low level, and the data voltage DATA may have a level corresponding to a predetermined grayscale. Therefore, during the data writing period P3, the data voltage DATA may be sequentially written to the pixel PX in units of pixel rows.

[0080] In the light emitting period P4, the first power voltage ELVDD may have a high level, the second power voltage ELVSS may have a low level, the first gate signal GW may have a low level, the second gate signal GC may have a high level, and the data voltage DATA may have a high level. Therefore, during the light emitting period P4, all pixels PX may emit light at the same time.

[0081] That is, the display device DD may sequentially write the data voltages DATA in units of pixel rows in one frame 1FRAME, and may emit light from all pixels PX at the same time.

[0082] As a result, in embodiments, the first power voltage ELVDD may have a low level in the initialization period P1 , and may have a high level after the initialization period P1 .

[0083] The second power voltage ELVSS may have a low level in the light emitting period P4, and may have a high level in the remaining periods (i.e., the initialization period P1, the threshold voltage compensation period P2, and the data writing period P3) except the light emitting period P4. The first gate signal GW may have a high level in the initialization period P1, may have a low level in the threshold voltage compensation period P2 and the light emitting period P4, may change from a low level to a high level in the data writing period P3, and may change from a high level to a low level after a predetermined time has passed. The second gate signal GC may have a high level in the initialization period P1 and the light emitting period P4, and may have a low level in the threshold voltage compensation period P2 and the data writing period P3.

[0084] In an embodiment, as described above, the first power voltage ELVDD has a low level in the initialization period P1 and has a high level after the initialization period P1, and the second power voltage ELVSS has a low level in the light emitting period P4 and has a high level in the remaining periods except the light emitting period P4, so that the data swing range can be reduced.

[0085] However, the disclosed embodiments are not limited thereto, and Figure 3 The waveforms of the first power voltage ELVDD, the second power voltage ELVSS, the first gate signal GW, the second gate signal GC, and the data voltage DATA shown in the figure are only examples. In the disclosed embodiments, the waveforms of the first power voltage ELVDD, the second power voltage ELVSS, the first gate signal GW, the second gate signal GC, and the data voltage DATA can be changed in various ways.

[0086] Figure 4 It is schematically shown Figure 1 A cross-sectional view of the display portion.

[0087] Reference Figure 4 In an embodiment, the display portion DP may include a substrate SUB, a circuit layer CL, a light emitting element LED, a pixel defining layer PDL, and an encapsulation layer TFE. Here, the circuit layer CL and the light emitting element LED may define a pixel PX. Here, a third direction DR3 perpendicular to the first direction DR1 and the second direction DR2 may be a thickness direction of the display portion DP or the substrate SUB.

[0088] The substrate SUB may include a transparent material or an opaque material. The substrate SUB may include a transparent resin substrate or be made of a transparent resin substrate. Examples of transparent resin substrates may include polyimide substrates. In this case, the polyimide substrate may include a first organic layer, a first barrier layer, a second organic layer, and the like. Alternatively, the substrate SUB may include a quartz substrate, a synthetic quartz substrate, a calcium fluoride substrate, a F-doped quartz substrate, a soda-lime glass substrate, a non-alkaline glass substrate, and the like. These may be used alone or in combination with one another.

[0089] The circuit layer CL may be disposed on the substrate SUB. The circuit layer CL may provide a signal and a voltage to the light emitting element LED so that the light emitting element LED emits light. For example, the circuit layer CL may include a transistor, a conductive layer, an insulating layer, and the like.

[0090] The pixel electrode PE may be disposed on the circuit layer CL. The pixel electrode PE may receive a signal and a voltage from the circuit layer CL. For example, the pixel electrode PE may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination with each other. For example, the pixel electrode PE may be an anode terminal. Alternatively, the pixel electrode PE may be a cathode terminal.

[0091] The pixel defining layer PDL may be disposed on the circuit layer CL and the pixel electrode PE. The pixel defining layer PDL may define an opening that exposes a portion of the pixel electrode PE. When the pixel defining layer PDL defines an opening, the pixel defining layer PDL may define a pixel (eg, Figure 2 The pixel defining layer PDL may include an organic material and / or an inorganic material. Examples of organic materials that may be used as the pixel defining layer PDL may include photoresist, polyacrylic resin, polyimide resin, polyamide resin, siloxane resin, acrylic resin, epoxy resin, etc. These may be used alone or in combination with each other.

[0092] The light emitting layer EML may be disposed on the pixel electrode PE. In an embodiment, the light emitting layer EML may be disposed in an opening of the pixel defining layer PDL. The light emitting layer EML may include a light emitting material to emit light.

[0093] The common electrode CE may be disposed on the pixel defining layer PDL and the light emitting layer EML. For example, the common electrode CE may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination with each other. For example, the common electrode CE may be a cathode terminal. Alternatively, the common electrode CE may be an anode terminal.

[0094] In the embodiment, as described above, the light emitting element LED including the pixel electrode PE, the light emitting layer EML, and the common electrode CE may be disposed on the substrate SUB.

[0095] The encapsulation layer TFE may be disposed on the common electrode CE. The encapsulation layer TFE may protect the light emitting element LED from external oxygen and moisture. The encapsulation layer TFE may include at least one inorganic layer and at least one organic layer. For example, the encapsulation layer TFE may include a first inorganic layer TFE1 disposed on the common electrode CE, an organic layer TFE2 disposed on the first inorganic layer TFE1, and a second inorganic layer TFE3 disposed on the organic layer TFE2.

[0096] Figures 5 to 15 It is shown Figure 1 and Figure 2 A floor plan showing part of the floors. Fig.16 It is along Fig.15 A cross-sectional view taken along line II'. Fig.17 It is along Fig.15 A cross-sectional view taken along line II-II'.

[0097] Reference Figure 5 In an embodiment, the display portion DP may include a first pixel PX1 and a second pixel PX2 adjacent to each other. In an embodiment, the second pixel PX2 may have a structure symmetrical to that of the first pixel PX1 based on an imaginary symmetry line. Hereinafter, components included in the display portion DP will be described.

[0098] The display part DP may include a lower metal layer LCL disposed on the substrate SUB. The lower metal layer LCL may include first, second, and third conductive patterns CP1, CP2, and CP3. The first, second, and third conductive patterns CP1, CP2, and CP3 may be disposed to be spaced apart from each other.

[0099] The first conductive pattern CP1, the second conductive pattern CP2, and the third conductive pattern CP3 may be disposed in the same layer as each other. In addition, the first conductive pattern CP1, the second conductive pattern CP2, and the third conductive pattern CP3 may include the same material as each other and be formed through the same process.

[0100] The first conductive pattern CP1 may be disposed in the first pixel PX1 and the second pixel PX2, respectively. The first conductive pattern CP1 disposed in the first pixel PX1 and the first conductive pattern CP1 disposed in the second pixel PX2 may be symmetrical to each other based on an imaginary symmetry line at a boundary between the first pixel PX1 and the second pixel PX2. For example, the first conductive pattern CP1 may be Fig. 9 The back gate terminal of the second transistor T2.

[0101] In such an embodiment, the second conductive pattern CP2 may also be disposed in the first pixel PX1 and the second pixel PX2, respectively. The second conductive pattern CP2 disposed in the first pixel PX1 and the second conductive pattern CP2 disposed in the second pixel PX2 may be symmetrical to each other based on an imaginary symmetry line.

[0102] The third conductive pattern CP3 may be shared by the first region where the first pixel PX1 is disposed and the second region where the second pixel PX2 is disposed. That is, the third conductive pattern CP3 may include a first portion disposed in the first region and a second portion disposed in the second region. In other words, the first portion of the third conductive pattern CP3 may be symmetrical to the second portion based on an imaginary symmetry line vertically passing through the center of the third conductive pattern CP3. For example, the third conductive pattern CP3 may be Fig. 9 A back gate terminal of the third transistor T3.

[0103] For example, the lower metal layer LCL may include metal, alloy, metal nitride, conductive metal oxide, transparent conductive material, etc. These may be used alone or in combination with each other.

[0104] Further references Figure 6 and Figure 7 , the display portion DP may further include an active layer ACT disposed on the lower metal layer LCL. In an embodiment, the buffer layer BUF may be disposed on the lower metal layer LCL, and the active layer ACT may be disposed on the buffer layer BUF. For example, the buffer layer BUF may include a silicon compound such as silicon oxide, silicon nitride, etc. These may be used alone or in combination with each other (see Fig.16 and Fig.17 ).

[0105] The active layer ACT may include a first active pattern AP1 and a second active pattern AP2. The first active pattern AP1 and the second active pattern AP2 may be disposed to be spaced apart from each other.

[0106] The first active pattern AP1 and the second active pattern AP2 may be disposed in the same layer as each other. In addition, the first active pattern AP1 and the second active pattern AP2 may include the same material as each other and be formed through the same process.

[0107] The first active pattern AP1 may at least partially overlap the second conductive pattern CP2 and the third conductive pattern CP3 in a plan view (or when viewed in the third direction DR3). The first active pattern AP1 may be shared by a first region where the first pixel PX1 is disposed and a second region where the second pixel PX2 is disposed. That is, the first active pattern AP1 may include a first portion disposed in the first region and a second portion disposed in the second region. In other words, the first portion of the first active pattern AP1 may be symmetrical to the second portion based on an imaginary symmetry line vertically passing through the center of the first active pattern AP1.

[0108] The second active pattern AP2 may at least partially overlap the first conductive pattern CP1 in a plan view. The second active pattern AP2 may be disposed in the first pixel PX1 and the second pixel PX2, respectively. The second active pattern AP2 disposed in the first pixel PX1 and the second active pattern AP2 disposed in the second pixel PX2 may be symmetrical to each other based on an imaginary symmetry line.

[0109] In an embodiment, the active layer ACT may include a metal oxide semiconductor. The metal oxide semiconductor may include a two-component compound (AB x ), three-component compound (AB x C y ), four-component compound (AB x C y D z ) etc. For example, the metal oxide semiconductor may include zinc oxide (ZnO x ), gallium oxide (GaO x )、Tin Oxide(SnO x )、Indium oxide(InO x ), indium gallium oxide (IGO), indium zinc oxide (IZO), indium tin oxide (ITO), indium zinc tin oxide (IZTO), indium gallium zinc oxide (IGZO), etc. These may be used alone or in combination with each other.

[0110] In another embodiment, the active layer ACT may include a silicon semiconductor such as amorphous silicon or polycrystalline silicon.

[0111] Further references Figure 8 and Fig. 9 , the display portion DP may further include a first gate layer GL1 disposed on the active layer ACT. In an embodiment, the first insulating layer IL1 ( Fig.16 and Fig.17) may be disposed on the active layer ACT, and the first gate layer GL1 may be disposed on the first insulating layer IL1. For example, the first insulating layer IL1 may include a silicon compound such as silicon oxide, silicon nitride, etc. These may be used alone or in combination with each other (see Fig.16 and Fig.17 ).

[0112] The first gate layer GL1 may include a first gate electrode GE1, a second gate electrode GE2, and a third gate electrode GE3. The first gate electrode GE1, the second gate electrode GE2, and the third gate electrode GE3 may be disposed to be spaced apart from each other.

[0113] The first gate electrode GE1, the second gate electrode GE2, and the third gate electrode GE3 may be disposed in the same layer as each other. In addition, the first gate electrode GE1, the second gate electrode GE2, and the third gate electrode GE3 may include the same material as each other and may be formed by the same process.

[0114] The first gate electrode GE1 may at least partially overlap each of the second conductive pattern CP2, the first active pattern AP1, and the second active pattern AP2 in a plan view. The first gate electrode GE1 may be disposed in the first pixel PX1 and the second pixel PX2, respectively. The first gate electrode GE1 disposed in the first pixel PX1 and the first gate electrode GE1 disposed in the second pixel PX2 may be symmetrical to each other based on an imaginary symmetry line at a boundary between the first pixel PX1 and the second pixel PX2.

[0115] In an embodiment, a portion of the first active pattern AP1 and a portion of the first gate electrode GE1 overlapping the portion of the first active pattern AP1 (ie, a gate terminal) may constitute the first transistor T1 . Fig. 9 The first transistor T1 can be connected with Figure 2 corresponds to the first transistor T1.

[0116] The second gate electrode GE2 may at least partially overlap each of the first conductive pattern CP1 and the second active pattern AP2 in a plan view. The second gate electrode GE2 may be connected to the first conductive pattern CP1 through the first contact hole CNT1. The second gate electrode GE2 may be disposed in the first pixel PX1 and the second pixel PX2, respectively. The second gate electrode GE2 disposed in the first pixel PX1 and the second gate electrode GE2 disposed in the second pixel PX2 may be symmetrical to each other based on an imaginary symmetry line at a boundary between the first pixel PX1 and the second pixel PX2.

[0117] In an embodiment, a portion of the second active pattern AP2 and a portion of the second gate electrode GE2 overlapping the portion of the second active pattern AP2 (ie, a gate terminal) may constitute the second transistor T2 . Fig. 9The second transistor T2 can be connected with Figure 2 The second transistor T2 corresponds to.

[0118] The third gate electrode GE3 may at least partially overlap each of the third conductive pattern CP3 and the first active pattern AP1 in a plan view. The third gate electrode GE3 may be connected to the third conductive pattern CP3 through a second contact hole CNT2. The third gate electrode GE3 may be shared by a first region where the first pixel PX1 is provided and a second region where the second pixel PX2 is provided. That is, the third gate electrode GE3 may include a first portion provided in the first region and a second portion provided in the second region. In other words, the first portion of the third gate electrode GE3 may be symmetrical with the second portion based on an imaginary symmetry line vertically passing through the center of the third gate electrode GE3.

[0119] In an embodiment, another portion of the first active pattern AP1 and a portion of the third gate electrode GE3 overlapping the another portion of the first active pattern AP1 (ie, a gate terminal) may constitute the third transistor T3 . Fig. 9 The third transistor T3 can be connected with Figure 2 The third transistor T3 corresponds to.

[0120] Therefore, the first pixel PX1 may include the first transistor T1, the second transistor T2, and the third transistor T3, and the second pixel PX2 may also include the first transistor T1, the second transistor T2, and the third transistor T3.

[0121] For example, the first gate layer GL1 may include metal, alloy, metal nitride, conductive metal oxide, transparent conductive material, etc. These may be used alone or in combination with each other.

[0122] Further references Fig.10 and Fig.11 , the display portion DP may further include a second gate layer GL2 disposed on the first gate layer GL1. In an embodiment, the second insulating layer IL2 ( Fig.16 and Fig.17 ) may be disposed on the first gate layer GL1, and the second gate layer GL2 may be disposed on the second insulating layer IL2. For example, the second insulating layer IL2 may include a silicon compound such as silicon oxide, silicon nitride, etc. These may be used alone or in combination with each other (see Fig.16 and Fig.17 ).

[0123] The second gate layer GL2 may include a first gate line GAL1, a second gate line GAL2, a first connection pattern CNP1, and a capacitor electrode CPE. The first gate line GAL1, the second gate line GAL2, the first connection pattern CNP1, and the capacitor electrode CPE may be arranged to be spaced apart from each other.

[0124] The first gate line GAL1, the second gate line GAL2, the first connection pattern CNP1 and the capacitor electrode CPE may be disposed in the same layer as each other. In addition, the first gate line GAL1, the second gate line GAL2, the first connection pattern CNP1 and the capacitor electrode CPE may include the same material as each other and may be formed by the same process.

[0125] The first gate line GAL1 may extend in the first direction DR1. The first gate line GAL1 may be connected to the second gate electrode GE2 through the third contact hole CNT3. In addition, the first gate signal (eg, Figure 2 The first gate signal GW) may be applied to the first gate line GAL1. In addition, the first gate signal may be transmitted to the second gate electrode GE2 and the first conductive pattern CP1 through the first gate line GAL1.

[0126] The second gate line GAL2 may extend in the first direction DR1. The second gate line GAL2 may be connected to the third gate electrode GE3 through the sixth contact hole CNT6. In addition, the second gate signal (eg, Figure 2 The second gate signal GC in the embodiment may be applied to the second gate line GAL2. In addition, the second gate signal may be transmitted to the third gate electrode GE3 and the third conductive pattern CP3 through the second gate line GAL2.

[0127] The first connection pattern CNP1 may connect the second active pattern AP2 and the first gate electrode GE1 through the fourth contact hole CNT4. In addition, the first transistor T1 and the second transistor T2 may be electrically connected to each other. The first connection pattern CNP1 may be disposed in the first pixel PX1 and the second pixel PX2, respectively. The first connection pattern CNP1 disposed in the first pixel PX1 and the first connection pattern CNP1 disposed in the second pixel PX2 may be symmetrical to each other based on an imaginary symmetry line at a boundary between the first pixel PX1 and the second pixel PX2.

[0128] The capacitor electrode CPE may connect the first active pattern AP1 and the second conductive pattern CP2 through the fifth contact hole CNT5. In addition, the capacitor electrode CPE may at least partially overlap each of the second conductive pattern CP2, the first active pattern AP1, and the first gate electrode GE1 in a plan view. In an embodiment, the first gate electrode GE1 and a portion of the capacitor electrode CPE overlapping the first gate electrode GE1 may constitute a first capacitor C1 (see Fig.16 ). Fig.11 The first capacitor C1 can be connected with Figure 2 The first capacitor C1 corresponds to.

[0129] The capacitor electrode CPE may be disposed in the first pixel PX1 and the second pixel PX2, respectively. The capacitor electrode CPE disposed in the first pixel PX1 and the capacitor electrode CPE disposed in the second pixel PX2 may be symmetrical to each other based on an imaginary symmetry line at a boundary between the first pixel PX1 and the second pixel PX2.

[0130] Therefore, the first pixel PX1 may include the first capacitor C1, and the second pixel PX2 may also include the first capacitor C1.

[0131] For example, the second gate layer GL2 may include metal, alloy, metal nitride, conductive metal oxide, transparent conductive material, etc. These may be used alone or in combination with each other.

[0132] Further references Fig.12 and Fig.13 , the display portion DP may further include a first upper conductive layer UCL1 disposed on the second gate layer GL2. In an embodiment, the third insulating layer IL3 ( Fig.16 and Fig.17 ) may be disposed on the second gate layer GL2, and the first upper conductive layer UCL1 may be disposed on the third insulating layer IL3. For example, the third insulating layer IL3 may include a silicon compound such as silicon oxide, silicon nitride, etc. These may be used alone or in combination with each other (see Fig.16 and Fig.17 ).

[0133] The first upper conductive layer UCL1 may include the data line DL and the additional power line APL The data line DL and the additional power line APL may be disposed to be spaced apart from each other in the first direction DR1.

[0134] The data line DL and the additional power line APL may be disposed in the same layer as each other. In addition, the data line DL and the additional power line APL may include the same material as each other and be formed through the same process.

[0135] The data line DL may extend in the second direction DR2. The data line DL may be connected to the second active pattern AP2 through the seventh contact hole CNT7. In addition, the data voltage (eg, Figure 2 The data voltage DATA) may be applied to the data line DL. In addition, the data voltage may be transmitted to the second active pattern AP2 through the data line DL.

[0136] The data line DL may be disposed in the first pixel PX1 and the second pixel PX2, respectively. The data line DL disposed in the first pixel PX1 and the data line DL disposed in the second pixel PX2 may be symmetrical to each other based on an imaginary symmetry line at a boundary between the first pixel PX1 and the second pixel PX2.

[0137] As described above, in embodiments, the first upper conductive layer UCL1 may include the additional power line APL. The additional power line APL may extend in the second direction DR2.

[0138] In an embodiment, the first power voltage (eg, Figure 2 The first power voltage ELVDD) may be applied to the additional power line APL. In this case, a voltage drop of the first power voltage may be reduced due to the additional power line APL.

[0139] In another embodiment, a DC power voltage (eg, a gate high voltage or a gate low voltage) different from the first power voltage may be applied to the additional power line APL.

[0140] The additional power line APL may be provided in the first pixel PX1 and the second pixel PX2, respectively. The additional power line APL provided in the first pixel PX1 and the additional power line APL provided in the second pixel PX2 may be symmetrical to each other based on an imaginary symmetry line at a boundary between the first pixel PX1 and the second pixel PX2.

[0141] For example, the first upper conductive layer UCL1 may include metal, alloy, metal nitride, conductive metal oxide, transparent conductive material, etc. These may be used alone or in combination with each other.

[0142] Reference Fig.14 and Fig.15 , the display part DP may further include a second upper conductive layer UCL2 disposed on the first upper conductive layer UCL1. In an embodiment, the fourth insulating layer IL4 ( Fig.16 and Fig.17 ) may be disposed on the first upper conductive layer UCL1, and the second upper conductive layer UCL2 may be disposed on the fourth insulating layer IL4. For example, the fourth insulating layer IL4 may include an organic material such as phenolic resin, polyacrylate resin, polyimide resin, polyamide resin, siloxane resin, epoxy resin, etc. These may be used alone or in combination with each other.

[0143] The second upper conductive layer UCL2 may include the transmission line TL, the second connection pattern CNP2, and the power line PL. The transmission line TL, the second connection pattern CNP2, and the power line PL may be disposed to be spaced apart from each other.

[0144] The transmission line TL, the second connection pattern CNP2, and the power line PL may be disposed in the same layer as each other. In addition, the transmission line TL, the second connection pattern CNP2, and the power line PL may include the same material as each other and be formed through the same process.

[0145] The transmission line TL may extend in the second direction DR2. The transmission line TL may be connected to the second gate line GAL2 through the eighth contact hole CNT8. In addition, the second gate signal may be applied to the transmission line TL. In addition, the transmission line TL may transmit the second gate signal applied to the second gate line GAL2 to the adjacent pixel in the second direction DR2.

[0146] In an embodiment, the transmission line TL may be shared by a region where two adjacent pixels are disposed. For example, the transmission line TL may be shared by a region where a first pixel PX1 and a pixel adjacent to the first pixel PX1 in a direction opposite to the first direction DR1 are disposed, and may be shared by a region where a second pixel PX2 and a pixel adjacent to the second pixel PX2 in the first direction DR1 are disposed.

[0147] The power line PL may extend in the second direction DR2. The power line PL may be connected to the first active pattern AP1 through the ninth contact hole CNT9. In addition, the first power voltage (eg, Figure 2 The first power voltage ELVDD) may be applied to the power line PL. In addition, the first power voltage may be transmitted to the first active pattern AP1 through the power line PL.

[0148] The power line PL may be shared by a region where two adjacent pixels are disposed. For example, the power line PL may be shared by a region where a first pixel PX1 and a second pixel PX2 adjacent to each other in a first direction DR1 are disposed. For example, the power line PL may extend along an imaginary symmetry line at a boundary between the first pixel PX1 and the second pixel PX2.

[0149] The second connection pattern CNP2 may be connected to the capacitor electrode CPE through the tenth contact hole CNT10. In addition, the second connection pattern CNP2 may be connected to the pixel electrode (eg, Figure 4 In addition, the light emitting element (for example, Figure 2 and Figure 4 light emitting element LED) and pixel circuit (for example, Figure 2 The pixel circuits PC) may be electrically connected to each other through the second connection pattern CNP2.

[0150] The second connection pattern CNP2 may at least partially overlap each of the data line DL and the additional power line APL in a plan view. In an embodiment, a portion of the second connection pattern CNP2 and a portion of the additional power line APL overlapping the portion of the second connection pattern CNP2 may constitute a second capacitor C2. Fig.15 The second capacitor C2 can be connected with Figure 2 The second capacitor C2 corresponds to (see Fig.17 ).

[0151] The second connection pattern CNP2 may be disposed in the first pixel PX1 and the second pixel PX2, respectively. The second connection pattern CNP2 disposed in the first pixel PX1 and the second pixel PX2 may be symmetrical to each other based on an imaginary symmetry line at a boundary between the first pixel PX1 and the second pixel PX2.

[0152] For example, the second upper conductive layer UCL2 may include metal, alloy, metal nitride, conductive metal oxide, transparent conductive material, etc. These may be used alone or in combination with each other.

[0153] Therefore, the first pixel PX1 may include the second capacitor C2, and the second pixel PX2 may also include the second capacitor C2.

[0154] The fifth insulating layer IL5 ( Fig.16 and Fig.17 ) may be disposed on the second upper conductive layer UCL2. For example, the fifth insulating layer may include an organic material such as phenolic resin, acrylic resin, polyimide resin, polyamide resin, siloxane resin, epoxy resin, etc. These may be used alone or in combination with each other.

[0155] Fig.18 It shows that Fig.15 A plan view of an example of a power line and additional power line connections.

[0156] Reference Fig.12 , Fig.13 , Fig.14 , Fig.15 and Fig.18 , an embodiment of the display device DD may include a display area DA and a peripheral area PA. Since the display device DD includes the display area DA and the peripheral area PA, Figure 4 , Fig.16 and Fig.17 The substrate SUB may also include a display area DA and a peripheral area PA.

[0157] In an embodiment, the first power voltage (eg, Figure 2 The first power voltage ELVDD) may be applied to the additional power line APL. In an embodiment, the additional power line APL may be connected to the power line PL through the contact hole CNT in the peripheral area PA. However, the disclosed embodiments are not limited thereto.

[0158] Fig.19 It shows that Fig.15 A plan view of another example of a power line and additional power line connections.

[0159] In addition to the connection position of the additional power line APL' and the power line PL, Fig.19The embodiment of the display device shown in FIG. Figures 5 to 17 The embodiments of the display device DD described are substantially the same or similar. Hereinafter, any repetitive detailed description of elements that are the same or similar to the above-mentioned elements will be omitted or simplified.

[0160] In an embodiment, the first upper conductive layer UCL1 ′ may include the data line DL and the additional power line APL′, and the second upper conductive layer UCL2 ′ may include the transmission line TL, the power line PL, and the second connection pattern CNP2 .

[0161] In an embodiment, the additional power line APL' may at least partially overlap with each of the power line PL and the second connection pattern CNP2 in a plan view. The additional power line APL' may be shared by a first region where the first pixel PX1 is disposed and a second region where the second pixel PX2 is disposed. That is, the additional power line APL' may include a first portion disposed in the first region and a second portion disposed in the second region. In other words, the first portion of the additional power line APL' may be symmetrical to the second portion based on an imaginary symmetry line vertically passing through the center of the additional power line APL' or an imaginary symmetry line at a boundary between the first pixel PX1 and the second pixel PX2.

[0162] In an embodiment, a portion of the second connection pattern CNP2 and a portion of the additional power line APL′ overlapping the portion of the second connection pattern CNP2 may constitute the second capacitor C2. Fig.19 The second capacitor C2 can be connected with Figure 2 The second capacitor C2 corresponds to.

[0163] In such an embodiment, the first power voltage (e.g., Figure 2 The first power voltage ELVDD) may be applied to the additional power line APL'. In such an embodiment, the additional power line APL' may be connected to the display portion (eg, Figure 1 The display area corresponding to the display portion DP) (for example, Fig.18 In an embodiment, the additional power line APL′ may be connected to the power line PL through the eleventh contact hole CNT11.

[0164] As mentioned above Figures 1 to 19As described, in the display device DD according to the disclosed embodiment, the pixel PX may include a pixel circuit PC and a light emitting element LED, the pixel circuit PC includes three transistors and two capacitors, and the light emitting element LED is electrically connected to the pixel circuit PC. A first capacitor C1 among the capacitors may be connected between the gate terminal of the first transistor T1 and the first terminal of the first transistor T1, and a second capacitor C2 among the capacitors may be connected between the first terminal of the first transistor T1 and the first power voltage ELVDD. A plurality of pixels PX may simultaneously emit light during the light emitting period P4.

[0165] In such an embodiment, the first power voltage ELVDD may have a low level in the initialization period P1 and may have a high level after the initialization period P1, and the second power voltage ELVSS may have a low level in the light emitting period P4 and may have a high level in the remaining periods except the light emitting period P4.

[0166] In such an embodiment, a portion of the second connection pattern CNP2 connected to the pixel electrode PE and a portion of the additional power lines APL and APL' overlapping the portion of the second connection pattern CNP2 may constitute a second capacitor C2. The first power voltage ELVDD or a DC power voltage may be applied to the additional power lines APL and APL'.

[0167] Therefore, the data swing range can be relatively reduced. In such an embodiment, the pixel PX can be applied to small and medium-sized high-resolution display devices.

[0168] For example, the disclosed embodiments may be applied to various display devices, such as display devices for vehicles, ships, and aircraft, portable communication devices, display devices for presentation or information transmission, medical display devices, and the like.

[0169] The invention should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art.

[0170] While the invention has been particularly shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit or scope of the invention as defined by the claims.

Claims

1. A pixel, wherein the pixel sequentially performs an initialization operation, a threshold voltage compensation operation, a data writing operation, and a light emitting operation during one frame, the pixel comprising: a first transistor including a gate terminal connected to the first node, a second terminal, and a first terminal connected to the second node; a second transistor including a gate terminal to which a first gate signal is applied, a first terminal to which a data voltage is applied, and a second terminal connected to the first node; a third transistor including a gate terminal to which a second gate signal is applied, a first terminal to which a first power voltage is applied, and a second terminal connected to the second terminal of the first transistor; a first capacitor including a first terminal connected to the first node and a second terminal connected to the second node; a second capacitor including a first terminal to which the first power voltage is applied and a second terminal connected to the second node; as well as The light emitting element includes a first terminal connected to the second node and a second terminal to which a second power voltage is applied.

2. The pixel according to claim 1, wherein: The first power voltage has a low level during an initialization period in which the initialization operation is performed, and The first power voltage has a high level after the initialization period.

3. The pixel according to claim 1, wherein: The second power voltage has a low level in a light emitting period in which the light emitting operation is performed, and The second power voltage has a high level in a remaining period except the light emitting period in one frame, and in the remaining period, the initialization operation, the threshold voltage compensation operation, and the data writing operation are performed.

4. The pixel according to claim 1, wherein: The first gate signal is a global clock signal for simultaneous light emission.

5. The pixel according to claim 1, wherein: The second gate signal has a high level in an initialization period in which the initialization operation is performed and a light emission period in which the light emission operation is performed, and The second gate signal has a low level in a threshold voltage compensation period in which the threshold voltage compensation operation is performed and a data write period in which the data write operation is performed.

6. A display device, comprising: Display part, displaying images; as well as a driving circuit that drives the display portion by supplying a driving signal to the display portion, Wherein, the display part includes: An active layer is disposed on a substrate; a first gate layer, disposed on the active layer and comprising a first gate electrode; a second gate layer disposed on the first gate layer and comprising a capacitor electrode, wherein the capacitor electrode overlaps with the first gate electrode in a plan view and constitutes a first capacitor together with a portion of the first gate electrode overlapping with the capacitor electrode; a first upper conductive layer disposed on the second gate layer and including an additional power line to which a first power voltage is applied; a second upper conductive layer disposed on the first upper conductive layer and comprising a power line to which a second power voltage is applied and a connection pattern connected to the capacitor electrode through a contact hole, wherein the connection pattern partially overlaps with the additional power line in a plan view and constitutes a second capacitor together with a portion of the additional power line overlapping with the connection pattern; and A pixel electrode is disposed on the second upper conductive layer and connected to the connection pattern through a contact hole.

7. The display device according to claim 6, wherein: The substrate includes a display area corresponding to the display portion and a peripheral area located around the display area, wherein the driving circuit is arranged in the peripheral area, The additional power line is connected to the portion of the power line in the peripheral area through a contact hole, and The first power voltage and the second power voltage are the same voltage as each other.

8. The display device according to claim 6, wherein: The first power voltage is different from the second power voltage, and The first power voltage is a DC power voltage.

9. The display device according to claim 6, wherein: The substrate includes a display area corresponding to the display portion and a peripheral area located around the display area, wherein the driving circuit is arranged in the peripheral area, The additional power line is connected to the portion of the power line in the display area through a contact hole, and The power line at least partially overlaps the additional power line in a plan view.

10. The display device according to claim 6, wherein: The active layer includes a first active pattern and a second active pattern spaced apart from each other, The first gate layer further includes a second gate electrode overlapping the second active pattern in a plan view and a third gate electrode overlapping the first active pattern in a plan view, The first active pattern and a portion of the first gate electrode overlapping the first active pattern together constitute a first transistor, The second active pattern and a portion of the second gate electrode overlapping the second active pattern together constitute a second transistor, and The first active pattern and a portion of the third gate electrode overlapping the first active pattern together constitute a third transistor.

Images