Memory device and memory system

Abstract

A memory device includes at least one bank including at least a first sub-bank and a second sub-bank disposed in a word line direction. The first sub-bank may include a normal data region connected to a plurality of first word lines and storing normal data, the second sub-bank may include a metadata region connected to a plurality of second word lines and storing metadata corresponding to the normal data, the plurality of first word lines may be matched with the plurality of second word lines to form a plurality of word line pairs, and the first sub-bank and the second sub-bank may share a row hammer region that stores the number of accesses to the plurality of word line pairs.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0108520 filed in the Korean Intellectual Property Office on August 18, 2023, and Korean Patent Application No. 10-2024-0022950 filed in the Korean Intellectual Property Office on February 16, 2024, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure relates to a memory device and a memory system, and more particularly to a memory device and a memory system that can be implemented in a smaller area while preventing a row hammer effect. Background Art

[0004] Memory devices are used to store data and are classified into volatile memory devices and nonvolatile memory devices. Volatile memory devices lose their stored data when their power supply is interrupted. Dynamic random access memory (DRAM) is a volatile memory device used in various fields such as mobile systems, servers, and graphic devices.

[0005] When a specific word line is actively accessed, data stored in memory cells included in word lines adjacent to the corresponding memory cell row may be lost. This phenomenon is called the row hammer effect. Therefore, there is a need for a memory device that can be implemented in a smaller area while effectively preventing such a row hammer effect. Summary of the invention

[0006] The present disclosure provides a memory device that can be implemented in a smaller area while preventing the row hammer effect.

[0007] According to some embodiments, a memory device includes at least one memory bank, the at least one memory bank including at least a first sub-memory bank and a second sub-memory bank arranged along a word line direction. The first sub-memory bank may include a normal data area connected to a plurality of first word lines and storing normal data, the second sub-memory bank may include a metadata area connected to a plurality of second word lines and storing metadata corresponding to the normal data, the plurality of first word lines may be matched with a plurality of second word lines to form a plurality of word line pairs, and the first sub-memory bank and the second sub-memory bank may share a row hammer area, the row hammer area storing the number of accesses to the plurality of word line pairs.

[0008] According to some embodiments, a memory device includes: at least one memory bank including at least a first sub-memory bank and a second sub-memory bank arranged along a word line direction; a first row decoder connected to the first sub-memory bank through a plurality of first word lines; a first column decoder connected to the first sub-memory bank through a plurality of first column selection lines; a second row decoder connected to the second sub-memory bank through a plurality of second word lines; and a second column decoder connected to the second sub-memory bank through a plurality of second column selection lines. The first sub-memory bank may include a plurality of first memory slices, and the second sub-memory bank may include a plurality of second memory slices. Each of the plurality of first memory slices may include a normal data region connected to a portion of the plurality of word lines and storing normal data. Each of the plurality of second memory slices may include a metadata region connected to a portion of the plurality of second word lines and storing metadata corresponding to the normal data. The plurality of first word lines may be matched with the plurality of second word lines to form a plurality of word line pairs. At least one of the plurality of first memory slices included in the first sub-memory bank may include a counting unit storing count data, the count data being the number of accesses to the plurality of word line pairs.

[0009] According to some embodiments, a memory system includes: a memory device including at least one memory bank including at least a first sub-memory bank and a second sub-memory bank arranged along a word line direction; and a memory controller configured to control the memory device. The first sub-memory bank may include a normal data area connected to a plurality of first word lines and storing normal data, the second sub-memory bank may include a metadata area connected to a plurality of second word lines and storing metadata corresponding to the normal data, the plurality of first word lines may be matched with the plurality of second word lines to form a plurality of word line pairs, and the first sub-memory bank and the second sub-memory bank may share a row hammer area storing the number of accesses to the plurality of word line pairs. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other aspects, features and advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0011] Figure 1A is a block diagram illustrating a storage system according to some embodiments.

[0012] Figure 1B is a block diagram illustrating a storage system according to some embodiments.

[0013] Figure 2 is a block diagram illustrating an example of a configuration of a storage controller according to some embodiments.

[0014] Figure 3 is a block diagram illustrating an example of a memory device according to some embodiments.

[0015] Figure 4 is a diagram illustrating an example of a memory bank array according to some embodiments.

[0016] Figure 5 is a diagram illustrating an example of a memory device according to some embodiments.

[0017] Figure 6 It shows Figure 5 A diagram of memory banks defined in a memory device.

[0018] FIG. 7A to FIG. 7C is a diagram illustrating an example of operation of a memory bank of a memory device according to some embodiments.

[0019] Figure 8 is a block diagram illustrating an example of a memory cell according to some embodiments.

[0020] Figures 9 to 12 is a diagram illustrating a matching relationship between normal data and metadata in a storage body according to some embodiments.

[0021] Fig.13 is a diagram illustrating an example of a memory device that updates count data through a read-modify-write (RMW) operation according to some embodiments.

[0022] Fig.14 is a diagram illustrating some embodiments of implementing hammer zones in a distributed manner.

[0023] Fig.15 is a diagram showing an example of an RMW operation performed when the row hammer area is implemented in a distributed manner.

[0024] Fig.16 is a diagram illustrating an example of a memory bank according to some embodiments.

[0025] Fig.17 yes Fig.16 A more detailed view of area "A".

[0026] 18A to 18C is a diagram showing various examples of memory banks in which row hammer regions are set in various ways according to some embodiments. DETAILED DESCRIPTION

[0027] Hereinafter, embodiments will be described with reference to the accompanying drawings.

[0028] Figure 1A is a block diagram illustrating a storage system according to some embodiments.

[0029] According to some embodiments, the memory system 10A may include multiple memory banks. Each of the multiple memory banks may include a first sub-memory bank and a second sub-memory bank arranged along a word line direction. In some embodiments, the first sub-memory bank and the second sub-memory bank may correspond to different global input / output lines GIO.

[0030] The memory system 10A can manage the number of accesses to each of the plurality of word lines to prevent a row hammer effect caused by intensive accesses to a specific word line. To this end, the memory system 10A can perform a read-modify-write (RMW) operation to read count data corresponding to a target word line in an active state, update the read count data, and rewrite the updated count data.

[0031] In some embodiments, the first sub-storage bank and the second sub-storage bank can share count data. For example, when count data is stored in one of the sub-storage banks, the other sub-storage bank can use the count data to perform RMW operations. Therefore, the space required for storing count data can be significantly reduced. Therefore, the storage system 10A can be implemented in a smaller area while preventing the row hammer effect.

[0032] Now refer to Figure 1A A more detailed description is provided. The memory system 10A may include a memory controller 100 and a memory device 200 .

[0033] The storage controller 100 may control the storage device 200. For example, the storage controller 100 may control the storage device 100 based on a request from a processor supporting various applications such as a server application, a personal computer (PC) application, or a mobile application. For example, the storage controller 100 may be included in a host including a processor, and may control the storage device 200 based on a request from the processor.

[0034] The memory controller 100 may transmit a command and / or an address to the memory device 200 to control the memory device 200. In addition, the memory controller 100 may transmit data to the memory module 100 or receive data from the memory device 200.

[0035] In some embodiments, the memory device 200 may operate in a first write mode or a second write mode.

[0036] The storage controller 100 may control the storage device 200 to operate in a first write mode or a second write mode. For this control, the storage controller 100 may adjust the value of a specific bit of the additional storage space (such as a mode register included in the storage device 200) to perform the above control. For example, when the value of the specific bit is set to 0, the storage device 200 may operate in the first write mode. When the value of the specific bit is set to 1, the storage device 200 may operate in the second write mode.

[0037] For example, the memory controller 100 may control the memory device 200 to simultaneously write or read normal data and metadata through a word line corresponding to normal data and a word line corresponding to metadata.

[0038] In some embodiments, the memory system 10A may turn off the metadata mode and also operate in the normal mode. In the normal mode, the word lines allocated for metadata in the metadata mode may also be allocated for normal data. Therefore, in the normal mode, the memory system 10A may activate at least a portion of the plurality of word lines included in the memory device 200 to write normal data in the memory device 120 or read normal data from the memory device 120. In addition, the operation of the memory system 100 in the normal mode may follow the operation in a dynamic random access memory (DRAM), a double data rate (DDR) 4 (DDR4), a synchronous SRAM (SDRAM), a DDR5 SDRAM, a DDR6 SDRAM, a low power DDR4 (LPDDR4) SDRAM, a LPDDR5 SDRAM, or a LPDDR6 SDRAM.

[0039] The memory device 200 may receive data from the memory controller 100 and store the received data. The memory device 200 may read the stored data in response to a request from the memory controller 100 and transmit the read data to the memory controller 100.

[0040] In some embodiments, the memory device 200 may be a memory device including a volatile memory cell. For example, the memory device 200 may be one of various DRAM devices such as a double data rate synchronous dynamic random access memory (DDR SDRAM) device, a DDR2 SDRAM device, a DDR3 SDRAM device, a DDR4 SDRAM device, a DDR5 SDRAM device, a DDR6 SDRAM device, a low power double data rate (LPDDR) SDRAM device, a LPDDR2 SDRAM device, a LPDDR3 SDRAM device, a LPDDR4 SDRAM device, a LPDDR4X SDRAM device, a LPDDR5 SDRAM device, a graphic double data rate synchronous graphic random access memory (GDDR SGRAM) device, a GDDR2 SGRAM device, a GDDR3 SGRAM device, a GDDR4 SGRAM device, a GDDR5 SGRAM device, or a GDDR6 SGRAM device.

[0041] In some embodiments, the memory device 200 may be a stacked memory device in which DRAM dies are stacked, such as a high bandwidth memory (HBM) device, an HBM2 device, or an HBM3 device.

[0042] In some embodiments, the memory device 200 may be a memory module such as a dual in-line memory module (DIMM). For example, the memory module 100A may be a registered DIMM (RDIMM), a load reduced DIMM (LRDIMM0), an unbuffered DIMM (UDIMM), a fully buffered DIMM (FB-DIMM), a small form factor DIMM (SO-DIMM). However, this is only an example, and the memory device 200 may be another memory module such as a single in-line memory module (SIMM).

[0043] In some embodiments, the memory device 200 may be an SRAM device, a NAND flash memory device, a NOR flash memory device, an RRAM device, a FRAM device, a PRAM device, a TRAM device, or an MRAM device.

[0044] The memory device 200 includes a memory cell array 310 and a row hammer management circuit 500 .

[0045] The memory cell array 310 may include a plurality of memory bank arrays, and each memory bank array may include memory cells storing data. For example, the memory cell array 310 includes a first memory bank array BA1 and a second memory bank array BA2, and each of the first memory bank array BA1 and the second memory bank array BA2 may include a memory cell.

[0046] For ease of description, an example will be provided in which each memory array includes DRAM cells. However, this is only an example, and each memory array may be implemented to include volatile memory cells other than DRAM cells. Alternatively, each memory array may be implemented to include the same type of memory cells, or may be implemented to include different types of memory cells.

[0047] The first memory bank array BA1 includes a plurality of sub memory banks SB1_1 to SB1_m. The plurality of sub memory banks SB1_1 to SB1_m included in the first memory bank array BA1 may share the same global input / output line.

[0048] The second memory bank array BA2 includes a plurality of sub-memory banks SB2_1 to SB2_m. The plurality of sub-memory banks SB2_1 to SB2_m included in the second memory bank array BA2 may share the same global input / output line.

[0049] Each of the plurality of sub-banks SB1_1 to SB1_m of the first bank array BA1 includes a first normal data region NDR1 and a second metadata region MDR2. Each of the plurality of sub-banks SB2_1 to SB2_m of the second bank array BA2 includes a second normal data region NDR2 and a first metadata region MDR1.

[0050] The storage units of the first normal data area NDR1 and the second normal data area NDR2 may store normal data. The storage units of the first metadata area MDR1 and the second metadata area MDR2 may store metadata. Metadata may refer to data used to improve performance or enhance the security of a storage device. For example, metadata may be parity data to perform an error correction operation on the corresponding normal data. For example, metadata may include information about the type, length, and attributes of the corresponding normal data, but the implementation is not limited thereto.

[0051] In some embodiments, the plurality of memory banks B1 to Bm may each be defined to include different sub-memory banks arranged along a word line direction.

[0052] For example, the first memory bank B1 includes the 1_1th sub-memory bank SB1_1 of the first memory bank array BA1 and the 2_1th sub-memory bank SB2_1 of the second memory bank array BA2. In some embodiments, the 1_1th sub-memory bank SB1_1 and the 2_1th sub-memory bank SB2_1 may correspond to different global I / O lines, respectively. For example, the 1_1th sub-memory bank SB1_1 and the 2_1th sub-memory bank SB2_1 may be connected to different global I / O lines. Therefore, the 1_1th sub-memory bank SB1_1 and the 2_1th sub-memory bank SB2_1 may input or output data at the same time.

[0053] Similarly, the m-th memory bank Bm includes the 1_m-th sub-memory bank SB1_m of the first memory bank array BA1 and the 2_m-th sub-memory bank SB2_m of the second memory bank array BA2. In some embodiments, the 1_m-th sub-memory bank SB1_m and the 2_m-th sub-memory bank SB2_m may correspond to different global I / O lines, respectively. For example, the 1_m-th sub-memory bank SB1_m and the 2_m-th sub-memory bank SB2_m may be connected to different global I / O lines. Therefore, the 1_m-th sub-memory bank SB1_m and the 2_m-th sub-memory bank SB2_m may input or output data at the same time.

[0054] In some implementations, normal data and corresponding metadata may be stored in a sub-storage volume included in the same storage volume.

[0055] For example, the first memory bank B1 includes a 1_1th sub-memory bank SB1_1 and a 2_1th sub-memory bank SB2_1, and the first normal data may be stored in a first normal data region NDR1 of the 1_1th sub-memory bank SB1_1. In some embodiments, the first metadata corresponding to the first normal data of the 1_1th sub-memory bank SB1_1 may be stored in a first metadata region MDR1 of the 2_1th sub-memory bank SB2_1.

[0056] For example, the second normal data may be stored in the second normal data region NDR2 of the 2_1th sub bank SB2_1. In some embodiments, the second metadata corresponding to the second normal data of the 2_1th sub bank SB2_1 may be stored in the second metadata region MDR2 of the 1_1th sub bank SB1_1.

[0057] As described above, normal data and corresponding metadata can be distributed and stored in sub-memory banks included in the same memory bank. In some embodiments, sub-memory banks included in the same memory bank can be connected to different global I / O lines so that normal data and corresponding metadata can be input or output simultaneously.

[0058] In some embodiments, the plurality of word lines of the normal data region may correspond to the plurality of word lines of the metadata region, respectively. For example, the plurality of word lines of the normal data region and the plurality of word lines corresponding to the metadata region may form a pair.

[0059] In some embodiments, the sub-memory banks included in the same memory bank may each include a plurality of word lines, and the plurality of word lines included in one sub-memory bank may correspond to the plurality of word lines included in another sub-memory bank, respectively. For example, the plurality of word lines included in one sub-memory bank may match the plurality of word lines included in another sub-memory bank, respectively. Thus, a word line pair may be formed.

[0060] For example, the 1_1th word line WL1_1 of the 1_1th sub-memory bank SB1_1 may correspond to the 2_1th word line WL2_1 of the 2_1th sub-memory bank SB2_1, and the 1_1th word line WL1_1 and the 2_1th word line WL2_1 may form a first word line pair. Similarly, the 1_nth word line WL1_n of the 1_1th sub-memory bank SB1_1 may correspond to the 2_nth word line WL2_n of the 2_1th sub-memory bank SB2_1, and the 1_nth word line WL1_n and the 2_nth word line WL2_n may form an nth word line pair.

[0061] In some embodiments, normal data and corresponding metadata may be stored in a normal data region and a metadata region of the same word line pair.

[0062] For example, if the first normal data is stored in a storage cell connected to the 1_1 word line WL1_1 of the first normal data region NDR1 of the 1_1 sub-storage body SB1_1, the first metadata corresponding to the first normal data may be stored in a storage cell connected to the 2_1 word line WL2_1 of the first metadata region MDR1 of the 2_1 sub-storage body SB2_1. Similarly, when the nth normal data is stored in a storage cell connected to the 1_n word line WL1_n of the first normal data region NDR1 of the 1_1 sub-storage body SB1_1, the nth metadata corresponding to the nth normal data may be stored in a storage cell connected to the 2_n word line WL2_n of the first metadata region MDR1 of the 2_1 sub-storage body SB2_1.

[0063] For example, when the first normal data is stored in a storage cell connected to the 2_1 word line WL2_1 of the second normal data region NDR2 of the 2_1 sub-storage body SB2_1, the first metadata corresponding to the first normal data may be stored in a storage cell connected to the 1_1 word line WL1_1 of the second metadata region MDR2 of the 1_1 sub-storage body SB1_1. Similarly, when the nth normal data is stored in a storage cell connected to the 2_n word line WL2_n of the second normal data region NDR2 of the 2_1 sub-storage body SB2_1, the nth metadata corresponding to the nth normal data may be stored in a storage cell connected to the 1_n word line WL1_n of the second metadata region MDR2 of the 1_1 sub-storage body SB1_1.

[0064] As described above, a plurality of word lines included in one sub-storage bank and a plurality of word lines included in another sub-storage bank may form a word line pair, and thus a plurality of metadata of a plurality of normal data stored in the 1_1th sub-storage bank SB1_1 may be distributed and stored in the word line of the 2_1th sub-storage bank SB2_1, and a plurality of metadata of a plurality of normal data stored in the 2_1th sub-storage bank SB2_1 may be stored in the word line of the 1_1th sub-storage bank SB1_1. Therefore, a plurality of metadata may be densely stored in a specific word line. Therefore, the occurrence of a row hammer due to dense access to a specific word line may be suppressed.

[0065] In some embodiments, at least one of the plurality of sub-memory banks SB1_1 to SB1_m of the first memory bank array BA1 and / or the plurality of sub-memory banks SB2_1 to SB2_m of the second memory bank array BA2 includes a row hammer region RHR. For example, the plurality of sub-memory banks SB1_1 to SB1_m of the first memory bank array BA1 may include a row hammer region RHR, such as Figure 1A However, this is an example, and the embodiment is not limited thereto. For example, the row hammer region RHR may be formed in the second memory bank array BA2. Alternatively, the row hammer region RHR may be formed in a portion of the first memory bank array BA1 and a portion of the second memory bank array BA2.

[0066] The row hammer region RHR may include a counting unit. The counting unit may refer to a storage unit that stores the number of accesses to the corresponding word line as counting data. In some embodiments, sub-memory banks included in the same memory bank may share counting data with each other.

[0067] For example, the count data of the 1_1th word line WL1_1 of the 1_1th sub memory bank SB1_1 may be stored in the count unit of the row hammer region RHR. In some embodiments, the 1_1th word line WL1_1 of the 1_1th sub memory bank SB1_1 and the 2_1th word line WL2_1 of the 2_1th sub memory bank SB2_1 form a word line pair, so that the count data of the 2_1th word line WL2_1 may be the same as the count data of the 1_1th word line WL1_1.

[0068] Therefore, when the 2_1st word line WL2_1 of the 2_1st sub-memory bank SB2_1 is activated (for example, when a read or write operation is performed on the 2_1st word line WL2_1), the RMW operation may be performed using the count data stored in the count unit of the row hammer region RHR of the 1_1st sub-memory bank SB1_1. For example, the 2_1st sub-memory bank SB2_1 does not include an additional count unit, and may share the count unit of the row hammer region RHR of the 1_1st sub-memory bank SB1_1.

[0069] As described above, sub-banks included in the same bank can share count data with each other to significantly reduce a space required to store the count data.

[0070] Continue to refer to Figure 1A The row hammer management circuit 500 may manage the number of accesses to each of the plurality of word lines based on a command received from the memory controller 100. For example, when an activation command is received from the memory controller 100 and a target word line is activated, the row hammer management circuit 500 may count the number of activations corresponding to the activated word line. The row hammer management circuit 500 may then store the count data, the number of activations, in a counting unit corresponding to the target word line of the row hammer region RHR.

[0071] In some embodiments, the word lines forming the word line pair may be activated together. Therefore, the row hammer management circuit 500 may use a shared counting unit to collectively manage the number of accesses to the word lines forming the word line pair.

[0072] For example, when a read request for normal data stored in a memory cell connected to the 1_1 word line WL1_1 of the 1_1 sub-memory bank SB1_1 is executed, the 1_1 word line WL1_1 may be activated. In some embodiments, the 2_1 word line WL2_1 paired with the 1_1 word line WL1_1 may also be activated together to read metadata corresponding to the normal data requested for read together.

[0073] In some embodiments, the row hammer management circuit 500 may perform a RMW operation to read count data from a count unit corresponding to the 1_1th word line WL1_1 of the row hammer region RHR, add "1" to the read count data to generate updated count data, and write the updated count data back to the count unit. In some embodiments, the 2_1th word line WL2_1 paired with the 1_1th word line WL1_1 is also activated, so that the updated count data may be not only a value corresponding to the 1_1th word line WL1_1, but also a value corresponding to the 2_1th word line WL2_1.

[0074] Similarly, when a read request for normal data stored in a memory cell connected to the 2_1st word line WL2_1 of the 2_1st sub-memory body SB2_1 is performed, the 2_1st word line WL2_1 may be activated. In some embodiments, the 1_1st word line WL1_1 paired with the 2_1st word line WL2_1 may also be activated, and the row hammer management circuit 500 may perform an RMW operation to read count data from a count cell corresponding to the 1_1st word line WL1_1 of the row hammer region RHR, add "1" to the read count data to generate updated count data, and write the updated count data back to the count cell.

[0075] As described above, the 1_1th sub-bank SB1_1 and the 1_2th sub-bank SB1_2 may share the counting unit of the row hammer region RHR to significantly reduce the space required to store the counting data.

[0076] As described above, the memory device 200 according to some embodiments may include a plurality of memory banks, and each memory bank may include a sub-memory bank arranged along a word line direction. In some embodiments, the sub-memory banks included in the same memory bank may share a counting unit with each other. For example, the same counting unit may be used to perform an RMW operation on the sub-memory banks included in the same memory bank. Therefore, the memory device 200 according to some embodiments may be implemented in a smaller area while preventing a row hammer effect.

[0077] Figure 1B is a block diagram illustrating a storage system according to some embodiments. Figure 1B The storage system 10B and Figure 1A Therefore, the same or similar components are denoted by the same or similar reference numerals, and repeated description will be omitted below.

[0078] Reference Figure 1B , the plurality of sub-banks SB1_1 to SB1_m of the first bank array BA1 include a first normal data region NDR1, a second metadata region MDR2, and a first sub-row hammer region SRHR1. The plurality of sub-banks SB121 to SB2_m of the second bank array BA2 include a second normal data region NDR2, a first metadata region MDR1, and a second sub-row hammer region SRHR2.

[0079] exist Figure 1A In the above, it has been described that the row hammer region RHR including the counting unit is formed in the first memory bank array BA1. However, it should be understood that this is only an example and the implementation is not limited thereto. Figure 1B As shown, a portion of the row hammer region including the counting unit may be formed in the first memory bank array BA1, and another portion thereof may be formed in the second memory bank array BA2. For example, the row hammer region may be divided into a first sub-row hammer region SRHR1 and a second sub-row hammer region SRHR2, and the first sub-row hammer region SRHR1 may be formed in the first memory bank array BA1, and the second sub-row hammer region SRHR2 may be formed in the second memory bank array BA2.

[0080] In some embodiments, the first sub-row hammer region SRHR1 and the second sub-row hammer region SRHR2 may be disposed adjacent to each other, such as Figure 1BHowever, this is only an example, and the first sub-row hammer region SRHR1 and the second sub-row hammer region SRHR2 may be disposed in various ways in the first memory bank array BA1 and the second memory bank array BA2.

[0081] Figure 2 is a block diagram illustrating an example of a configuration of a storage controller according to some embodiments. Figure 2 The storage controller 100 may correspond to Figure 1A or Figure 1B A storage controller 100 is provided.

[0082] Reference Figure 2 , the memory controller 100 includes a central processing unit (CPU) 110, an RFM control logic 120, a refresh logic 130, a host interface 140, a scheduler 150, and a memory interface 160 connected through a bus.

[0083] The CPU 110 may control the overall operation of the memory controller 100. For example, the CPU 110 may control the RFM control logic 120, the refresh logic 130, the host interface 140, the scheduler 150, and the memory interface 160.

[0084] RFM control logic 120 may generate row hammer-related refresh management (RFM) commands. For example, when it is determined that there are intensive accesses to a specific word line, RFM control logic 120 may generate a command to refresh memory cells connected to word lines adjacent to the intensively accessed word line.

[0085] The refresh logic 130 may generate a command to perform a normal refresh operation on a plurality of word lines of the memory device 200. For example, the refresh logic 130 may generate an auto-refresh command to sequentially refresh the plurality of word lines according to a refresh cycle.

[0086] The host interface 140 may perform interfacing with a host. The memory interface 160 may perform interfacing with the memory device 200.

[0087] Scheduler 150 may manage the scheduling and transmission of command sequences generated within storage controller 100 .

[0088] In some embodiments, the RFM control logic 120 may be based on the row hammer region RHR (see Figure 1A ) or the first sub-hammer region SRHR1 and the second sub-hammer region SRHR2 (see Figure 1B ) to determine whether access is concentrated on a specific word line. In some embodiments, sub-memory banks included in the same memory bank may share a counting unit, and the RFM control logic 120 may use the shared counting unit to check whether there is a densely accessed word line in each sub-memory bank.

[0089] Figure 3 is a block diagram illustrating an example of a memory device 200 according to some embodiments. Figure 3 The memory device 200 may correspond to Figure 1A and Figure 1B A storage device 200 is provided.

[0090] Reference Figure 3 The memory device 200 includes a control logic circuit 210, an address register 220, a memory body control logic 230, a refresh control circuit 400, a row address multiplexer 240, a column address latch 250, a row decoder group 260, a column decoder group 270, a memory cell array 310, a sense amplifier 285, an input / output selection circuit 290, an ECC engine 350, a data input / output buffer 320 and a row hammer management circuit 500.

[0091] The memory cell array 310 includes a plurality of memory bank arrays 310_1 to 310_n. Each memory bank in the plurality of memory bank arrays 310_1 to 310_n may include a plurality of memory cells. For example, each memory cell in the plurality of memory cells may be formed at an intersection of a corresponding word line and a bit line.

[0092] The row decoder group 260 includes a plurality of row decoders 260_1 to 260_n. Each of the plurality of row decoders 260_1 to 260_n may be connected to a corresponding memory bank array among the plurality of memory bank arrays 310_1 to 310_n.

[0093] The sense amplifier unit 285 includes a plurality of sense amplifiers 285_1 to 285_n. Each of the plurality of sense amplifiers 285_1 to 285_n may be connected to a corresponding bank array among the plurality of bank arrays 310_1 to 310_n.

[0094] The column decoder group 270 includes a plurality of column decoders 270_1 to 270_n. Each of the plurality of column decoders 270_1 to 270_n may be connected to a corresponding memory bank array among the plurality of memory bank arrays 310_1 to 310_n through a column selection line CLS.

[0095] In some embodiments, each memory array in the plurality of memory arrays 310_1 to 310_n may include a plurality of sub-memory banks. Each memory bank may be defined as a different sub-memory bank including different memory arrays. For example, each memory array in the plurality of memory arrays 310_1 to 310_n may include a first sub-memory bank and a second sub-memory bank. The first memory bank may be defined as a first sub-memory bank including a first memory array 310_1 and a first sub-memory bank including a second memory array 310_2. The second memory bank may be defined as a second sub-memory bank including a first memory array 310_1 and a second sub-memory bank including a second memory array 310_2. However, this is merely an example, and the number of sub-memory banks included in a memory bank may be defined in various ways according to some embodiments.

[0096] The address register 220 may receive an address ADDR including a bank address BANK_ADDR, a row address ROW_ADDR, and a column address COL_ADDR from the memory controller 100. The address register 220 may provide the received bank address BANK_ADDR to the bank control logic 230, provide the received row address ROW_ADDR to the row address multiplexer 240, and provide the received column address COL_ADDR to the column address latch 250. In addition, the address register 220 may provide the bank address BANK_ADDR and the row address ROW_ADDR to the row hammer management circuit 500 and the RMW driver 600.

[0097] The bank control logic 230 may generate a bank control signal in response to the bank address BANK_ADDR. For example, a row decoder corresponding to the bank address BANK_ADDR among the plurality of row decoders 260_1 to 260_n may be activated in response to the bank control signal. A column decoder corresponding to the bank address BANK_ADDR among the plurality of column decoders 270_1 to 270_n may be activated in response to the bank control signal.

[0098] The row address multiplexer 240 may receive a row address ROW_ADDR from the address register 220 and a refresh row address REF_ADDR from the refresh control circuit 400. The row address multiplexer 240 may selectively output the row address ROW_ADDR or the refresh row address REF_ADDR as the row address RA. The row address RA output from the row address multiplexer 240 may be applied to each of the plurality of row decoders 260_1 to 260_n.

[0099] In the normal refresh mode, the refresh control circuit 400 may sequentially increase or decrease the refresh row address REF_ADDR in response to a refresh signal from the control logic circuit 210 .

[0100] In the hammer refresh mode, the refresh control circuit 400 may receive a hammer address HADDR and may output an address of a word line adjacent to a densely accessed word line as a refresh row address REF_ADDR based on the hammer address HADDR.

[0101] Among the plurality of row decoders 260_1 to 260_n, a row decoder selected by the bank control logic 230 may activate a word line corresponding to a row address RA output from the row address multiplexer 240. For example, the selected row decoder may apply a word line driving voltage to a word line corresponding to the row address RA.

[0102] The column address latch 250 may receive the column address COL_ADDR from the address register 220 and temporarily store the received column address COL_ADDR. For example, in the burst mode, the column address latch 250 may increment the received column address COL_ADDR. The column address latch 250 may apply the temporarily stored or incremented column address COL_ADDR' to each of the plurality of column decoders 270_1 to 270_n.

[0103] Among the plurality of column decoders 270_1 to 270 — n, a column decoder activated by the bank control logic 230 may activate a sense amplifier corresponding to a bank address BANK_ADDR and a column address COL_ADDR through an input / output gating circuit 290 .

[0104] The input / output gating circuit 290 may include a circuit for gating input / output data. In addition, the input / output gating circuit 290 may include: a data latch storing code words output from the plurality of memory bank arrays 310_1 to 310_n; and a write driver writing data into the plurality of memory bank arrays 310_1 to 310_n.

[0105] In some embodiments, during a read operation, a codeword CW read from a selected memory bank array among the plurality of memory bank arrays 310_1 to 310_n may be detected by a sense amplifier corresponding to the selected memory bank array and stored in a data latch of the input / output strobe circuit 290. In addition, the codeword CW stored in the data latch may be ECC-decoded by the ECC engine 350 and provided as data DTA to the data input / output buffer 320. The data input / output buffer 320 may generate a data signal DQ based on the data DTA and provide the generated data signal DQ to the memory controller 100 together with the strobe signal DQS.

[0106] In some embodiments, during a write operation, the data input / output buffer 320 may receive data DTA to be written to a selected memory bank array among the plurality of memory bank arrays 310_1 to 310_n as a data signal DQ. The data input / output buffer 320 may convert the data signal DQ into data DTA and provide the data DTA to the ECC engine 350. The ECC engine 350 may generate a parity bit (or parity data) based on the data DTA and provide a codeword CW including the data DTA and the parity bit to the input / output gating circuit 290. The input / output gating circuit 290 may write the codeword CW into the selected memory bank array.

[0107] In a write operation, the data input / output buffer 320 may convert the data signal DQ into data DTA and provide the data DTA to the ECC engine 350. In a read operation, the data input / output buffer 320 may convert the data DTA provided by the ECC engine 350 into the data signal DQ.

[0108] In a write operation, the ECC engine 350 may perform ECC encoding on the data DTA. In a read operation, the ECC engine 350 may perform ECC decoding on the codeword CW. In addition, the ECC engine 350 may perform ECC encoding and ECC decoding on the count data CNTD provided from the row hammer management circuit 500.

[0109] The control logic circuit 210 may control the operation of the memory device 200. For example, the control logic circuit 210 may generate a control signal so that the memory device 200 performs a write operation, a read operation, a normal refresh operation, and a hammer refresh operation. The control logic circuit 210 includes: a command decoder 211 that decodes a command CMD received from the memory controller 100; and a mode register set (MRS) 212 that sets the operation mode of the memory device 200.

[0110] The command decoder 211 may decode the command CMD to generate an internal command signal such as an internal activation signal IACT, an internal precharge signal IPRE, an internal read signal IRD, or an internal write signal IWR. In addition, the command decoder 211 may decode a chip select signal and a command / address signal to generate a control signal corresponding to the command CMD.

[0111] The mode register set 212 may set an operation mode of the memory device 200 .

[0112] In some embodiments, the mode register set 212 may set the operation mode of the memory device 200 to a metadata mode. The term "metadata mode" may refer to a mode in which both user data and metadata are stored in the memory device 200. Metadata may be data used to improve the performance or security of the memory device.

[0113] In some implementations, the mode register set 212 may set the operation mode of the memory device 200 to a normal mode. The term "normal mode" may refer to a mode in which only user data (excluding metadata) is stored in the memory device 200.

[0114] In some embodiments, each memory bank may be defined as a different sub-memory bank including different memory bank arrays. In addition, a word line of a sub-memory bank included in the same memory bank forms a word line pair with a word line of another sub-memory bank. Therefore, the sub-memory banks included in the same memory bank may share a counting unit. Therefore, the memory device 200 according to some embodiments may be implemented in a smaller area while preventing the row hammer effect.

[0115] Figure 4 is a diagram of an example of a memory bank array according to some embodiments. Figure 4 The memory bank array 310_1 may correspond to Figure 3 The first memory bank array 310_1. Figure 4 In the present invention, for the convenience of description, an example is provided in which the first memory bank array 310_1 includes two sub-memory banks SB1_1 and SB1_2. In addition, an example is provided in which a single column selection line CSL corresponds to eight bit lines.

[0116] Reference Figure 4 , the first memory bank array 310_1 includes a plurality of word lines WL0 to WLi, a plurality of bit lines BL0 to BLj, and a plurality of memory cells MC disposed at intersections of the word lines WL0 to WLi and the bit lines BL0 to BLj.

[0117] In some embodiments, each memory cell MC may be a DRAM cell. For example, each memory cell MC may include a cell transistor connected to a word line and a bit line, and a cell capacitor connected to the cell transistor.

[0118] A single column selection line CSL may be electrically connected to a plurality of bit lines. For example, a single column selection line CSL may be electrically connected to eight bit lines. In some embodiments, 8-bit data may be read from or written to a memory cell MC via a single word line and a single column selection line CSL.

[0119] According to some embodiments, the word lines extending in the row direction may be referred to as rows of the first memory array 310_1. The column selection lines CSL extending in the column direction may be referred to as columns of the first memory array 310_1. However, this is only an example, and the bit lines extending in the column direction may also be referred to as columns of the first memory array 310_1.

[0120] In some embodiments, the first memory bank array 310_1 includes a 1_1th sub-memory bank SB1_1 and a 1_2th sub-memory bank SB1_2. For example, memory cells connected to the 0th word line WL0 to the k-1th word line WLk-1 may constitute the 1_1th sub-memory bank SB1_1, and memory cells connected to the kth word line WLk to the i-th word line WLi may constitute the 1_2th sub-memory bank SB1_2. In some embodiments, the 1_1th sub-memory bank SB1_1 and the 1_2th sub-memory bank SB1_2 may correspond to different memory banks. For example, the sub-memory banks constituting a single memory bank array may correspond to different memory banks, respectively.

[0121] Figure 5 is a diagram illustrating an example of a memory device according to some embodiments. Figure 5 An example of an arrangement of a bank array and corresponding row and column decoders is shown. Figure 5 The memory device 200 may correspond to Figure 1A , Figure 1B and Figure 3 For convenience of description, an example is provided in which the memory device 200 includes 32 memory bank arrays and a single memory bank group BG includes 4 memory bank arrays.

[0122] Reference Figure 5 , the first memory bank group BG1 includes a first memory bank array BA1 to a fourth memory bank array BA4. For example, the first memory array BA1 and the second memory array BA2 may be disposed adjacent to each other on an upper portion of a substrate (not shown), and the third memory array BA3 and the fourth memory array BA4 may be disposed adjacent to each other on a lower side of the substrate.

[0123] The first row decoder RD1 and the first column decoder CD1 may correspond to the first memory array BA1, and the second row decoder RD2 and the second column decoder CD2 may correspond to the second memory array BA2. In addition, the third row decoder RD3 and the column decoder CD3 may correspond to the third memory array BA3, and the fourth row decoder RD4 and the fourth column decoder CD4 may correspond to the fourth memory array BA4.

[0124] The memory array, row decoder and column decoder arranged adjacent to each other may be referred to as a memory unit. For example, the first memory array BA1, the second memory array BA2, the first row decoder RD1 and the second row decoder RD2, and the first column decoder CD1 and the second column decoder CD2 may be referred to as a first memory unit BU1.

[0125] The first row decoder RD1 and the second row decoder RD2 may be disposed between the adjacent first memory array BA1 and the second memory array BA2. In addition, the third row decoder RD3 and the fourth row decoder RD4 may be disposed between the third memory array BA3 and the fourth memory array BA4 disposed adjacent to each other. However, this is only an example, and the memory array, the row decoder, and the column decoder may be disposed in various forms according to some embodiments.

[0126] Similarly, the second memory bank group BG2 includes the fifth memory bank array BA5 to the eighth memory bank array BA8, and the fifth row decoder RD5 and the sixth row decoder RD6 can be arranged between the fifth memory bank array BA5 and the sixth memory bank array BA6 adjacent to each other, and the seventh row decoder RD7 and the eighth row decoder RD8 can be arranged between the seventh memory bank array BA7 and the eighth memory bank array BA8 adjacent to each other. Similarly, the eighth memory bank group BG8 includes the 29th memory bank array BA29 to the 32nd memory bank array BA32, and the row decoders can be placed between the memory bank arrays adjacent to each other.

[0127] Figure 6 It shows Figure 5 For ease of description, an example is provided in which a single memory bank array includes two sub-memory banks.

[0128] Reference Figure 5 and Figure 6 Each memory bank array may include two sub-memory banks. For example, the first memory bank array BA1 includes a 1_1th sub-memory bank SB1_1 and a 1_2th sub-memory bank SB1_2, and the second memory bank array BA2 includes a 2_1th sub-memory bank SB2_1 and a 2_2nd sub-memory bank SB2_2.

[0129] A memory bank may be defined using two sub-memory banks disposed adjacent to each other in a word line direction. For example, a first memory bank B1 may be defined to include a 1_1th sub-memory bank SB1_1 and a 2_1th sub-memory bank SB2_1, and a second memory bank B2 may be defined to include a 1_2th sub-memory bank SB1_2 and a 2_2nd sub-memory bank SB2_2.

[0130] In some embodiments, two sub-memory banks included in a single memory bank may operate independently.

[0131] For example, the 1_1 sub-memory bank SB1_1 of the first memory bank B1 can be connected to the first row decoder RD1 and the first column decoder CD1, and can independently perform read and write operations. In addition, the 2_1 sub-memory bank SB2_1 of the first memory bank B1 can be connected to the second row decoder RD2 and the second column decoder CD2, and can independently perform read and write operations.

[0132] For example, the 1_2 sub-memory bank SB1_2 of the second memory bank B2 can be connected to the first row decoder RD1 and the first column decoder CD1, and can independently perform read and write operations. In addition, the 2_2 sub-memory bank SB2_2 of the second memory bank B2 can be connected to the second row decoder RD2 and the second column decoder CD2, and can independently perform read and write operations.

[0133] As described above, a memory bank may be defined as including sub-memory banks adjacent to each other in a word line direction. Therefore, two different read or write operations may be independently performed in a single memory bank.

[0134] FIG. 7A to FIG. 7C is a diagram illustrating an example of the operation of a memory bank of a memory device according to some embodiments. For example, Fig. 7A An example of a read operation in a general memory device in which a single memory bank includes a single memory bank array is shown. Figure 7B and Figure 7C Shows Figure 6 An example of a read operation in the memory device 200 in which a single memory bank includes two sub-memory banks.

[0135] Reference Fig. 7A Generally speaking, a memory bank is defined as comprising a single memory bank array. For example, Fig. 7A As shown, a first memory bank is defined as including a first memory bank array, a first row decoder, and a first column decoder, and a second memory bank is defined as including a second memory bank array, a second row decoder, and a second column decoder.

[0136] When a read operation is performed on normal data ND and corresponding metadata MD stored in the first bank array, a first read operation of reading the normal data ND and a second read operation of reading the metadata MD may be sequentially performed.

[0137] In some embodiments, both normal data ND and metadata MD may be output to the outside through the first global I / O line GIO1. Therefore, after performing the first read operation, the first global I / O line GIO1 should be precharged to perform the second read operation. Therefore, it takes a lot of time to read the normal data ND and the corresponding metadata MD in a general memory device.

[0138] Reference Figure 7B According to some embodiments, the first memory bank B1 may be defined to include a 1_1th sub-memory bank SB1_1 and a 2_1th sub-memory bank SB2_1. In some embodiments, normal data ND may be stored in the 1_1th sub-memory bank SB1_1, and metadata MD may be stored in the 2_1th sub-memory bank SB2_1.

[0139] Since the 1_1th sub-memory bank SB1_1 is connected to the first row decoder RD1 and the first column decoder CD1, a read operation of normal data ND stored in the 1_1th sub-memory bank SB1_1 can be independently performed. In addition, since the 2_1th sub-memory bank SB2_1 is connected to the second row decoder RD2 and the second column decoder CD2, a read operation of metadata MD stored in the 2_1th sub-memory bank SB2_1 can be independently performed.

[0140] In addition, since the 1_1th sub memory bank SB1_1 may correspond to the first global I / O line GIO1 and the 2_1th sub memory bank SB2_1 may correspond to the second global I / O line GIO2, the normal data ND and the metadata MD may be output to the outside through the first global I / O line GIO1 and the second global I / O line GIO2, respectively. Therefore, it is not necessary to precharge the global I / O lines between the read operation of the normal data ND and the read operation of the metadata MD.

[0141] Therefore, according to some embodiments, the normal data ND and the metadata MD stored in the first memory bank B1 may be output simultaneously.

[0142] In some embodiments, even if the normal data ND and the metadata MD are stored in the second memory bank B2, the normal data ND and the metadata MD may be output simultaneously.

[0143] For example, Figure 7C As shown, normal data ND and metadata MD may be stored in the 1_2nd sub-bank SB1_2 and the 2_2nd sub-bank SB2_2, respectively. In some embodiments, normal data ND and metadata MD may be simultaneously output through the first global I / O line GIO1 and the second global I / O line GIO2, respectively.

[0144] exist Figure 7Band Figure 7C In the above, an example of a read operation on normal data ND and metadata MD has been described. However, it should be understood that this is only an example, and the implementation is not limited thereto. According to some embodiments, even if the normal data ND and metadata MD are stored in the first storage body B1 or the second storage body B2, a write operation on the normal data ND and a write operation on the metadata MD may be performed simultaneously.

[0145] Figure 8 is a block diagram illustrating an example of a memory cell according to some embodiments. Figure 8 The memory unit BU may correspond to Figure 5 and Figure 6 For ease of description, an example is provided in which each memory bank array corresponds to 64 word line pairs.

[0146] Reference Figure 8 The memory unit BU includes first and second memory arrays BA1 and BA2, first and second row decoders RD1 and RD2, and first and second column decoders CD1 and CD2.

[0147] The first memory array BA1 may be connected to the first row decoder RD1 through a plurality of word lines WL1_0 to WL1_63 and may be connected to the first column decoder CD1 through a plurality of column selection lines CSL0 to CSLn-1. The first memory array BA1 includes a first normal data region NDR1, a second metadata region MDR2 and a row hammer region RHR.

[0148] The first normal data region NDR1 includes a plurality of normal regions NR1_0 to NR1_63 arranged in a column direction. Each of the plurality of normal regions NR1_0 to NR1_63 may store normal data.

[0149] In some embodiments, each of the plurality of normal regions NR1_0 to NR1_63 may include a memory cell, and a single normal region may correspond to a single word line. However, this is merely an example, and according to some embodiments, a single normal region may correspond to a plurality of word lines.

[0150] The second metadata region MDR2 includes a plurality of meta regions MR2_0 to MR2_63 arranged along a column direction. Each of the plurality of meta regions MR2_0 to MR2_63 may correspond to a plurality of normal regions NR2_0 to NR2_63 of the second memory bank array BA2, respectively. Each of the plurality of meta regions MR2_0 to MR2_63 may store metadata corresponding to normal data.

[0151] In some embodiments, each of the plurality of meta regions MR2_0 to MR2_63 may include a memory cell, and a single meta region may correspond to a single word line. However, this is only an example, and according to some embodiments, a single meta region may correspond to a plurality of word lines.

[0152] The row hammer region RHR includes a plurality of row count regions RC0 to RC63 arranged along the column direction. Each of the row count regions RC0 to RC63 may store count data and / or count parity data of a corresponding word line. The count parity data may be generated based on the count data and may refer to data for ECC encoding or decoding the count data.

[0153] In some embodiments, each of the plurality of row count regions RC0 to RC63 may include a storage unit. A storage unit storing count data may be referred to as a count unit. A storage unit storing count parity data may be referred to as a count parity unit. A single row count region may correspond to a single word line. However, this is merely an example, and according to some embodiments, a single row count region may correspond to a plurality of word lines.

[0154] Continue to refer to Figure 8 The second memory array BA2 may be connected to the second row decoder RD2 through a plurality of word lines WL2_0 to WL2_63, and may be connected to the second column decoder CD2 through a plurality of column selection lines CSL0 to CSLn-1. The second memory array BA2 includes a second normal data region NDR2 and a first metadata region MDR1.

[0155] The second normal data region NDR2 includes a plurality of normal regions NR2_0 to NR2_63 arranged in a column direction. Each of the plurality of normal regions NR2_0 to NR2_63 may store normal data.

[0156] In some embodiments, each of the plurality of normal regions NR2_0 to NR2_63 may include a memory cell, and a single normal region may correspond to a single word line. However, this is merely an example, and according to some embodiments, a single normal region may correspond to a plurality of word lines.

[0157] The first metadata region MDR1 includes a plurality of meta regions MR1_0 to MR1_63 arranged along a column direction. Each of the plurality of meta regions MR1_0 to MR1_63 may correspond to a plurality of normal regions NR1_0 to NR1_63 of the first bank array BA1, respectively. Each of the plurality of meta regions MR1_0 to MR1_63 may store metadata corresponding to normal data.

[0158] In some embodiments, each of the plurality of meta regions MR1_0 to MR1_63 may include a memory cell, and a single meta region may correspond to a single word line. However, this is merely an example, and according to some embodiments, a single meta region may correspond to a plurality of word lines.

[0159] In some embodiments, a first memory bank B1 may be defined to include a portion of a first memory bank array BA1 and a portion of a second memory bank array BA2, and a second memory bank B2 may be defined to include another portion of the first memory bank array BA1 and another portion of the second memory bank array BA2.

[0160] For example, the first memory bank B1 may be defined as including: a plurality of normal regions NR1_0 to NR1_31, a plurality of meta regions MR2_0 to MR2_31, and a plurality of row count regions RC0 to RC31 included in the first memory bank array BA1, and a plurality of normal regions NR2_0 to NR2_31 and a plurality of meta regions MR1_0 to MR1_31 included in the second memory bank array BA2. The second memory bank B2 may be defined as including: a plurality of normal regions NR1_32 to NR1_63, a plurality of meta regions MR2_32 to MR2_63, and a plurality of row count regions RC32 to RC63 included in the first memory bank array BA1, and a plurality of normal regions NR2_32 to NR2_63 and a plurality of meta regions MR1_32 to MR1_63 included in the second memory bank array BA2.

[0161] In some embodiments, a plurality of word lines WL1_0 to WL1_63 corresponding to the first bank array BA1 and a plurality of word lines WL2_0 to WL2_63 corresponding to the second bank array BA2 may constitute a word line pair.

[0162] For example, the 1_0th word line WL1_0 of the first memory bank array BA1 may correspond to the 2_0th word line WL2_0 of the second memory bank array BA2, and the 1_0th word line WL1_0 and the 2_0th word line WL2_0 may constitute the 0th word line pair. For example, the 1_1th word line WL1_1 of the first memory bank array BA1 may correspond to the 2_1th word line WL2_1 of the second memory bank array BA2, and the 1_1th word line WL1_1 and the 2_1th word line WL2_1 may constitute the first word line pair. Similarly, the 1_63rd word line WL1_63 of the first memory bank array BA1 may correspond to the 2_63rd word line WL2_63 of the second memory bank array BA2, and the 1_63rd word line WL1_63 and the 2_63rd word line WL2_63 may constitute the 63rd word line pair.

[0163] In some embodiments, when a read or write operation of normal data and corresponding metadata is requested, two word lines constituting a word line pair may be activated.

[0164] For example, when a read operation is requested for normal data stored in the 1_0th normal region NR1_0 and metadata stored in the corresponding 1_0th meta region MR1_0, the 1_0th word line WL1_0 and the 2_0th word line WL2_0 may be activated. Then, the normal data stored in the 1_0th normal region NR1_0 corresponding to the 1_0th word line WL1_0 may be output, and the metadata stored in the 1_0th meta region MR1_0 corresponding to the 2_0th word line WL2_0 may be output.

[0165] As described above, two word lines constituting a word line pair are activated together. Therefore, the two word lines constituting a word line pair may have the same count data. For example, the number of times the 1_0th word line WL1_0 is activated is the same as the number of times the 2_0th word line WL2_0 is activated, so that the 1_0th word line WL1_0 and the 2_0th word line WL2_0 may have the same count data.

[0166] In some embodiments, the plurality of row counting regions RC0 to RC63 of the row hammer region RHR may each store count data and / or count parity data of a corresponding word line pair. For example, the count data of two word lines constituting a word line pair are the same, so that the count data and / or count parity data of the two word lines constituting the word line pair may be managed as a whole through the plurality of row counting regions RC0 to RC63 of the row hammer region RHR.

[0167] As described above, the row hammer region RHR may integrally manage count data and / or count parity data of word lines constituting a word line pair, so that a space required to implement the row hammer region RHR may be significantly reduced.

[0168] Figures 9 to 12 is a diagram illustrating a matching relationship between normal data and metadata in a storage body according to some embodiments. Fig. 9 and Fig.10 An example of a matching relationship between the first normal data region NDR1 and the first metadata region MDR1 is shown, and Fig.11 and Fig.12 An example of a matching relationship between the second normal data region NDR2 and the second metadata region MDR2 is shown. Figures 9 to 12 The first memory bank B1 may correspond to, for example Figure 8 The first memory bank B1.

[0169] For ease of description, the following example is provided: normal data and metadata are matched at a ratio of 8:1, each normal data region corresponds to 56 column selection lines, and each metadata region corresponds to 8 column selection lines. In addition, for ease of description, an example is provided in which the first memory bank B1 corresponds to 32 word line pairs.

[0170] Reference Fig. 9 and Fig.10 The first memory bank B1 includes a 1_1th sub-memory bank SB1_1 and a 2_1th sub-memory bank SB2_1. The 1_1th sub-memory bank SB1_1 includes a first normal data region NDR1, a second metadata region MDR2 and a row hammer region RHR. The 2_1th sub-memory bank SB2_1 includes a second normal data region NDR2 and a first metadata region MDR1.

[0171] The first normal data region NDR1 of the 1_1th sub-memory bank SB1_1 may match the first metadata region MDR1 of the 2_1th sub-memory bank SB2_1. The plurality of word lines WL1_0 to WL1_31 corresponding to the 1_1th sub-memory bank SB1_1 may constitute a word line pair with the plurality of word lines WL2_0 to WL2_31 corresponding to the 2_1th sub-memory bank SB2_1. Therefore, the plurality of normal regions NR1_0 to NR1_31 connected to the plurality of word lines WL1_0 to WL1_31 may each match the plurality of meta regions MR1_0 to MR1_31 connected to the plurality of word lines WL2_0 to WL2_31.

[0172] For example, the 1_0th normal region NR1_0 may correspond to the 1_0th word line WL1_0 and 0th to 55th column selection lines CSL0 to CSL55 of the 1_1th sub memory bank SB1_1. The 1_0th meta region MR1_0 may correspond to the 2_0th word line WL2_0 and 56th to 63rd column selection lines CSL56 to CSL63 of the 2_1th sub memory bank SB2_1.

[0173] The memory cells corresponding to the 1_0th word line WL1_0 and the 0th to 7th column selection lines CSL0 to CSL7 of the 1_0th normal region NR1_0 may store normal data, and metadata corresponding to the normal data may be stored in the memory cells corresponding to the 2_0th word line WL2_0 and the 56th column selection line CSL56 of the 1_0th meta region MR1_0.

[0174] The memory cells corresponding to the 1_0th word line WL1_0 and the 8th to 15th column selection lines CSL8 to CSL15 of the 1_0th normal region NR1_0 may store normal data, and metadata corresponding to the normal data may be stored in the memory cells corresponding to the 2_0th word line WL2_0 and the 57th column selection line CSL57 of the 1_0th meta region MR1_0.

[0175] Similarly, storage cells corresponding to the 1_0th word line WL1_0 and the 48th to 55th column selection lines CSL48 to CSL55 of the 1_0th normal region NR1_0 may store normal data, and metadata corresponding to the normal data may be stored in storage cells corresponding to the 2_0th word line WL2_0 and the 62nd column selection line CSL62 of the 1_0th meta region MR1_0.

[0176] Since normal data and metadata are matched at a ratio of 8:1, data may not be stored in memory cells corresponding to the 2_0 th word line WL2_0 and the 63 th column selection line CSL63 .

[0177] Similarly, the 1_1st normal region NR1_1 may correspond to the 1_1st word line WL1_1 and the 0th column selection line CSL0 to the 55th column selection line CSL55, and the 1_1st meta region MR1_1 may correspond to the 2_1st word line WL2_1 and the 56th column selection line CSL56 to the 63rd column selection line CSL63. The normal data stored in the 1_1st normal region NR1_1 and the meta data stored in the 1_1st meta region MR1_1 may match each other. Similarly, the 1_31st normal region NR1_31 may correspond to the 1_31st word line WL1_31 and the 0th column selection line CSL0 to the 55th column selection line CSL55, and the 1_31st meta region MR1_31 may correspond to the 2_31st word line WL2_31 and the 56th column selection line CSL56 to the 63rd column selection line CSL63. The normal data stored in the 1_31th normal region NR1_31 and the metadata stored in the 1_31th meta region MR1_31 may match each other.

[0178] Reference Fig.11 and Fig.12 , the second normal data region NDR2 of the 2_1th sub-memory bank SB2_1 may match the second metadata region MDR2 of the 1_1th sub-memory bank SB1_1. The plurality of normal regions NR2_0 to NR2_31 connected to the plurality of word lines WL2_0 to WL2_31 may respectively match the plurality of meta regions MR2_0 to MR2_31 connected to the plurality of word lines WL1_0 to WL1_31.

[0179] For example, the 2_0th normal region NR2_0 may correspond to the 2_0th word line WL2_0 and the column selection lines CSL0 to CSL55 of the 2_1th sub memory bank SB2_1. The 2_0th meta region MR2_0 may correspond to the 1_0th word line WL1_0 and the column selection lines CSL56 to CSL63.

[0180] The memory cells corresponding to the 2_0th word line WL2_0 and the column selection lines CSL0 to CSL7 of the 2_0th normal region NR2_0 may store normal data, and metadata corresponding to the normal data may be stored in the memory cells corresponding to the 1_0th word line WL1_0 and the 56th column selection line CSL56 of the 2_0th meta region MR2_0.

[0181] The memory cells corresponding to the 2_0th word line WL2_0 and column selection lines CSL8 to CSL15 of the 2_0th normal region NR2_0 may store normal data, and metadata corresponding to the normal data may be stored in the memory cells corresponding to the 1_0th word line WL1_0 and the 57th column selection line CSL57 of the 2_0th meta region MR2_0.

[0182] Similarly, the memory cells corresponding to the 2_0th word line WL2_0 and the column selection lines CSL48 to CSL55 of the 2_0th normal region NR2_0 may store normal data, and metadata corresponding to the normal data may be stored in the memory cells corresponding to the 1_0th word line WL1_0 and the 62nd column selection line CSL62 of the 2_0th meta region MR2_0.

[0183] Since normal data and metadata are matched at a ratio of 8:1, data may not be stored in memory cells corresponding to the 1_0 th word line WL1_0 and the 63 th column selection line CSL63 .

[0184] Similarly, the 2_1st normal region NR2_1 may correspond to the 2_1st word line WL2_1 and the column selection lines CSL0 to CSL55, and the 2_1st meta region MR2_1 may correspond to the 1_1st word line WL1_1 and the column selection lines CSL56 to CSL63. The normal data stored in the 2_1st normal region NR2_1 and the metadata stored in the 2_1st meta region MR2_1 may match each other. Similarly, the 2_31st normal region NR2_31 may correspond to the 2_31st word line WL2_31 and the column selection lines CSL0 to CSL55, and the 2_31st meta region MR2_31 may correspond to the 1_31st word line WL1_31 and the column selection lines CSL56 to CSL63. The normal data stored in the 2_31st normal region NR2_31 and the metadata stored in the 2_31st meta region MR2_31 may match each other.

[0185] like Figures 9 to 12 As shown, a plurality of word lines WL1_0 to WL1_31 corresponding to the 1_1 sub-memory bank SB1_1 and a plurality of word lines WL2_0 to WL2_31 corresponding to the 2_1 sub-memory bank SB2_1 may be matched at a ratio of 1:1 to form a word line pair. In some embodiments, normal data may be stored in a memory cell connected to one of the two word lines forming the word line pair, and metadata corresponding to the normal data may be stored in a memory cell connected to the other word line. Therefore, when normal data and corresponding metadata are input or output, the two word lines forming the word line pair may be activated.

[0186] Return to Fig. 9 and Fig.11 , the row hammer region RHR includes a plurality of row counting regions RC0 to RC31, and the plurality of row counting regions RC0 to RC31 may correspond to a plurality of word line pairs, respectively. For example, the 0th row counting region RC0 may correspond to the 0th word line pair including the 1_0th word line WL1_0 and the 2_0th word line WL2_0, and the first row counting region RC1 may correspond to the first word line pair including the 1_1th word line WL1_1 and the 2_1th word line WL2_1.

[0187] Each row counting region may include a counting unit and a counting parity unit. For example, the 0th row counting region RC0 includes a 0th counting unit CC0 and a 0th counting parity unit PC0, and the first row counting region RC1 includes a first counting unit CC1 and a first counting parity unit PC1.

[0188] The counting unit may store counting data of the corresponding word line pair. The counting parity unit may store counting parity data for ECC encoding or decoding operation. For example, the 0th counting unit CC0 of the 0th row counting region RC0 may store counting data corresponding to the 1_0th word line WL1_0 and the 2_0th word line WL2_0 forming the 0th word line pair, and the 0th counting parity unit PC0 may store counting parity data corresponding to the 1_0th word line WL1_0 and the 2_0th word line WL2_0 forming the 0th word line pair. For example, the first counting unit CC1 of the first row counting region RC1 may store counting data corresponding to the 1_1th word line WL1_1 and the 2_1th word line WL2_1 forming the first word line pair, and the first counting parity unit PC1 stores counting parity data corresponding to the 1_1th word line WL1_1 and the 2_1th word line WL2_1 forming the first word line pair.

[0189] In some embodiments, the 1_1th sub-bank SB1_1 and the 2_1th sub-bank SB2_1 may share counting data stored in the counting unit and counting parity data stored in the counting parity unit.

[0190] For example, as described above, the multiple word lines WL1_0 to WL1_31 of the 1_1 sub-storage body SB1_1 and the multiple word lines WL2_0 to WL2_31 of the 2_1 sub-storage body SB2_1 can form a word line pair, and the two word lines included in each word line pair can be activated together. Therefore, the number of accesses to the multiple word lines WL1_0 to WL1_31 of the 1_1 sub-storage body SB1_1 and the number of accesses to the multiple word lines WL2_0 to WL2_31 of the 2_1 sub-storage body SB2_1 can be the same. Therefore, the 1_1 sub-storage body SB1_1 and the 2_1 sub-storage body SB2_1 do not need to have the same count data and count parity data, and can share the count data and count parity data. Therefore, the area occupied by the row hammer region required to prevent the row hammer effect can be significantly reduced.

[0191] Fig.13 is a diagram of an example of a memory device that updates count data through an RMW operation according to some embodiments. Figures 8 to 12 A similar example is shown in which the row hammer region RHR is included in the 1_1th sub-bank SB1_1.

[0192] Reference Fig.13 , an access request to a target word line pair may be received. For example, an access request to normal data corresponding to the 1_0th word line WL1_0 of the first normal data region NDR1 may be received. In some embodiments, the 1_0th word line WL1_0 and the 2_0th word line WL2_0 may be activated to read normal data and metadata corresponding to the normal data. Alternatively, an access request to normal data corresponding to the 2_0th word line WL2_0 of the second normal data region NDR2 may be received. In some embodiments, the 1_0th word line WL1_0 and the 2_0th word line WL2_0 may be activated to read normal data and metadata corresponding to the normal data.

[0193] Then, the read operation in the RMW operation can be performed.

[0194] For example, the count data CNTD on the 1_0th word line WL1_0 and the 2_0th word line WL2_0 may be read from the 0th count unit CC0, and the read count data CNTD may be provided to the ECC engine 350 through the input / output gating circuit 290. In addition, the count parity data CPRT corresponding to the count data CNTD may be read from the 0th count parity unit PC0, and the read count parity data CPRT may be provided to the ECC engine 350 through the input / output gating circuit 290.

[0195] The ECC engine 350 may perform ECC decoding on the count data CNTD and the count parity data CPRT to correct error bits of the count data CNTD, and may provide the count data CNTD to the row hammer management circuit 500 .

[0196] Then, the correction operation in the RMW operation can be performed.

[0197] For example, the row hammer management circuit 500 may perform an update operation to increase the count data CNTD by “1”.

[0198] Then, the write operation in the RMW operation can be performed.

[0199] For example, the row hammer management circuit 500 may provide updated count data UCNTD to the ECC engine 350. The ECC engine 350 may perform ECC encoding on the updated count data UCNTD to generate updated count parity data UCPRT. The updated count data UCNTD may be restored in the 0th count unit CC0. In addition, the updated count parity data UCPRT may be restored in the 0th count parity unit PC0.

[0200] In some embodiments, the updated count data UCNTD and the updated count parity data UCPRT may correspond to the target word line pair, the 1_0th word line WL1_0 and the 2_0th word line WL2_0. For example, the updated count data UCNTD and the updated count parity data UCPRT may be shared by the 1_1th sub-memory bank SB1_1 and the 2_1th sub-memory bank SB2_1, and thus the 2_1th sub-memory bank SB2_1 does not need to have a separate row hammer region RHR. Therefore, the sub-memory banks SB1_1 and SB2_1 included in the same first memory bank B1 may share count data and count parity data with each other to significantly reduce the area required to implement the row hammer region RHR.

[0201] exist Figures 8 to 13In the above description, it has been described that the row hammer region RHR is arranged in a single sub-memory bank. However, it should be understood that this is only an example, and the implementation is not limited thereto. Fig.14 As described, the row hammer regions RHR may be distributed and disposed in two sub-memory banks included in the same memory bank.

[0202] Fig.14 is a diagram showing some embodiments of implementing the row hammer area in a distributed manner, and Fig.15 is a diagram showing an example of an RMW operation performed when the hammer zone is implemented in a distributed manner. Fig.14 The first memory bank B1 and Fig. 9 The first memory bank B1 is similar, and Fig.15 The memory device 200 and Fig.13 Therefore, the same or similar components will be denoted by the same or similar reference numerals, and repeated description will be omitted below.

[0203] Reference Fig.14 , the first memory bank B1 includes a 1_1th sub-memory bank SB1_1 and a 2_1th sub-memory bank SB2_1. The 1_1th sub-memory bank SB1_1 includes a first normal data region NDR1, a second metadata region MDR2, and a first sub-row hammer region SRHR1. The 2_1th sub-memory bank SB2_1 includes a second normal data region NDR2, a first metadata region MDR1, and a second sub-row hammer region SRHR2.

[0204] The first sub-hammer region SRHR1 and the second sub-hammer region SRHR2 may correspond to Fig. 9 The hammer area RHR. For example, Fig. 9 Each of the plurality of row count regions RC0 to RC31 included in the row hammer region RHR may be divided into a first sub-row hammer region SRHR1 and a second sub-row hammer region SRHR2 .

[0205] For example, the first sub-row hammer region SRHR1 may be implemented to include a plurality of counting cells CC0 to CC31, and the second sub-row hammer region SRHR2 may be implemented to include a plurality of counting parity cells PC0 to PC31. Each of the plurality of counting cells CC0 to CC31 may store counting data of a corresponding word line pair. Each of the plurality of counting parity cells PC0 to PC31 may store counting parity data of the corresponding counting data.

[0206] Reference Fig.15, an access request to a target word line pair may be received. For example, the target word line pair may be a 1_0th word line WL1_0 and a 2_0th word line WL2_0. In some embodiments, the 1_0th word line WL1_0 and the 2_0th word line WL2_0 may be activated.

[0207] Then, the read operation in the RMW operation can be performed.

[0208] For example, the count data CNTD on the 1_0th word line WL1_0 and the 2_0th word line WL2_0 may be read from the 0th count unit CC0 of the first sub-row hammer region SRHR1, and the read count data CNTD may be provided to the ECC engine 350 through the input / output gating circuit 290. In addition, the count parity data CPRT corresponding to the count data CNTD may be read from the 0th count parity unit PC0 of the second sub-row hammer region SRHR2, and the read count parity data CPRT may be provided to the ECC engine 350 through the input / output gating circuit 290.

[0209] The ECC engine 350 may perform ECC decoding on the count data CNTD and the count parity data CPRT to correct error bits of the count data CNTD, and may provide the count data CNTD to the row hammer management circuit 500 .

[0210] Then, the correction operation in the RMW operation can be performed.

[0211] For example, the row hammer management circuit 500 may perform an update operation to increase the count data CNTD by “1”.

[0212] Then, the write operation in the RMW operation can be performed.

[0213] For example, the row hammer management circuit 500 may provide updated count data UCNTD to the ECC engine 350. The ECC engine 350 may perform ECC encoding on the updated count data UCNTD to generate updated count parity data UCPRT. The updated count data UCNTD may be restored in the 0th count unit CC0. In addition, the updated count parity data UCPRT may be restored in the 0th count parity unit PC0.

[0214] As described above, the counting unit and the parity counting unit may be implemented to be distributed in the 1_1th sub-bank SB1_1 and the 2_1th sub-bank SB2_1.

[0215] exist Figures 8 to 15In the above description, it has been described that the ratio of the count data and the parity count data corresponding to the same word line pair is 1:1. However, it should be understood that this is only an example, and the implementation is not limited thereto. According to some embodiments, the ratio of the count data and the parity count data may be set to N:1 (where N is a positive integer). According to some embodiments, the ECC engine may not be set. In some embodiments, the parity count unit may not be set.

[0216] exist Figures 9 to 15 In the embodiment, it has been described that the ratio of normal data to metadata is 8:1. However, it should be understood that this is only an example, and the implementation is not limited thereto. According to some embodiments, the ratio of normal data to metadata may be set to N:1 (where N is a positive integer). For example, the ratio of normal data to metadata may be set to 16:1.

[0217] Fig.16 is a diagram illustrating an example of a memory bank according to some embodiments, and Fig.17 yes Fig.16 A more detailed view of area "A". Fig.16 The first memory bank B1 may correspond to Figures 1A to 8 For the convenience of description, an example in which the ratio of normal data to metadata is 8:1 is provided.

[0218] Reference Fig.16 , the first memory bank B1 includes a 1_1th sub-memory bank SB1_1 and a 2_1th sub-memory bank SB2_1 arranged along a word line direction.

[0219] The 1_1th sub memory bank SB1_1 may be electrically connected to the first row decoder RD1 and the first column decoder CD1. The 1_1th sub memory bank SB1_1 may be connected to a plurality of word lines WL1_0 to WL1_32k-1 through the first row decoder RD1. In addition, the 1_1th sub memory bank SB1_1 may be connected to a plurality of column selection lines CSL through the first column decoder CD1.

[0220] The 2_1st sub-memory bank SB2_1 may be electrically connected to the second row decoder RD2 and the second column decoder CD2. The 2_1st sub-memory bank SB2_1 may be connected to a plurality of word lines WL2_0 to WL2_32k-1 through the second row decoder RD2. In addition, the 2_2nd sub-memory bank SB2_1 may be connected to a plurality of column selection lines CSL through the second column decoder CD2.

[0221] Each of the 1_1th sub-memory bank SB1_1 and the 2_1th sub-memory bank SB2_1 includes a plurality of memory slices MAT. Each memory slice MAT may be connected to a portion of a word line and a portion of a column selection line CSL. Each memory slice MAT may include a plurality of memory cells, and each memory cell may be connected to one of the word lines connected to the corresponding MAT and one of the column selection lines CSL connected to the corresponding MAT.

[0222] The first column decoder CD1 includes a plurality of CSL blocks CB0 to CB7. Each of the plurality of CSL blocks CB0 to CB7 may be configured to select a column selection line to be activated among a plurality of column selection lines based on a column address decoded from the first column decoder CD1. Similarly, the second column decoder CD2 includes a plurality of CSL blocks CB0 to CB7. Each of the plurality of CSL blocks CB0 to CB7 may be configured to select a column selection line to be activated among a plurality of column selection lines based on a column address decoded from the second column decoder CD2.

[0223] In some embodiments, each CSL block CB may correspond to two CSL groups CS. For example, the 0th CSL block CB0 may correspond to the 0th CSL group CS0 and the first CSL group CS1, and the first CSL block CB1 may correspond to the second CSL group CS2 and the third CSL group CS3. Similarly, the sixth CSL block CB6 may correspond to the twelfth CSL group CS12 and the thirteenth CSL group CS13, and the seventh CSL block CB7 may correspond to the fourteenth CSL group CS14 and the fifteenth CSL group CS15.

[0224] Each CSL group CS may include a plurality of column selection lines. For example, each CSL group CS may include 64 column selection lines. A portion of the 64 column selection lines may be allocated to the normal data area, and another portion thereof may be allocated to the metadata area.

[0225] Will describe in more detail Fig.17 An example of the sixth CSL block CB6 is shown. The sixth CSL block CB6 may be connected to the twelfth CSL group CS12 and the thirteenth CSL group CS13. The twelfth CSL group CS12 includes the 0th column selection line CSL0 to the 63rd column selection line CSL63, and the thirteenth CSL group CS13 includes the 0th column selection line CSL0 to the 63rd column selection line CSL63. Therefore, a total of 128 column selection lines may be connected to the sixth CSL block CB6.

[0226] In the twelfth CSL group CS12, the 0th column selection line CSL0 to the 55th column selection line CSL55 may be allocated to the normal data region NDR, and the remaining 56th column selection line CSL56 to the 63rd column selection line CSL63 may be allocated to the metadata region MDR. In the thirteenth CSL group CS13, the 0th column selection line CSL0 to the 55th column selection line CSL55 may be allocated to the normal data region NDR, and the remaining 56th column selection line CSL56 to the 63rd column selection line CSL63 may be allocated to the metadata region MDR. As described above, a part of the column selection lines of each CSL group CS may be allocated to the normal data region NRD, and another part thereof may be allocated to the metadata region MDR.

[0227] Continue to refer to Fig.16 , a single column select line in a single CSL group CS can be selected and activated during a single access operation. Since two CSL groups CS correspond to a single CSL block CB, a single CSL block CB can select one or two column select lines during a single access operation.

[0228] For ease of description, an example is provided where the decoded column address is “CSLx[a:b].” In some embodiments, “x” may refer to the number of a column selection line, and “[a:b]” may refer to a range of a selected CSL group.

[0229] In addition, an example is provided in which the column address decoded by the first column decoder CD1 is "CSL0[0:15]". In some embodiments, the 0th CSL group CS0 to the 15th CSL group CS15 may be selected, and the 0th column selection line CSL0 may be selected in each of the 0th CSL group CS0 to the 15th CSL group CS15. Since each CSL block CB corresponds to two CSL groups CS, each CSL block CB of the 1_1th sub-storage body SB1_1 may select two 0th column selection lines CSL0. The two column selection lines selected by each CSL block CB may be referred to as a "CSL subset".

[0230] In some embodiments, the 0th to 55th column selection lines CSL0 to CSL55 are allocated to the normal data region NDR so that when the decoded column address is CSL0 [0:15], normal data may be input or output to the 1_1th sub-bank SB1_1.

[0231] In addition, an example is provided in which the column address decoded by the second column decoder CD2 is "CSL56[0:1]". In some embodiments, the 0th CSL group CS0 and the first CSL group CS1 may be selected, and the 56th column selection line CSL56 may be selected in each of the 0th CSL group CS0 and the first CSL group CS1. Since the 0th CSL block CB0 corresponds to the 0th CSL group CS0 and the first CSL group CS1, the 0th CSL block CB0 of the second sub-memory body SB2_1 may select two 56th column selection lines CSL56.

[0232] In some embodiments, the 56th to 63rd column selection lines CSL56 to CSL63 are allocated to the metadata region MDR, and when the decoded column address is CSL56 [0:1], metadata may be input or output to the 2_1th second sub-bank SB2_1.

[0233] In some embodiments, a plurality of word lines WL1_0 to WL1_32k-1 corresponding to the 1_1th sub-memory bank SB1_1 may be matched with a plurality of word lines WL2_0 to WL2_32k-1 corresponding to the 2_1th sub-memory bank SB2_1 to form a word line pair. For example, the 1_0th word line WL1_0 and the 2_0th word line WL2_0 may form a 0th word line pair, and the 1_1th word line WL1_1 and the 2_1th word line WL2_1 may form a first word line pair.

[0234] In some embodiments, metadata corresponding to normal data stored in the 1_1th sub-bank SB1_1 may be stored in the 2_1th sub-bank SB2_1 , and the normal data and the metadata may correspond to the same word line pair.

[0235] In addition, an example is provided in which the first row decoder RD1 and the second row decoder RD2 select the 1_0th word line WL1_0 and the 2_0th word line WL2_0 , and the ratio of normal data and metadata is 8:1.

[0236] In some embodiments, when the column address decoded by the first column decoder CD1 is "CSL0[0:15]", the column address decoded by the column decoder CD2 may be "CSL56[0:1]". When the column address decoded by the first column decoder CD1 is "CSL1[0:15]", the column address decoded by the column decoder CD2 may be "CSL56[2:3]". Similarly, when the column address decoded by the first column decoder CD1 is "CSL54[0:15]", the column address decoded by the column decoder CD2 may be "CSL56[12:13]". When the column address decoded by the first column decoder CD1 is "CSL55[0:15]", the column address decoded by the column decoder CD2 may be "CSL62[14:15]". Therefore, normal data corresponding to the 1_0th word line WL1_0 of the 1_1th sub-bank SB1_1 may be matched with metadata corresponding to the 2_0th word line WL2_0 of the 2_1th sub-bank SB2_1.

[0237] As described above, a plurality of word lines included in one sub-storage bank and a plurality of word lines included in another sub-storage bank form a word line pair, and thus a plurality of metadata of a plurality of normal data stored in the 1_1th sub-storage bank SB1_1 can be distributed and stored in the word line of the 2_1th sub-storage bank SB2_1, and a plurality of metadata of a plurality of normal data stored in the 2_1th sub-storage bank SB2_1 can be distributed and stored in the word line of the 1_1th sub-storage bank SB1_1. Therefore, it is possible to prevent a plurality of metadata from being distributed and stored in a specific word line. Therefore, it is possible to suppress a row hammer effect caused by intensive access to a specific word line.

[0238] Continue to refer to Fig.16 and Fig.17 In some embodiments, at least one of the sub-memory banks SB1_1 and SB2_1 included in the first memory bank B1 includes a row hammer region RHR, and count data and / or count parity data of each word line pair stored in the row hammer region RHR can be shared by the 1_1th sub-memory bank SB1_1 and the 2_1th sub-memory bank SB2_1.

[0239] For example, the memory slice MAT corresponding to the sixth CSL block CB6 of the 1_1th sub-bank SB1_1 and the memory slice MAT corresponding to the seventh CSL block CB7 may be provided with a row hammer region RHR, such as Fig.16 shown.

[0240] In some embodiments, the multiple word lines WL1_0 to WL1_31 of the 1_1 sub-memory body SB1_1 and the multiple word lines WL2_0 to WL2_31 of the 2_1 sub-memory body SB2_1 may form a word line pair, and the two word lines included in each word line pair may be activated together. Therefore, the number of accesses to the multiple word lines WL1_0 to WL1_31 of the 1_1 sub-memory body SB1_1 and the number of accesses to the multiple word lines WL2_0 to WL2_31 of the 2_1 sub-memory body SB2_1 may be the same. Therefore, the 1_1 sub-memory body SB1_1 and the 2_1 sub-memory body SB2_1 do not need to have the same count data and count parity data, and may share the count data and count parity data. Therefore, the area occupied by the row hammer region required to prevent the row hammer effect may be significantly reduced.

[0241] 18A to 18C is a diagram showing various examples of memory banks in which row hammer regions are set in various ways according to some embodiments.

[0242] Reference 18A to 18C , hammer area RHR (see Fig.17 ) may include a parity check unit region and a counting unit region. In addition, the ratio and arrangement of the parity check unit region and the counting unit region may be changed according to some embodiments. The parity check unit region may refer to a region in which a counting parity check unit is disposed, and the counting unit region may refer to a region in which a counting unit is disposed.

[0243] For example, the ratio of the parity check unit area to the counting unit area may be 1:2, as shown in FIG. Fig.18A Both the parity cell region and the count cell region may be provided in a single sub-bank SB1_1.

[0244] For example, the ratio of the parity check unit area to the counting unit area may be 1:2, as shown in FIG. Fig.18B As shown, the parity cell region may be arranged in a single sub-bank SB1_1. The counting cell region may be distributed and arranged in the 1_1th sub-bank SB1_1 and the 2_1th sub-bank SB2_1.

[0245] For example, the ratio of the parity check unit area to the counting unit area may be 1:1, as Fig. 18C The parity cell region may be disposed in a single sub-bank SB2_1, and the count cell region may be disposed in a single sub-bank SB1_1.

[0246] exist Figures 16 to 18CIn the embodiment, it has been described that the ratio of normal data to metadata is 8:1. However, it should be understood that this is only an example, and the implementation is not limited thereto. In some embodiments, the ratio of normal data to metadata may be set to N:1 (where N is a positive integer). For example, the ratio of normal data to metadata may be set to 16:1.

[0247] As described above, a memory device according to some embodiments may be implemented in a smaller area while preventing the row hammer effect.

[0248] Although the present disclosure includes many specific implementation details, these details should not be interpreted as limiting the scope of what can be claimed. In a single embodiment, specific features described in the context of independent embodiments in the present disclosure can also be implemented in combination. Conversely, various features described in the context of a single embodiment can also be implemented separately in multiple embodiments, or in appropriate sub-combinations. In addition, although features can be described above as working in certain combinations, one or more features from a combination can be deleted from the combination in some cases, and the combination can be directed to a sub-combination or a variant of a sub-combination.

[0249] While embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. A storage device, comprising: at least one memory bank, comprising at least a first sub-memory bank and a second sub-memory bank arranged along a word line direction, in, The first sub-memory bank includes a normal data region connected to a plurality of first word lines, the normal data region being configured to store normal data, The second sub-memory bank includes a metadata area connected to a plurality of second word lines, the metadata area being configured to store metadata of the normal data, The plurality of first word lines are matched with the plurality of second word lines to form a plurality of word line pairs, and The first sub-memory bank and the second sub-memory bank share a row hammer region, and the row hammer region stores the number of accesses to the plurality of word line pairs.

2. The memory device according to claim 1, in, The hammer area includes: a plurality of counting units storing the number of accesses to the plurality of word line pairs; and a plurality of counting parity check units, storing counting parity check data corresponding to the plurality of counting units, and The plurality of counting units and the plurality of counting parity check units are arranged in the first sub-memory bank.

3. The memory device according to claim 1, in, The hammer area includes: a plurality of counting units storing the number of accesses to the plurality of word line pairs; and a plurality of counting parity check units, storing counting parity check data corresponding to the plurality of counting units, and The plurality of counting units are arranged in the first sub-memory bank, and the plurality of counting parity check units are arranged in the second sub-memory bank.

4. The memory device according to claim 1, in, The hammer area includes: a plurality of counting units storing the number of accesses to the plurality of word line pairs; and a plurality of counting parity check units, storing counting parity check data corresponding to the plurality of counting units, and The plurality of counting units are arranged in both the first sub-memory bank and the second sub-memory bank, and the plurality of counting parity check units are arranged in the second sub-memory bank.

5. The memory device according to claim 1, wherein: The first sub-bank and the second sub-bank correspond to different global input / output lines.

6. The memory device according to claim 5, wherein: In response to performing a read operation on the normal data stored in the normal data area, The normal data is output through a first global input / output line corresponding to the first sub-bank, and the metadata is output through a second global input / output line corresponding to the second sub-bank simultaneously with the output of the normal data.

7. The memory device according to claim 1, wherein: The normal data region includes a plurality of normal regions, and the plurality of normal regions are respectively connected to the plurality of first word lines; The metadata area includes a plurality of meta areas which are respectively connected to the plurality of second word lines and matched with the plurality of normal areas, and The row hammer region includes a plurality of row count regions that are disposed in the first sub-bank and are respectively connected to the plurality of first word lines.

8. The memory device according to claim 7, wherein: Each of the plurality of normal areas corresponds to a plurality of first column selection lines and a plurality of second column selection lines, and A ratio of the number of the plurality of first column selection lines to the number of the plurality of second column selection lines is 8:

1.

9. The memory device according to claim 7, wherein: Each of the plurality of normal areas corresponds to a plurality of first column selection lines and a plurality of second column selection lines, A ratio of the number of the plurality of first column selection lines to the number of the plurality of second column selection lines is 16:

1.

10. The memory device according to claim 1, wherein: The normal data region includes a plurality of normal regions, and the plurality of normal regions are respectively connected to the plurality of first word lines; The metadata area includes a plurality of meta areas which are respectively connected to the plurality of second word lines and matched with the plurality of normal areas, and The hammer area includes: a plurality of first sub-row counting regions, arranged in the first sub-memory bank and respectively connected to the plurality of first word lines; as well as A plurality of second sub-row counting regions are disposed in the second sub-memory bank and are respectively connected to the plurality of second word lines.

11. The memory device according to claim 1, further comprising: A row hammer management circuit is configured to manage the number of accesses to the plurality of word line pairs, in, The row hammer management circuit is configured to read count data corresponding to a selected word line pair among the plurality of word line pairs from the row hammer region, update the read count data, and re-store the updated count data in the row hammer region in response to activation of the selected word line pair.

12. The memory device according to claim 11, further comprising: The ECC engine is configured to read count parity data corresponding to the count data from the row hammer area and perform a decoding operation on the count data using the count parity data.

13. The memory device according to claim 1, wherein: The first sub-memory bank further includes a metadata area connected to the plurality of first word lines, the metadata area being configured to store metadata, and The second sub memory bank further includes a normal data region connected to the plurality of second word lines, the normal data region being configured to store normal data.

14. A storage device comprising: At least one memory bank, comprising at least a first sub-memory bank and a second sub-memory bank arranged along a word line direction; a first row decoder connected to the first sub-memory bank via a plurality of first word lines; a first column decoder connected to the first sub-memory bank via a plurality of first column selection lines; a second row decoder connected to the second sub-memory bank via a plurality of second word lines; as well as A second column decoder connected to the second sub-memory bank via a plurality of second column selection lines, in, The first sub-memory bank includes a plurality of first memory slices, and the second sub-memory bank includes a plurality of second memory slices, Each of the plurality of first memory slices includes a normal data region connected to a portion of the plurality of first word lines, the normal data region being configured to store normal data, Each of the plurality of second memory slices includes a metadata area connected to a portion of the plurality of second word lines, the metadata area being configured to store metadata corresponding to the normal data, The plurality of first word lines are matched with the plurality of second word lines to form a plurality of word line pairs, and At least one first memory slice among the plurality of first memory slices included in the first sub-memory bank includes one or more counting units configured to store counting data including the number of accesses to the plurality of word line pairs.

15. The memory device according to claim 14, wherein: At least one first memory slice among the plurality of first memory slices included in the first sub-memory bank includes one or more counting parity units configured to store counting parity data of the counting data.

16. The memory device according to claim 14, wherein: A ratio of the number of the counting units to the number of the counting parity check units is 2:

1.

17. The memory device according to claim 14, wherein: At least one second memory slice among the plurality of second memory slices included in the second sub-memory bank includes one or more counting parity units configured to store counting parity data of the counting data.

18. The memory device according to claim 14, wherein: The first sub-bank and the second sub-bank correspond to different global input / output lines.

19. The memory device according to claim 14, wherein: In response to performing a read operation on the normal data stored in the normal data area, The normal data is output through a first global input / output line corresponding to the first sub-bank, and the metadata is output through a second global input / output line corresponding to the second sub-bank simultaneously with the output of the normal data.

20. A memory system comprising: A memory device, comprising at least one memory bank, wherein the at least one memory bank comprises at least a first sub-memory bank and a second sub-memory bank arranged along a word line direction; as well as a memory controller configured to control the memory device, in, The first sub-memory bank includes a normal data region connected to a plurality of first word lines, the normal data region being configured to store normal data, The second sub-memory bank includes a metadata area connected to a plurality of second word lines, the metadata area being configured to store metadata corresponding to the normal data; The plurality of first word lines are matched with the plurality of second word lines to form a plurality of word line pairs, and The first sub-bank and the second sub-bank share a row hammer region configured to store access times to the plurality of word line pairs.

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