Memory, operating method thereof, memory system, and electronic device

Abstract

The embodiment of the invention provides a memory, an operation method of the memory, a memory system and electronic equipment. The memory includes: a memory cell array including: a plurality of memory cells; a peripheral circuit coupled to the memory cell array; the peripheral circuit is configured to: receive at least one set of random data of a time sequence; the time sequence comprises L random events; the random data is used for indicating the current states of the L random events; the L random events are in one-to-one correspondence with the L storage units located in the same row; applying a word line programming pulse to a word line coupled to the L memory cells, and applying a bit line programming pulse to a bit line coupled to a selected memory cell in the L memory cells to write random data into the memory cell corresponding to the random event; determining the correlation degree of the random event according to the threshold voltage distribution of the storage unit; wherein the correlation degree is used for predicting the future state of the random event.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and more particularly to a memory and an operating method thereof, a memory system, and an electronic device. Background Art

[0002] In recent years, the semiconductor integrated circuit industry has experienced rapid development. With the continuous advancement of semiconductor manufacturing technology, the characteristic size of semiconductor devices has continued to shrink, the integration density of memory has become higher and higher, and its performance has become more and more powerful, which can be applied to massive data processing. For example, time correlation detection.

[0003] Time correlation detection is usually based on the traditional von Neumann architecture, that is, the storage and computation separation architecture, which uses memory to store raw data, intermediate data and calculation results, and uses processors to calculate various data. However, the existing time correlation detection has problems such as small input information level, difficulty in detecting a large number of random events, and long time consumption. Summary of the invention

[0004] The present disclosure provides a memory and an operating method thereof, and a memory system.

[0005] In a first aspect, the present disclosure provides a memory, comprising:

[0006] A memory cell array, comprising: a plurality of memory cells arranged in a plurality of rows and a plurality of columns; wherein the memory cells in the same row are coupled to a word line, and the memory cells in the same column are coupled to a bit line;

[0007] A peripheral circuit is coupled to the memory cell array through a plurality of the word lines and a plurality of the bit lines; the peripheral circuit is configured as follows:

[0008] Receive at least one set of random data of a time series; wherein the time series includes L random events, L is an integer greater than 1; the random data is used to indicate the current state of the L random events; each of the L random events corresponds to each of the L storage units in the same row;

[0009] Applying a word line programming pulse to the word lines coupled to the L memory cells, and applying a bit line programming pulse to the bit lines coupled to the selected memory cells among the L memory cells, so as to write the random data into the memory cells corresponding to the random events respectively;

[0010] The correlation degree of the plurality of random events is determined according to the threshold voltage distribution of the storage unit; wherein the correlation degree is used to predict the future states of the L random events.

[0011] In some embodiments, the peripheral circuit is further configured to:

[0012] receiving the time series;

[0013] A set of random data is generated according to the current states of the plurality of random events at a preset time; wherein the random data includes at least one of a first logic value and a second logic value; the current state includes a first current state and a second current state; the first logic value is used to indicate the first current state of a first random event among the plurality of random events at the preset time, and the second logic value is used to indicate the second current state of a second random event among the plurality of random events at the preset time; the second current state is different from the first current state, and the second logic value is different from the first logic value.

[0014] In some embodiments, the peripheral circuit is further configured to:

[0015] Determine the selected storage cell among the L storage cells according to one of the first logic value and the second logic value, and write one of the first logic value and the second logic value into the selected storage cell;

[0016] The unselected memory cells among the L memory cells are determined according to the other of the first logic value and the second logic value, and the other of the first logic value and the second logic value is written into the unselected memory cells.

[0017] In some embodiments, the peripheral circuit is further configured to: determine the number of the bit lines selected within the preset time; wherein the selected bit line is coupled to the selected memory cell among the L memory cells;

[0018] According to the number of the selected bit lines, the pulse width of the word line programming pulse and / or the peak value of the word line programming pulse are adjusted.

[0019] In some embodiments, the memory further comprises:

[0020] A common source line is coupled to a plurality of memory strings in the memory cell array and the peripheral circuit respectively; wherein the memory string comprises a plurality of the memory cells connected in series, and the memory strings in the same column are coupled to one of the bit lines;

[0021] The peripheral circuit is specifically configured to determine the number of the bit lines selected within the preset time according to the current of the common source line.

[0022] In some embodiments, the storage string further includes:

[0023] A top selection transistor coupled between the bit line and a plurality of the memory cells connected in series;

[0024] A bottom selection transistor coupled between the common source line and a plurality of the memory cells connected in series;

[0025] The peripheral circuit is further configured as:

[0026] Applying a word line pass pulse to the gate of the top selection transistor, the gate of the bottom selection transistor, and the plurality of word lines; applying the bit line program pulse to the selected bit line and applying a bit line inhibit program pulse to the unselected bit line; applying the bit line inhibit program pulse to the common source line; wherein the unselected bit line is coupled to the unselected memory cells among the L memory cells;

[0027] A current in the common source line is measured.

[0028] In some embodiments, the storage unit is configured to store M bits of data, and a plurality of the storage units have 2 M threshold voltage intervals, M is a positive integer; the correlation degree includes 2 M relevant levels; wherein said 2 M each of the related levels and the 2 M Each of the threshold voltage intervals in the threshold voltage intervals corresponds one to one;

[0029] The peripheral circuit is also specifically configured as follows:

[0030] According to the threshold voltage interval of the storage unit, a correlation level of the random event corresponding to the storage unit is determined.

[0031] In some embodiments, the 2 M The relevance levels include at least: relevant and non-relevant.

[0032] In some embodiments, the memory includes a flash memory, a phase change memory, or a resistive memory.

[0033] In a second aspect, the present disclosure provides an operating method of a memory, wherein the memory comprises: a memory cell array and a peripheral circuit; the memory cell array comprises: a plurality of memory cells arranged in a plurality of rows and a plurality of columns; wherein the memory cells in the same row are coupled to a word line, and the memory cells in the same column are coupled to a bit line; the peripheral circuit is coupled to the memory cell array through a plurality of the word lines and a plurality of the bit lines; the operating method comprises:

[0034] Receive at least one set of random data of a time series; wherein the time series includes L random events, L is an integer greater than 1; the random data is used to indicate the current state of the L random events; each of the L random events corresponds to each of the L storage units in the same row;

[0035] Applying a word line programming pulse to the word lines coupled to the L memory cells, and applying a bit line programming pulse to the bit lines coupled to the selected memory cells among the L memory cells, so as to write the random data into the memory cells corresponding to the random events respectively;

[0036] The correlation degree of the plurality of random events is determined according to the threshold voltage distribution of the storage unit; wherein the correlation degree is used to predict the future states of the L random events.

[0037] In some embodiments, the operating method further includes:

[0038] receiving the time series;

[0039] A set of random data is generated according to the current states of the plurality of random events at a preset time; wherein the random data includes at least one of a first logic value and a second logic value; the current state includes a first current state and a second current state; the first logic value is used to indicate the first current state of a first random event among the plurality of random events at the preset time, and the second logic value is used to indicate the second current state of a second random event among the plurality of random events at the preset time; the second current state is different from the first current state, and the second logic value is different from the first logic value.

[0040] In some embodiments, the method further comprises:

[0041] Determine the selected storage cell among the L storage cells according to one of the first logic value and the second logic value, and write one of the first logic value and the second logic value into the selected storage cell;

[0042] The unselected memory cells among the L memory cells are determined according to the other of the first logic value and the second logic value, and the other of the first logic value and the second logic value is written into the unselected memory cells.

[0043] In some embodiments, the operating method further includes:

[0044] Determining the number of the bit lines selected within the preset time; wherein the selected bit lines are coupled to the selected memory cells among the L memory cells;

[0045] According to the number of the selected bit lines, the pulse width of the word line programming pulse and / or the peak value of the word line programming pulse are adjusted.

[0046] In some embodiments, the memory further comprises a common source line respectively coupled to a plurality of memory strings in the memory cell array and the peripheral circuit; wherein the memory string comprises a plurality of the memory cells connected in series, and the memory strings in the same column are coupled to one of the bit lines;

[0047] The determining the number of the bit lines selected within the preset time includes:

[0048] The number of the bit lines selected within the preset time is determined according to the current of the common source line.

[0049] In some embodiments, the memory string further includes a top selection transistor and a bottom selection transistor; the top selection transistor is coupled between the bit line and the plurality of memory cells connected in series; the bottom selection transistor is coupled between the common source line and the plurality of memory cells connected in series; the operation method further includes:

[0050] Applying a word line pass pulse to the gate of the top selection transistor, the gate of the bottom selection transistor, and the plurality of word lines; applying the bit line program pulse to the selected bit line and applying a bit line inhibit program pulse to the unselected bit line; applying the bit line inhibit program pulse to the common source line; wherein the unselected bit line is coupled to the unselected memory cells among the L memory cells;

[0051] A current in the common source line is measured.

[0052] In some embodiments, the storage unit is configured to store M bits of data, and a plurality of the storage units have 2 M threshold voltage intervals, M is a positive integer; the correlation degree includes 2 M relevant levels; wherein said 2 M each of the related levels and the 2 M Each of the threshold voltage intervals in the threshold voltage intervals corresponds to each other one by one; the operation method further includes:

[0053] According to the threshold voltage interval of the storage unit, a correlation level of the random event corresponding to the storage unit is determined.

[0054] In some embodiments, the 2 M The relevance levels include at least: relevant and non-relevant.

[0055] In some embodiments, the memory includes a flash memory, a phase change memory, or a resistive memory.

[0056] In a third aspect, the present disclosure provides a memory system, including the memory described in any embodiment of the first aspect;

[0057] A memory controller is coupled to the memory and is configured to control the memory.

[0058] In a fourth aspect, the present disclosure provides an electronic device, comprising the memory system in the above embodiment.

[0059] In the embodiment of the present disclosure, L random events correspond to L storage cells located in the same row, respectively, and the peripheral circuit is configured to apply a word line programming pulse to the word line coupled to the L storage cells, and apply a bit line programming pulse to the bit line coupled to the selected storage cell among the L storage cells, so as to write random data into the corresponding storage cell, and then determine the correlation degree of the random event according to the threshold voltage distribution of the storage cell. In this way, the memory can be used to perform in-memory calculation to realize time correlation detection. On the one hand, the L storage cells corresponding to the L random events in the present disclosure are coupled to the same word line, and the bit line programming pulse is applied to the bit line corresponding to the selected storage cell, so that the random data can be written into the corresponding storage cell at one time, which improves the parallelism of the input, reduces the time of writing random data, and the time correlation detection takes a short time; on the other hand, the number of random events that can be counted in the present disclosure depends on the number of bit lines, and the number of bit lines is significantly higher than the number of word lines, so the input information level is large, and a large number of random events can be detected. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] Figure 1 A schematic diagram of a system with a memory provided in an embodiment of the present disclosure;

[0061] Figure 2a A schematic diagram of a memory card provided by an embodiment of the present disclosure;

[0062] Figure 2b A schematic diagram of a solid state drive (SSD) provided in an embodiment of the present disclosure;

[0063] Figure 3 A schematic diagram of a storage-computing separation architecture provided in an embodiment of the present disclosure;

[0064] Figure 4 A schematic diagram of a time series provided by an embodiment of the present disclosure;

[0065] Figure 5 A schematic diagram of writing random data into a memory cell array provided by an embodiment of the present disclosure;

[0066] Figure 6 A schematic diagram of a memory provided by an embodiment of the present disclosure;

[0067] Figure 7 A schematic diagram of a method for determining a selected storage unit provided by an embodiment of the present disclosure;

[0068] Figure 8 A schematic diagram of detecting the current of a common source line provided by an embodiment of the present disclosure;

[0069] Fig. 9 A schematic diagram of determining a word line programming pulse and using the word line programming pulse to write random data provided by an embodiment of the present disclosure;

[0070] Fig.10 A schematic diagram of a threshold voltage distribution of a memory cell provided in an embodiment of the present disclosure;

[0071] Fig.11 A schematic diagram of a memory system provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0072] In order to facilitate the understanding of the present disclosure, the exemplary embodiments of the present disclosure will be described in more detail below with reference to the relevant drawings. Although the exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0073] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In some embodiments, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of the actual embodiment may not be described here, and well-known functions and structures may not be described in detail.

[0074] Generally, terms can be understood at least in part from their use in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure or characteristic in a singular sense, or can be used to describe a combination of features, structures or characteristics in a plural sense. Similarly, terms such as "one" or "the" can also be understood to convey singular usage or to convey plural usage, depending at least in part on the context. In addition, the term "based on" can be understood to not necessarily be intended to convey an exclusive set of factors, and can alternatively allow for the presence of additional factors that are not necessarily explicitly described, which also depends at least in part on the context.

[0075] Unless otherwise defined, the purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates another way. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0076] In order to thoroughly understand the present disclosure, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present disclosure. The preferred embodiments of the present disclosure are described in detail below, but in addition to these detailed descriptions, the present disclosure may also have other implementations.

[0077] Figure 1 A schematic diagram of a system 100 having a memory according to some aspects of the present disclosure is shown. The system 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory therein.

[0078] like Figure 1As shown in , system 100 may include a host 108 and a memory system 102, the memory system 102 having one or more memories 104 and a memory controller 106. The host 108 may be a processor (e.g., a central processing unit (CPU) or a system on chip (SoC) (e.g., an application processor (AP)) of an electronic device. The host 108 may be configured to send data to the memory 104 or receive data from the memory 104.

[0079] According to some embodiments, the memory controller 106 is coupled to the memory 104 and the host 108 and is configured to control the memory 104. The memory controller 106 can manage data stored in the memory 104 and communicate with the host 108. In some embodiments, the memory controller 106 is designed to operate in a low duty cycle environment, such as a Secure Digital Memory Card (SD Card), a Compact Flash Card (CFCard), a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 106 is designed to operate in a high duty cycle environment solid state drive or embedded Multi Media Card (eMMC), which is used as a data storage for mobile devices such as smart phones, tablet computers, laptop computers, etc. and enterprise storage arrays.

[0080] The memory controller 106 may be configured to control operations of the memory 104, such as read, erase, and write (also known as programming) operations. The memory controller 106 may also be configured to manage various functions regarding data stored or to be stored in the memory 104, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction codes (ECC) regarding data read from or written to the memory 104. The memory controller 106 may also perform any other suitable functions, such as formatting the memory 104. The memory controller 106 may communicate with a host (e.g., the host 108) according to a specific communication protocol. For example, the memory controller 106 can communicate with the host 108 through at least one of various interface protocols, such as USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI Express (PCIE) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer System Interface (SCSI) protocol, Enhanced System Device Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, Firewire protocol, etc.

[0081] The memory controller 106 and the one or more memories 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a universal flash storage package or an eMMC package). That is, the memory system 102 can be implemented and packaged into different types of terminal electronic products. Figure 2aIn one example shown in , the memory controller 106 and the single memory 104 can be integrated into a memory card 202. The memory card 202 may include a PC card (Personal Computer Memory Card International Association, PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (Smart Media, SM) card, a memory stick, a Multi Media Card (Multi Media Card, MMC), a Reduced-Size MMC (RS-MMC), a Micro Multi Media Card (Multi Media Card Micro, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a Universal Flash Storage (Univeral Flash Storage, UFS), etc. The memory card 202 may also include a method for connecting the memory card 202 to a host (e.g., Figure 1 The memory card connector 204 is coupled to the host 108 in the embodiment. Figure 2b In another example shown in , the memory controller 106 and the plurality of memories 104 may be integrated into the SSD 206. The SSD 206 may also include a processor that interfaces the SSD 206 with a host (e.g., Figure 1 In some implementations, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0082] In an embodiment of the present disclosure, each of the memory chips (Die) may include one or more memory cell arrays. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cells (MLC), tri-level cells (TLC), quad-level cells (QLC), and penta-level cells (PLC) may store multiple bits per cell. In some embodiments, each of the memories may include one or more memory cell arrays, such as an SLC array, an MLC array, a TLC array, a QLC array, or any combination of such memory cell arrays.

[0083] Figure 3A schematic diagram of time correlation detection using a storage-computation separation architecture (i.e., von Neumann architecture) provided for an embodiment of the present disclosure. In the von Neumann architecture, computing and storage are separated, and the processor 11 includes but is not limited to a central processing unit in a host, a field programmable gate array (FPGA), etc., and the memory 12 includes but is not limited to SSD, eMMC, UFS, etc. The processor 11 can obtain at least one set of random data of a time series from the memory 12, and the time series includes multiple random events, and each set of random data is used to indicate the current state of multiple random events at a time (or time period). Next, the logic circuit in the processor 12 can perform a covariance matrix operation, thereby calculating the degree of correlation of each random event by a mathematical method, wherein the degree of correlation can be used to predict the future state of the random event.

[0084] For example, Figure 4 A schematic diagram of a time series provided by an embodiment of the present disclosure. The time series includes K random events (respectively denoted as X1 to X2). K ), T1 to T N Represents N different moments (or time periods), where N and K are both positive integers. The occurrence of a random event at a moment (or time period) is represented by a black square, and the non-occurrence of a random event at a moment (or time period) is represented by a white square. The "occurrence" and "non-occurrence" here are the "current state" of the above-mentioned random events. The processor can obtain N groups of random data of the time series from the memory, and then obtain the covariance matrix through logical operations, and finally generate the correlation degree distribution of K random events, wherein multiple random events with a correlation degree of "correlated" tend to occur at the same time or not occur at the same time, while multiple random events with a correlation degree of "non-correlated" occur or do not occur without correlation. In this way, the future state of multiple random events can be predicted.

[0085] Time series exist in various fields, such as sales records of goods on e-commerce platforms, stock data in financial markets, and monitoring performance indicators of Internet companies. With the advent of the big data era, the scale of time series is also increasing. Detecting time series can reveal the inherent laws of movement, change, and development of things. Time correlation detection can be used to filter out relevant information in massive random data streams (not limited to image information, but any random data).

[0086] However, when processing random data in temporal correlation detection, data is transferred back and forth between the processor and the memory through a serial bus, which causes additional delays and power consumption due to the von Neumann bottleneck. Moreover, the steps of covariance matrix calculation by the processor are complicated and computationally intensive, resulting in low computational efficiency.

[0087] Therefore, the present disclosure provides a memory, and uses the memory to perform in-memory computing to achieve time correlation detection. In-memory computing uses the characteristics of the storage unit itself in the memory to perform computing processing on a specific task, thereby breaking through the bottleneck of the traditional von Neumann architecture, reducing delay and power consumption and improving computing efficiency. The following is an example of NAND memory.

[0088] The peripheral circuit in the memory can receive at least one group of random data of the time series, wherein each group of random data is used to indicate the current state of multiple random events at a moment (or time period), and the time series can include multiple moments (or time periods), that is, there are multiple groups of random data. The current state of each random event at a moment (or time period) can correspond to one bit in a group of random data. Exemplarily, the current states of random events X1 to X5 at T1 are respectively "occurrence, no occurrence, no occurrence, occurrence, occurrence", and the corresponding random data can be "10011". It should be noted that in the present disclosure, "occurrence" can correspond to a logical value "1", "no occurrence" corresponds to a logical value "0", or "occurrence" corresponds to a logical value "0", and "no occurrence" corresponds to a logical value "1", which is not limited here.

[0089] Next, the peripheral circuit writes at least one set of random data into the plurality of storage cells respectively. Figure 5 Schematic diagram of writing a set of random data corresponding to the current state of multiple random events at time T1 (or time period) into a storage cell array. Figure 5 The memory cells in the same row are coupled to a word line, and the memory cells in the same column are coupled to a bit line ( Figure 5 Only one bit line is shown in the figure). The memory cell array also includes a plurality of memory strings (String), one memory string includes a plurality of memory cells connected in series, and the memory strings in the same column are coupled to a bit line. Each memory string also includes a top selection transistor coupled between the plurality of memory cells connected in series and the bit line, and a bottom selection transistor coupled between the plurality of memory cells connected in series and a common source line (Array Common Source, ACS), the gate of the top selection transistor is called the top selection gate (Top Selected Gate, TSG), and the gate of the bottom selection transistor is called the bottom selection gate (Bottom Selected Gate, BSG). By applying a certain voltage to the corresponding word line, bit line, top selection gate, bottom selection gate, and common source line, operations such as writing, reading, or erasing can be performed on the selected memory cell.

[0090] Exemplarily, if "1" is written to a memory cell, a write operation is performed on the memory cell; if "0" is written to the memory cell, no write operation is performed on the memory cell (the reverse is also possible and is not limited here). It should be noted that each time a write operation is performed on a memory cell, the charge in the channel will tunnel into the charge trapping layer of the memory cell and accumulate continuously, thereby increasing the threshold voltage (Threshold Voltage, Vt) of the memory cell. For phase change memory and resistive memory, the write operation will cause the resistance value of the memory cell to change.

[0091] refer to Figure 5 The time series includes (Q×P) random events arranged in Q rows and P columns, where Q and P are both integers greater than 1; Q word lines WL1 to WL Q and the top selection gates TSG1 to TSG2 of the P top selection transistors. P (Q×P) memory cells are defined, and the (Q×P) random events correspond to the (Q×P) memory cells one by one. In this way, the peripheral circuit applies a word line programming pulse to the selected word line and applies a pass pulse to the top selection gate of the selected top selection transistor, thereby performing a write operation on the selected memory cell (i.e., writing "1" in the random data into the selected memory cell), wherein the selected word line and the selected top selection transistor are coupled to the selected memory cell among the (Q×P) memory cells.

[0092] Repeat the above writing operation, the peripheral circuit will change T1 to T N N groups of random data corresponding to a time (or time period) are written into the memory cell array N times. In this way, the threshold voltages of (Q×P) memory cells are distributed in different intervals. For example, the threshold voltages of memory cells corresponding to multiple random events that tend to occur at the same time (i.e., multiple related random events) will be significantly higher than other memory cells after multiple write operations.

[0093] Finally, the peripheral circuit determines the correlation degree of (Q×P) random events as "correlated" or "uncorrelated" according to the threshold voltage distribution of (Q×P) storage cells. Here, the correlation degree can be used to predict the future state of each random event, for example, multiple "correlated" random events are more likely to occur at the same time (or not occur at the same time) in the future. It can be understood that the correlation degree here can also be used to predict random events with opposite tendencies, such as if random event X1 occurs, random event X2 tends not to occur.

[0094] The above embodiment determines the selected memory cells, that is, which memory cells need to be written, by the combination of word lines and top selection transistors. However, a write operation can only apply a word line programming pulse to one word line. As the number of word line stacking layers in the three-dimensional memory continues to increase, multiple selected memory cells corresponding to multiple logical values ​​"1" in a set of random data may be coupled with multiple selected word lines respectively, which causes multiple write operations to be required to write a set of random data, and ultimately leads to an increase in the time consumption of time correlation detection. In addition, the scale of input random data (that is, the number of random events) is limited by the number of word line stacking layers and the number of top selection transistors, and can only be in the order of hundreds, and it is impossible to perform time correlation detection on a large number of random events. Furthermore, time correlation detection needs to determine the pulse width and / or peak value of the word line programming pulse according to the number of random events that occur each time, but the above-mentioned method of performing write operations by combining word lines and top selection transistors is difficult to count the number of selected memory cells.

[0095] Based on this, in order to solve one or more of the above technical problems, an embodiment of the present disclosure provides a memory.

[0096] like Figure 6 As shown, the present disclosure provides a memory 200, including:

[0097] The memory cell array 210 includes: a plurality of memory cells arranged in a plurality of rows and a plurality of columns; wherein the memory cells in the same row are coupled to a word line WL, and the memory cells in the same column are coupled to a bit line BL;

[0098] The peripheral circuit 220 is coupled to the memory cell array 210 through a plurality of the word lines WL and a plurality of the bit lines BL; the peripheral circuit 220 is configured as follows:

[0099] Receive at least one set of random data of a time series; wherein the time series includes L random events, L is an integer greater than 1; the random data is used to indicate the current state of the L random events; each of the L random events corresponds to each of the L storage units in the same row;

[0100] Applying a word line programming pulse to the word line WL coupled to the L memory cells, and applying a bit line programming pulse to the bit line BL coupled to a selected memory cell among the L memory cells, so as to write the random data into the memory cells corresponding to the random events respectively;

[0101] The correlation degree of the plurality of random events is determined according to the threshold voltage distribution of the storage unit; wherein the correlation degree is used to predict the future states of the L random events.

[0102] In some embodiments, the memory 200 includes a flash memory, a phase change memory, or a resistive memory.

[0103] In the embodiment of the present disclosure, the memory 200 includes, but is not limited to, any memory in which the electrical parameters of any memory cell continuously change, such as a flash memory, a phase change memory (PCM), a resistive random access memory (RRAM), etc. The memory 200 includes a memory cell array 210 and a peripheral circuit 220 for controlling the memory cell array 210 to perform various operations. The memory cell array 210 includes a plurality of memory cells arranged in an array.

[0104] The following description will be made by taking the memory 200 as a NAND type memory in a flash memory as an example. The peripheral circuit 220 is coupled to the memory cell array 210 through a plurality of word lines and a plurality of bit lines, the memory cells in the same row are coupled to a word line, and the memory cells in the same column are coupled to a bit line. Exemplarily, if "1" is written to a memory cell, a write operation is performed on the memory cell; if "0" is written to the memory cell, no write operation is performed on the memory cell. Each time a write operation is performed on a memory cell, the charge in the channel will tunnel into the charge trapping layer of the memory cell and accumulate continuously, thereby increasing the threshold voltage of the memory cell. For phase change memory and resistive memory, the write operation will cause the resistance value of the memory cell to change.

[0105] The peripheral circuit 220 may receive at least one set of random data in a time series, each set of random data being used to indicate the current state of multiple random events at a time (or time period), where the time series may include multiple time periods (or time periods), that is, there are multiple sets of random data. For example, the time series includes L random events (respectively denoted as X1 to X2). L ), T1 to T N Represents N different moments (or time periods). N and L are both positive integers. The occurrence of a random event at a moment (or time period) is represented by a black square, and the non-occurrence of a random event at a moment (or time period) is represented by a white square, where "occurrence" and "non-occurrence" are the "current state" of the above-mentioned random event. Each random event can correspond to one bit in a group of random data. Exemplarily, the current states of random events X1 to X5 at T1 are "occurrence, non-occurrence, non-occurrence, occurrence, occurrence", respectively, and the corresponding random data can be "10011". It should be noted that in the present disclosure, "occurrence" can correspond to a logical value "1", "non-occurrence" can correspond to a logical value "0", or "occurrence" can correspond to a logical value "0", and "non-occurrence" can correspond to a logical value "1", which is not limited here.

[0106] Each of the L random events corresponds one-to-one to each of the L storage cells in the same row. Figure 6 The memory cell array 210 includes i rows and j columns of memory cells, that is, there are i word lines WL1-WL2. i , and j bit lines BL1~BL j The L storage cells corresponding to the L random events may be located in a row of storage cells coupled to the word line WL2, that is, j≥L. For ease of understanding, the following description is made by taking j=L as an example.

[0107] Next, the peripheral circuit 220 writes at least one set of random data into the plurality of storage cells. Specifically, the peripheral circuit 220 applies a word line programming pulse to the word line WL2 coupled to the L storage cells, where the peak value of the word line programming pulse is V pgm , and apply a bit line programming pulse to the bit line BL coupled to the selected memory cell among the L memory cells, where the bit line programming pulse can be a constant voltage, and its voltage value can be 0V (i.e., the ground voltage GND), so as to perform a write operation on the selected memory cell (i.e., write the logic value "1" in the random data into the selected memory cell).

[0108] Exemplarily, the peripheral circuit 220 writes a set of random data corresponding to the L random events at time T4 (or time period) into the corresponding L storage cells in a row of storage cells coupled to the word line WL2. j-2 and X j The current state is "occurrence", random events X1, X2 and X j-1 The current state is "not occurred". At this time, a word line programming pulse is applied to word line WL2, and a word line programming pulse is applied to bit lines BL3 and BL j-2 and BL j Apply bit line programming pulses to bit lines BL1, BL2 and BL j-1 Apply bit line inhibit programming pulse (peak value is V dd , such as 2.2V), thereby the selected memory cell C 23 , C 2(j-2) and C 2j Perform a write operation, that is, write a logical value "1" and write the unselected storage cell C 21 , C 22 and C 2(j-1) No write operation is performed, that is, a logical value "0" is written.

[0109] That is, here only one word line WL2 and the bit lines BL3, BL4 and BL6 of the L bit lines coupled to the selected memory cell are used. j-2 and BL j, determine the selected storage cell, so writing a group of random data only requires applying a word line programming pulse to one word line, that is, writing a group of random data only requires one write operation, which makes the time correlation detection time-consuming shorter.

[0110] Repeat the above writing operation, the peripheral circuit 220 changes T1 to T N N groups of random data corresponding to a time (or time period) are written into the memory cell array N times. In this way, the threshold voltages of L memory cells are distributed in different intervals. For example, the threshold voltage of a memory cell corresponding to multiple random events that tend to occur at the same time (i.e., multiple related random events) will be significantly higher than that of other memory cells after multiple write operations.

[0111] Finally, the peripheral circuit determines the correlation degree of the L random events as "correlated" or "uncorrelated" according to the threshold voltage distribution of the L storage cells. Here, the correlation degree can be used to predict the future state of each random event, for example, multiple "correlated" random events are more likely to occur at the same time in the future. It is understandable that the correlation degree here can also be used to predict random events with opposite tendencies, such as if random event X1 occurs, random event X2 tends not to occur.

[0112] Figure 7 A schematic diagram showing the difference between determining a selected memory cell by a combination of multiple word lines and multiple top selection transistors and determining a selected memory cell by a single word line and multiple bit lines, wherein black squares represent selected memory cells and white squares represent unselected memory cells. It can be understood that Figure 7 The combination of multiple word lines and multiple top selection transistors on the left side determines the selected storage cell (i.e., two-dimensional information input), and word line programming pulses need to be applied to the multiple word lines multiple times, so it takes a long time; while the selected storage cell on the right side is determined by one word line and multiple bit lines (i.e., one-dimensional information input), and only a word line programming pulse needs to be applied to one word line to write a group of random data from the bit line end at one time, so it takes less time.

[0113] In this way, on the one hand, the L storage cells corresponding to the L random events in the present disclosure are coupled to the same word line, and a bit line programming pulse is applied to the bit line corresponding to the selected storage cell, so that the random data can be written into the corresponding storage cell at one time, thereby improving the parallelism of the input, reducing the time for writing random data, and shortening the time consumption for time correlation detection; on the other hand, the number of random events that can be counted in the present disclosure depends on the number of bit lines, and the number of bit lines is significantly higher than the number of word lines, so the input information magnitude is large, and a large number of random events can be detected.

[0114] In some embodiments, the peripheral circuit 220 is further configured to:

[0115] receiving the time series;

[0116] A set of random data is generated according to the current states of the plurality of random events at a preset time; wherein the random data includes at least one of a first logic value and a second logic value; the current state includes a first current state and a second current state; the first logic value is used to indicate the first current state of a first random event among the plurality of random events at the preset time, and the second logic value is used to indicate the second current state of a second random event among the plurality of random events at the preset time; the second current state is different from the first current state, and the second logic value is different from the first logic value.

[0117] In the embodiments of the present disclosure, the preset time may be any moment or time period in the above embodiments, and the time sequence may include multiple different preset times. Figure 6 As shown, the time series includes N preset times T1 to T N In this way, the peripheral circuit generates a corresponding set of random data according to the current states of L random events in a preset time. That is to say, when the current states of multiple random events at N preset times are obtained by statistics, the time series can correspond to N sets of random data.

[0118] The current state may include a first current state and a second current state, such as "occurrence" and "not occurrence" in the above embodiments. It is worth noting that the current state in the present disclosure may also refer to other states of random events, such as if the random event is "a user of an e-commerce platform purchases a beverage", the first current state is "purchase of carbonated beverage", and the second current state is "purchase of non-carbonated beverage". The present disclosure does not impose too many restrictions on the types of "random events" and "current state". For ease of understanding, the following is explained using the first logical value of "1" and the second logical value of "0" as an example, but this is not used as a limitation, that is, the first logical value may be "0" and the second logical value may be "1".

[0119] The peripheral circuit can generate a first logic value according to the first current state of the first random event in the L random events at the preset time. For example, the peripheral circuit generates a first logic value "1" according to the occurrence of the first random events X1, X4, and X5 at the preset time T1, and generates a second logic value "0" according to the non-occurrence of the second random events X2 and X3 at the preset time T1. At this time, the random data generated by the peripheral circuit according to the random events X1 to X5 is "10011". That is to say, the L random events may include several first random events in the first current state and several second random events in the second current state at the preset time T1. It is understandable that in a preset time, there may be only the first random event in the first current state, or only the second random event in the second current state. Exemplarily, the L random events X1 to X3 may be in the first current state. L All of the random events X1 to X1 occur at the preset time T1. L All of them are first random events. At this time, a group of random data generated by the peripheral circuit contains only the first logic value "1", that is, the group of random data includes K first logic values ​​"1".

[0120] In some embodiments, the peripheral circuit is further configured to:

[0121] Determine the selected storage cell among the L storage cells according to one of the first logic value and the second logic value, and write one of the first logic value and the second logic value into the selected storage cell;

[0122] The unselected memory cells among the L memory cells are determined according to the other of the first logic value and the second logic value, and the other of the first logic value and the second logic value is written into the unselected memory cells.

[0123] In the disclosed embodiment, the peripheral circuit can determine the selected storage cell according to the first logic value "1" in a set of random data, determine the unselected storage cell according to the second logic value "0", write the first logic value "1" to the selected storage cell, and write the second logic value "0" to the unselected storage cell. Conversely, the peripheral circuit can also determine the unselected storage cell according to the first logic value "1" in a set of random data, determine the selected storage cell according to the second logic value "0", write the first logic value "1" to the unselected storage cell, and write the second logic value "0" to the selected storage cell. In this way, it is possible to more flexibly choose to correspond the "occurrence" of a random event to writing "1" in a selected storage cell, or correspond the "occurrence" of a random event to writing "0" in a selected storage cell, so as to meet different detection requirements.

[0124] In some embodiments, the peripheral circuit is further configured to: determine the number of the bit lines selected within the preset time; wherein the selected bit line is coupled to the selected memory cell among the L memory cells;

[0125] According to the number of the selected bit lines, the pulse width of the word line programming pulse and / or the peak value of the word line programming pulse are adjusted.

[0126] In the embodiment of the present disclosure, since the selected memory cell is determined by a word line and a plurality of bit lines, a selected memory cell corresponds to a selected bit line respectively. For example, Figure 6 As shown, the selected memory cell C 23 , C 2(j-2) and C 2j Corresponding to the selected bit lines BL3, BL j-2 and BL j In this way, the peripheral circuit can determine the number of bit lines selected within a preset time (ie, the number of selected memory cells), and adjust the pulse width and / or peak value of the word line programming pulse according to the number of selected bit lines.

[0127] For example, if there are m first random events (1≤m≤L) in the first current state ("occurrence") at the preset time T1, the number of first logic values ​​"1" in the group of random data is m, the number of selected storage cells to which the first logic value "1" needs to be written is m, and the number of selected bit lines is also m. In this way, the peripheral circuit can determine the pulse width of the word line programming pulse and / or the peak value of the word line programming pulse according to the number of selected bit lines m.

[0128] It should be noted that the larger m is, the larger the pulse width and / or the peak value of the word line programming pulse is, and the more the threshold voltage of the selected memory cell increases. This means that the more random events tend to occur simultaneously in a preset time, the stronger the correlation between these random events is, and therefore a larger magnitude of write operations is required, so that the threshold voltages of the memory cells corresponding to "related" and "unrelated" random events can be distinguished to form different threshold voltage distribution areas.

[0129] In this way, the more random events that are in the first current state (or in the second current state) within a preset time, the more the number of selected storage cells (selected bit lines) that need to write the first logic value (or the second logic value) when writing the group of random data, the larger the pulse width and / or peak value of the word line programming pulse, thereby accelerating the rate of the write operation; on the contrary, if the fewer random events that are in the first current state (or in the second current state) within a preset time, the fewer the number of selected storage cells (selected bit lines) that need to write the first logic value (or the second logic value) when writing the group of random data, the smaller the pulse width and / or peak value of the word line programming pulse, thereby reducing the power consumption of the memory. It can be understood that the embodiment of the present disclosure can accurately adjust the pulse width and / or peak value of each word line programming pulse according to the number of selected bit lines, so as to meet the pulse required for the write operation and greatly reduce the power consumption.

[0130] In some embodiments, Figure 8 As shown, the memory also includes:

[0131] A common source line ACS is coupled to a plurality of memory strings 211 in the memory cell array 210 and the peripheral circuit respectively; wherein the memory string 211 includes a plurality of memory cells connected in series, and the memory strings 211 in the same column are coupled to one bit line;

[0132] The peripheral circuit is specifically configured as follows: according to the current I of the common source line ACS ACS , determining the number of the bit lines selected within the preset time.

[0133] In the embodiments of the present disclosure, reference Figure 8 The memory also includes a common source line ACS, and each memory string 211 in the memory cell array 210 is coupled to the common source line ACS. For ease of understanding, Figure 8 Only one memory string 211 coupled to each bit line BL is shown. Actually, the memory cell array 210 may be three-dimensional, and each bit line is coupled to a plurality of memory strings 211 located in the same column.

[0134] Thus, before applying a word line programming pulse to the word line WL2 coupled to the L memory cells, the number of selected bit lines (i.e., the number of selected memory cells) can be determined by counting the number of turned-on memory strings 211. Specifically, a certain pass voltage is applied to all word lines, the top selection gate TSG, and the bottom selection gate BSG, so that all memory cells, the top selection transistor 212, and the bottom selection transistor 213 are turned on, and then a certain voltage (such as V dd ), the unselected bit lines are applied with the same voltage as the common source line (such as Vdd ), the selected bit line applies a voltage different from the common source line (such as 0V). In this way, only the memory string 211 where the selected memory cell is located will have current flowing through it. By detecting the total current I on the common source line ACS ACS , the number of bit lines selected within a preset time (ie, the number of selected memory cells) can be determined. It can be understood that the current I of the common source line ACS is ACS Proportional to the number of bit lines selected.

[0135] In some embodiments, Figure 8 and Fig. 9 As shown, the storage string 211 also includes:

[0136] A top selection transistor 212 coupled between the bit line BL and a plurality of the memory cells connected in series;

[0137] A bottom selection transistor 213, coupled between the common source line ACS and a plurality of the memory cells connected in series;

[0138] The peripheral circuit is further configured as:

[0139] Applying a word line pass pulse to the gate of the top selection transistor 212, the gate of the bottom selection transistor 213, and the plurality of word lines; applying the bit line programming pulse to the selected bit line and applying a bit line inhibit programming pulse to the unselected bit line; applying the bit line inhibit programming pulse to the common source line ACS; wherein the unselected bit line is coupled to the unselected memory cell among the L memory cells;

[0140] Measure the current I of the common source line ACS ACS .

[0141] In the embodiment of the present disclosure, the current of the common source line ACS can be measured in the first stage to obtain the current I of the common source line ACS. ACS Determine the number of selected bit lines, and determine the pulse width T of the word line programming pulse according to the number of selected bit lines pgm and / or the peak value of the word line programming pulse V pgm ; Then in the second stage, a word line programming pulse is used to write the first logic value "1" (or the second logic value "0") in the random data into the selected memory cell.

[0142] Specifically, refer to Fig. 9 In the first stage, the top select gate TSG, the bottom select gate BSG, and the selected word line WL sel , unselected word line WL unsel Apply word line pass pulse (peak value is V pass_r), so that all memory cells, top selection transistors and bottom selection transistors are turned on; and the selected bit line BL sel Apply a bit line programming pulse (ground voltage GND) to the unselected bit lines BL unsel Apply bit line inhibit programming pulse (peak value is V dd ), a bit line inhibit programming pulse (peak value is V dd ). In this way, by measuring the current I of the common source line ACS ACS , the number of selected bit lines can be determined, thereby determining the pulse width T of the word line programming pulse pgm and / or the peak value of the word line programming pulse V pgm .

[0143] In the second stage, the selected bit line BL sel , unselected bit line BL unsel The bit line programming pulse and the bit line inhibit programming pulse are still applied respectively; the top selection gate TSG and the unselected word line WL unsel Apply a word line programming pulse (peak value is V pass_p , V pass_p >V pass_r ); On the selected word line WL sel A word line programming pulse is applied to the bottom selection gate BSG and the common source line ACS, thereby writing the first logic value (or the second logic value) into the selected memory cell using the word line programming pulse.

[0144] It is understandable that the embodiments of the present disclosure can accurately adjust the pulse width and / or peak value of each word line programming pulse according to the number of selected bit lines, thereby meeting the pulse required for the write operation and greatly reducing power consumption.

[0145] In some embodiments, the storage unit is configured to store M bits of data, and a plurality of the storage units have 2 M threshold voltage intervals, M is a positive integer; the correlation degree includes 2 M relevant levels; wherein said 2 M each of the related levels and the 2 M Each of the threshold voltage intervals in the threshold voltage intervals corresponds one to one;

[0146] The peripheral circuit is also specifically configured as follows:

[0147] According to the threshold voltage interval of the storage unit, a correlation level of the random event corresponding to the storage unit is determined.

[0148] In the embodiment of the present disclosure, the memory 200 may be a NAND type memory, and the types of storage units include SLC, MLC, TLC, etc.

[0149] For example, Fig.10 As shown, an SLC type storage cell can store 1 bit of data, and the storage cell can have 2 threshold voltage intervals, corresponding to 2 storage states with logical values ​​of "0" and "1", respectively. After writing multiple groups of random data into the storage cell array, the threshold voltages of multiple storage cells have 2 distribution intervals, where each distribution interval corresponds to a correlation level, that is, the correlation degree of multiple random events can be divided into 2 correlation levels, such as the first threshold voltage interval corresponds to "non-correlation" and the second threshold voltage interval corresponds to "correlation". In this way, correlation detection of multiple random events can be achieved.

[0150] For example, Fig.10 As shown, an MLC type storage cell can store 2 bits of data, and the storage cell can have 4 threshold voltage intervals, corresponding to 4 storage states with logic values ​​of "11", "10", "01", and "00". After writing multiple sets of random data into the storage cell array, the threshold voltages of multiple storage cells have 4 distribution intervals, each of which corresponds to a correlation level. That is to say, the correlation degree of multiple random events can be divided into 4 correlation levels, such as the first threshold voltage interval corresponds to "non-correlation", the second threshold voltage interval corresponds to "low correlation", the third threshold voltage interval corresponds to "moderate correlation", and the fourth threshold voltage interval corresponds to "high correlation".

[0151] By analogy, the threshold voltage of a TLC type storage cell has 8 distribution intervals, and the 8 distribution intervals correspond to different degrees of correlation levels; the threshold voltage of a QLC type storage cell has 16 distribution intervals, and the 16 distribution intervals correspond to different degrees of correlation levels; in this way, a more refined time correlation detection can be performed on multiple random events in a time series, thereby producing more accurate correlation analysis results.

[0152] In some embodiments, the 2 M The relevance levels include at least: relevant and non-relevant.

[0153] The present disclosure provides an operating method of a memory, wherein the memory comprises: a memory cell array and a peripheral circuit; the memory cell array comprises: a plurality of memory cells arranged in a plurality of rows and a plurality of columns; wherein the memory cells in the same row are coupled to a word line, and the memory cells in the same column are coupled to a bit line; the peripheral circuit is coupled to the memory cell array through a plurality of the word lines and a plurality of the bit lines; the operating method comprises:

[0154] Receive at least one set of random data of a time series; wherein the time series includes L random events, L is an integer greater than 1; the random data is used to indicate the current state of the L random events; each of the L random events corresponds to each of the L storage units in the same row;

[0155] Applying a word line programming pulse to the word lines coupled to the L memory cells, and applying a bit line programming pulse to the bit lines coupled to the selected memory cells among the L memory cells, so as to write the random data into the memory cells corresponding to the random events respectively;

[0156] The correlation degree of the plurality of random events is determined according to the threshold voltage distribution of the storage unit; wherein the correlation degree is used to predict the future states of the L random events.

[0157] In some embodiments, the operating method further includes:

[0158] receiving the time series;

[0159] A set of random data is generated according to the current states of the plurality of random events at a preset time; wherein the random data includes at least one of a first logic value and a second logic value; the current state includes a first current state and a second current state; the first logic value is used to indicate the first current state of a first random event among the plurality of random events at the preset time, and the second logic value is used to indicate the second current state of a second random event among the plurality of random events at the preset time; the second current state is different from the first current state, and the second logic value is different from the first logic value.

[0160] In some embodiments, the method further comprises:

[0161] Determine the selected storage cell among the L storage cells according to one of the first logic value and the second logic value, and write one of the first logic value and the second logic value into the selected storage cell;

[0162] The unselected memory cells among the L memory cells are determined according to the other of the first logic value and the second logic value, and the other of the first logic value and the second logic value is written into the unselected memory cells.

[0163] In some embodiments, the operating method further includes:

[0164] Determining the number of the bit lines selected within the preset time; wherein the selected bit lines are coupled to the selected memory cells among the L memory cells;

[0165] According to the number of the selected bit lines, the pulse width of the word line programming pulse and / or the peak value of the word line programming pulse are adjusted.

[0166] In some embodiments, the memory further comprises a common source line respectively coupled to a plurality of memory strings in the memory cell array and the peripheral circuit; wherein the memory string comprises a plurality of the memory cells connected in series, and the memory strings in the same column are coupled to one of the bit lines;

[0167] The determining the number of the bit lines selected within the preset time includes:

[0168] The number of the bit lines selected within the preset time is determined according to the current of the common source line.

[0169] In some embodiments, the memory string further includes a top selection transistor and a bottom selection transistor; the top selection transistor is coupled between the bit line and the plurality of memory cells connected in series; the bottom selection transistor is coupled between the common source line and the plurality of memory cells connected in series; the operation method further includes:

[0170] Applying a word line pass pulse to the gate of the top selection transistor, the gate of the bottom selection transistor, and the plurality of word lines; applying the bit line program pulse to the selected bit line and applying a bit line inhibit program pulse to the unselected bit line; applying the bit line inhibit program pulse to the common source line; wherein the unselected bit line is coupled to the unselected memory cells among the L memory cells;

[0171] A current in the common source line is measured.

[0172] In some embodiments, the storage unit is configured to store M bits of data, and a plurality of the storage units have 2 M threshold voltage intervals, M is a positive integer; the correlation degree includes 2 M relevant levels; wherein the 2 M each of the related levels and the 2M Each of the threshold voltage intervals in the threshold voltage intervals corresponds to each other one by one; the operation method further includes:

[0173] According to the threshold voltage interval of the storage unit, a correlation level of the random event corresponding to the storage unit is determined.

[0174] In some embodiments, the 2 M The relevance levels include at least: relevant and non-relevant.

[0175] In some embodiments, the memory includes a flash memory, a phase change memory, or a resistive memory.

[0176] The present disclosure provides a memory system 20, such as Fig.11 As shown, it includes the memory 200 described in any of the above embodiments;

[0177] The memory controller 300 is coupled to the memory 200 and is configured to control the memory 200 .

[0178] The memory system 20 may correspond to Figure 1 The memory system 102 and the memory 200 in the embodiment shown may correspond to the reference Figure 1 The memory 104 in the embodiment shown in FIG. 1 and the memory controller 300 may correspond to the memory 104 in the embodiment shown in FIG. Figure 1 The memory controller 106 in the illustrated embodiment will not be further described herein with respect to the functions, applications and interaction between the memory 200 and the memory controller 300 .

[0179] The present disclosure provides an electronic device, comprising the memory system in the above embodiment.

[0180] The present disclosure utilizes a memory to perform in-memory calculations to achieve time correlation detection. On the one hand, in the present disclosure, L storage cells corresponding to L random events are coupled to the same word line, and a bit line programming pulse is applied to the bit line corresponding to the selected storage cell, so that random data can be written into the corresponding storage cell at one time, thereby improving the parallelism of input, reducing the time of writing random data, and the time-consuming time of time correlation detection is relatively short; on the other hand, the number of random events that can be counted in the present disclosure depends on the number of bit lines, and the number of bit lines is significantly higher than the number of word lines, so the input information level is relatively large, and a large number of random events can be detected; on the other hand, the number of selected bit lines (i.e., the number of selected storage cells) can be quickly counted by applying pressure to the common source line ACS end, thereby accurately regulating the pulse width and / or peak value of the word line programming pulse used in the subsequent write operation, while meeting the pulse required for the write operation, and greatly reducing power consumption.

[0181] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial number of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0182] The above description is only a preferred embodiment of the present disclosure, and does not limit the patent scope of the present disclosure. All equivalent structural changes made by using the contents of the present disclosure and the drawings under the inventive concept of the present disclosure, or directly / indirectly applied in other related technical fields are included in the patent protection scope of the present disclosure.

Claims

1. A memory, characterized in that: include: A memory cell array, comprising: a plurality of memory cells arranged in a plurality of rows and a plurality of columns; wherein the memory cells in the same row are coupled to a word line, and the memory cells in the same column are coupled to a bit line; A peripheral circuit is coupled to the memory cell array through a plurality of the word lines and a plurality of the bit lines; the peripheral circuit is configured as follows: Receive at least one set of random data of a time series; wherein the time series includes L random events, L is an integer greater than 1; the random data is used to indicate the current state of the L random events; each of the L random events corresponds to each of the L storage units in the same row; Applying a word line programming pulse to the word lines coupled to the L memory cells, and applying a bit line programming pulse to the bit lines coupled to the selected memory cells among the L memory cells, so as to write the random data into the memory cells corresponding to the random events respectively; The correlation degree of the plurality of random events is determined according to the threshold voltage distribution of the storage unit; wherein the correlation degree is used to predict the future states of the L random events.

2. The memory according to claim 1, characterized in that: The peripheral circuit is further configured as: receiving the time series; A set of random data is generated according to the current states of the plurality of random events at a preset time; wherein the random data includes at least one of a first logic value and a second logic value; the current state includes a first current state and a second current state; the first logic value is used to indicate the first current state of a first random event among the plurality of random events at the preset time, and the second logic value is used to indicate the second current state of a second random event among the plurality of random events at the preset time; the second current state is different from the first current state, and the second logic value is different from the first logic value.

3. The memory according to claim 2, characterized in that: The peripheral circuit is further configured as: Determine the selected storage cell among the L storage cells according to one of the first logic value and the second logic value, and write one of the first logic value and the second logic value into the selected storage cell; The unselected memory cells among the L memory cells are determined according to the other of the first logic value and the second logic value, and the other of the first logic value and the second logic value is written into the unselected memory cells.

4. The memory according to claim 2, characterized in that: The peripheral circuit is further configured to: determine the number of the bit lines selected within the preset time; wherein the selected bit line is coupled to the selected memory cell among the L memory cells; According to the number of the selected bit lines, the pulse width of the word line programming pulse and / or the peak value of the word line programming pulse are adjusted.

5. The memory according to claim 4, characterized in that: The memory also includes: A common source line is coupled to a plurality of memory strings in the memory cell array and the peripheral circuit respectively; wherein the memory string comprises a plurality of the memory cells connected in series, and the memory strings in the same column are coupled to one of the bit lines; The peripheral circuit is specifically configured to determine the number of the bit lines selected within the preset time according to the current of the common source line.

6. The memory according to claim 5, characterized in that: The storage string also includes: A top selection transistor coupled between the bit line and a plurality of the memory cells connected in series; A bottom selection transistor coupled between the common source line and a plurality of the memory cells connected in series; The peripheral circuit is further configured as: Applying a word line pass pulse to the gate of the top selection transistor, the gate of the bottom selection transistor, and the plurality of word lines; applying the bit line program pulse to the selected bit line and applying a bit line inhibit program pulse to the unselected bit line; applying the bit line inhibit program pulse to the common source line; wherein the unselected bit line is coupled to the unselected memory cells among the L memory cells; A current in the common source line is measured.

7. The memory according to claim 1, characterized in that: The storage unit is configured to store M bits of data, and a plurality of the storage units have 2 M threshold voltage intervals, M is a positive integer; the correlation degree includes 2 M relevant levels; wherein the 2 M each of the related levels and the 2 M Each of the threshold voltage intervals in the threshold voltage intervals corresponds one to one; The peripheral circuit is also specifically configured as follows: According to the threshold voltage interval of the storage unit, a correlation level of the random event corresponding to the storage unit is determined.

8. The memory according to claim 7, characterized in that: 2 M The relevance levels include at least: relevant and non-relevant.

9. The memory according to claim 1, characterized in that: The memory includes a flash memory, a phase change memory or a resistive memory.

10. A method for operating a memory, characterized in that: The memory comprises: a memory cell array and a peripheral circuit; the memory cell array comprises: a plurality of memory cells arranged in a plurality of rows and a plurality of columns; wherein the memory cells in the same row are coupled to a word line, and the memory cells in the same column are coupled to a bit line; the peripheral circuit is coupled to the memory cell array through a plurality of the word lines and a plurality of the bit lines; the operation method comprises: Receive at least one set of random data of a time series; wherein the time series includes L random events, L is an integer greater than 1; the random data is used to indicate the current state of the L random events; each of the L random events corresponds to each of the L storage units in the same row; Applying a word line programming pulse to the word lines coupled to the L memory cells, and applying a bit line programming pulse to the bit lines coupled to the selected memory cells among the L memory cells, so as to write the random data into the memory cells corresponding to the random events respectively; The correlation degree of the plurality of random events is determined according to the threshold voltage distribution of the storage unit; wherein the correlation degree is used to predict the future states of the L random events.

11. The operating method according to claim 10, characterized in that: The operation method further includes: receiving the time series; A set of random data is generated according to the current states of the plurality of random events at a preset time; wherein the random data includes at least one of a first logic value and a second logic value; the current state includes a first current state and a second current state; the first logic value is used to indicate the first current state of a first random event among the plurality of random events at the preset time, and the second logic value is used to indicate the second current state of a second random event among the plurality of random events at the preset time; the second current state is different from the first current state, and the second logic value is different from the first logic value.

12. The operating method according to claim 11, characterized in that: The method further comprises: Determine the selected storage cell among the L storage cells according to one of the first logic value and the second logic value, and write one of the first logic value and the second logic value into the selected storage cell; The unselected memory cells among the L memory cells are determined according to the other of the first logic value and the second logic value, and the other of the first logic value and the second logic value is written into the unselected memory cells.

13. The operating method according to claim 11, characterized in that: The operation method further includes: Determining the number of the bit lines selected within the preset time; wherein the selected bit lines are coupled to the selected memory cells among the L memory cells; According to the number of the selected bit lines, the pulse width of the word line programming pulse and / or the peak value of the word line programming pulse are adjusted.

14. The operating method according to claim 13, characterized in that: The memory further comprises a common source line respectively coupled to a plurality of memory strings in the memory cell array and the peripheral circuit; wherein the memory string comprises a plurality of the memory cells connected in series, and the memory strings in the same column are coupled to one of the bit lines; The determining the number of the bit lines selected within the preset time includes: The number of the bit lines selected within the preset time is determined according to the current of the common source line.

15. The operating method according to claim 14, characterized in that: The memory string further includes a top selection transistor and a bottom selection transistor; the top selection transistor is coupled between the bit line and the plurality of memory cells connected in series; The bottom selection transistor is coupled between the common source line and a plurality of the memory cells connected in series; The operation method further includes: Applying a word line pass pulse to the gate of the top selection transistor, the gate of the bottom selection transistor, and the plurality of word lines; applying the bit line program pulse to the selected bit line and applying a bit line inhibit program pulse to the unselected bit line; applying the bit line inhibit program pulse to the common source line; wherein the unselected bit line is coupled to the unselected memory cells among the L memory cells; A current in the common source line is measured.

16. The operating method according to claim 10, characterized in that: The storage unit is configured to store M bits of data, and a plurality of the storage units have 2 M threshold voltage intervals, M is a positive integer; the correlation degree includes 2 M relevant levels; wherein the 2 M each of the related levels and the 2 M Each of the threshold voltage intervals in the threshold voltage intervals corresponds to each other one by one; the operation method further includes: According to the threshold voltage interval of the storage unit, a correlation level of the random event corresponding to the storage unit is determined.

17. The operating method according to claim 16, characterized in that: 2 M The relevance levels include at least: relevant and non-relevant.

18. The operating method according to claim 10, characterized in that: The memory includes a flash memory, a phase change memory or a resistive memory.

19. A memory system, characterized in that: include: One or more memories as claimed in any one of claims 1 to 9; A memory controller is coupled to the memory and is configured to control the memory.

20. An electronic device, characterized in that: include: The memory system of claim 19.

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