Data storage using deactive memory line

Abstract

Methods, apparatuses, and systems related to storing non-task critical data using deactivated memory slots are described. In one embodiment, an apparatus includes circuitry configured to determine that a post-package repair (PPR) operation associated with a memory row of a memory device has been requested by a host device communicatively coupled to the circuitry. The memory row is associated with a physical address. The circuitry determines a location of a defective bit in the memory row. Desented row data including the physical address and a defective bit position associated with the memory row is maintained in a non-transitory memory of the device.

Description

Technical Field

[0001] The present disclosure relates to devices, and in particular to semiconductor memory interface or controller devices that store data using disabled memory rows. Background Art

[0002] An apparatus (e.g., a processor, a memory system, and / or other electronic device) may include one or more semiconductor circuits configured to store and / or process information. For example, the apparatus may include a memory device, such as a volatile memory device, a nonvolatile memory device, or a combination device. A memory device, such as a dynamic random access memory (DRAM), may utilize electrical energy to store and access data. Summary of the invention BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Many aspects of the present disclosure may be better understood with reference to the accompanying drawings. The components in the drawings are not necessarily drawn to scale. Rather, emphasis is placed on clearly illustrating the principles of the present disclosure. The accompanying drawings should not be considered to limit the present disclosure to the specific embodiments depicted, but are rather intended only for explanation and understanding.

[0004] Figure 1 is a block diagram schematically illustrating a memory device according to an embodiment of the present technology.

[0005] Figure 2 is a block diagram of a system having a memory device configured in accordance with an embodiment of the present technology.

[0006] Figure 3 is a block diagram of an example environment in which devices according to embodiments of the present technology may operate.

[0007] Figure 4 is an illustration of an example disabled row table in accordance with an embodiment of the present technology.

[0008] Figure 5 is a flow chart illustrating a process for generating row data for disabling a row of memory in accordance with an embodiment of the present technology.

[0009] Figure 6 is a flow chart illustrating a process for writing data to a disabled memory row in accordance with an embodiment of the present technology.

[0010] Figure 7 is a schematic diagram of a system including devices according to embodiments of the present technology. DETAILED DESCRIPTION

[0011] A semiconductor memory device may store information in an array of memory cells. The information may be stored as a binary code, and each memory cell may store a bit of information as a logic high (e.g., "1") or a logic low (e.g., "0"). Memory cells may be organized at the intersection of word lines (rows) and bit lines (columns). The memory may be further organized into one or more memory groups, each of which may include multiple rows and columns. During operation, the memory device may receive a command and an address specifying one or more rows and one or more columns, and then execute the command on the memory cells at the intersection of the specified row and column (and / or along the entire row / column).

[0012] For example, a memory device (e.g., a random access memory (RAM), such as a dynamic RAM (DRAM), including 3DRAM and DRAM) typically includes one or more memory cell arrays storing data on a substrate (e.g., of a die). Some memory devices may include circuits configured to repair damaged memory cells, and typically include multiple memory cells and redundant memory cells (e.g., spare rows and / or columns). For example, damaged rows and columns in a memory device may be tested before shipping to a customer. A memory device may include one or more redundant structures for storing the addresses of damaged memory cells. If a portion of an original row or column is damaged (e.g., a damaged memory cell), a redundant (or replacement) row or column may be used to replace the damaged (or defective) row or column. This is referred to as "repair". When a redundant row or column is used, the memory device is "programmed" to access the redundant (or replacement) memory cells of the redundant row or column instead of accessing the damaged original memory cell.

[0013] Memory cell programming typically occurs before the memory device is shipped to a customer. Test circuits and / or test sequences that access memory bits can determine which memory cells, if any, have electrical problems—that is, which memory cells are damaged (also referred to herein as "defective"). Bit information associated with the addresses of defective rows and / or columns can be programmed (stored) into a nonvolatile memory circuit, which is referred to herein as a fuse set circuit or fuse set. For example, each fuse set may include one or more address latch circuits. Each address latch circuit may represent a bit of a defective address and include, for example, a fuse or antifuse connected to a latch. In addition, a redundancy enabling circuit with a nonvolatile memory circuit may be programmed to indicate that a corresponding programmed redundant column and / or row should be used instead of a defective row and / or column. The nonvolatile memory circuit may include a fusible link (fuse), an antifuse, a latch (e.g., a dual integrated storage cell latch (DICE)), and / or other types of nonvolatile memory. A fuse is an integrated circuit component designed to be disconnected (or burned) when a relatively high current is selectively applied. This cuts off the connection between two points. Alternatively, an antifuse is designed to connect two points. A memory device may have an array of fuse sets stored in an area of ​​the memory device, and each bit of the damaged memory address may correspond to a fuse or an antifuse or another non-volatile memory circuit in the fuse set. As discussed above, the programmed address (bit information) in the fuse set may correspond to a damaged row address and / or a damaged column address. If during the operation of the memory device (e.g., memory operations such as reading, writing, etc.), the address (e.g., row address and / or column address) of the memory cell being accessed (also referred to herein as "external memory address") matches the bit information (programmed address) in the fuse set, and the corresponding redundant enable circuit indicates that the bit information is identified as damaged, then logic is set so that access to the damaged cell is redirected to a redundant memory cell (also referred to herein as "repair or repair external memory address"). The fuse set address that is not programmed with the defective memory cell address remains at and / or is programmed to the default memory address (e.g., the default column address and / or the default row address). The default memory address may correspond to an address of all zeros ("0"), all ones ("1"), or any combination of one and zero. In some cases, the original memory cell address corresponding to the default memory address may be defective. That is, a memory cell having a default address of all zeros ("0") or all ones ("1") or another default address of a column and / or row is defective. In such a case, similar to the non-default address case, the redundant enable circuit corresponding to the column and / or row address is set to indicate that a redundant memory cell should be used instead of the original memory cell.

[0014] Overview

[0015] Memory devices such as DRAM and other byte-addressable non-volatile media may experience data errors when they are used (e.g., after performing the above-mentioned device programming before customer delivery). Memory devices may employ various techniques to remedy such errors. For example, data in a memory array may be protected with additional error correction code (ECC) parity bytes, which may be used to verify the data stored in the memory array during certain operations (e.g., during the reading of data). Typically, the ECC parity bytes implement the detection and correction of only a specific number of errors within the protected area of ​​the memory array (e.g., one bit error is corrected per protected portion). However, when the underlying physical location on the memory device is defective, such as when the underlying capacitor or cell has a physical defect, the data errors may be too many to be remedied using only the ECC parity bytes. In such cases, the host device may use a post-package repair (PPR) operation to disable the physical memory row with the physical defect so that the memory device will replace the disabled row with a different redundant physical memory row.

[0016] To address defects in a memory array, a memory device may be configured to implement one or more types of PPR operations. For example, a memory group may generally include several additional memory rows, which may generally be referred to as redundant rows. During a repair operation, a row address associated with a defective row may be associated with one of the redundant rows. Then, during a subsequent operation (e.g., a read and / or write operation) that accesses the row address, access is redirected from the defective row to the redundant row. In some operating modes, the repair operation may be a hard (or permanent) repair operation, in which case the updated row address information is stored in a non-volatile form in the memory (e.g., stored in a manner that is maintained even when the memory device is powered off). In other operating modes, the repair operation may be a soft (or temporary) repair operation, in which (a) a set of volatile memory cells (e.g., latches, registers, and / or flip-flops) may be used to temporarily store updated addresses for the repair operation, and (b) a decoder may map the defective address to another set of memory cells. The other set of memory cells may be a set of redundant memory cells (e.g., a row of redundant memory cells) dedicated to soft post-packaging repair.

[0017] In the embodiments described below, memory devices and systems are described primarily in the context of devices incorporating DRAM storage media. However, memory devices configured in accordance with other embodiments of the present technology may include other types of memory devices and systems incorporating other types of storage media, including PCM, SRAM, FRAM, RRAM, MRAM, read-only memory (ROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEROM), ferroelectric, magnetoresistive, and other storage media, including non-volatile, flash (e.g., NAND and / or NOR) storage media, and other forms of persistent media.

[0018] As described above, a host device may perform a PPR operation on a row of a memory device when the number of defects in the row exceeds certain error correction capabilities of the memory device. For example, when the row has more defects than can be corrected by the ECC during normal operation of the memory device (e.g., when responding to a read request from a host device), the host device may perform a PPR. However, the error correction capability is typically limited to correcting a total number of errors that reflects a small percentage of the entire row. For example, in a memory device where the error correction circuit can correct one bit error per portion of a row (e.g., a codeword), the error correction capability may be exceeded when any codeword within the row contains two errors (which may be detectable but uncorrectable). Therefore, the host device may perform a PPR when only a relatively small number of bits within the row to be retried are defective. For example, when only a small number of bits (e.g., approximately 10 bits) within the row are defective, the host device may perform a PPR operation on a 512-byte row (i.e., during normal operation, the row can store 512 bytes of host-provided data). In other words, typically when PPR is performed to deactivate a row, the entire physical row is no longer used (e.g., permanently for a hard repair, or for the duration that the memory device is powered for a soft repair), even though in fact most of the storage within the row is still usable (e.g., not defective).

[0019] Therefore, embodiments of the present technology relate to memory devices, memory controllers, memory systems including memory devices, memory controllers and other components (e.g., host devices), and methods of operating the memory devices, memory controllers, and memory systems, wherein data may be stored in disabled memory rows of the memory devices. The term "disabled" herein refers to memory rows that are no longer used for functional operations by the host device due to a PPR operation (e.g., the memory rows have been replaced by redundant rows that are now mapped to addresses requested by the host, and have therefore been swapped out or disabled). As described herein, data may be stored in and / or written from disabled memory rows using one or more test modes accessible to a memory controller of the memory system, and the data may not be accessible by the host device using conventional access mechanisms (e.g., read and / or write commands issued by the host). Because disabled memory rows may not be accessible by the host and / or access to disabled memory rows may utilize one or more test modes, it may be advantageous to store only certain (e.g., not performance-sensitive) types of data in disabled memory rows.

[0020] In some embodiments, disabled memory rows are used to store non-mission critical data that can be used for purposes other than host storage. The non-mission critical data can be used to monitor, debug, or analyze the operation of a host device, a memory module (e.g., a compute express link (CXL) memory module), or a memory device (e.g., a DRAM array). For example, a memory controller coupled to a memory device can generate debug or log data and store it in one or more disabled memory rows of the memory device, where the data can be accessed later by the memory controller. Compared to conventional devices, the memory controller described herein determines that a PPR operation has been requested by a communicatively coupled host device, determines whether a physical memory row associated with the PPR operation is suitable for storing non-mission critical data (e.g., based on how many bits in the row are defective), and enables writing non-mission critical data to and reading data from the physical memory row after the physical memory row has been disabled. As described herein, a memory controller can include circuitry and / or firmware to enable the use of disabled memory rows for storing non-mission critical data. The memory array may be byte-addressable volatile (eg, DRAM) or non-volatile (eg, persistent memory) media.

[0021] The memory controller determines when it receives a PPR command from a host device requesting a PPR operation. The PPR operation may be requested when the memory controller and / or the memory device is operating in a functional or task operating mode. The PPR command may indicate the address of a row to be repaired (a "row failure address"); in an embodiment, the PPR command may additionally indicate other address bits (e.g., groups and / or groups of groups) that identify the row to be repaired in the memory device. The memory controller determines a physical memory row within the memory array associated with the row failure address (e.g., a "disabled memory row"). Additionally, the memory controller determines the location of a defective bit in the disabled memory row.

[0022] In an embodiment, the memory controller determines the location of the defective bit in the disabled row using circuitry and / or firmware, and the determination may be made when the controller is operating in a task operation mode or in a test operation mode different from the task mode. For example, in response to determining that a PPR operation has been requested, the memory controller may switch from the task operation mode to the test operation mode, and in the test mode, one or more write sequences to the disabled memory row and one or more read sequences from the disabled memory row may be performed to determine the location of the defective bit (e.g., using one or more test patterns). For example, the memory controller may write a known data pattern to the disabled memory row, read data from the disabled memory row, and compare the known write data pattern with the read data to identify the defective bit location. The memory controller may repeat the sequence of writing pattern data, reading data, and comparing multiple times (e.g., the memory controller may write 10 data patterns).

[0023] The memory controller may evaluate the number of identified defective bit positions in the disabled memory row and determine whether the disabled memory row is suitable for non-mission critical data storage. For example, the memory controller may determine whether the number of defective bit positions is less than a threshold number. If the number of defective bit positions is less than the threshold number, the memory row may be used to store non-mission critical data. The memory controller (e.g., circuit system and / or firmware) maintains (e.g., in a disabled row table) disabled row data including physical addresses associated with disabled memory rows and characterizations of bit defects in the disabled memory rows (e.g., counts of defective bits, defective bit positions, and / or write masks). The disabled row data may be maintained in a non-transitory memory of the memory controller.

[0024] The memory controller may receive and / or generate data to be stored in one or more of the disabled memory rows of the memory device. In some embodiments, the data may be non-mission critical data related to the operation of the host device, the memory controller, the memory device, other components of the memory system, or a combination thereof. For example, the memory controller may generate debug or logging data to be stored in the disabled rows of the memory device during operation of the memory system. The memory controller may use the disabled row data to facilitate identification of the disabled memory rows to which the non-mission critical data may be written, and the memory controller may use the test operation mode to write the non-mission critical data to the identified disabled memory rows of the memory device.

[0025] The memory controller may evaluate the maintained disabled row data to identify idle disabled memory rows (e.g., rows that have not been used to store other non-mission critical data). The memory controller may further evaluate the maintained disabled row data to identify disabled memory rows with sufficient capacity for storing non-mission critical data (e.g., rows with sufficient available non-defective bits). Based on the evaluation of the disabled row data, the memory controller selects one or more disabled memory rows that will write non-mission critical data. The memory controller may generate a write mask based on the defective bit positions maintained in the disabled row data, or obtain a write mask corresponding to the disabled memory rows to be stored in the disabled row data maintained in the disabled row data. The memory controller uses a write mask corresponding to the selected one or more disabled memory rows to prevent non-mission critical data from being stored at the defective bit positions of those disabled memory rows. For example, the memory controller may apply a write mask to non-mission critical data to generate masked data. The memory controller may use a test operation mode to write masked data to one or more selected disabled memory rows. In some embodiments, the memory controller may maintain data indicating which disabled memory rows are currently being used to store non-mission critical data (e.g., whether the disabled memory rows are free to store non-mission critical data or in use). As described herein, the memory controller may use the data to determine which disabled memory rows are already in use (e.g., storing non-mission critical data) and should not be overwritten, so that the memory controller may select an idle disabled memory row for storing new non-mission critical data. In addition, in some embodiments, the memory controller may additionally maintain data indicating the type of non-mission critical data stored in the disabled memory rows in use. As described herein, the memory controller may use the maintained type information during subsequent reads of the disabled memory rows (e.g., to identify the disabled memory rows in use storing non-mission critical data of interest to the memory controller).

[0026] A memory controller may receive and / or generate a request to read previously stored data (e.g., non-mission critical data) from a disabled row of a memory device. For example, the memory controller may (e.g., in a volatile or non-volatile memory) maintain a state indicating which disabled memory rows have been used to store non-mission critical data of interest (e.g., associated with a particular debug or logging event), and may initiate a read of the data. Using the disabled row data corresponding to the disabled memory rows, the memory controller may generate a read mask (e.g., a mask indicating which physical bits in the disabled memory rows contain valid data). In some embodiments, the read mask may be the same as a write mask previously used to write non-mission critical data to the disabled memory rows. The memory controller may then read the requested non-mission critical data from the disabled memory rows of the memory device using one or more test patterns.

[0027] In an embodiment, the memory device and memory controller described herein are part of a CXL memory module. In the embodiment, the CXL memory module includes a memory device and a controller (e.g., a CXL controller). The controller may include a non-transitory memory storing firmware instructions. The instructions, when executed by the controller, cause the controller to determine that a PPR operation has been requested by a host device communicatively coupled to the CXL memory module, and as described herein, determine whether a physical memory row associated with the PPR operation is suitable for storing certain (e.g., non-mission critical) data.

[0028] Benefits and advantages of the systems, methods, and apparatus described herein include the ability to use otherwise unused storage capacity on a memory array (e.g., DRAM or byte-addressable non-volatile RAM) to occupy areas (e.g., memory rows disabled by a PPR operation). During the life of a memory device, multiple PPR operations may be performed, which will typically result in multiple unused disabled memory rows. The disclosed system tracks the addresses of these disabled memory rows and uses their non-defective bits to store non-mission critical data for logging and debugging operations. Thus, the system disclosed herein utilizes post-PPR locations on a memory array. The reclaimed memory storage and the non-mission critical data stored thereon can provide important insights from debugging and fault analysis of memory arrays, memory controllers, and host devices. Deep insights from logging and debugging enable improved product quality, reduced defects per million (DPM) levels, tracking of process variations, and improved tracking of customer feedback metrics.

[0029] Example Memory Devices

[0030] Figure 11 is a block diagram schematically illustrating a memory device 100 according to an embodiment of the present technology. The memory device 100 may include a memory cell array, such as a memory array 150. The memory array 150 may include a plurality of groups (e.g., Figure 1 1-15 in the example of ), and each group may include a plurality of word lines (WL), a plurality of bit lines (BL), and a plurality of memory cells (e.g., m×n memory cells) arranged at the intersection of word lines (e.g., m word lines, which may also be referred to as rows) and bit lines (e.g., n bit lines, which may also be referred to as columns). Each of the plurality of word lines may be coupled to a corresponding word line driver (WL driver) configured to control a voltage of the word line during memory operation. Similarly, embodiments of memory device 100 may include different and / or additional components, or may be connected in different ways.

[0031] The memory cells may include any of a number of different memory media types, including capacitive, phase change, magnetoresistive, ferroelectric, etc. In some embodiments, a portion of the memory array 150 may be configured to store ECC parity bits (ECC check bits). Selection of word lines WL may be performed by a row decoder 140, and selection of bit lines BL may be performed by a column decoder 145. A sense amplifier (SAMP) may be provided for a corresponding bit line BL and connected to at least one corresponding local I / O line pair (LIOT / B), which in turn may be coupled to at least one corresponding main I / O line pair (MIOT / B) via a transmission gate (TG) that may act as a switch. The memory array 150 may also include plate lines and corresponding circuitry for managing the operation of the plate lines.

[0032] The memory device 100 may employ a plurality of external terminals, including a command terminal and an address terminal coupled to a command bus and an address bus to receive a command signal CMD and an address signal ADDR, respectively. The memory device may further include a chip select terminal for receiving a chip select signal CS, a clock terminal for receiving clock signals CK and CKF, a data clock terminal for receiving data clock signals WCK and WCKF, data terminals DQ, RDQS, DBI (for a data bus inversion function) and DMI (for a data mask inversion function), power supply terminals VDD, VSS and VDDQ.

[0033] The address signal and the group address signal can be supplied to the command terminal and the address terminal from the outside. The address signal and the group address signal supplied to the address terminal can be transmitted to the address decoder 110 via the command / address input circuit 105. The address decoder 110 is a binary decoder having an input for address bits and an output for device selection signals. When the address of a specific device is received on the address input, the address decoder 110 asserts the selection output for the device. For example, the address decoder 110 decodes the row address received from the host device and generates a physical group address, row address, and column address associated with the physical location corresponding to the received row address in the memory array 150. The generation of the group address, row address, and column address according to the received address bits can be based on a default decoding map. However, the decoding can be additionally based on whether a repair has been performed on the physical location corresponding to the address.

[0034] The memory array 150 may have redundant rows ( Figure 1 (not shown), the disabled memory rows of the memory array 150 are remapped to the redundant rows through the PPR operation. For example, the address decoder 110 includes or has access to a remapping table or a repair table ( Figure 1 ), the remapping table or repair table stores the correspondence between the disabled memory rows and the redundant rows of the memory array 150.

[0035] In some implementations, the address decoder 110 receives the address bits and supplies a decoded row address signal (XADD) to a row decoder 140 (which may be referred to as a row driver), and supplies a decoded column address signal (YADD) to a column decoder 145 (which may be referred to as a column driver). The address decoder 110 may also receive the bank address portion of the ADDR input and supply a decoded bank address signal (BADD) and the bank address signal to both the row decoder 140 and the column decoder 145.

[0036] A command signal CMD, an address signal ADDR, and a chip select signal CS may be supplied from a memory controller to the command terminal and the address terminal. The command signal may represent various memory commands (e.g., refresh commands, activation commands, precharge commands, access commands that may include read commands and write commands) from the memory controller. The selection signal CS may be used to select the memory device 100 to respond to the commands and addresses provided to the command terminals and the address terminals. When a valid CS signal is provided to the memory device 100, the commands and addresses may be decoded, and a memory operation may be performed. The command signal CMD may be provided to the command decoder 115 as an internal command signal ICMD via the command / address input circuit 105.

[0037] The command decoder 115 may include circuits for decoding the internal command signal ICMD to generate various internal signals and commands for performing memory operations (e.g., row command signals for selecting word lines and column command signals for selecting bit lines). Other examples of memory operations that the memory device 100 may perform based on decoding the internal command signal ICMD include refresh commands (e.g., rebuilding the full charge stored in individual memory cells of the memory array 150), activation commands (e.g., activating rows in a particular group, in some cases for subsequent access operations), or precharge commands (e.g., deactivating activated rows in a particular group). The internal command signals may also include output and input activation commands, such as the timing command CMDCK ( Figure 1 not shown).

[0038] In some embodiments, the command decoder 115 may further include one or more registers 118 for tracking various counts and / or values ​​(e.g., a count of refresh commands received by the memory device 100 or self-refresh operations performed by the memory device 100) and / or for storing various operating conditions of the memory device 100 to perform certain functions, features, and modes (or test modes). Therefore, in some embodiments, the registers 118 (or a subset of the registers 118) may be referred to as mode registers. Additionally or alternatively, the memory device 100 may include the registers 118 as a separate component from the command decoder 115. In some embodiments, the registers 118 may include multi-purpose registers (MPRs) configured to write and / or read special data to and from the memory device 100.

[0039] When a read command is issued to a group with an open row and a column address is supplied in time as part of the read command, read data may be read from a memory cell specified by a row address (which may have been provided as part of an activation command identifying the open row) and a column address in the memory array 150. The read command may be received by a command decoder 115, which may provide an internal command to an input / output circuit 160 so that the read data may be output from data terminals DQ, RDQS, DBI, and DMI via a read / write amplifier 155 and input / output circuit 160 according to the RDQS clock signal. The read data may be provided at a time defined by read latency information RL, which may be programmed in the memory device 100, such as in a mode register (e.g., register 118). The read latency information RL may be defined in terms of clock cycles of a CK clock signal. For example, the read latency information RL may be the number of clock cycles of a CK signal after the memory device 100 receives the read command when the associated read data is provided.

[0040] When a write command is issued to a group with an open row and a column address is supplied in time as part of the write command, write data may be supplied to data terminals DQ, DBI, and DMI according to WCK and WCKF clock signals. The write command may be received by a command decoder 115, which may provide an internal command to an input / output circuit 160, so that the write data may be received by a data receiver in the input / output circuit 160 and supplied to the memory array 150 via the input / output circuit 160 and the read / write amplifier 155. The write data may be written to a memory cell specified by a row address and a column address. The write data may be provided to the data terminal at a time defined by write latency WL information. The write latency WL information may be programmed in the memory device 100, for example, in a mode register (e.g., register 118). The write latency WL information may be defined in terms of clock cycles of a CK clock signal. For example, the write latency information WL may be the number of clock cycles of a CK signal after the memory device 100 receives a write command when the associated write data is received.

[0041] The memory array 150 may be accessed via one or more test modes. In these test modes, the memory controller or CXL controller provides access to specific physical groups, rows, or columns to perform reads and writes. For example, the memory controller may use the test operation mode to write data (e.g., non-mission critical data) to one or more selected disabled memory rows. In addition, the memory controller may receive and / or generate a request to read previously stored data from a disabled row of a memory device. For example, the memory controller may use one or more test modes to read the requested data from a disabled row of a memory device.

[0042] The power supply terminal may be supplied with power supply potentials VDD and VSS. These power supply potentials VDD and VSS may be supplied to the internal voltage generator circuit 170. The internal voltage generator circuit 170 may generate various internal potentials VPP, VOD, VARY, VPERI, etc. based on the power supply potentials VDD and VSS. The internal potential VPP may be used in the row decoder 140, the internal potentials VOD and VARY may be used in the sense amplifier included in the memory array 150, and the internal potential VPERI may be used in many other circuit blocks.

[0043] The power supply terminal may also be supplied with a power supply potential VDDQ. The power supply potential VDDQ may be supplied to the input / output circuit 160 together with the power supply potential VSS. In an embodiment of the present technology, the power supply potential VDDQ may be the same potential as the power supply potential VDD. In another embodiment of the present technology, the power supply potential VDDQ may be a potential different from the power supply potential VDD. However, a dedicated power supply potential VDDQ may be used for the input / output circuit 160 so that the power supply noise generated by the input / output circuit 160 does not propagate to other circuit blocks.

[0044] An external clock signal and a complementary external clock signal may be supplied to the clock terminal and the data clock terminal. The external clock signals CK, CKF, WCK, and WCKF may be supplied to the clock input circuit 120. The CK and CKF signals may be complementary, and the WCK and WCKF signals may also be complementary. The complementary clock signals may have opposite clock levels and may simultaneously switch between opposite clock levels. For example, when the clock signal is at a low clock level, the complementary clock signal is at a high level, and when the clock signal is at a high clock level, the complementary clock signal is at a low clock level. In addition, when the clock signal changes from a low clock level to a high clock level, the complementary clock signal changes from a high clock level to a low clock level, and when the clock signal changes from a high clock level to a low clock level, the complementary clock signal changes from a low clock level to a high clock level.

[0045] An input buffer included in the clock input circuit 120 may receive an external clock signal. For example, when enabled by the CKE signal from the command decoder 115, the input buffer may receive the CK and CKF signals and the WCK and WCKF signals. The clock input circuit 120 may receive an external clock signal to generate an internal clock signal ICLK. The internal clock signal ICLK may be supplied to the internal clock circuit 130. The internal clock circuit 130 may provide various phase- and frequency-controlled internal clock signals based on the received internal clock signal ICLK and the clock enable signal CKE from the command decoder 115.

[0046] For example, the internal clock circuit 130 may include a clock path ( Figure 1100 and 100. The clock path of the memory device 100 may be configured to receive an internal clock signal ICLK and provide various clock signals to the command decoder 115. The internal clock circuit 130 may further provide an input / output (IO) clock signal. The IO clock signal may be supplied to the input / output circuit 160 and may be used as a timing signal for determining the output timing of read data and the input timing of write data. The IO clock signal may be provided at multiple clock frequencies so that data may be output from the memory device 100 and input to the memory device at different data rates. When high memory speeds are desired, higher clock frequencies may be desirable. When lower power consumption is desired, lower clock frequencies may be desirable. The internal clock signal ICLK may also be supplied to the timing generator 135, and various internal clock signals may be generated accordingly.

[0047] The memory device 100 may be connected to any of a number of electronic devices or components thereof that are capable of utilizing memory to temporarily or permanently store information. For example, the host device of the memory device 100 may be a computing device, such as a desktop or portable computer, a server, a handheld device (e.g., a mobile phone, a tablet computer, a digital reader, a digital media player), or some component thereof (e.g., a central processing unit, a coprocessor, a dedicated memory controller, etc.). The host device may be a networking device (e.g., a switch, a router, etc.) or a recorder of digital images, audio, and / or video, a vehicle, an appliance, a toy, or any of a number of other products. In one embodiment, the host device may be directly connected to the memory device 100, but in other embodiments, the host device may be indirectly connected to the memory device (e.g., through a networking connection or through an intermediate device).

[0048] Figure 2 2 is a block diagram of a system 201 having a memory device 200 configured in accordance with an embodiment of the present technology. The memory device 200 may be a reference Figure 1 Examples of memory device 100 described herein or including aspects of the memory device. As shown, memory device 200 includes a main memory 202 (e.g., DRAM, NAND flash, NOR flash, FeRAM, phase change memory (PCM), etc.) and control circuitry 206 (e.g., an upstream central processing unit (CPU), a memory controller) operably coupled to a host device 208. Control circuitry 206 may include reference Figure 1 For example, control circuitry 206 may include aspects of command / address input circuitry 105, command decoder 110, and command decoder 115, etc. Similarly, embodiments of system 201 may include different and / or additional components, or may be connected in different ways.

[0049] The main memory 202 includes a plurality of memory units 220, each of which includes a plurality of memory cells. The memory units 220 may be individual memory dies, memory planes in a single memory die, stacks of memory dies vertically connected with through silicon vias (TSVs), etc. For example, in one embodiment, each of the memory units 220 may be formed by a semiconductor die and arranged in a single device package with other memory unit dies. In other embodiments, the plurality of memory units 220 may be co-located on a single die and / or distributed across a plurality of device packages. In some embodiments, the memory units 220 may also be subdivided into memory regions 228 (e.g., groups, rows, lanes, blocks, pages, etc.).

[0050] The memory cells may include, for example, floating gates, charge traps, phase change, capacitive, ferroelectric, magnetoresistive, and / or other suitable storage elements configured to store data permanently or semi-permanently. The main memory 202 and / or individual memory cells 220 may also include other circuit components, such as multiplexers, decoders, buffers, read / write drivers, address registers, data output / data input registers, etc., for accessing and / or programming (e.g., writing) memory cells and other functions, such as for processing information and / or communicating with the control circuit system 206 or the host device 208. Although a certain number of memory cells, rows, columns, regions, and memory cells are shown in the illustrated embodiments for illustrative purposes, the number of memory cells, rows, columns, regions, and memory cells may vary and, in other embodiments, may be larger or smaller in proportion than shown in the illustrated examples. For example, in some embodiments, the memory device 200 may include only one memory cell 220. Alternatively, the memory device 200 may include two, three, four, eight, ten, or more (eg, 16, 32, 64, or more) memory cells 220. Although the memory cells 220 are Figure 2 2 as each including four memory regions 228, but in other embodiments, each memory unit 220 may include one, two, three, eight or more (e.g., 16, 32, 64, 100, 128, 256 or more) memory regions.

[0051] In one embodiment, control circuit system 206 may be disposed on the same die as main memory 202 (e.g., including command / address / clock input circuit system, decoders, voltage and timing generators, IO circuit system, etc.). In another embodiment, control circuit system 206 may be a microcontroller, dedicated logic circuit system (e.g., field programmable gate array (FPGA), application specific integrated circuit (ASIC), control circuit system on memory die, etc.), or other suitable processor. In one embodiment, control circuit system 206 may include a processor configured to execute instructions stored in memory to perform various processes, logic flows, and routines for controlling the operation of memory device 200, including managing main memory 202 and handling communications between memory device 200 and host device 208. In some embodiments, control circuit system 206 may include embedded memory with memory registers for storing (e.g., memory addresses, row counters, group counters, memory pointers, fetched data, etc.). In another embodiment of the present technology, memory device 200 may not include control circuitry, and may instead rely on external control (eg, provided by host device 208, or by a processor or controller separate from memory device 200).

[0052] Host device 208 may be any of a number of electronic devices or components thereof that are capable of utilizing memory to temporarily or permanently store information. For example, host device 208 may be a computing device, such as a desktop or portable computer, a server, a handheld device (e.g., a mobile phone, a tablet computer, a digital reader, a digital media player), or some component thereof (e.g., a central processing unit, a coprocessor, a dedicated memory controller, etc.). Host device 208 may be a networking device (e.g., a switch, a router, etc.) or a recorder of digital images, audio, and / or video, a vehicle, an appliance, a toy, or any of a number of other products. In one embodiment, host device 208 may be directly connected to memory device 200, but in other embodiments, host device 208 may be indirectly connected to memory device 200 (e.g., through a networking connection or through an intermediate device).

[0053] In operation, the control circuit system 206 may directly write or otherwise program various memory areas of the main memory 202. The control circuit system 206 communicates with the host device 208 via a host device bus or interface 210. In some embodiments, the host device 208 and the control circuit system 206 may communicate via a dedicated memory bus (e.g., a DRAM bus). In other embodiments, the host device 208 and the control circuit system 206 may communicate via a serial interface, such as a serially attached SCSI (SAS), a serial AT attachment (SATA) interface, a peripheral component interconnect express (PCIe), or other suitable interface (e.g., a parallel interface). The host device 208 may send various requests (in the form of, for example, packets or packet streams) to the control circuit system 206. The request may include a command to read, write, return information, and / or perform a specific operation (e.g., a refresh operation, a trim operation, a precharge operation, an activation operation, a wear leveling operation, a dead cell collection operation, etc.).

[0054] In operation, the control circuit system 206 may further receive a request for a PPR operation for the memory array from the host device. As described herein, the control circuit system 206 may identify a disabled memory row in the memory array associated with the PPR operation. In some embodiments, the control circuit system 206 determines the position of the defective bit in the memory row maintained in the disabled row data. The control circuit system 206 may further receive a request to write non-mission critical data to the memory row. As described herein, the control circuit system 206 applies an error mask previously generated based on the defective bit position of the memory row to the non-mission critical data to generate storage data. The non-mission critical data is written to the physical location of the memory row using a specific test pattern sequence.

[0055] Figure 3 305 may operate in an example environment 300. The example environment 300 may correspond to a computing device or system. The device 305 may include a memory 310 (e.g., Figure 1 310) and a controller 315. The controller 315 may include one or more computer processors and include non-transitory memory that stores firmware instructions. The firmware provides low-level control for specific hardware of the controller 315 and / or memory 310. The firmware may also provide higher-level hardware abstraction services to software such as an operating system 325.

[0056] Memory 310 (sometimes referred to as a "memory device" or "memory array") may include volatile memory, non-volatile memory, or a combination device / system. For example, memory 310 may include DRAM. Similarly, embodiments of environment 300 may include different and / or additional components, or may be connected in different ways.

[0057] Device 305 may be a CXL module (sometimes referred to as a "CXL card"), a memory controller, or another type of memory interface control device. CXL modules operate according to standards for high-speed, high-capacity central processing unit (CPU)-to-device connections and CPU-to-memory connections. Memory 310 may be electrically coupled to a controller 315 (e.g., a memory controller such as a CXL controller; a buffer; and / or a repeater device such as an RCD, etc.), a host 320 (e.g., a computer or a group of processors), and / or an operating system 325. Some example operating environments may include a computing system with a central processing unit (CPU) as the host 320 that interacts with a memory controller to write data to and read data from the DRAM.

[0058] The host 320 (sometimes referred to as a "host device") may function according to an operating system 325 and send operational communications, such as read / write commands, write data (sometimes referred to as a "write data pattern"), or addresses to the memory controller. The device 305 may also send read data (sometimes referred to as a "read data pattern") back to a system controller (not shown) as an operational communication. The controller 315 may manage the flow of data into and out of the device 305 according to the address and / or operation. The memory 310 and the controller 315 may be electrically coupled together to form the device 305. The controller 315 may track data entering the device 305 and initiate a test mode.

[0059] The controller 315 and / or the memory 310 may include Figure 1 . For example, the controller 315 may have and maintain a read counter and a write counter, based on which the controller may write a first data pattern (e.g., a write data pattern) to a memory row of the memory 310 and read a second data pattern (e.g., a read data pattern) from the memory row. The controller 315 may compare the first data pattern and the second data pattern to determine defective bit locations in the memory row of the memory 310.

[0060] In some embodiments, instructions stored in firmware of the controller 315 are executed by the controller 315 to cause the device 305 to determine that the host 320 has requested a PPR operation. For example, the host 320 signals or provides a message (e.g., a specific code or alert) to the device 305 that one or more PPR operations have been requested. The device 305 determines that the requested PPR operation is associated with a memory row of the memory 310. For example, the host 320 may send a message to the device 305 requesting a PPR operation, the message including a logical address (e.g., a row fail address). As described herein, the device 305 may determine the physical memory row in the memory 310 that is currently associated with the row fail address, and assign a new physical memory row (e.g., a redundant row) to the row fail address, thereby disabling the physical memory row associated with the row fail address. As described herein, the device 305 may (e.g., in reference to the description, for example) Figure 4 The disabled row data) maintains the logical address and / or physical address of the disabled memory row.

[0061] Once the device 305 identifies the memory row associated with the row failure address for which the PPR operation is requested, the device 305 can identify the defective bits in the memory row to be disabled. For example, the device 305 writes a data pattern to the memory row and reads the data pattern from the memory row to determine which bits and how many bits in the memory row are defective. The device 305 stores the number of defective bits and / or the position of the defective bits identified for each disabled memory row in the disabled row data, and the device 305 can use the number and / or position to facilitate the storage of non-mission critical data in the disabled memory row. In some embodiments, the device 305 maintains the disabled row data of all disabled memory rows, including the disabled row data of the memory rows that are not suitable for storing non-mission critical data, but indicates (for example, using one or more status bits in the disabled row data) whether the corresponding disabled memory row is suitable for storing non-mission critical data. In some embodiments, the device 305 maintains only the disabled row data of the disabled memory row suitable for storing non-mission critical data; in the embodiments, the disabled row data can be used to facilitate the storage of non-mission critical data, and the additional data structure and / or memory of the device can be used to identify the physical row corresponding to the address requested by the host. In an embodiment, the disabled memory row can be suitable for storing non-mission critical data based on the number of defective bits in the row, and the device 305 can determine the number when disabling the row. For example, the device 305 can compare the number (or percentage) of defective bit positions in the disabled memory row with a threshold number (or percentage) to determine whether the disabled memory row is suitable for storing non-mission critical data. If the number (or percentage) of defective bit positions is less than the threshold number (or percentage), the disabled memory row can be used to store non-mission critical data. In some instances, if the size of each memory row is 512 bytes (i.e., 4,096 bits), the threshold number of bits can be 1,000 bits, 800 bits, 600 bits, 100 bits, 10 bits, 5 bits, etc. In some embodiments, the threshold is expressed as a percentage. For example, if at least 80% of the bits in a memory row are non-defective, then the disabled memory row may be used to store non-mission critical data. Thus, the threshold percentage may be 30%, 20%, 10%, etc. Figure 5 Various operations for determining defective bit locations in disabled memory rows, evaluating whether the disabled memory rows have sufficient usable (eg, non-defective) storage, and generating disabled row data for the rows are described in greater detail.

[0062] In some embodiments, device 305 determines the location of each defective bit in a memory row. As described herein, device 305 may maintain the location of the defective bit in a memory row as part of the disabled row data associated with the memory row. Device 305 may generate and / or update the disabled row data associated with the memory row as part of performing a PPR operation associated with the memory row and / or after device 305 runs read and write tests on the memory row to determine the defective bit locations. Device 305 may store the defective bit in a non-transitory memory of controller 315 (an example of which is shown in FIG. 1 ). Figure 4 ) For example, in a disabled row table, disabled row data of one or more disabled rows is maintained.

[0063] As described herein, the controller 315 may receive and / or generate non-mission critical data related to the operation of the host 320, the device 305, or the memory 310. The device 305 may store at least a portion of the non-mission critical data in one or more disabled memory rows for logging, debugging, or monitoring operations of the host 320, the device 305, the memory 310, or other devices and systems. In order to avoid storing non-mission critical data at defective bit positions in the disabled rows, the device 305 may generate a mask for the disabled memory rows, for example, to mask or mark the defective bit positions. For example, the controller 315 may generate a bit mask (e.g., using defective bit position information of the disabled row data), according to which a plurality of bits in a byte, a half byte, a word, etc. may be set to be available or unavailable. The controller 315 may use the generated bit mask when writing non-mission critical data to the disabled memory rows (e.g., so that no defective bits are used to store data) and when reading non-mission critical data from the disabled memory rows (e.g., to determine the location of the stored data within the disabled memory rows). In some implementations, if a memory bit in a particular byte of a disabled memory row is defective, the entire byte is masked or marked as unusable.

[0064] Figure 4 4 is a diagrammatic illustration of an example disabled row table 400 according to an embodiment of the present technology. Figure 4 As shown in FIG. 4 , the disabled row table 400 may include one or more entries of disabled row data 405 (eg, disabled row data 405-0, disabled row data 405-1, disabled row data 405-2, etc., up to disabled row data 405-n), each of which is associated with a disabled memory row. Figure 4 The disabled row data 405 shown in the figure is obtained by referring to Figure 3An example embodiment of the disabled row data maintained by the device 305 is illustrated and described in more detail. For example, the disabled row table 400 and / or the disabled row data 405 may be generated and / or maintained by the controller 315 and / or firmware running on the controller. The disabled row data 405 may or may not include Figure 4 Any of the columns of the disabled row table 400 illustrated in FIG. Similarly, embodiments of the disabled row data may include different and / or additional fields, or may be arranged in a different manner.

[0065] Each entry of the disabled row data 405 may include an identification of the disabled memory row associated with the entry, and data characterizing the location of a defective bit within the memory row. Figure 4 As described in , the disabled row data 405 may include a memory row field that identifies a disabled memory row. As another example, the disabled row data 405 may include the number of defective bits in the memory row and / or the position of the defective bits in the memory row. For example, each defective bit position in the disabled row data 405 is indicated by a binary "1" in a vector representing the bit position of the memory row. In another example, each defective bit position in the disabled row data 405 may be indicated by a binary "0" in a vector representing the bit position of the memory row, and each non-defective bit position is indicated by a binary "1". In some embodiments, the defective bit position is not stored in the disabled row data to reduce overhead. Alternatively, a mask can be developed to mask each defective bit position when each defective bit position is identified.

[0066] although Figure 4 The embodiment in which the defective bit positions are maintained as a mask in the disabled row data 405 is described, but in embodiments, the defective bit positions may be stored in an encoded form. In some embodiments, the disabled row data 405 includes information identifying a host identification address associated with the corresponding memory row when the corresponding memory row is disabled. For example, Figure 4 As illustrated in FIG. 4 , the disabled row data 405 may include a logical address and / or a physical address. Each disabled row data 405 may also have a flag (not shown) indicating whether the disabled memory row should be used to store non-mission critical data based on how many bits in the disabled memory row are defective. Each disabled row data 405 may further have a flag (not shown) indicating whether the corresponding row is currently used to store non-mission critical data (e.g., whether the row is free to store data).

[0067] The disabled row table 400 may include an extra column (not shown), which tracks the disabled row being used. Extra columns are sometimes referred to as "in use" columns. Extra columns store, for example, binary values, such as 0 or 1 (or true or false) for each disabled row address, depending on whether non-mission critical data is filled in the disabled row. In some embodiments, an extra table (not shown) that is different from the disabled row table 400 is also produced and stored. The extra table may have two columns. The first column stores the disabled row address, and the second column is a "in use" column that stores a binary value, which indicates which disabled rows are filled with non-mission critical data.

[0068] When the power supply of the device 305 or the controller 315 (reference Figure 3 In more detail, when the device 305 is cycled and the device or controller is restarted, the "in use" column of the disabled row table 400 and / or the additional table can be cleared so that its entries are deleted. That is, after a power cycle and / or restart, the "in use" data (whether in the disabled row table 400 or in the additional table) can be cleared so that all disabled rows are no longer designed to be in use and can therefore be used to store non-mission critical data. In an embodiment in which the "in use" column is implemented in an additional table different from the disabled row table 400, entries are created in the additional table only when the row is disabled and the information specifying the disabled row appears in the disabled row table 400. In some embodiments, when the device 305 determines that the non-mission critical data stored in a specific disabled row is no longer needed and / or can be deleted (for example, the non-mission critical data is out of date, the device no longer uses the non-mission critical data, etc.), the device updates the "in use" column entry of the specific disabled row to indicate that the specific disabled row is available. When the device 305 or controller 315 fills a specific disabled row with new non-mission critical data, the "in use" column entry of the specific disabled row is updated to indicate that the specific disabled row is in use. In this way, the device or controller tracks the disabled rows in use that should not be overwritten.

[0069] In some embodiments, the above-mentioned disabled row table 400 or additional tables have a column that specifies the details or type of non-mission critical data stored in each disabled row. For example, the column that specifies the details or type of non-mission critical data may indicate whether the non-mission critical data stored in a particular disabled row is debugging data, logging data, fault analysis data, etc. In some examples, the column that specifies the details or type of non-mission critical data may indicate the system operation or system function to which the non-mission critical data stored in a particular disabled row relates.

[0070] As described herein, the system can generate and maintain disabled row data 405 for disabled memory rows that have been disabled due to PPR operations. Figure 4As a result of the PPR operation, the memory row MR2 may have been disabled. Therefore, the system may generate disabled row data 405-2 corresponding to the memory row MR2, wherein the system may store the number of defective bits (e.g., 25) and / or the defective bit positions (e.g., positions 0100001 ...) in the disabled row. The disabled row data 405-2 may also include a logical address (e.g., logical address L2) and / or a physical address (e.g., physical address PA2).

[0071] In some examples, a 512-byte long memory row MR0 has 16 defective bits (2 bytes), such as Figure 4 Therefore, 510 bytes (512 bytes - 2 bytes) of memory row MR0 are defect-free and can be used to store non-mission-critical data.

[0072] In some embodiments, the disabled row table 400 may be implemented as a lookup table stored in a non-volatile memory. In some embodiments, the disabled row table 400 may be implemented in other machine-readable forms. Figure 4 The embodiment that the entries of the disabled row data 405 are organized as a table (e.g., the disabled row table 400) is described, but in an embodiment, the disabled row data can be organized in other machine-readable forms. In some embodiments, the disabled row data 405 is stored in an array, a linked list, a tree, a stack, a dynamic data structure or a combination thereof.

[0073] Process for storing and retrieving non-mission-critical data using retired storage rows

[0074] Figure 5 1 is a flow chart illustrating a process 500 for generating row data for disabling a memory row according to an embodiment of the present technology. Aspects of the process 500 may be performed by, for example, a memory controller, a reference Figure 1 The memory device 100 is illustrated and described in more detail with reference to Figure 3 The device 305 and / or controller 315 are illustrated and described in more detail with reference to Figure 3 The process may be performed by the host device 320 or a combination thereof as described and illustrated in more detail. At least a portion of the process may be performed by a CXL memory module. Likewise, embodiments may include different and / or additional steps, or perform the steps in a different order.

[0075] Process 500 begins at block 504, where process 500 receives a request from a host device for a PPR operation of a memory array. The memory array may be a byte-addressable volatile or non-volatile medium. The request for a PPR operation includes a row fail address or a physical address of the memory array.

[0076] At block 508, process 500 identifies a memory row in the memory array associated with the row fail address or physical address to be disabled. For example, process 500 can decode the row fail address or physical address to determine the bank group, bank, memory array row, etc. corresponding to the address received from the host.

[0077] At block 512, process 500 determines the location of a defective bit in a memory row. Circuitry within a device performing process 500 may operate in two modes: (1) a mission mode (sometimes referred to as a "functional mode") used during normal operation; and (2) a specific test mode in which some processing related to storage and retrieval of non-mission critical data described herein is performed. In response to determining that a PPR operation has been requested, process 500 switches from the mission mode of operation to the test mode of operation. Determining the location of the defective bit is performed in the test mode of operation. The test mode is different from the mission mode. In the test mode, the host device is unaware that the circuitry (e.g., within a CXL module) is testing and using / reclaiming a memory row that has been disabled by a PPR operation.

[0078] In the test mode, write operations and read operations are performed to determine the location of the defective bit. Known test patterns (e.g., march 1 or gallop 1) are written to the entire disabled row and then read back to determine the erroneous bit in the disabled row. The test mode is also used to write non-mission critical data to the disabled row and read non-mission critical data from the disabled row. When the device 305 or controller 315 writes non-mission critical data to the disabled row in the test mode, the device or controller omits the use of a mask to write to the defective bit position. A mask is generated based on the defective bit position to prevent non-mission critical data from being stored at the defective bit position.

[0079] In some embodiments, to determine defective bit locations, the CXL memory module writes a write data pattern to a memory row, reads a read data pattern from the memory row, and compares the write data pattern and the read data pattern. For example, the CXL memory module writes 10 data patterns to a memory row, and reads 10 data patterns from the memory row. The data patterns written and read may be marching test patterns, galloping test patterns, checkerboard test patterns, Galpat test patterns, or combinations thereof. The CXL module may generate a mask for the memory row to prevent non-mission critical data from being stored at defective bit locations.

[0080] The CXL memory module can determine the number of defective bit positions in each memory row disabled by the PPR operation. The number of defective bit positions can be stored in a non-volatile memory (e.g., reference Figure 3In some embodiments, the CXL module evaluates whether the disabled row has too many defects to be used for storing non-mission critical data. For example, if the number of defective bit positions in the memory row is less than a threshold number, then the memory row is used for storing non-mission critical data. Thus, the disabled row data maintained may be only for disabled rows that have enough non-defective bits for the CXL module to store data (e.g., non-mission critical data).

[0081] At block 516 , process 500 maintains the disabled row data including the physical address associated with the memory row and the determined defective bit location in the non-transitory memory of the CXL memory module.

[0082] Figure 6 6 is a flow chart illustrating a process 600 for writing data to a disabled memory row according to an embodiment of the present technology. Aspects of the process 600 may be performed by, for example, a memory controller, a reference Figure 1 The memory device 100 is illustrated and described in more detail with reference to Figure 3 The device 305 and / or controller 315 are illustrated and described in more detail with reference to Figure 3 The process may be performed by the host device 320 or a combination thereof as described and illustrated in more detail. At least a portion of the process may be performed by a CXL memory module. Likewise, embodiments may include different and / or additional steps, or perform the steps in a different order.

[0083] Process 600 begins at block 604, where process 600 receives a request to write non-mission critical data to a disabled memory row of a memory device. The request may be received from and / or generated by a controller (e.g., a CXL controller) electrically coupled to the memory device. In some embodiments, the non-mission critical data is related to the operation of a host device, a CXL memory module, or a memory device.

[0084] At block 608 , the process identifies disabled memory rows that may store at least a portion of non-mission critical data used to monitor operation of a host device, CXL card, or memory device.

[0085] At block 612, process 600 applies the error mask previously generated based on the defective bit positions of the disabled memory row to the non-mission critical data to generate stored data. The stored data is a version of the non-mission critical data that would actually be stored in the disabled memory row that is generated to avoid the defective bit positions in the disabled memory row.

[0086] At block 616, process 600 writes storage data to physical locations of the disabled memory rows using a test mode sequence (in test mode). At least a portion of non-mission critical data is stored in some disabled memory rows by process 600 for use in monitoring operation of a host device, CXL card, or memory device.

[0087] Although Figure 6 The process 600 for writing non-mission critical data to a disabled memory row is described, but other processes (not shown) may be used to read non-mission critical data from a disabled memory row. For example, a process may receive and / or generate a request to read non-mission critical data from a specified disabled row, generate a read mask using the corresponding disabled row data, etc.

[0088] Figure 7 is a schematic diagram of a system 700 including devices according to an embodiment of the present technology. Figure 1-3 Any of the aforementioned apparatus described (eg, memory devices, CXL memory modules, etc.) may be incorporated into any of a number of larger and / or more complex systems, a representative example of which is Figure 7 Similarly, embodiments of system 700 may include different and / or additional components, or may be connected in different ways.

[0089] System 700 may include a memory device 705, a power supply 710, a driver 715, a processor 720, and / or other subsystems or components 725. Memory device 705 may include generally the same subsystems or components as described above with reference to FIG. Figure 1 The system 700 may be configured to store data in a manner similar to that of the memory device 100 described above. The resulting system 700 may perform any of a wide variety of functions, such as memory storage, data processing, and / or other suitable functions. Thus, the representative system 700 may include, but is not limited to, handheld devices (e.g., mobile phones, tablet computers, digital readers, and digital audio players), computers, vehicles, appliances, servers, and other products. The components of the system 700 may be housed in a single cell or distributed across multiple interconnected cells (e.g., via a communication network). The components of the system 700 may also include remote devices and any of a wide variety of computer-readable media.

[0090] It should be noted that the methods described above describe possible implementations, and that the operations and steps may be rearranged or otherwise modified, and other implementations are possible. Furthermore, embodiments from two or more methods may be combined.

[0091] Although in the above example embodiments, the memory modules and devices have been illustrated and described with respect to DRAM devices, embodiments of the present technology may be applied to other memory technologies, including SRAM, SDRAM, NAND and / or NOR flash, PCM, magnetic RAM (MRAM), ferroelectric RAM (FeRAM), etc. In addition, although the memory module has been illustrated and described as a dual in-line memory module (DIMM) having nine memory devices, embodiments of the present disclosure may include more or fewer memory devices, and / or involve other memory modules or packaging formats (e.g., single in-line memory module (SIMM), small outline DIMM (SODIMM), single in-line pin package (SIPP), custom memory packages, etc.).

[0092] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some figures may illustrate a signal as a single signal; however, one of ordinary skill in the art will appreciate that the signal may represent a bus signal, where the bus may have various bit widths.

[0093] The devices discussed herein, including memory devices, may be formed on a semiconductor substrate or die, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, and the like. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of a semiconductor material on another substrate. The conductivity of a substrate or a sub-region of a substrate may be controlled by doping using various chemical species including, but not limited to, phosphorus, boron, or arsenic. Doping may be performed by ion implantation during the initial formation or growth of the substrate or by any other doping means.

[0094] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. Other examples and implementations are within the scope of the present disclosure and the appended claims. Features implementing the functions may also be physically located at various locations, including being distributed so that parts of the functions are implemented at different physical locations.

[0095] As used herein, including as used in the claims, "or" used in a list of items (e.g., a list of items preceding, for example, "at least one of" or "one or more of") indicates an inclusive list, such that a list of, for example, at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Additionally, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase "based on" should be understood in the same manner as the phrase "based at least in part on."

[0096] It should be understood from the foregoing that specific embodiments of the present invention have been described herein for illustrative purposes, but various modifications may be made without departing from the scope of the present invention. In fact, in the foregoing description, numerous specific details are discussed to provide a thorough and inspiring description of embodiments of the present invention. However, those skilled in the relevant art will recognize that the present disclosure may be practiced without one or more of the specific details. In other cases, well-known structures or operations often associated with memory systems and devices are not shown or described in detail to avoid confusing other aspects of the technology. In general, it should be understood that various other devices, systems, and methods other than those specific embodiments disclosed herein may be within the scope of the present invention.

Claims

1. A computing high-speed link CXL memory module, comprising: Memory device; as well as a controller comprising a non-volatile memory including firmware instructions, wherein the instructions, when executed by the controller, cause the CXL memory module to: determining that a post-package repair (PPR) operation associated with a memory row of the memory device has been requested by a host device communicatively coupled to the CXL memory module; determining a location of a defective bit in the memory row; as well as Disabled row data including an address of the memory row and the location of the defective bit is maintained in the nonvolatile memory.

2. The CXL memory module of claim 1 , wherein determining the location of the defective bit in the memory row comprises: writing a write data pattern into the memory row; reading a read data pattern from the memory row; as well as The write data pattern is compared to the read data pattern.

3. The CXL memory module of claim 1 , wherein the non-volatile memory further comprises instructions for causing the CXL memory module to: receiving non-mission critical data related to operation of at least one of the host device, the CXL memory module, or the memory device; and At least a portion of the non-mission critical data is stored in the memory row for use in monitoring operation of the at least one of the host device, the CXL memory module, or the memory device.

4. The CXL memory module of claim 1 , wherein the disabled row data comprises a mask, and wherein the instruction causes the CXL memory module to: The mask for the memory row is generated based on the determined locations of the defective bits in the memory row.

5. The CXL memory module of claim 1 , wherein the instructions cause the CXL memory module to: determining a number of defective bit locations in the memory row; and The number of defective bit positions is stored in the disabled row data.

6. The CXL memory module of claim 1, wherein the memory device is a byte-addressable volatile or non-volatile media.

7. The CXL memory module of claim 1 , wherein determining that the PPR operation has been requested is performed in a task mode of operation, and Determining the location of the defective bit is performed in a test operation mode different from a mission mode.

8. The CXL memory module of claim 1 , wherein the instructions cause the CXL memory module to: In response to determining that the PPR operation has been requested, switching is performed from the mission operation mode to a test operation mode different from the mission mode.

9. The CXL memory module of claim 1 , wherein determining the location of the defective bit comprises: Writing 10 data patterns into the memory row; as well as The 10 data patterns are read from the memory row.

10. The CXL memory module of claim 1 , wherein the instructions cause the CXL memory module to: determining a number of defective bit locations in the memory row; and A determination is made as to whether the number of defective bit locations is less than a threshold number.

11. A method of operating a memory system, the memory system comprising a controller communicatively coupled to a memory device, the method comprising: determining that a post-package repair (PPR) operation associated with a memory row of the memory device has been requested by a host device; determining a location of a defective bit in the memory row; as well as Disabled row data including an address of the memory row and the location of the defective bit is maintained in a non-volatile memory of the memory system.

12. The method of claim 11, wherein determining the defective bit location comprises: writing a first data pattern to the memory row; reading a second data pattern from the memory row; as well as The first data pattern is compared with the second data pattern.

13. The method according to claim 11, comprising: receiving non-mission critical data related to operation of at least one of the host device, the CXL memory module, or the memory device; as well as At least a portion of the non-mission critical data is stored in the memory row for use in debugging operation of the at least one of the host device, the CXL memory module, or the memory device.

14. The method according to claim 11, wherein the disabled row data comprises a mask, the method comprising The mask for the memory row is generated based on the determined locations of the defective bits in the memory row.

15. The method according to claim 11, comprising: determining a percentage of defective bit positions in the memory row; as well as In response to determining that the percentage is less than a threshold percentage, the memory row is used to store non-mission critical data.

16. A memory controller comprising: a host interface coupled to a host device; a memory array interface coupled to the memory array; as well as A circuit system configured to: determining that a post-package repair (PPR) operation associated with a memory row of the memory array has been requested by a host device communicatively coupled to the host interface; determining a location of a defective bit in the memory row; as well as Disabled row data including an address of the memory row and the location of the defective bit is maintained in a non-transitory memory of the memory controller.

17. The memory controller of claim 15, wherein determining the location of the defective bit comprises: sending a first data pattern to the memory array interface; as well as A second data pattern is received from the memory array interface to compare the first data pattern to the second data pattern.

18. The memory controller of claim 15, wherein the circuitry is configured to: receiving non-mission critical data related to operation of at least one of the host device, the memory controller, or the memory array; and At least a portion of the non-mission critical data is stored in the memory row in a test mode of operation.

19. The memory controller of claim 15, wherein the disabled row data comprises a mask, and wherein the circuitry is configured to: The mask for the memory row is generated based on the determined locations of the defective bits in the memory row.

20. The memory controller of claim 15, wherein the circuitry is configured to: determining a number of defective bit locations in the memory row; and The number of defective bit positions is stored in the disabled row data.

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