Tracking latch inversion events using trim registers

Abstract

Devices, systems, and methods are described for tracking latch inversion events using trim registers. An example method includes reading trim data from a trim register in a non-volatile memory device. The example method may further include generating parity data for the trim data. The example method may further include storing the parity data in the trim register. The example method may further include, after the generation and storage of the parity data, rereading the trim data from the trim register, generating additional parity data, and comparing the parity data to the additional parity data.

Description

Technical Field

[0001] Embodiments of the present disclosure relate generally to semiconductor memory devices, systems, and methods, and more particularly, to devices, systems, and methods related to tracking latch rollover events using a trim register. Background Art

[0002] Memory devices are typically provided as internal semiconductor integrated circuits in computers or other electronic systems. There are many different types of memory, including volatile and non-volatile memory. Volatile memory may require power to maintain its data (e.g., host data, error data, etc.), and includes random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), and synchronous dynamic random access memory (SDRAM), etc. Non-volatile memory can provide persistent data by retaining stored data when not powered, and may include NAND flash memory, NOR flash memory, and resistance variable memory, such as phase change random access memory (PCRAM), resistive random access memory (RRAM), and magnetoresistive random access memory (MRAM), such as spin torque transfer random access memory (STT RAM), etc.

[0003] The memory devices may be coupled to a host (e.g., a host computing device) to store data, commands, and / or instructions used by the host while the computer or electronic system is operating. For example, during operation of the computing or other electronic system, data, commands, and / or instructions may be transferred between the host and the memory device(s). Summary of the invention

[0004] In one aspect, the present disclosure relates to a method for tracking latch rollover events, comprising: reading trimming data from a trimming register in a non-volatile memory device; generating parity data for the trimming data; storing the parity data in the trimming register; and after the generation and storage of the parity data: rereading the trimming data from the trimming register; generating additional parity data; and comparing the parity data with the additional parity data.

[0005] In another aspect, the present disclosure relates to an apparatus for tracking latch flipping events, comprising: a first memory device comprising a trim register configured to store trim data; a second memory device coupled to the first memory device; and a controller coupled to the first memory device and the second memory device, the controller being configured to: read a first set of trim data from the first memory device; read a second set of trim data from the second memory device; compare the first set of trim data with the second set of trim data; and overwrite the first set of trim data in the first memory device with the second set of trim data in the second memory device in response to the first set of trim data being different from the second set of trim data.

[0006] In yet another aspect, the present disclosure relates to an apparatus for tracking latch flipping events, comprising: a memory device, comprising: a static trim register, configured to store static trim data; and a dynamic trim register, configured to store dynamic trim data; and a controller, coupled to the memory device and configured to: read the static trim data from the static trim register; read the dynamic trim data from the dynamic trim register; generate parity data using the static trim data and the dynamic trim data; store the parity data in the static trim register; and after the generation and storage of the parity data: reread the static trim data from the static trim register and reread the dynamic trim data from the dynamic trim register; generate additional parity data; and compare the parity data with the additional parity data. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 An example computing environment including a memory subsystem according to some embodiments of the present disclosure is described.

[0008] Figure 2 is an example memory system for tracking latch rollover events using a trim register according to some embodiments of the present disclosure.

[0009] Figure 3 is a flow chart of an example method for tracking latch rollover events using a trim register according to some embodiments of the present disclosure.

[0010] Figure 4 is a flow chart of an example method for tracking latch rollover events using a trim register according to some embodiments of the present disclosure.

[0011] Figure 5 is a flow chart of an example method for tracking latch rollover events using a trim register according to some embodiments of the present disclosure.

[0012] Figure 6 is a block diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0013] An apparatus, system, and method for tracking latch flipping events using a trim register are described. The memory device may be a non-volatile memory device. An example of a non-volatile memory device is a flash memory system. Figure 1 Other examples of non-volatile memory devices are described. A memory device may include physical blocks (eg, sets of data) of memory cells. A memory device may be coupled to a controller within a memory subsystem.

[0014] The memory subsystem may be a memory system, a memory device, a memory module, or a combination thereof. Figure 1 Examples of storage devices and memory modules are described. In general, a host system may utilize a memory subsystem that includes one or more memory components (hereinafter also referred to as a "memory device"). The host system may provide data to be stored at the memory subsystem and may request data to be retrieved from the memory subsystem.

[0015] A memory operation (e.g., a read, write, or other memory operation) may be initiated to read data from a memory device of the memory subsystem and / or to write data to store data in a memory device of the memory subsystem. A controller of the memory subsystem may access (several) fine tuning registers stored within the memory device. (Several) fine tuning registers may store fine tuning data. Fine tuning data refers to data stored in fine tuning registers, which are registers in a memory device that store factory settings that govern the operation of the device. A portion of the fine tuning data may be used to indicate which blocks of data in the memory device are no longer considered "in use" and may therefore be erased internally. The fine tuning data may enable the memory device to more efficiently handle obsolete item collection, voltage level settings, timing settings, feature enable settings, redundancy settings, and address mapping, among other such operations, which may otherwise slow down subsequent write operations to the associated blocks. In some examples, a latch flip event may introduce errors into the fine tuning data in (several) fine tuning registers in the memory device (e.g., a latch flip event may cause bits of the fine tuning data to flip or change and therefore become inaccurate). For example, trimming data used to indicate which blocks are no longer in use (or in the alternative, which blocks are in use and should not be erased) may be incorrectly flipped by a latch flip event, causing blocks that may still be in use to be indicated as not in use, or conversely, causing blocks that may no longer be in use to be indicated as being in use. This mis-marking may incorrectly allow erasure of blocks that should be prevented from being erased or incorrectly prevent erasure of blocks that should be erased, thereby reducing efficient use of memory blocks and reducing performance of the memory device. In addition, this mis-marking may allow and / or prevent access to blocks in the memory device that should or should not be allowed or prevented and consume additional memory resources to correct errors or use the blocks in a manner that should not occur.

[0016] Aspects of the present disclosure address the above shortcomings by generating parity data using trimming data stored in (several) trimming registers. The parity data may be a cyclic redundancy check (CRC). A cyclic redundancy check (CRC) refers to an error detection code commonly used in digital networks and storage devices to detect unexpected changes to original data. However, embodiments are not limited thereto and other error detection methods may be used. Data blocks entering these systems may obtain an additional short check value based on the remainder of a polynomial division of their contents. Upon retrieval, the calculation may be repeated and in the event that the check values ​​do not match, corrective measures may be taken for data corruption. For example, a first set of parity data generated using trimming data may be the same data (e.g., matching data) as a second set of parity data subsequently generated using trimming data (which may have changed due to the occurrence of a latch flip event and / or other event). Similarly, due to the trimming data changing over time or being affected by a latch flip event, the first set of parity data generated using trimming data may be different data (e.g., non-matching data) from a second set of parity data subsequently generated.

[0017] CRC can be used in error correction systems to detect errors. In addition, it can be called CRC because the check (data verification) value is redundant (it extends the message without adding information) and can be based on cyclic codes. CRC can be used because they are easy to implement in binary hardware, easy to analyze, and are particularly good at detecting common errors caused by noise in the transmission channel. Because the check value has a fixed length, the generated function can be used as a hash function. Parity data generated from the fine-tuning data can be stored in (several) fine-tuning registers and / or additional memory locations. During the operation of the memory device, subsequent parity data values ​​can be generated from the currently stored fine-tuning data (for example, during CRC data verification), thereby tracking whether the fine-tuning data has been changed or modified. The change or modification of the fine-tuning data may be attributed to the previously mentioned latch reversal event. Therefore, the parity data verification can track the occurrence of the latch reversal event. In another example, the static fine-tuning data stored in (several) static fine-tuning registers and the dynamic fine-tuning data stored in (several) dynamic fine-tuning registers can be used to generate parity data. While using the parity data to provide better coverage, the parity data may be updated in response to the dynamic trimming data being changed.

[0018] In an example, aspects of the present disclosure may address the above shortcomings by tracking latch flip events by comparing trim data in trim registers with trim data stored in a one-time programmable (OTP) memory. In this manner, differences (e.g., mismatches or mismatches) in trim data in trim registers and trim data stored in the OTP memory may indicate that a latch flip event has occurred. To correct the latch flip event, the controller may cause the trim data stored in the OTP memory to be transferred to the trim registers of the memory device to correct errors in the trim data of the trim registers. The latch flip event may be caused by a neutron strike. As used herein, the term "neutron strike" refers to the interaction between one or more neutrons and components of a memory device. The components may include, but are not limited to, a memory cell array, a latch, and logic circuitry. Errors may include, but are not limited to, changing a memory address stored in a latch or flipping a data bit. A processor coupled on or to the memory device may include an error correction code (ECC) circuitry to correct errors. However, if the number of errors exceeds the ability of the ECC circuit to correct the errors, the memory device may function improperly.

[0019] Figure 1 An example computing system 100 is illustrated that includes a memory subsystem 110 according to some embodiments of the present disclosure. The memory subsystem 110 may include media, such as one or more non-volatile memory devices (e.g., memory device 130). In other embodiments, the memory subsystem 110 may include volatile memory devices (e.g., memory device 140) and / or a combination of volatile memory devices and non-volatile memory devices.

[0020] The memory subsystem 110 may be a storage device, a memory module, or a hybrid of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage (UFS) drives, secure digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0021] Computing system 100 may be a computing device such as a desktop computer, a laptop computer, a server, a network server, a mobile device, a vehicle (e.g., an airplane, a drone, a train, a car, or other transportation), an Internet of Things (IoT)-enabled device, an embedded computer (e.g., a computer included in a vehicle, industrial equipment, or a networked business device), or such a computing device that includes a memory and a processing device.

[0022] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to memory subsystems 110 of different types. Figure 1 An example of a host system 120 coupled to one memory subsystem 110 is illustrated. As used herein, "coupled to" or "coupled with" generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical connections, optical connections, magnetic connections, and the like.

[0023] The host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an SSD controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 120 uses the memory subsystem 110, for example, to write data to the memory subsystem 110 and read data from the memory subsystem 110.

[0024] The host system 120 may be coupled to the memory subsystem 110 via a physical host interface. Examples of the physical host interface include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), a Small Computer System Interface (SCSI), a Double Data Rate (DDR) memory bus, a Dual In-line Memory Module (DIMM) interface (e.g., a DIMM slot interface supporting Double Data Rate (DDR)), an Open NAND Flash Interface (ONFI), Double Data Rate (DDR), Low Power Double Data Rate (LPDDR), or any other interface. The physical host interface may be used to transfer data between the host system 120 and the memory subsystem 110. When the memory subsystem 110 is coupled to the host system 120 through a PCIe interface, the host system 120 may further utilize an NVM Express (NVMe) interface to access components (e.g., memory devices 130, 140). The physical host interface may provide an interface for passing control, address, data, and other signals between the memory subsystem 110 and the host system 120 . Figure 1 Memory subsystem 110 is illustrated. In general, host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0025] The memory devices 130, 140 may include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM). Some examples of non-volatile memory devices (e.g., memory device 130) include non-and (NAND) type flash memory and write-in-place memory, such as a three-dimensional cross-point ("3D cross-point") memory device, which is a cross-point array of non-volatile memory cells. The cross-point array of non-volatile memory can perform bit storage based on changes in body resistance in combination with a stackable cross-grid data access array. In addition, compared to many flash-based memories, cross-point non-volatile memory can perform write-in-place operations, where non-volatile memory cells can be programmed without first erasing non-volatile memory cells. NAND-type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0026] The memory device 130 may include one or more arrays of memory cells. One type of memory cell, such as a single level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cells (MLC), three-level cells (TLC), four-level cells (QLC), and five-level cells (PLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, PLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion, an MLC portion, a TLC portion, a QLC portion, or a PLC portion of a memory cell. The memory cells of the memory device 130 may be grouped into pages, which may refer to a logical unit of a memory device used to store data. For some types of memory, such as NAND, pages may be grouped to form blocks.

[0027] The memory device 130 may include a trim register ("register") 132. The trim register 132 may store factory settings that govern the operation of the device. The data stored within the trim register may be referred to as trim data. Examples include, but are not limited to, voltage level settings, timing settings, feature enable settings, redundancy settings, and address mappings. The trim data stored in the trim register 132 may indicate whether a block in the memory device 130, 140 is in use and therefore whether the block is allowed to be erased. The trim register 132 may store trim data that is transferred or written from a block in the memory device 130 and / or stored in the trim register 132 by the subsystem controller 115. In some examples, the trim data stored in the trim register 132 is the same as the trim data stored in the OTP 113. In some examples, the trim data stored in the trim register 132 has been corrupted or has undergone a latch flip event, as described herein. The latch flip event may cause the trimming data stored in the trimming register 132 to be corrupted or flip bits of the trimming data or store data that is different from the trimming data stored in the OTP 113. The OTP memory 113 may store trimming data that is unchanged and / or incorruptible. In response to the trimming data in the trimming register 132 being different from the trimming data in the OTP 113, the trimming data stored in the OTP memory 113 may be loaded into the trimming register 132 to correct the error introduced by the latch flip event.

[0028] The trim register 132 of the memory device 130 may include parity data 134. The parity data 134 may be generated using trim data stored in another location of the trim register 132. For example, the parity data may be generated using the trim data in the trim register 132. In some examples, the parity data 134 may be generated using a static trim register storing static trim data and a dynamic trim register storing dynamic trim data. In this way, a wider coverage of parity data protection may be performed. However, in this example, the parity data 134 may be updated whenever the dynamic trim data is changed or updated.

[0029] Parity data 134 may be stored in trim register 132 for comparison during subsequent parity checks performed on the trim data. For example, a subsequent parity data value may be generated using the trim data stored in trim register 132 and the subsequently generated parity data value may be compared to parity data 134. In response to parity data 134 matching a subsequently generated parity data value (e.g., being the same as a previously generated parity data), it may be determined that the trim data has not changed or has not undergone a latch flip event. Additionally, in response to parity data 134 not matching a subsequently generated parity data value, it may be determined that the trim data has changed or has undergone a latch flip event.

[0030] Although a non-volatile memory component such as a NAND-type memory (e.g., 2D NAND, 3D NAND) is described, the memory device 130 may be based on any other type of non-volatile memory or storage device, such as read-only memory (ROM), phase-change memory (PCM), self-select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), non-OR (NOR) flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0031] In some embodiments, the memory subsystem 110 includes at least a portion of the OTP memory 113. For example, the memory subsystem controller 115 may communicate with the portion of the OTP memory 113 within the memory subsystem 110 to perform the operations described herein. Trimming data may be stored in the OTP memory 113. A portion of the trimming data may be used to indicate whether a particular memory block in the memory devices 130, 140 is in use and should therefore be prevented from being erased or is not in use and therefore may be erased without causing problems with the memory operations of the memory devices 130, 140.

[0032] The memory subsystem controller 115 (or simply controller 115) can communicate with the memory devices 130, 140 to perform operations such as reading data, writing (e.g., programming) data, or erasing data and other such operations at the memory devices 130, 140. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The hardware may include digital circuitry with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor.

[0033] The memory subsystem controller 115 may include a processing device configured to execute instructions stored in a local memory 119, which may include one or more processors (e.g., processor 117). In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes an embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120. For example, the processor 117 (e.g., a processing device) may be configured to execute instructions stored in the local memory 119 for performing the operations described herein to read and / or write to memory blocks within the memory device 130 and / or read from the OTP 113.

[0034] The memory subsystem controller 115 may include a comparison component 131. The comparison component 131 may include hardware, firmware, and / or circuitry for comparing parity data with subsequently generated parity data. The comparison component 131 may compare initially generated parity data 134 with subsequently generated parity data during a specific time interval or period of time in order to perform parity checks on the trimming data at regular time intervals.

[0035] In some embodiments, local memory 119 may include memory registers that store memory pointers, fetched data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Figure 1 The example memory subsystem 110 in FIG. 1 has been described as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but may rely on external control (e.g., provided by an external host, or provided by a processor or controller separate from the memory subsystem).

[0036] In general, the memory subsystem controller 115 may receive commands or operations from the host system 120 and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130 and / or the memory device 140. The memory subsystem controller 115 may be responsible for other operations associated with the memory devices 130, 140, such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation between logical addresses (e.g., logical block addresses (LBA), namespaces) and physical addresses (e.g., physical block addresses, physical media locations, etc.). The memory subsystem controller 115 may further include a host interface circuit system for communicating with the host system 120 via a physical host interface. The host interface circuit system may convert commands received from the host system into command instructions for accessing the memory device 130 and / or the memory device 140, and convert responses associated with the memory device 130 and / or the memory device 140 into information for the host system 120.

[0037] Memory subsystem 110 may also include additional circuitry or components not illustrated. In some embodiments, memory subsystem 110 may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoder and column decoder) that may receive addresses from memory subsystem controller 115 and decode the addresses to access memory device 130 and / or memory device 140.

[0038] In some embodiments, memory device 130 includes a local media controller that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) can manage memory device 130 externally (e.g., perform media management operations on memory device 130). In some embodiments, memory device 130 is a managed memory device, which is a raw memory device combined with a local controller for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0039] The non-volatile memory device 130 may store multiple physical blocks (e.g., sets of data) of memory cells. The multiple physical blocks may be indicated within the trimming data as being in use or not in use in order to keep track of which of the multiple physical blocks may be erased or which should be blocked from being erased. The trimming data may be stored within the OTP memory device 113 within the non-volatile memory device 130 using latches. For example, the OTP memory device 113 may include one or more latches configured to store the trimming data. Although not shown in the figure to avoid obscuring the drawings, the trimming data may be stored within the OTP memory device 113. Figure 11, but the OTP memory device 113 may include various circuit systems to facilitate data storage. For example, the OTP memory device 113 may include dedicated circuit systems in the form of an ASIC, FPGA, state machine, and / or other logic circuit systems that can allow the OTP memory device 113 to store fine-tuned data.

[0040] The stored trim data within the OTP memory device 113 may be compared to the trim data stored in the trim register 132 of the memory device 130. In some examples, the comparison of the trim data in the trim register 132 to the trim data in the OTP 113 may occur at specific time intervals or time periods and / or may be coordinated or associated with specific memory operations or cycle operations associated with erasing memory blocks or waste collection operations. Furthermore, the comparison may occur at specific time intervals or time periods, thereby tracking the occurrence of latch flip events in a repeating pattern. In the event that the comparison of the trim data in the OTP 113 to the trim data in the trim register 132 in the memory device 130 determines a match, the trim data in the memory device 130 may be considered valid (and thus does not need to be loaded or overwritten by the trim data in the OTP 113). Likewise, in the event that the comparison does not determine a match, the trim data may be considered invalid and the trim data stored in the memory device may be overwritten by the trim data in the OTP 113.

[0041] Figure 2 2 is an example memory system 202 for tracking latch rollover events using a trim register according to some embodiments of the present disclosure. The example memory system 202 may include a memory subsystem controller 215. The memory subsystem controller 215 may monitor memory blocks 234-1, 234-2, ..., 234-N (hereinafter collectively referred to as memory blocks 234) within the non-volatile memory device 230 and provide an input for trim data indicating whether any of the memory blocks 234 is in use. The trim data may be stored in the OTP memory device 213 (e.g., similar to Figure 1 13) and / or within a trim register 232 of a memory device 230. Although only a portion of a block of memory cells is illustrated, embodiments are not so limited, and portions of an unlimited number of memory blocks may be within a non-volatile memory device, whose associated trim data may be stored in part or in whole within the OTP memory device 213. The trim data may indicate whether a particular memory block is to be used for erase and / or obsolete item collection purposes. For example, the trim data may indicate whether a block may be read, erased, programmed, or written without generating or inserting errors (e.g., without incurring an amount of errors that exceeds the error correction capability associated with the OTP memory device 213).

[0042] A latch flip event may be defined as an event that causes a latch to be unexpectedly enabled. For example, a latch flip event may flip a latch of trimming data within the memory device 230. A latch flip event may prevent the controller 215 from accessing data within a particular block due to the trimming data being inaccurate or no longer valid. For example, a block that is in use and should not be erased may be erased if the trimming data incorrectly indicates that the block is not in use, and vice versa.

[0043] The controller 215 may include a comparison component 231 (e.g., similar to Figure 1 2. The comparison component 231 in the memory device 230 may be used to compare the trimming data stored in the trimming register 232 of the memory device 230 with the trimming data stored in the OTP memory device 213. In this manner, it may be determined whether the trimming data has changed from a first point in time to a second point in time. In this manner, it may be verified whether the trimming data in the trimming register 232 is correct or incorrect and / or the occurrence of a latch rollover event may be determined. In addition, the comparison component 231 may be used to compare the parity data 236 previously generated using the trimming data at a first point in time with the parity data value subsequently generated using the current trimming data at a second point in time.

[0044] Comparison of the trim data and / or parity data 236 may indicate that a latch reversal event has occurred. For example, when there is a difference between the trim data in the trim register 232 and the trim data in the OTP 113 or between the parity data at a first point in time and the parity data at a second point in time, it may be determined that an error has occurred. In one example, a latch reversal event may be caused by a neutron collision (e.g., referred to as a neutron strike) of a latch within the memory device 230 by a silicon particle. The silicon particle may attract charge and change the data within the latch. In another example, a latch reversal event may be caused by a neutron collision of an alpha particle with a latch. However, embodiments are not limited thereto, and any event that causes a neutron collision with a latch may cause a latch reversal event. In response to the comparison of the trim data or the parity data being different values, a flag may be set by the controller 215. Furthermore, reloading or overwriting of the trimming data in the trimming register 232 of the memory device 230 may be performed by transferring the trimming data in the OTP memory device 213 to the trimming register 232 .

[0045] Figure 3is a flow chart corresponding to an example method 341 for tracking latch rollover events using a trim register according to some embodiments of the present disclosure. The method 341 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 341 is respectively performed by Figures 1 to 2 The memory subsystem controllers 115 and 215 of the present invention are executed. Although shown in a particular order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood to be examples only, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0046] At operation 342, method 341 includes reading the trimming data from a trimming register in a non-volatile memory device. The trimming register may be similar to Figures 1 to 2 The fine tuning registers 132 and 232 in FIG. The non-volatile memory device may be similar to Figures 1 to 2 130 and 230 in the memory devices 130 and 230. Trimming data refers to data used to indicate which blocks of data in the memory device are no longer considered "in use" and can therefore be erased internally. Trimming data enables the memory device to more efficiently handle obsolete item collection and other such operations that might otherwise slow down subsequent write operations to the associated blocks. In some examples, a latch flip event can introduce errors into the trimming data in the trimming register(s) in the memory device (e.g., a latch flip event can cause bits of the trimming data to flip or change and thus become inaccurate).

[0047] At operation 343, method 341 includes generating parity data for the trimming data. Data blocks for parity data may have a short check value attached based on the remainder of a polynomial division of their contents. Upon retrieval, the calculation may be repeated and in the event of a mismatch in the check values, corrective action may be taken for data corruption. Parity data may be used in an error correction system to detect errors.

[0048] At operation 344, method 341 includes storing parity data in a fine-tuning register. For example, the parity data may be stored in a portion of the fine-tuning register that is different from the portion in which the fine-tuning data is stored. In this way, the parity data may be stored in a location similar to the fine-tuning data protected by the parity data. At operation 345, method 341 includes rereading the fine-tuning data from the fine-tuning register. The fine-tuning data may be reread at a later time point or time period than when the fine-tuning data was initially read to generate the parity data. For example, the fine-tuning data may be read at a first time point and the initial parity data may be generated from the fine-tuning data read at the first time point. The fine-tuning data may be reread or read again at a second time point later than the first time point.

[0049] At operation 346, method 341 includes generating additional parity data. The additional parity data may be generated from the trimming data that is reread or read again at a second point in time. At operation 347, method 341 includes comparing the parity data with the additional parity data. For example, the parity data stored in the trimming register may be compared with the additional parity data generated from reading the trimming data again or reading the trimming data at a later point in time. In this manner, the parity data in the trimming register may be compared with the additional parity data to determine whether a latch rollover event has occurred and / or to determine whether to reload the trimming data from a trusted location (e.g., from an OTP memory storing trimming data that cannot be changed) or to perform error correction on the trimming data (if possible).

[0050] In some example methods, the trim data may be determined to be valid in response to the parity data matching the additional parity data. In some example methods, the trim data may be determined to be invalid in response to the parity data being different from the additional parity data. In some example methods, a latch flip event may be determined to have affected the trim data in response to the parity data being different from the additional parity data. In some example methods, valid trim data may be reinitialized to the trim register in response to the parity data being different from the additional parity data. In some example methods, a flag indicating that a latch flip event has occurred in the trim register may be set in response to the parity data being different from the additional parity data (e.g., a bit may be flipped to indicate that a latch flip event has occurred). In some examples, setting the flag may be sent to an external device. The external device may be a host and / or a user. In some examples, determining that a latch flip event has occurred may include determining that a neutron strike has occurred on the trim data in the trim register.

[0051] Figure 4is a flow chart corresponding to an example method 450 for tracking latch rollover events using a trim register according to some embodiments of the present disclosure. The method 450 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 450 is respectively performed by Figures 1 to 2 The memory subsystem controllers 115 and 215 of the present invention are executed. Although shown in a particular order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood to be examples only, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0052] At operation 452, method 450 includes reading a first set of trimming data from a first memory device. The first memory device may be similar to Figures 1 to 2 The method 450 includes a non-volatile memory device (NVM) of the non-volatile memory (NVM) device 130 and the non-volatile memory device 230 in the first memory device. The first memory device may include a trim register configured to store the trim data. At operation 454, the method 450 includes reading a second set of trim data from the second memory device. The second memory device may be an OTP memory. The OTP memory may be similar to Figures 1 to 2 The OTP memory devices 113 and 213 in.

[0053] At operation 456, method 450 includes comparing the first set of trimming data with the second set of trimming data. In some examples, the controller may cause a flag to be set in response to the first set of trimming data being different from the second set of trimming data to indicate the occurrence of a neutron strike. The setting of the flag may refer to changing a data bit to indicate that a neutron strike has occurred. The flag may be accessed by a user of the data, a system monitoring the data, etc. In response to detecting that the flag is set, additional measures may be taken to correct the neutron strike event or determine that a grouping of neutron strikes or a pattern of neutron strikes may be caused by a specific event or series of events that may need to be addressed. Conversely, it may be determined that there is no neutron strike on the non-volatile memory in response to the first set of trimming data matching the second set of trimming data. In addition, in some examples, the trimming data may be determined to be invalid trimming data in response to the first set of trimming data being different from the second set of trimming data. In some examples, the first set of trimming data may be maintained (e.g., not changed, not overwritten) in response to the first set of trimming data matching the second set of trimming data.

[0054] At operation 458, method 450 includes overwriting the first set of trimming data in the first memory device with the second set of trimming data in the second memory device. For example, the first set of trimming data may be overwritten with the second set of trimming data in response to the first set of trimming data being different from the second set of trimming data based on the comparison at 456.

[0055] Figure 5 is a flow chart corresponding to an example method 551 for tracking latch rollover events using a trim register according to some embodiments of the present disclosure. The method 551 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 551 is respectively performed by Figures 1 to 2 The memory subsystem controllers 115 and 215 of the present invention are executed. Although shown in a particular order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood to be examples only, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0056] At operation 553, method 551 includes reading static fine-tuning data from a static fine-tuning register. A static fine-tuning register refers to a fine-tuning register that does not change over time (e.g., does not change dynamically). At operation 555, method 551 includes reading dynamic fine-tuning data from a dynamic fine-tuning register. A dynamic fine-tuning register refers to a fine-tuning register that changes over time (e.g., changes dynamically) in response to environmental changes or when data is read or written in different portions of memory. For example, a dynamic fine-tuning register may store dynamic fine-tuning data that changes over time as the memory system performs memory operations. Although Figures 1 to 2 A single fine tuning register (eg, fine tuning registers 132 and 232) is illustrated in FIG, but the example is not limited thereto. The fine tuning registers may be divided into static fine tuning registers and dynamic fine tuning registers to store static fine tuning data and dynamic fine tuning data, respectively.

[0057] At operation 557, method 551 includes generating parity data using static fine-tuning data and dynamic fine-tuning data. Parity data can be used to protect both static fine-tuning data and dynamic fine-tuning data and provide a wider coverage of protection for the fine-tuning data. At operation 559, method 551 includes storing parity data in static fine-tuning registers. At operation 561, method 551 includes rereading static fine-tuning data from static fine-tuning registers and rereading dynamic fine-tuning data from dynamic fine-tuning registers. The static and dynamic fine-tuning data can be reread at a later time point or time period than when the initial static fine-tuning data and dynamic fine-tuning data were initially read to generate parity data. For example, static fine-tuning data and dynamic fine-tuning data can be read at a first time point, and initial parity data can be generated from the static fine-tuning data and dynamic fine-tuning data read at the first time point. The static fine-tuning data and dynamic fine-tuning data can be reread or read again at a second time point later than the first time point. Since the dynamic trim data changes over time, the parity data stored in the static trim registers may be updated in response to the dynamic trim data changes.

[0058] At operation 563, method 551 includes generating additional parity data. The additional parity data may be generated from the static trim data and the dynamic trim data that are reread or read again at a second point in time. At operation 565, method 551 includes comparing the parity data with the additional parity data. For example, the parity data stored in the static trim register may be compared with the additional parity data generated from reading the static trim data and the dynamic trim register again or reading the static trim data and the dynamic trim register at a later point in time. In this manner, the parity data in the static trim register may be compared with the additional parity data to determine whether a latch flip event has occurred, and / or to determine whether to reload the static trim data and / or the dynamic trim data from a trusted location (e.g., from an OTP memory storing trim data that cannot be changed) or to perform error correction on the static trim data and / or the dynamic trim data (if possible).

[0059] In some examples, the static fine-tuning data and the dynamic fine-tuning data may be determined to be valid in response to the parity data matching the additional parity data. In some examples, at least one of the static fine-tuning data and the dynamic fine-tuning data may be determined to be invalid in response to the parity data being different from the additional parity data. In some examples, in response to the parity data being different from the additional parity data, it may be determined that a latch flip event has affected the static fine-tuning data and the dynamic fine-tuning data. In response to the determination of the latch flip event, the static fine-tuning data in the static fine-tuning register and the dynamic fine-tuning data in the dynamic fine-tuning register may be reinitialized. For example, error correction may be performed on the static fine-tuning data and the dynamic fine-tuning data and / or trusted fine-tuning data may be reloaded into the static fine-tuning register and the dynamic fine-tuning register. In some examples, the parity data may be updated in response to the dynamic fine-tuning data changing. In some examples, the dynamic fine-tuning data may be periodically checked to determine whether the dynamic fine-tuning data has changed.

[0060] Figure 6 An example machine illustrating a computer system 600 in which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In some embodiments, the computer system 600 may correspond to a host system (e.g., Figure 1 1) a host system 120 that includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The machine may be connected (e.g., using a network) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine may operate as a server or a client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

[0061] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Furthermore, while a single machine is described, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0062] The example computer system 600 includes a processing device 602, a main memory 604 (e.g., a read-only memory (ROM), a flash memory, a dynamic random access memory (DRAM) (e.g., synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), etc.), a static memory 606 (e.g., a flash memory, a static random access memory (SRAM), etc.), and a data storage system 618, which communicate with each other via a bus 633. The processing device 602 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, or the like. More specifically, the processing device can be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets or a processor that implements a combination of instruction sets. The processing device 602 can also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. The processing device 602 is configured to execute instructions 626 for performing the operations and stages discussed herein. The computer system 600 may further include a network interface device 608 for communicating over a network 620.

[0063] The data storage system 618 may include a machine-readable storage medium 624 (also referred to as a computer-readable medium) having stored thereon one or more sets of instructions 626 or software embodying any one or more of the methodologies or functionality described herein. The instructions 626 may also reside, completely or at least partially, within the main memory 604 and / or within the processing device 602 during execution by the computer system 600, the main memory 604 and the processing device 602 also constituting machine-readable storage media. The machine-readable storage medium 624, the data storage system 618, and / or the main memory 604 may correspond to Figure 1 Memory subsystem 110.

[0064] In one embodiment, the instructions 626 include instructions to implement functionality using data stored in the OTP memory device 613. Although the machine-readable storage medium 624 is shown as a single medium in the example embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions for execution by a machine and causing the machine to perform any one or more methodologies of the present disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but not be limited to, solid-state memory, optical media, and magnetic media.

[0065] Some portions of the foregoing detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the art of data processing to most effectively convey the substance of their work to others skilled in the art. An algorithm is herein and generally considered to be a self-consistent sequence of operations leading to a desired result. The operations are those requiring physical manipulation of physical quantities. Typically, although not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, primarily for common sense reasons, to refer to these signals as bits, values, elements, symbols, characters, items, numbers, or the like.

[0066] It should be remembered, however, that all of these and similar terms are associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may be directed to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0067] The present disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specially constructed for the intended purpose, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. This computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0068] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general purpose systems may be used with programs according to the teachings herein, or it may prove convenient to build more specialized equipment to perform the methods. The structures of a variety of these systems will appear as described in the following description. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages ​​may be used to implement the teachings of the present disclosure as described herein.

[0069] The present disclosure may be provided as a computer program product or software that may include a machine-readable medium having instructions stored thereon, which instructions may be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage component, a flash memory component, etc.

[0070] In the foregoing description, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made to the present disclosure without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. Accordingly, the description and drawings should be regarded in an illustrative rather than a restrictive sense.

Claims

1. A method for tracking latch flipping events, comprising: reading trimming data from a trimming register (132, 232) in a non-volatile memory device (130, 230); generating parity data (134, 236) for the fine-tuning data; storing the parity data (134, 236) in the fine tuning register (132, 232); and After said generation and storage of said parity data (134, 236): rereading the fine-tuning data from the fine-tuning register (132, 232); generating additional parity data (134, 236); and The parity data (134, 236) is compared to the additional parity data. 2 . The method of claim 1 , wherein the trimming data is determined to be valid in response to the parity data matching the additional parity data.

3. The method of claim 1 , wherein in response to the parity data being different from the additional parity data: Determining that the fine-tuning data is invalid; and Reinitialize the valid trim data into the trim register.

4. The method of claim 1 , wherein in response to the parity data being different from the additional parity data, a flag is set to indicate that the latch rollover event has occurred in the trimming register and the set flag is sent to an external device.

5. A device for tracking latch flipping events, comprising: a first memory device (130, 230) comprising a trim register (132, 232) configured to store trim data; a second memory device (113, 213) coupled to the first memory device (130, 230); and A controller (115, 215) coupled to the first memory device (130, 230) and the second memory device (113, 213), the controller (115, 215) being configured to: reading a first set of trimming data from the first memory device (130, 230); reading a second set of fine-tuning data from the second memory device (113, 213); comparing the first set of fine-tuned data with the second set of fine-tuned data; and In response to the first set of trimming data being different from the second set of trimming data, the first set of trimming data in the first memory device (130, 230) is overwritten with the second set of trimming data in the second memory device (113, 213).

6. The apparatus of claim 5, wherein the first memory device is a non-volatile memory device and the second memory device is a one-time programmable (OTP) memory device.

7. The apparatus of any one of claims 5-6, wherein the controller is configured to determine that a latch flip event has occurred in the trim register in response to the first set of trim data being different from the second set of trim data.

8. The apparatus of claim 7, wherein the controller is configured to: determining that a neutron strike has occurred on the first set of trimming data in response to determining that the latch flip event has occurred; and A flag indicating the occurrence of a neutron strike is set in response to determining that the latch flip event has occurred in the fine tuning register.

9. The apparatus of any one of claims 5-6, wherein the controller is configured to determine that the trimming data is invalid trimming data in response to the first set of trimming data being different from the second set of trimming data.

10. The apparatus of any one of claims 5 to 6, wherein the controller is configured to, in response to the first set of fine-tuning data matching the second set of fine-tuning data: Maintaining the first set of fine-tuning data unchanged; and An absence of neutron strikes on the fine tuning register is determined.

11. An apparatus for tracking latch flipping events, comprising: A memory device (130, 230) comprising: a static trim register configured to store static trim data; and a dynamic trim register configured to store dynamic trim data; and A controller (115, 215) coupled to the memory device (130, 230) and configured to: Read the static fine-tuning data from the static fine-tuning register; Read the dynamic fine-tuning data from the dynamic fine-tuning register; generating parity data (134, 236) using the static fine-tuning data and the dynamic fine-tuning data; storing the parity data (134, 236) in the static fine tuning register; and After said generation and storage of said parity data (134, 236): rereading the static trimming data from the static trimming register and rereading the dynamic trimming data from the dynamic trimming register; generating additional parity data (134, 236); and The parity data (134, 236) is compared to the additional parity data (134, 236).

12. The apparatus of claim 11, wherein the controller is configured to determine that the static trimming data and the dynamic trimming data are valid in response to the parity data matching the additional parity data.

13. The apparatus of claim 11, wherein the controller is configured to determine that at least one of the static fine-tuning data and the dynamic fine-tuning data is invalid in response to the parity data being different from the additional parity data.

14. The apparatus of claim 11, wherein the controller is configured to, in response to the parity data being different from the additional parity data: determining that a latch flip event has affected the static trimming data and the dynamic trimming data; and The static fine-tuning data in the static fine-tuning register and the dynamic fine-tuning data in the dynamic fine-tuning register are reinitialized.

15. The apparatus of claim 11, wherein: The controller is configured to update the parity data in response to the dynamic trimming data changing; and The controller is configured to periodically check the dynamic trim data to determine if the dynamic trim data has changed.

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