A memory chip testing method and testing device

Abstract

The present invention provides a test method and a test device for a storage chip, belonging to the field of storage technology. The test method for the storage chip includes the following steps: writing fill data into the storage chip until the memory is filled with the fill data; enabling the cache function of the storage chip and writing test data into the storage chip, wherein the data format of the test data in each data unit is related to the writing order, and the data format of the test data written in each data unit is the same; when the amount of the test data written into the storage chip reaches a set threshold, disconnecting the power supply of the storage chip during the process of writing the test data into the storage chip; and obtaining the capacity of the write cache according to the test data finally written in the memory and the test data finally written in the write cache. Through the test method and the test device for the storage chip provided by the present invention, the capacity of the write cache can be obtained.

Description

Technical Field

[0001] The present invention belongs to the field of storage technology, and particularly relates to a test method and a test device for a storage chip. Background Art

[0002] Solid-state memory is a new type of storage device. Multiple storage chips can be made using solid-state memory, such as storage chips including solid-state drives, embedded multimedia cards, universal flash storage, security cards, etc. A controller, a buffer, and a memory are provided in the storage chip, and the cost of the buffer is much higher than that of the memory.

[0003] When conducting competitive product analysis, it is necessary to evaluate the capacity of the buffer. Although the size of the internal buffer can be detected by physical means such as X-rays. However, the cost of this means is relatively high, and the size of specific types of buffers in the buffer cannot be obtained, such as the size of the write buffer. Summary of the Invention

[0004] The purpose of the present invention is to provide a test method and a test device for a storage chip, which can solve the problem of being unable to effectively obtain the size of specific types of buffers in the storage chip.

[0005] To achieve the above purpose, the present invention provides a test method and a test device for a storage chip, and the test method for the storage chip at least includes the following steps:

[0006] Write fill data into the storage chip until the memory is filled with the fill data;

[0007] Enable the cache function of the storage chip, and write test data into the storage chip. The data format of the test data in each data unit is related to the writing order, and the data format of the test data written in each data unit is the same;

[0008] When the amount of the test data written into the storage chip reaches a set threshold, during the process of writing the test data into the storage chip, cut off the power supply of the storage chip; and

[0009] Obtain the capacity of the write buffer based on the last-written test data in the memory and the last-written test data in the write buffer.

[0010] In an embodiment of the present invention, the data format of the fill data is different from that of the test data.

[0011] In an embodiment of the present invention, the value of the fill data is greater than the number of data units in the memory.

[0012] In one embodiment of the present invention, the amount of the padding data written into the storage chip is greater than the total capacity of the memory and the buffer.

[0013] In one embodiment of the present invention, when writing test data into the memory chip, each time the test data of one data unit is written, the value of the test data is increased by one.

[0014] In an embodiment of the present invention, the amount of the test data in each data format is equal to the capacity of the data unit divided by the size of one test data.

[0015] In an embodiment of the present invention, the set threshold is greater than the capacity of the write buffer.

[0016] In one embodiment of the present invention, the capacity of the write buffer is obtained by the following formula:

[0017] T = (mn) × Q;

[0018] Wherein, T is the capacity of the write buffer, m is the value of the test data last written in the write buffer, n is the value of the test data last written in the memory, and Q is the capacity of the data unit.

[0019] In one embodiment of the present invention, the testing method further includes:

[0020] The capacity of the data unit is reduced to regain the capacity of the write buffer.

[0021] The present invention also provides a test device for a memory chip, the test device comprising:

[0022] a memory storing program instructions; and

[0023] A processor runs the program instructions to implement any one of the memory chip testing methods described above.

[0024] In summary, the present invention provides a test method and a test device for a memory chip, in which a host sends fill data to a memory chip to fill up the memory. Then, under the condition that the cache function is turned on, the test data is written into the memory chip. After the test data fills up the write buffer, the memory chip is powered off. According to the test data last written into the write buffer and the test data last sent, the amount of test data stored in the write buffer is obtained, and then the size of the write buffer is obtained. Therefore, through this application, when the internal structure of the memory chip is not clear, the size of the read buffer can be tested more accurately. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] To more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the accompanying drawings required for the description of the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can also be obtained based on these drawings.

[0026] Figure 1 It is a schematic structural diagram of a storage chip in an embodiment of the present application.

[0027] Figure 2 It is a flowchart of a test method for a storage chip in an embodiment of the present application.

[0028] Figure 3 It is a schematic structural diagram of a test device in an embodiment of the application. Detailed implementation manners

[0029] To facilitate the understanding of the present application, the following will describe the present application more comprehensively with reference to the relevant accompanying drawings. The preferred embodiments of the present application are shown in the accompanying drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0030] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs. The terms used in the description of this application herein are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0031] In the description of the present invention, it should be understood that the orientation or positional relationship indicated by terms such as "center", "upper", "lower", "front", "rear", "left", "right", etc. is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or component referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present invention. The degrees indicated by "high", "low", etc. are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or component referred to must have a high or low degree, and therefore cannot be understood as a limitation of the present invention. In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0032] Please refer to Figure 1As shown, in an embodiment of the present invention, compared with traditional disks, the storage chip 200 with Nand flash as the storage medium has the characteristics of non-volatility, fast read and write speed, earthquake resistance, low power consumption, small size, etc., and has been widely used in embedded systems, consumer electronics, aerospace and other fields. According to different protocols for the storage chip 200 to communicate with the host 100, it can be divided into the standard specification of the embedded memory 203 (Embedded Multi Media Card, eMMC), Universal Flash Storage (UFS), Serial ATA (SATA), and peripheral component interconnect express (PCIe), etc.

[0033] Please refer to Figure 1 As shown, in an embodiment of the present invention, the storage chip 200 is provided with a controller 201, a buffer 202, and a memory 203. Among them, the controller 201 can execute multiple logic gates or control instructions implemented in the form of hardware or firmware, and perform operations such as data writing, reading, and erasing in the memory 203 according to the instructions of the host 100.

[0034] Please refer to Figure 1 As shown, in an embodiment of the present invention, the memory 203 is a non-volatile storage unit, and the memory 203 stores data written by the host 100 and other necessary data such as a mapping table. Among them, the memory 203 can be NAND flash, vertical NAND (VNAND), NOR flash, resistive random access memory (RRAM), phase change memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), or spin transfer torque random access memory (STT-RAM). The memory 203 can include a memory cell array block connected to word lines, string selection lines, ground selection lines, and bit lines. The memory 203 can include a super block containing multiple storage blocks. The multiple storage blocks can include multiple pages. The memory 203 can include a two-dimensional (2D) memory cell array block or a three-dimensional (3D) memory cell array block. Other types of non-volatile storage units can also be used. In this embodiment, taking the structure of the NAND flash memory 203 as an example for illustration, the memory 203 includes multiple flash blocks 2031. It can be understood that in other embodiments, the memory 203 can also adopt other types of non-volatile storage unit structures.

[0035] Please refer to Figure 1As shown, in an embodiment of the present invention, the flash memory blocks 2031 in the memory 203 may belong to the same memory 203 die or to different memory 203 dies. Each flash memory block 2031 has a plurality of physical pages respectively, and each physical page has at least one physical sector, wherein the physical pages belonging to the same flash memory block 2031 can be independently written and simultaneously erased. For example, each flash memory block 2031 is composed of 128 physical pages, and each physical page has 8 physical sectors. That is to say, in the example where each physical sector is 512 bytes, the capacity of each physical page is 4 kilobytes (K). However, in an embodiment, each flash memory block 2031 can be composed of 64 physical pages, 256 physical pages or any other number of physical pages.

[0036] Please refer to Figure 1 As shown, in an embodiment of the present invention, the flash memory block 2031 is the smallest unit for erasure. That is, each flash memory block 2031 contains the smallest number of storage units that are erased together. The physical page is the smallest programmable unit. That is, the physical page is the smallest unit for writing data. However, in some embodiments, the smallest unit for writing data may also be a physical sector or other sizes. Each physical page generally includes a data bit area and a redundant bit area. The data bit area is used to store user data, and the redundant bit area is used to store system data (for example, error checking and correction codes).

[0037] Please refer to Figure 1As shown in the figure, in an embodiment of the present invention, the buffer 202 is a high-speed storage device with a faster access speed than the memory 203. The buffer 202 includes a read buffer 2021 and a write buffer 2022. When the caching function of the storage chip 200 is enabled, when the host 100 reads data from the storage chip 200, it first looks for the data in the buffer 202. If the data is found, it is immediately read and sent to the controller 201 for processing. If the data is not found in the buffer 202, it is read from the relatively slower memory 203 and sent to the controller 201 for processing. At the same time, the data block where this data is located is transferred into the cache, so that subsequent reads of the entire data block can be performed from the cache without having to call the memory again. This greatly saves the time for data reading and also enables the controller 201 to basically not wait when reading data. When writing data to the storage chip 200, the written data is first stored in the write buffer 2022, and then a "data has been written" signal is fed back to the host 100. At this time, the host 100 will think that the data has been written. When the write buffer 2022 is full of written data, or the amount of written data in the write buffer 2022 reaches a set threshold, the written data in the write buffer 2022 is then batch-transferred to the memory 203. If the storage chip 200 loses power during data transmission, the data in the write buffer 2022 will be lost.

[0038] Please refer to Figure 1 and Figure 2 As shown in the figure, the present invention provides a test method and a test device for a storage chip, which can obtain the size of the write buffer 2022 in the storage chip 200. Specifically, the test method for the storage chip includes steps S101 to S104.

[0039] Step S101: Write fill data to the storage chip until the memory is filled with the fill data.

[0040] Step S102: Enable the caching function of the storage chip and write test data to the storage chip. The data format of the test data in each data unit is related to the writing order, and the data format of the test data written in each data unit is the same.

[0041] Step S103: When the amount of test data written to the storage chip reaches the set threshold, during the process of writing test data to the storage chip, disconnect the power supply of the storage chip.

[0042] Step S104: Obtain the capacity of the write buffer based on the last-written test data in the memory and the last-written test data in the write buffer.

[0043] Please refer to Figure 1 and Figure 2As shown, in an embodiment of the present invention, in step S101, first, fill data is written into the storage chip 200 until the memory 203 is filled with the fill data. At this time, the cache function of the storage chip 200 is not enabled. In some embodiments, when writing the fill data into the storage chip 200, the written fill data can be directly stored in the memory 203 of the storage chip 200. In other embodiments, when writing the fill data into the storage chip 200, the written fill data can be first stored in the write buffer 2022 and then sent to the memory 203.

[0044] Please refer to Figure 1 and Figure 2 As shown, in an embodiment of the present invention, the data format of the fill data is different from the data format of the data subsequently written into the storage chip 200, so as to avoid confusion when obtaining the capacity of the write buffer 2022 through the data format of the test data subsequently. Since the data format of the test data subsequently written is related to the writing order, and the data format of the test data in each data unit is the same, the maximum value of the test data subsequently written is equal to the number of data units. Therefore, when writing the fill data, setting the value of the fill data to be greater than the number of data units in the memory 203 can ensure that the data format of the fill data is different from the data format of the data subsequently written into the storage chip 200. In a specific embodiment of the present invention, if the size of the memory 203 in the storage chip 200 is 1 GB and the capacity of each data unit is 4 KB, then there are a total of 1 GB / 4 KB = 256K data units in the memory 203. Converted to hexadecimal, there are a total of 0x40000 data units in the memory 203. Then, setting the value of the fill data to be greater than 0x40000 can make the data format of the fill data different from the data format of the test data subsequently written into the storage chip 200. Specifically, the data format of the fill data is, for example, 0xFFFFF, 0x100000, or 0xFFFFFF, etc. In this application, the data format of the fill data is 0xFFFFFFFF for illustration.

[0045] It should be noted that, please refer to Figure 1 and Figure 2 As shown, the data unit is the smallest programmable unit. In this embodiment, the data unit is the size of a physical page, which is 4 KB. And the format of the fill data is 0xFFFFFFFF, and the size of the fill data is 4 B, so 1024 fill data are required to fill one data unit. In other embodiments, the data unit can also be the size of a physical sector, for example, 512 B. Of course, the data unit can also be of other sizes. Then, the number of fill data required to fill one data unit needs to be set according to the capacity of the data unit and the size of the fill data.

[0046] Please refer to Figure 1 andFigure 2 As shown, in an embodiment of the present invention, to ensure that the filling data fills the memory 203, the data volume of the filling data written into the storage chip 200 is greater than the total capacity of the memory 203 and the write buffer 2022. This ensures that even if part of the filling data is stored in the write buffer 2022, the remaining filling data can fill the memory 203.

[0047] Please refer to Figure 1 and Figure 2 As shown, in an embodiment of the present invention, after the filling data fills the memory 203, the cache function of the storage chip 200 is enabled. At this time, the test data written into the storage chip 200 is first stored in the write buffer 2022. When the write buffer 2022 is filled with test data, the test data is then written into the storage chip 200, and the test data that was first written into the write buffer 2022 will be sent down to the memory 203, and the subsequently written test data is stored in the write buffer 2022.

[0048] Please refer to Figure 1 and Figure 2 As shown, in an embodiment of the present invention, when writing test data into the storage chip 200, the data format of the test data in each data unit is related to the writing order, and the data format of the test data written into each data unit is the same. In this embodiment, for each data unit of test data written, the value of the test data is incremented by one, so that the data format of the test data in one data unit is different from the data format of the test data in the previous data unit, while the data format of the test data in the same data unit is the same. And the number of test data of each data format is equal to the capacity of the data unit divided by the size of one test data.

[0049] Specifically, please refer to Figure 1 and Figure 2 As shown, in an embodiment of the present invention, for the test data of the first data format sent to the storage chip 200, if the test data of the first data format is, for example, 0x00000001, then the size of the test data of the first data format is 4B. And the capacity of the data unit is, for example, 4KB. Then 1024 test data of the first data format are sent to the storage chip 200, that is, 1024 0x00000001 are sent to the storage chip 200.

[0050] After sending test data in the first data format of a data unit to the storage chip 200, the value of the test data is incremented by one to form test data in the second data format, and the test data in the second data format is sent to the storage chip 200. For example, if the test data in the second data format is 0x00000002, the size of the test data in the second data format is 4B. The capacity of the data unit is, for example, 4KB. Then, 1024 test data in the second data format are sent to the storage chip 200, that is, 1024 0x00000002 are sent to the storage chip 200.

[0051] Next, 1024 test data in the third data format, 1024 test data in the fourth data format, 1024 test data in the fifth data format, etc. are successively sent to the storage chip 200. That is, 1024 0x00000003, 1024 0x00000004, 1024 0x00000005, etc. are successively sent to the storage chip 200. These test data are first stored in the write buffer 2022. When the write buffer 2022 is filled with test data, the test data in the write buffer 2022 are sent to the memory 203 in the writing order. Then, 1024 test data in the first data format are first sent to the memory 203, and the 1024 test data in the first data format overwrite the padding data in the original data unit. That is, 1024 0x00000001 first overwrite the padding data 0xFFFFFFFF in a data unit in the memory 203.

[0052] Then, as data is written to the input end of the write buffer 2022, the write buffer 2022 sends 1024 test data in the second data format, 1024 test data in the third data format, 1024 test data in the fourth data format, 1024 test data in the fifth data format, etc. to the memory 203. That is, successively, 1024 0x00000002 overwrite the padding data 0xFFFFFFFF in a data unit in the memory 203, 1024 0x00000003 overwrite the padding data 0xFFFFFFFF in a data unit in the memory 203, 1024 0x00000004 overwrite the padding data 0xFFFFFFFF in a data unit in the memory 203, and 1024 0x00000005 overwrite the padding data 0xFFFFFFFF in a data unit in the memory 203, etc.

[0053] Please refer to Figure 1 and Figure 2As shown, in an embodiment of the present invention, in step S103, the set threshold is greater than the capacity of the write buffer 2022. When the amount of test data written to the storage chip 200 is greater than the capacity of the write buffer 2022, the test data in the write buffer 2022 will be sent to the memory 203 according to the writing order of the test data, thereby ensuring that there is test data sent to the memory 203. When sending the test data in the write buffer 2022 to the memory 203, since the speed of writing test data to the write buffer 2022 is much faster than the speed of the write buffer 2022 sending test data to the memory 203, the write buffer 2022 is always in a state of being full.

[0054] Please refer to Figure 1 and Figure 2 As shown, in an embodiment of the present invention, since the capacity of the write buffer 2022 cannot be confirmed, it can be processed according to the maximum value of the capacity of the write buffer 2022 on the market, or according to twice or three times the maximum value of the capacity of the write buffer 2022 on the market. Thereby ensuring that the test data fills the write buffer 2022 and there is test data sent to the memory 203.

[0055] Please refer to Figure 1 and Figure 2 As shown, in an embodiment of the present invention, between the host 100 and the storage chip 200, a control switch 101 is provided, and the control switch 101 can be a control switch 101 such as a relay or a circuit breaker. When the amount of test data written to the storage chip 200 reaches the set threshold, during the process of writing test data to the storage chip 200, by disconnecting the control switch 101, the power supply of the storage chip 200 is disconnected. At this time, since the external power supply of the storage chip 200 suddenly cuts off, the test data stored in the write buffer 2022 will be lost, while the test data saved in the memory 203 remains in the memory 203.

[0056] Please refer to Figure 1 and Figure 2 As shown, in an embodiment of the present invention, at the host 100 side, a monitoring program is provided, which can monitor the last test data sent to the storage chip 200, that is, the last test data written to the write buffer 2022 before the power failure.

[0057] Please refer to Figure 1 and Figure 2As shown, in an embodiment of the present invention, after powering off the storage chip 200 and then restoring the power supply of the storage chip 200 through the control switch 101, by querying the test data and padding data stored in the memory 203, the test data and padding data can be distinguished according to the formats of the test data and padding data. And since the value of the last-written test data is the maximum among all the test data, the test data with the largest value is the last-written test data.

[0058] Please refer to Figure 1 and Figure 2 As shown, in an embodiment of the present invention, after obtaining the last-written test data in the memory 203 and the last-written test data in the write buffer 2022, the range of the value of the test data saved in the write buffer 2022 can be obtained according to the value of the last-written test data in the memory 203 and the value of the last-written test data in the write buffer 2022, and then the capacity of the write buffer 2022 can be obtained. In this embodiment, the capacity of the write buffer 2022 is obtained by the following formula:

[0059] T = (m - n) × Q;

[0060] where T is the capacity of the write buffer 2022, m is the value of the last-written test data in the write buffer 2022, n is the value of the last-written test data in the memory 203, and Q is the capacity of the data unit.

[0061] It should be noted that under the condition that the value of the capacity Q of the data unit is the same, the larger the value of m - n, the larger the capacity of the write buffer 2022 in the storage chip 200. If the value of m - n is zero, it means that there is no write buffer 2022 in the storage chip 200.

[0062] Please refer to Figure 1 and Figure 2 As shown, in a specific embodiment of the present invention, the last-written test data in the memory 203 is, for example, 0x00008000, and the last-written test data in the memory 203 is, for example, 0x00007000, and the capacity of the data unit is, for example, 4KB, then the capacity of the write buffer 2022 is:

[0063] T = (0x00008000 - 0x00007000) × 4KB = 0x1000 × 4KB = 16MB.

[0064] Please refer to Figure 1 and Figure 2As shown, in an embodiment of the present invention, when it is necessary to obtain a more accurate capacity of the write buffer 2022, the capacity of the data unit is reduced. For example, it is reduced from 4KB to 512B. Then, steps S101 to S104 are repeatedly executed in a loop until the capacity of the write buffer 2022 is obtained again. As the capacity of the data unit decreases, the value of the test data increases, and the range of the obtained capacity of the write buffer 2022 is more accurate.

[0065] Please refer to Figure 3 As shown, the present invention also provides a test device for a storage chip. The test device includes a memory 302 and a processor 301. Program instructions are stored in the memory 302, and the processor 301 runs the program instructions in the memory 302 to implement the test method for the storage chip described above.

[0066] Please refer to Figure 3 As shown, the memory 302 includes at least one type of readable storage medium. The readable storage medium includes flash memory, mobile hard disks, multimedia cards, card-type memories (such as SD or DX memories, etc.), magnetic memories, magnetic disks, optical discs, etc. In some embodiments, the memory can be an internal storage unit of an electronic device, such as the mobile hard disk of the electronic device. In other embodiments, the memory can also be an external storage device of the electronic device, such as a plug-in mobile hard disk, a Smart Media Card (SMC), a Secure Digital (SD) card, a Flash Card, etc. equipped on the electronic device. Further, the memory can also include both the internal storage unit and the external storage device of the electronic device. The memory can be used not only to store application software installed in the electronic device and various types of data, but also to temporarily store data that has been output or will be output.

[0067] Please refer to Figure 3 As shown, in some embodiments, the processor 301 can be composed of integrated circuits. For example, it can be composed of a single packaged integrated circuit, or can be composed of multiple integrated circuits with the same or different functions, including a combination of one or more Central Processing Units (CPUs), microprocessors, digital processing chips, graphics processors, and various control chips, etc. The processor is the control core (Control Unit) of the host. By running or executing programs or modules stored in the memory, and calling data stored in the memory, it performs various functions of the host and processes data.

[0068] The processor executes the operating system of the host and various installed application programs. The processor executes the application programs to implement the steps in the above method embodiments.

[0069] Exemplarily, the program may be divided into one or more modules, and the one or more modules are stored in the memory and executed by the processor to implement the present invention. The one or more modules may be a series of program instruction segments capable of performing specific functions, and the instruction segments are used to describe the execution process of the program in the host computer.

[0070] The integrated unit implemented in the form of a software functional module as described above may be stored in a computer-readable storage medium. The above software functional module is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a computer device, or a network device, etc.) or a processor to execute some functions of the lithium battery virtual soldering detection method according to various embodiments of the present invention.

[0071] In summary, a test method and a test device for a storage chip. The test method for the storage chip includes writing fill data into the storage chip until the memory is filled with the fill data. Then, the cache function of the storage chip is enabled, and test data is written into the storage chip. The data format of the test data in each data unit is related to the writing order, and the data format of the test data written in each data unit is the same. When the amount of the test data written into the storage chip reaches a set threshold, during the process of writing the test data into the storage chip, the power supply of the storage chip is disconnected. And the capacity of the write buffer is obtained based on the last-written test data in the memory and the last-written test data in the write buffer.

[0072] The embodiments of the present invention disclosed above are only used to help explain the present invention. The embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and variations can be made according to the content of this specification. These embodiments are selected and specifically described in this specification to better explain the principle and practical application of the present invention, so that those skilled in the art in the relevant technical field can well understand and utilize the present invention. The present invention is only limited by the claims and their full scope and equivalents.

Claims

1. A method for testing a memory chip, characterized in that: At least the following steps are included: Writing filling data to the memory chip until the filling data fills up the memory; Turning on the cache function of the memory chip and writing test data into the memory chip, wherein the data format of the test data in each data unit is related to the writing order, and the data format of the test data written in each data unit is the same, and the data format of the padding data is different from that of the test data, and the value of the padding data is greater than the number of the data units in the memory; When the amount of the test data written into the memory chip reaches a set threshold, disconnecting the power supply of the memory chip during the process of writing the test data into the memory chip; as well as The capacity of the write buffer is obtained according to the test data last written in the memory and the test data last written in the write buffer.

2. A memory chip testing method according to claim 1, characterized in that: The amount of the filling data written into the storage chip is greater than the total capacity of the memory and the buffer.

3. The memory chip testing method according to claim 1, characterized in that: When writing test data into the memory chip, each time the test data of one data unit is written, the value of the test data is increased by one.

4. The method for testing a memory chip according to claim 1, characterized in that: The amount of the test data in each data format is equal to the capacity of the data unit divided by the size of one test data.

5. The method for testing a memory chip according to claim 1, characterized in that: The set threshold is greater than the capacity of the write buffer.

6. The method for testing a memory chip according to claim 1, characterized in that: The capacity of the write buffer is obtained by the following formula: T = (mn) × Q; Wherein, T is the capacity of the write buffer, m is the value of the test data last written in the write buffer, n is the value of the test data last written in the memory, and Q is the capacity of the data unit.

7. The memory chip testing method according to claim 1, characterized in that: The test method also includes: The capacity of the data unit is reduced to regain the capacity of the write buffer.

8. A memory chip testing device, characterized in that: The testing device comprises: a memory storing program instructions; and A processor runs the program instructions to implement the memory chip testing method according to any one of claims 1 to 7.

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