Method of forming a semiconductor structure

Abstract

A method for forming a semiconductor structure, comprising: providing a wafer, including an isolation region and a device region; forming a device structure on the device region, the device structure including a first layer structure and a second layer structure on the first layer structure; forming an isolation structure on the wafer, the isolation structure on the isolation region and on a region outside the device structure in the device region, the device structure being inside the isolation structure; obtaining whether the second layer structure and the first layer structure are electrically failed; if the second layer structure and the first layer structure are electrically failed, obtaining a shift of the second layer structure and the first layer structure in a first direction; and performing a laser annealing process on the wafer according to the shift of the second layer structure and the first layer structure in the first direction, so as to restore the electrical connection of the second layer structure and the first layer structure. The method improves the stress condition of the semiconductor structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a method for forming a semiconductor structure. Background Technology

[0002] In IC design and manufacturing, some special structural layouts are designed based on customer needs. These layouts often exhibit pattern loading effects, which can affect the performance of semiconductor devices.

[0003] Therefore, this situation needs to be improved. Summary of the Invention

[0004] The technical problem solved by this invention is to provide a method for forming a semiconductor structure to improve the stress effect on wafers.

[0005] To address the aforementioned technical problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a wafer, the wafer including an isolation region and a device region, the isolation region and the device region being distributed along a first direction parallel to the wafer surface; forming a device structure located on the device region, the device structure including a first layer structure and a second layer structure located on the first layer structure; forming an isolation structure located on the wafer, the isolation structure being located on the isolation region and on a region outside the device structure in the device region, the device structure being located within the isolation structure; obtaining whether the second layer structure and the first layer structure have experienced electrical failure; if the second layer structure and the first layer structure have experienced electrical failure, obtaining the offset of the second layer structure and the first layer structure in the first direction; and performing laser annealing on the wafer according to the offset of the second layer structure and the first layer structure in the first direction to restore the electrical connection between the second layer structure and the first layer structure.

[0006] Optionally, the wafer edge has a positioning groove; the laser beam used in the laser annealing process has a projected spot on the wafer surface, the projected spot extends along the edge of the wafer to the center of the wafer, and the projected spot has a centerline along the radius of the wafer; the positioning groove and the center of the wafer are connected by a first line.

[0007] Optionally, the offset of the second layer structure and the first layer structure in the first direction includes: the degree of offset and the direction of offset. The degree of offset includes severe offset or slight offset. The direction of offset includes offset away from the isolation region or offset towards the isolation region. The absolute value of the offset in the severe case ranges from 30 nanometers to 48 nanometers. The absolute value of the offset in the slight case ranges from 12 nanometers to 30 nanometers.

[0008] Optionally, the wafer is subjected to laser annealing based on the offset of the second layer structure and the first layer structure in the first direction, including: adjusting the angle of the laser in the laser annealing process according to the degree and direction of the offset of the second layer structure and the first layer structure in the first direction, and performing laser annealing on the wafer.

[0009] Optionally, when the second layer structure and the first layer structure are severely misaligned, the wafer is subjected to a first laser annealing process.

[0010] Optionally, the first laser annealing process includes: performing a first processing and a second processing on the wafer; the first processing includes: rotating the wafer to perform the first processing with a first position as the initial point, wherein the center line of the laser spot at the first position has a first angle with the first connecting line; the second processing includes: rotating the wafer to perform the second processing with a second position as the initial point, wherein the center line of the laser spot at the second position has a second angle with the first connecting line.

[0011] Optionally, the absolute value of the difference between the first included angle and the second included angle is 180 degrees.

[0012] Optionally, when the offset directions of the second layer structure and the first layer structure are offset away from the isolation area, the first included angle ranges from 10 degrees to 45 degrees, and the second included angle ranges from 190 degrees to 225 degrees.

[0013] Optionally, when the offset directions of the second layer structure and the first layer structure are offset in the direction toward the isolation area, the range of the first included angle is 100 degrees to 135 degrees, and the range of the second included angle is 280 degrees to 335 degrees.

[0014] Optionally, when the second layer structure and the first layer structure are slightly offset, the wafer is subjected to a second laser annealing process.

[0015] Optionally, the second laser annealing process includes: performing a third process and a fourth process on the wafer; the third process includes: rotating the wafer to perform the third process with a third position as the initial point, wherein the center line of the laser spot at the third position has a third angle with the first connecting line; the fourth process includes: rotating the wafer to perform the fourth process with a fourth position as the initial point, wherein the center line of the laser spot at the fourth position has a fourth angle with the first connecting line.

[0016] Optionally, the absolute value of the difference between the third included angle and the fourth included angle is 180 degrees.

[0017] Optionally, when the offset directions of the second layer structure and the first layer structure are offset in the direction toward the isolation area, the range of the third included angle is 90 degrees to 100 degrees, and the range of the fourth included angle is 270 degrees to 280 degrees.

[0018] Optionally, when the offset directions of the second layer structure and the first layer structure are offset away from the isolation area, the range of the third included angle is 0 degrees to 10 degrees, and the range of the fourth included angle is 180 degrees to 190 degrees.

[0019] Optionally, the first layer structure includes: a gate structure located on the wafer and source / drain doped regions located on both sides of the gate structure within the wafer, wherein the source / drain doped regions are located on both sides of the gate structure along a first direction; the second layer structure includes: conductive plugs located on the source / drain doped regions, wherein the conductive plugs are electrically connected to the source / drain doped regions.

[0020] Optionally, determining whether the second layer structure and the first layer structure have experienced electrical failure includes: if the conductive plug and the gate structure are offset in a first direction, causing the conductive plug and the gate structure to bridge, then the second layer structure and the first layer structure have experienced electrical failure.

[0021] Optionally, the first layer structure includes: a first metal layer located on the wafer, the extension direction of the first metal layer being perpendicular to the first direction; the second layer structure includes: a connection plug located on the first metal layer.

[0022] Optionally, determining whether the second layer structure and the first layer structure have experienced electrical failure includes: if the connecting plug and the first metal layer are offset in a first direction, resulting in the connecting plug not contacting the first metal layer, then the second layer structure and the first layer structure have experienced electrical failure.

[0023] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0024] The technical solution of this invention involves obtaining the offset of the second and first layer structures in a first direction after electrical failure of the second and first layer structures. Then, based on this offset, the wafer is subjected to laser annealing. This method, by performing targeted laser annealing on the wafer according to the offset of the second and first layer structures in the first direction, can neutralize the stress in stress areas on the wafer, reduce stress from different directions, and correspondingly improve the electrical failure state in different directions, thereby restoring the second and first layer structures from an electrically failed state to an electrically connected state. The method is simple to operate, has minimal impact on the process, and has minimal impact on relevant parameters of the semiconductor process.

[0025] Furthermore, by adjusting the angle of the laser during laser annealing based on the degree and direction of offset of the second and first layer structures in the first direction, the wafer can be flexibly annealed, thereby mitigating the negative effects of stress.

[0026] Furthermore, the offset of the second layer structure and the first layer structure in the first direction includes: the degree of offset and the direction of offset. The degree of offset includes severe offset or slight offset, and the direction of offset includes offset away from the isolation region or offset towards the isolation region. Based on the degree and direction of offset, the wafer is subjected to targeted laser annealing to neutralize the stress in the stress regions on the wafer, thereby restoring the second layer structure and the first layer structure from an electrically failed state to an electrically connected state.

[0027] Furthermore, the absolute value of the difference between the first and second included angles is 180 degrees, and the absolute value of the difference between the third and fourth included angles is also 180 degrees. This ensures that the semiconductor structure undergoes laser annealing on both the front and back sides, preventing uneven stress on the semiconductor structure. Attached Figure Description

[0028] Figures 1 to 7 This is a schematic diagram of the formation process of a semiconductor structure in one embodiment;

[0029] Figure 8 This is a schematic flowchart illustrating the formation process of the semiconductor structure in an embodiment of the present invention;

[0030] Figure 9 and Figure 10 This is a schematic diagram of the formation process of a semiconductor structure in one embodiment of the present invention;

[0031] Figure 11 and Figure 12 This is a schematic diagram of the formation process of a semiconductor structure in another embodiment of the present invention;

[0032] Figure 13 and Figure 14 This is a schematic diagram of the formation process of a semiconductor structure in another embodiment of the present invention;

[0033] Figure 15 and Figure 16 This is a schematic diagram of the formation process of a semiconductor structure in another embodiment of the present invention. Detailed Implementation

[0034] As described in the background section, pattern loading effects can affect the performance of semiconductor devices. This will now be analyzed and explained with reference to specific embodiments.

[0035] Figures 1 to 7This is a schematic diagram of the formation process of a semiconductor structure in one embodiment.

[0036] Please refer to Figures 1 to 3 , Figure 1 This is a schematic diagram of the layout of a certain area on wafer 100. Figure 2 for Figure 1 An enlarged schematic diagram of device structure 103 in the middle device area. Figure 3 for Figure 2 A cross-sectional view of the semiconductor structure along section line AA1 is shown in the diagram. The semiconductor structure includes: a wafer 100, which includes an isolation region 101 and a device region 102. The isolation region 101 and the device region 102 are distributed along a first direction X parallel to the surface of the wafer 100. The device region 102 includes an active region; a device structure 103 located on the active region; and an isolation structure 107 located on the wafer 100. The isolation structure 107 is located on the isolation region 101 and in a region outside the device structure 103 in the device region 102. The device structure 103 is located within the isolation structure 107.

[0037] The device structure 103 includes a first layer structure and a second layer structure located on the first layer structure.

[0038] Please continue to refer to this. Figure 2 and Figure 3 In this embodiment, the first layer structure includes: a gate structure 104 located on the wafer 100 and source / drain doped regions 105 located on both sides of the gate structure 104 within the wafer 100, wherein the source / drain doped regions 105 are located on both sides of the gate structure 104 along a first direction X; the second layer structure includes: a conductive plug 106 located on the source / drain doped regions 105, wherein the conductive plug 106 is electrically connected to the source / drain doped regions 105.

[0039] In this embodiment, the device region 102 includes a substrate (not shown) and a fin structure (not shown) located on the substrate, and the active region is the fin structure.

[0040] Please refer to Figure 4 , Figure 4This is a schematic diagram of the stress distribution of wafer 100 after multiple processes. In the semiconductor structure, due to the presence of a large isolation region 101 in the first direction X, and the absence of device structure filling the isolation region 101, the isolation structure 107 filling the isolation region 101 will generate a large amount of stress, resulting in stress concentration in some areas of wafer 100. The edge of wafer 100 has a positioning groove Notch, which is connected to the center of wafer 100 by a first line. After wafer 100 undergoes multiple processes, regardless of... <110> Crystal orientation or <100> In terms of crystal orientation, wafer 100 exhibits a stress direction F with an angle of approximately 45° to the first connecting line, meaning that the stress is relatively concentrated in the region 108 of wafer 100 with an angle of approximately 45° to the first connecting line.

[0041] The isolation structure 107 filling the isolation region 101 will generate a large amount of stress. In this embodiment, this is manifested in the second semiconductor structure as follows: the stress causes the active region of the device region 102 to undergo displacement deformation, which in turn causes the position of the conductive plug 106 to shift in the first direction X, ultimately causing the conductive plug 106 to bridge with the gate structure 104. Figure 2 (As shown in region B).

[0042] Please refer to Figure 5 After multiple processing steps, wafer 100 typically undergoes a laser annealing process to eliminate stress defects, etc. Laser annealing is a CO2 laser annealing method with a wavelength of 9.2–10.8 μm. Typically, an 80 μm wide laser spot is used to scan at a high temperature with a 75° Brewster angle θ, gradually covering the surface of wafer 100. Figure 5 In the diagram, L1 is the normal perpendicular to the surface of wafer 100, and the angle between the laser spot (Laser) and L1 is the Brewster angle θ of 75°. Laser annealing processes include two methods: single scan and dual scan. A single scan involves scanning the wafer only once, while a dual scan involves scanning the wafer twice at different angles.

[0043] Please refer to Figure 6 and Figure 7 , Figure 6 and Figure 7 This is a schematic diagram of the dual scanning process. The commonly used dual scanning method employs angles of 45° / 225°. The specific working principle is as follows: the laser spot remains stationary, while wafer 100 rotates clockwise. The first scan is performed at a 45° angle to the first connecting line, and then the second scan is performed at a 225° angle to the first connecting line. The positioning groove Notch is connected to the center of wafer 100 by the first connecting line N1. Figure 6 The angle between the laser spot and the first line N1 is α1, where α1 is 45°.Figure 7 The angle between the laser spot and the first line N2 is α2, and α2 is 225°.

[0044] go through Figure 6 and Figure 7 After the dual scanning of laser annealing, the stress area generated on the wafer 100 after laser annealing overlaps with the stress area on the wafer 100 after multiple processes, which will further aggravate the stress level on the wafer 100. After the stress superposition effect, it will further aggravate the bridging between the conductive plug 106 and the gate structure 104.

[0045] To improve the stress phenomenon of wafer 100, on the one hand, a large number of pseudo-active regions are designed in the isolation region 101 to form pseudo-device structures on the pseudo-active regions. However, due to the limitations of design rules, the modifications in the isolation region 101 are limited. On the other hand, the layout can be redesigned, that is, without leaving a large area of ​​isolation region. However, this method is costly and the effect of improving stress is also limited.

[0046] To address the aforementioned problems, the present invention provides a method for forming a semiconductor structure. After the second and first layer structures experience electrical failure, the method acquires the offset of the second and first layer structures in a first direction. Then, based on this offset, the wafer undergoes laser annealing. This method, by performing targeted laser annealing on the wafer according to the offset of the second and first layer structures in the first direction, can neutralize stress in stress regions on the wafer, reduce stress from different directions, and correspondingly improve the electrical failure state in different directions. This allows the second and first layer structures to recover from an electrically failed state to an electrically connected state. The method is simple to operate, has minimal impact on the process flow, and has minimal influence on relevant parameters of the semiconductor process.

[0047] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0048] Figure 8 This is a schematic flowchart illustrating the formation process of the semiconductor structure in an embodiment of the present invention; Figure 9 and Figure 10 This is a schematic diagram of the formation process of a semiconductor structure in one embodiment of the present invention.

[0049] Please refer to Figure 8 The formation process of the semiconductor structure includes:

[0050] Step S10: Provide a wafer, the wafer including an isolation region and a device region, the isolation region and the device region being distributed along a first direction parallel to the wafer surface;

[0051] Step S20: Form a device structure located on the device region, the device structure including a first layer structure and a second layer structure located on the first layer structure;

[0052] Step S30: Form an isolation structure on the wafer, the isolation structure being located on an isolation region and on a region outside the device structure in the device region, the device structure being located within the isolation structure;

[0053] Step S40: Determine whether electrical failure has occurred in the second layer structure and the first layer structure;

[0054] Step S50: If the second layer structure and the first layer structure fail electrically, then obtain the offset of the second layer structure and the first layer structure in the first direction;

[0055] Step S60: Based on the offset of the second layer structure and the first layer structure in the first direction, the wafer is subjected to laser annealing to restore the electrical connection between the second layer structure and the first layer structure.

[0056] The method describes a targeted laser annealing process for the wafer 100 based on the offset of the second and first layer structures in the first direction X. This process neutralizes stress in stress-prone areas on the wafer 100, reduces stress from different directions, and correspondingly improves electrical failure states in different directions. Consequently, the second and first layer structures are restored from an electrical failure state to an electrically connected state. The method is simple to operate, has minimal impact on the process flow, and has minimal influence on relevant parameters of the semiconductor manufacturing process.

[0057] Next, each step will be analyzed and explained.

[0058] Please combine Figures 1 to 3 Continue to refer to Figure 8 Step S10: Provide a wafer 100, the wafer 100 including an isolation region 101 and a device region 102, the isolation region 101 and the device region 102 being distributed along a first direction X parallel to the surface of the wafer 100; Step S20: Form a device structure 103 located on the device region 102, the device structure 103 including a first layer structure and a second layer structure located on the first layer structure; Step S30: Form an isolation structure 107 located on the wafer 100, the isolation structure 103 being located on the isolation region 101 and on a region outside the device structure 103 in the device region 102, the device structure 103 being located within the isolation structure 107.

[0059] Please continue to refer to this. Figure 2 and Figure 3In this embodiment, the first layer structure includes: a gate structure 104 located on the wafer 100 and source / drain doped regions 105 located on both sides of the gate structure 104 within the wafer 100, wherein the source / drain doped regions 105 are located on both sides of the gate structure 104 along a first direction X; the second layer structure includes: a conductive plug 106 located on the source / drain doped regions 105, wherein the conductive plug 106 is electrically connected to the source / drain doped regions 105.

[0060] In this embodiment, the device region 102 includes an active region, and the device structure 103 is located on the active region. The device region 102 includes a substrate (not shown) and a fin structure (not shown) located on the substrate. The active region is the fin structure.

[0061] In this embodiment, the material of the wafer 100 is silicon.

[0062] In other embodiments, the wafer material includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0063] In another embodiment, the first layer structure includes: a first metal layer located on the wafer, the first metal layer extending perpendicular to a first direction; the second layer structure includes: a connection plug located on the first metal layer.

[0064] Please continue to refer to this. Figure 8 Step S40: Obtain whether electrical failure has occurred in the second layer structure and the first layer structure.

[0065] In this embodiment, whether the second layer structure and the first layer structure experience electrical failure includes: if the conductive plug 106 and the gate structure 104 are offset in the first direction X, causing the conductive plug 106 and the gate structure 104 to bridge, then the second layer structure and the first layer structure experience electrical failure.

[0066] In another embodiment, the first layer structure includes: a first metal layer located on the wafer, the first metal layer extending perpendicular to a first direction; the second layer structure includes: a connector plug located on the first metal layer. Whether the second layer structure and the first layer structure experience electrical failure is determined by: if the connector plug is offset from the first metal layer in the first direction, resulting in the connector plug not contacting the first metal layer, then the second layer structure and the first layer structure experience electrical failure.

[0067] The process of determining whether the second layer structure and the first layer structure have experienced electrical failure includes: performing an electrical test on the semiconductor structure; if the electrical test result of the semiconductor structure fails, then obtaining the offset of the second layer structure and the first layer structure; if the second layer structure and the first layer structure are offset in a first direction, then the second layer structure and the first layer structure have experienced electrical failure.

[0068] If the electrical test result of the semiconductor structure fails, and the second layer structure and the first layer structure do not shift in the first direction, it indicates that the failure of the electrical test result of the semiconductor structure is not caused by the second layer structure and the first layer structure. In this case, it is necessary to find other means to solve the problem of the failure of the electrical test result.

[0069] Please continue to refer to this. Figure 8 Step S50: If the second layer structure and the first layer structure fail electrically, then obtain the offset of the second layer structure and the first layer structure in the first direction X.

[0070] The offset of the second layer structure and the first layer structure in the first direction X includes: the degree of offset and the direction of offset. The degree of offset includes severe offset or slight offset. The direction of offset includes offset in a direction away from the isolation zone 101 or offset in a direction toward the isolation zone 101.

[0071] The method performs laser annealing on the wafer 100 according to the degree and direction of offset, so as to neutralize the stress in the stress area on the wafer, thereby restoring the second layer structure and the first layer structure from the electrical failure state to the electrical connection state.

[0072] In this embodiment, the absolute value of the offset in the severe offset case ranges from 30 nanometers to 48 nanometers; the absolute value of the offset in the minor offset case ranges from 12 nanometers to 30 nanometers.

[0073] Please continue to refer to this. Figure 8 Step S60: Based on the offset of the second layer structure and the first layer structure in the first direction, perform laser annealing on the wafer 100 to restore the electrical connection between the second layer structure and the first layer structure.

[0074] The offset includes the degree and direction of offset. Based on the degree and direction of offset of the second and first layer structures in the first direction, the wafer 100 is subjected to laser annealing, including adjusting the angle of the laser during laser annealing. This allows for flexible adjustment of offset in different directions, mitigating the negative effects of stress.

[0075] In this embodiment, the second layer structure and the first layer structure are restored from the electrical failure state to the electrical connection state, that is, the conductive plug 106 and the gate structure 104 are not bridged, and the spacing between the conductive plug 106 and the gate structure 104 is within a safe range.

[0076] In other embodiments, and in this embodiment, the electrical connection function is achieved by the connection plug contacting the first metal layer.

[0077] The wafer 100 has a positioning groove Notch on its edge; the laser beam used in the laser annealing process has a projected spot on the wafer surface, the projected spot extends along the edge of the wafer 100 to the center of the wafer, and the projected spot has a center line Laser along the radius of the wafer; the positioning groove Notch and the center of the wafer 100 are connected by a first line.

[0078] Please refer to Figure 9 and Figure 10 , Figure 9 and Figure 10 This is a schematic diagram of the first laser annealing process performed on wafer 100. Figure 9 As the first step, Figure 10 This is the second step.

[0079] In this embodiment, the second layer structure and the first layer structure are in a severe offset case. The wafer 100 is subjected to a first laser annealing process. The absolute value of the offset in the severe offset case ranges from 30 nanometers to 48 nanometers.

[0080] The first laser annealing process includes: performing a first process and a second process on the wafer 100.

[0081] Please continue to refer to this. Figure 9 The first processing includes: rotating the wafer 100 clockwise with the first position as the initial point to perform a first processing on the wafer 100, wherein the laser spot center line Laser at the first position and the first connecting line N1 have a first included angle α1.

[0082] Please continue to refer to this. Figure 10 The second processing includes: rotating the wafer 100 clockwise from the second position as the initial point to perform the second processing on the wafer 100, wherein the laser spot center line Laser at the second position has a second included angle α2 with the first connecting line N2.

[0083] In this embodiment, the absolute value of the difference between the first included angle α1 and the second included angle α2 is 180 degrees. This ensures that the semiconductor structure undergoes laser annealing on both the front and back sides, avoiding uneven stress on the front and back sides of the semiconductor structure.

[0084] In this embodiment, the offset directions of the second layer structure and the first layer structure are offset away from the isolation area 101, the first included angle α1 ranges from 10 degrees to 45 degrees, and the second included angle α2 ranges from 190 degrees to 225 degrees.

[0085] In this embodiment, the first processing is performed first, followed by the second processing. The first included angle of the first processing is smaller than the second included angle of the second processing. The wafer rotates clockwise. By first adjusting the angle from small to large along the wafer rotation direction, the wafer rotation time can be reduced, thereby improving production efficiency.

[0086] In other embodiments, the second process can be performed first, followed by the first process.

[0087] from Figure 9 and Figure 10 As can be seen from the diagram, F represents the stress direction of wafer 100 before the first laser annealing process, after multiple processing steps. The angle between F and the first connecting line is 45 degrees. F' represents the stress direction of wafer 100 after the first laser annealing process. F' and F have an angle that does not coincide. Therefore, the first laser annealing process with the adjusted direction can neutralize and disperse the stress in the stress area on wafer 100, thereby reducing the stress impact and restoring the second layer structure and the first layer structure from the electrical failure state to the electrical connection state.

[0088] Figure 11 and Figure 12 This is a schematic diagram of the formation process of a semiconductor structure in another embodiment of the present invention.

[0089] Please combine Figure 8 refer to Figure 11 and Figure 12 , Figure 11 and Figure 12 This is a schematic diagram of the first laser annealing process performed on wafer 100. Figure 11 As the first step, Figure 12 This is the second step.

[0090] In this embodiment, the second layer structure and the first layer structure are in a severe offset case. The wafer 100 is subjected to a first laser annealing process. The absolute value of the offset in the severe offset case ranges from 30 nanometers to 48 nanometers.

[0091] The first laser annealing process includes: performing a first process and a second process on the wafer 100.

[0092] Please continue to refer to this. Figure 11The first processing includes: rotating the wafer 100 clockwise with the first position as the initial point to perform a first processing on the wafer 100, wherein the laser spot center line Laser at the first position and the first connecting line N1 have a first included angle α1.

[0093] Please continue to refer to this. Figure 12 The second processing includes: rotating the wafer 100 clockwise from the second position as the initial point to perform the second processing on the wafer 100, wherein the laser spot center line Laser at the second position has a second included angle α2 with the first connecting line N2.

[0094] In this embodiment, the absolute value of the difference between the first included angle α1 and the second included angle α2 is 180 degrees. This ensures that the semiconductor structure undergoes laser annealing on both the front and back sides, avoiding uneven stress on the front and back sides of the semiconductor structure.

[0095] In this embodiment, the offset directions of the second layer structure and the first layer structure are offset towards the isolation area, the first included angle α1 ranges from 100 degrees to 135 degrees, and the second included angle α2 ranges from 280 degrees to 335 degrees.

[0096] In this embodiment, the first processing is performed first, followed by the second processing. The first included angle of the first processing is smaller than the second included angle of the second processing. The wafer rotates clockwise. By first adjusting the angle from small to large along the wafer rotation direction, the wafer rotation time can be reduced, thereby improving production efficiency.

[0097] In other embodiments, the second process can be performed first, followed by the first process.

[0098] from Figure 11 and Figure 12 As can be seen from the diagram, F represents the stress direction of wafer 100 before the first laser annealing process, after multiple processing steps. The angle between F and the first connecting line is 45 degrees. F' represents the stress direction of wafer 100 after the first laser annealing process. F' and F have an angle that does not coincide. Therefore, the first laser annealing process with the adjusted direction can neutralize and disperse the stress in the stress area on wafer 100, thereby reducing the stress impact and restoring the second layer structure and the first layer structure from the electrical failure state to the electrical connection state.

[0099] Figure 13 and Figure 14 This is a schematic diagram of the formation process of a semiconductor structure in another embodiment of the present invention.

[0100] Please combine Figure 8 refer to Figure 13 and Figure 14 , Figure 13 and Figure 14This is a schematic diagram of wafer 100 undergoing a second laser annealing process. Figure 13 As the first step, Figure 14 This is the second step.

[0101] In this embodiment, the second layer structure and the first layer structure are in the case of slight offset. The wafer is subjected to a second laser annealing process. The absolute value of the offset in the case of slight offset is in the range of 12 nanometers to 30 nanometers.

[0102] The second laser annealing process includes performing a third and a fourth process on the wafer 100.

[0103] Please continue to refer to this. Figure 13 The third processing includes: rotating the wafer 100 clockwise from the third position as the initial point to perform the third processing on the wafer 100, wherein the laser spot center line Laser at the third position has a third included angle α3 with the first connecting line N3.

[0104] Please continue to refer to this. Figure 14 The fourth processing includes: rotating the wafer 100 clockwise from the fourth position as the initial point to perform the fourth processing on the wafer 100, wherein the laser spot center line Laser at the fourth position has a fourth included angle α4 with the first connecting line N4.

[0105] In this embodiment, the absolute value of the difference between the third included angle α3 and the fourth included angle α4 is 180 degrees. This ensures that the semiconductor structure undergoes laser annealing on both the front and back sides, avoiding uneven stress on the front and back sides of the semiconductor structure.

[0106] In this embodiment, the offset directions of the second layer structure and the first layer structure are offset in the direction toward the isolation area 101, the range of the third included angle α3 is 90 degrees to 100 degrees, and the range of the fourth included angle α4 is 270 degrees to 280 degrees.

[0107] In this embodiment, the third process is performed first, followed by the fourth process. The included angle of the third process is smaller than the included angle of the fourth process. The wafer rotates clockwise. By first adjusting the angle from small to large along the wafer rotation direction, the wafer rotation time can be reduced, thus improving production efficiency.

[0108] In other embodiments, the fourth process can be performed first, followed by the third process.

[0109] from Figure 13 and Figure 14As can be seen from the diagram, F represents the stress direction of wafer 100 before the second laser annealing process, after multiple processing steps. The angle between F and the first connection line is 45 degrees. F' represents the stress direction of wafer 100 after the second laser annealing process. F' and F have an angle that does not coincide. Therefore, the second laser annealing process with the adjusted direction can neutralize and disperse the stress in the stress area on wafer 100, thereby reducing the stress impact and restoring the second layer structure and the first layer structure from the electrical failure state to the electrical connection state.

[0110] Figure 15 and Figure 16 This is a schematic diagram of the formation process of a semiconductor structure in another embodiment of the present invention.

[0111] Please combine Figure 8 refer to Figure 15 and Figure 16 , Figure 15 and Figure 16 This is a schematic diagram of wafer 100 undergoing a second laser annealing process. Figure 15 As the first step, Figure 16 This is the second step.

[0112] In this embodiment, the second layer structure and the first layer structure are in the case of slight offset. The wafer is subjected to a second laser annealing process. The absolute value of the offset in the case of slight offset is in the range of 12 nanometers to 30 nanometers.

[0113] The second laser annealing process includes performing a third and a fourth process on the wafer 100.

[0114] Please continue to refer to this. Figure 15 The third processing includes: rotating the wafer 100 clockwise from the third position as the initial point to perform the third processing on the wafer 100, wherein the laser spot center line Laser at the third position has a third included angle α3 with the first connecting line N3.

[0115] Please continue to refer to this. Figure 16 The fourth processing includes: rotating the wafer 100 clockwise from the fourth position as the initial point to perform the fourth processing on the wafer 100, wherein the laser spot center line Laser at the fourth position has a fourth included angle α4 with the first connecting line N4.

[0116] In this embodiment, the absolute value of the difference between the third included angle α3 and the fourth included angle α4 is 180 degrees. This ensures that the semiconductor structure undergoes laser annealing on both the front and back sides, avoiding uneven stress on the front and back sides of the semiconductor structure.

[0117] In this embodiment, the offset directions of the second layer structure and the first layer structure are offset away from the isolation area 101, the range of the third included angle α3 is 0 degrees to 10 degrees, and the range of the fourth included angle α4 is 180 degrees to 190 degrees.

[0118] In this embodiment, the third process is performed first, followed by the fourth process. The included angle of the third process is smaller than the included angle of the fourth process. The wafer rotates clockwise. By first adjusting the angle from small to large along the wafer rotation direction, the wafer rotation time can be reduced, thus improving production efficiency.

[0119] In other embodiments, the fourth process can be performed first, followed by the third process.

[0120] from Figure 15 and Figure 16 As can be seen from the diagram, F represents the stress direction of wafer 100 before the second laser annealing process, after multiple processing steps. The angle between F and the first connection line is 45 degrees. F' represents the stress direction of wafer 100 after the second laser annealing process. F' and F have an angle that does not coincide. Therefore, the second laser annealing process with the adjusted direction can neutralize and disperse the stress in the stress area on wafer 100, thereby reducing the stress impact and restoring the second layer structure and the first layer structure from the electrical failure state to the electrical connection state.

[0121] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method of forming a semiconductor structure, characterized by, The method comprises: providing a wafer, the wafer comprising an isolation region and a device region, the isolation region and the device region being distributed along a first direction parallel to a surface of the wafer; forming a device structure on the device region, the device structure comprising a first layer structure and a second layer structure on the first layer structure; forming an isolation structure on the wafer, the isolation structure being on the isolation region and on a region outside the device structure of the device region, the device structure being inside the isolation structure; obtaining whether the second layer structure and the first layer structure are electrically failed; if the second layer structure and the first layer structure are electrically failed, obtaining a shift of the second layer structure and the first layer structure along the first direction, the shift of the second layer structure and the first layer structure along the first direction comprising a shift degree and a shift direction; adjusting an angle of a laser in a laser annealing process according to the shift of the second layer structure and the first layer structure along the first direction, and performing laser annealing on the wafer to restore electrical connection of the second layer structure and the first layer structure.

2. The method of forming a semiconductor structure of claim 1, wherein, The wafer edge has a positioning groove; a laser beam used in the laser annealing process has a projected spot on the wafer surface, the projected spot extending along the edge of the wafer to the center of the wafer, the projected spot having a center line along the radial direction of the wafer; the positioning groove has a first connecting line with the center of the wafer.

3. The method of forming a semiconductor structure of claim 2, wherein, The shift degree comprises a severe shift case or a slight shift case, and the shift direction comprises a shift away from the isolation region or a shift toward the isolation region; the shift amount of the severe shift case has an absolute value in a range of 30 nm to 48 nm; the shift amount of the slight shift case has an absolute value in a range of 12 nm to 30 nm.

4. The method of forming a semiconductor structure of claim 3, wherein, When the second layer structure and the first layer structure are in the severe shift case, a first laser annealing process is performed on the wafer.

5. The method of forming a semiconductor structure of claim 4, wherein, The first laser annealing process comprises a first treatment and a second treatment; the first treatment comprises rotating the wafer with a first position as a starting point, the first position having a first included angle between the center line of the spot and the first connecting line; the second treatment comprises rotating the wafer with a second position as a starting point, the second position having a second included angle between the center line of the spot and the first connecting line.

6. The method of forming a semiconductor structure of claim 5, wherein, The absolute value of the difference between the first included angle and the second included angle is 180 degrees.

7. The method of forming a semiconductor structure of claim 6, wherein, When the shift direction of the second layer structure and the first layer structure is away from the isolation region, the first included angle is in a range of 10 degrees to 45 degrees, and the second included angle is in a range of 190 degrees to 225 degrees.

8. The method of forming a semiconductor structure of claim 6, wherein, When the shift direction of the second layer structure and the first layer structure is toward the isolation region, the first included angle is in a range of 100 degrees to 135 degrees, and the second included angle is in a range of 280 degrees to 335 degrees.

9. The method of forming a semiconductor structure of claim 3, wherein, When the second layer structure and the first layer structure are in the slight shift case, a second laser annealing process is performed on the wafer.

10. The method of forming a semiconductor structure of claim 9, wherein, The second laser annealing process comprises: performing a third process and a fourth process on the wafer; the third process comprises: rotating the wafer to perform the third process on the wafer with a third position as a starting point, the third position having a third included angle between a light spot center line and the first line; and the fourth process comprises: rotating the wafer to perform the fourth process on the wafer with a fourth position as a starting point, the fourth position having a fourth included angle between a light spot center line and the first line.

11. The method of forming a semiconductor structure of claim 10, wherein, An absolute value of a difference between the third included angle and the fourth included angle is 180 degrees.

12. The method of forming a semiconductor structure of claim 11, wherein, When the offset direction of the second layer structure and the first layer structure is offset in a direction towards the isolation region, the third included angle ranges from 90 degrees to 100 degrees, and the fourth included angle ranges from 270 degrees to 280 degrees.

13. The method of forming a semiconductor structure of claim 11, wherein, When the offset direction of the second layer structure and the first layer structure is offset in a direction away from the isolation region, the third included angle ranges from 0 degrees to 10 degrees, and the fourth included angle ranges from 180 degrees to 190 degrees.

14. The method of forming a semiconductor structure of claim 1, wherein, The first layer structure comprises: a gate structure on the wafer and source / drain doped regions in the wafer on both sides of the gate structure, the source / drain doped regions being on both sides of the gate structure along a first direction; and the second layer structure comprises: a conductive plug on the source / drain doped regions, the conductive plug being electrically connected to the source / drain doped regions.

15. The method of forming a semiconductor structure of claim 14, wherein, The condition of whether the second layer structure and the first layer structure are electrically failed is obtained, comprising: if the conductive plug and the gate structure are offset in the first direction to cause the conductive plug to bridge the gate structure, the second layer structure and the first layer structure are electrically failed.

16. The method of forming a semiconductor structure of claim 1, wherein, The first layer structure comprises: a first metal layer on the wafer, the first metal layer extending in a direction perpendicular to the first direction; and the second layer structure comprises: a connecting plug on the first metal layer.

17. The method of forming a semiconductor structure of claim 16, wherein, The condition of whether the second layer structure and the first layer structure are electrically failed is obtained, comprising: if the connecting plug and the first metal layer are offset in the first direction to cause the connecting plug to not contact the first metal layer, the second layer structure and the first layer structure are electrically failed.

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