Low-offset rail-to-rail operational amplifier

Abstract

The invention belongs to the technical field of integrated circuits, and relates to a low-offset rail-to-rail operational amplifier. Comprising a three-stage main operational amplifier circuit which is composed of an input stage module, a middle stage module and an output stage module which are connected in sequence; one end of the fuse trimming module is connected to rail-to-rail input differential signals Vin + and Vin-, and the other end of the fuse trimming module is connected to the first end of the input stage module; the fuse trimming module comprises: switching tubes MD1-MD8; the drain ends of the switching tubes MD1-MD8 are connected to the input stage module, the gate ends of the switching tubes MD1-MD8 are connected to a digital control signal, and the source ends of the switching tubes MD1-MD8 are sequentially connected to a grounded eight-time current source I1, a grounded four-time current source I1, a grounded two-time current source I1 and a grounded current source I1. According to the invention, the switching-on and switching-off of an input differential pair are controlled by detecting the size of a common-mode input level, so that constant transconductance is realized; the input offset voltage of the operational amplifier is eliminated through the fuse trimming module, so that the low offset requirement of the operational amplifier is met.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a low-offset rail-to-rail operational amplifier. Background Art

[0002] Rail-to-rail operational amplifiers are a special type of operational amplifier derived from the low-voltage development trend. The high level of its input and output can reach the power supply voltage, and the low level can be as low as the ground potential; if it is a dual-power application, the low rail can reach or even be lower than the negative power supply. High-performance rail-to-rail operational amplifiers are key building blocks in advanced signal processing systems, supporting the development of high-precision information acquisition, sensor receiving ports, analog filters, and low-noise amplifiers for medical imaging and communication applications. By improving the performance indicators of rail-to-rail operational amplifiers, the overall performance and efficiency of electronic systems can be improved, including improving signal-to-noise ratio, dynamic range, linearity, and power efficiency, thereby achieving better performance and reducing power consumption. Therefore, the study of high-performance rail-to-rail operational amplifiers has become a hot topic in the current field of operational amplifiers.

[0003] In the traditional rail-to-rail amplifier circuit, the chopper stabilization technology is used to modulate the offset voltage and low-frequency noise to high frequency through the modulation switch, and the signal is demodulated to the original frequency band. After the mixed signal passes through the filter, the high-frequency offset voltage and noise are filtered out, achieving the effect of eliminating the offset voltage and noise. In order to improve the output ripple caused by the chopper stabilization technology and eliminate the disadvantage of the low-pass filter limiting the effective bandwidth, a dual-channel chopper-stabilized operational amplifier circuit is designed. The circuit structure of the dual-channel chopper-stabilized operational amplifier is shown in Figure 1. Figure 1 As shown, the circuit consists of two paths: one is a high-speed, low-gain path Path1, which is composed of a two-stage operational amplifier formed by transconductance Gmf, AC equivalent impedance r2 and amplifier A3; the other is a low-speed, high-gain path Path2, which includes a three-stage operational amplifier formed by amplifier A1, transconductance Gm2, AC equivalent impedance r2 and amplifier A3, and also includes chopper switches chop1, chop2 and notch filter Notch-filter.

[0004] The process of offset suppression of this circuit is as follows: in path Path2, the offset voltage VOS1 of amplifier A1 is amplified by amplifier A1 and modulated to the chopping frequency by chopper switch chop2, and then filtered out by a notch filter. The remaining residual offset and the offset voltage of transconductance Gm2 together constitute VOS3, which is amplified by the subsequent amplifier circuit to obtain the output offset voltage of path Path2: Vout2 = VOS3 × Gm2 × r2 × A3; path Path1 does not process the offset, and the offset voltage VOS2 of transconductance Gmf is directly amplified to the output, so the output offset voltage of path Path1 is: Vout1 = VOS2 × Gmf × r2 × A3. For the entire operational amplifier, the total output offset voltage is the sum of the output offset voltages of the two paths: Vout = Vout1 + Vout2 = (Vos2 × Gmf + Vos3 × Gm2) × r2 × A3; therefore, the total output offset voltage is equivalent to the input: VOS,in = (Vos2 × Gmf + Vos3 × Gm2) / (A1 × Gm2 + Gmf); the dual-channel chopper-stabilized operational amplifier circuit does not completely eliminate the offset voltage, but uses the high gain of the three-stage operational amplifier to weaken the offset voltage of path Path1 and the residual offset voltage of path Path2, thereby suppressing the offset voltage of the operational amplifier. The circuit also has the same mechanism for suppressing noise. The above operational amplifier includes two paths, path Path1 is a two-stage operational amplifier path, and path 2 is a three-stage operational amplifier, which has many zeros and poles, bringing additional stability problems, so it is necessary to introduce a variety of additional frequency compensation technologies.

[0005] In view of the above situation, in traditional rail-to-rail amplifiers, on the one hand, introducing a chopper switching circuit to eliminate noise and offset will introduce additional switching and clock circuits; on the other hand, the complex amplifier structure leads to many system zeros and poles, introducing additional stability problems. The complex circuit structure leads to a significant increase in the layout area and high chip cost. Summary of the invention

[0006] The purpose of the present invention is to overcome the above-mentioned shortcomings of the prior art. The present invention provides a low offset rail-to-rail operational amplifier, which adopts a multi-stage structure to meet the high gain performance conditions. For the input stage, the complementary differential pair is controlled to be turned on and off by detecting the common-mode input level to achieve constant transconductance, and the structure is simple; the input offset voltage of the operational amplifier is eliminated by a fuse trimming module, and the offset is small.

[0007] In order to solve the above technical problems, the present invention provides a low offset rail-to-rail operational amplifier, comprising:

[0008] The three-stage main operational amplifier circuit is composed of an input stage module, an intermediate stage module and an output stage module connected in sequence; rail-to-rail input differential signals Vin+ and Vin- are input to the input stage module and the intermediate stage module, the input stage module outputs differential signals Vamp+ and Vamp- to the intermediate stage module, the intermediate stage module outputs differential signals OUT+ and OUT- to the output stage module, the output stage module outputs a rail-to-rail output signal OUT, and a Miller capacitor Cc is connected between the differential signal Vamp+ and the rail-to-rail output signal OUT;

[0009] A fuse trimming module, one end of which is connected to the rail-to-rail input differential signals Vin+ and Vin-, and the other end of which is connected to the first end of the input stage module; wherein the fuse trimming module comprises: switch tubes MD1-MD8; the drain ends of the switch tubes MD1-MD8 are connected to the input stage module, the gate ends of the switch tubes MD1-MD8 are connected to the control digital signals D1-D8 in sequence, the source ends of the switch tubes MD1-MD8 are connected to the grounded 8-fold current source I1, 4-fold current source I1, 2-fold current source I1 and current source I1 in sequence, and the source ends of the switch tubes MD1-MD8 are connected to the grounded 8-fold current source I1, 4-fold current source I1, 2-fold current source I1 and current source I1 in sequence;

[0010] A common mode detection circuit, one end of which is connected to the rail-to-rail input differential signal Vin+ and the input reference voltage Vb, and the other end of which is connected to the second end of the input stage module and the first end of the intermediate stage module; wherein the common mode detection circuit comprises: MOS tubes M1-M11; the gate end of the MOS tube M1 is connected to the rail-to-rail input differential signal Vin+, the source ends of the MOS tubes M1-M2 are connected to the grounded reference current source Iref, the drain end of the MOS tube M1 is connected to the drain end and the gate end of the MOS tube M3 and the gate end of the MOS tube M9, the drain end of the MOS tube M9 is connected to the drain end of the MOS tube M10, the gate end of the MOS tube M10 is connected to the input reference voltage Vb, the source end of the MOS tube M10 is connected to the drain end and the gate end of the MOS tube M11 and generates an output current I out1, the source end of the MOS tube M11 is grounded, the drain end of the MOS tube M2 is connected to the drain end and gate end of the MOS tube M4 and the gate end of the MOS tube M5 to generate an output current Iout2, the drain end of the MOS tube M5 is connected to the gate end of the MOS tube M6 and the grounded reference current source Iref to generate a voltage V1, the drain end of the MOS tube M6 is connected to the resistor R, the drain end and gate end of the MOS tube M7 and the gate end of the MOS tube M8 and the gate end of the MOS tube M2, and is connected to the input reference voltage Vb, the drain end of the MOS tube M8 is connected to the source end of the MOS tube M7, the source end of the MOS tube M8 is connected to the grounded reference current source Iref, the source ends of the MOS tube M9 and the MOS tubes M3 to M6, and the other end of the resistor R are all connected to the power supply end.

[0011] Preferably, the input stage module includes: MOS transistors MC1-MC12 and resistors RC1-RC4; the gate terminals of the MOS transistors MC2 and MOS transistors MC1 are respectively connected to rail-to-rail input differential signals Vin+ and Vin-, the source terminals of the MOS transistors MC1 and MOS transistors MC2 are connected to a 64-fold current source I2, the drain terminal of the MOS transistor MC1 is connected to the source terminal of the MOS transistor MC11 and the grounded resistor RC1; the drain terminal of the MOS transistor MC2 is connected to the source terminal of the MOS transistor MC12 and the grounded resistor RC2; the gate terminal of the MOS transistor MC11 is connected to the gate terminal and the drain terminal of the MOS transistor MC12, and the drain terminal and the differential signal Vamp- of the MOS transistor MC10, the drain terminal of the MOS transistor MC11 is connected to the drain terminal and the differential signal Vamp+ of the MOS transistor MC9, and the gate terminals of the MOS transistors MC9 and MOS transistors MC10 are connected to the bias voltage VC3; the source terminal of the MOS transistor MC9 is connected to the gate terminal of the MOS transistor MC11. The drain ends of the S transistor MC7 and the MOS transistor MC3, the gate end of the MOS transistor MC3 is connected to the rail-to-rail input differential signal Vin-, the source ends of the MOS transistor MC3 and the MOS transistor MC4 are connected to the grounded 50 times current source I1, the gate end of the MOS transistor MC4 is connected to the rail-to-rail input differential signal Vin+, the drain end of the MOS transistor MC4 is connected to the source end of the MOS transistor MC10 and the drain end of the MOS transistor MC8, the gate ends of the MOS transistor MC7 and the MOS transistor MC8 are connected to the bias voltage VC2; the source end of the MOS transistor MC7 is connected to the drain end of the MOS transistor MC5 and the resistor RC3, the gate ends of the MOS transistor MC5 and the MOS transistor MC6 are connected to the bias voltage VC1; the source end of the MOS transistor MC8 is connected to the drain end of the MOS transistor MC6 and the resistor RC4, the other ends of the resistors RC3-RC4, the source ends of the MOS transistors MC5-MC6 and the other end of the 64 times current source I2 are all connected to the power supply end.

[0012] Preferably, the MOS transistors MC1 to MC2 constitute a PMOS complementary differential input pair of transistors, and the MOS transistors MC3 to MC4 constitute a NMOS complementary differential input pair of transistors.

[0013] Preferably, the MOS transistors MC5 to MC10 form two groups of PMOS cascode current mirrors, and the MOS transistors MC11 to MC12 form two groups of NMOS cascode current mirrors.

[0014] Preferably, the MOS transistor M1 and the MOS transistor M2 are NMOS differential input pair transistors, and the MOS transistors M3-M4 and the MOS transistors M9-M10 form a PMOS current mirror structure.

[0015] Preferably, the intermediate module includes: MOS transistors Q13 to Q28; the gate terminals of the MOS transistors Q13 and Q14 are respectively connected to differential signals Vamp+ and Vamp-, the source terminals of the MOS transistors Q13 and Q14 are connected to a current source I3, the drain terminal of the MOS transistor Q13 is connected to the drain terminals of the MOS transistors Q15 and Q27 and the source terminal of the MOS transistor Q25 and is connected to a node P1, the drain terminal of the MOS transistor Q14 is connected to the drain terminals of the MOS transistors Q16 and Q28 The drain end and the source end of the MOS transistor Q26 are connected to the node P2; the gate ends of the MOS transistor Q16 and the MOS transistor Q15 are respectively connected to the rail-to-rail input differential signals Vin+ and Vin-, and the source ends of the MOS transistor Q16 and the MOS transistor Q15 are connected to the current source I4; the source ends of the MOS transistor Q27 and the MOS transistor Q28 are grounded, and the gate ends of the MOS transistor Q27 and the MOS transistor Q28 are connected to the drain ends of the MOS transistor Q25 and the MOS transistor Q23; the gate ends of the MOS transistor Q25 and the MOS transistor Q26 are connected to the drain ends of the MOS transistor Q25 and the MOS transistor Q23; The gate terminals of the MOS transistors Q23 and Q24 are connected to the bias voltage Vb7, the gate terminals of the MOS transistors Q23 and Q24 are connected to the bias voltage Vb6, the source terminals of the MOS transistors Q24 and Q26 are connected to the differential signals OUT+ and OUT- respectively; the source terminal of the MOS transistor Q23 is connected to the drain terminals of the MOS transistors Q21, Q17 and Q19 and is connected to the node N1, the gate terminals of the MOS transistors Q21 and Q22 are connected to the bias voltage Vb5; the source terminal of the MOS transistor Q24 ... gate terminal of the MOS transistor Q24 is connected to The drain ends of the MOS transistors Q22, Q20 and Q18 are connected to the node N2, the gate ends of the MOS transistors Q19 and Q20 are connected to the bias voltage Vb4, the gate ends of the MOS transistors Q18 and Q17 are respectively connected to the rail-to-rail input differential signals Vin+ and Vin-, the source ends of the MOS transistors Q17 and Q18 are connected to the grounded current source I5; the other ends of the current source I3 and the current source I4, and the source ends of the MOS transistors Q19 to Q22 are all connected to the power supply end.

[0016] Preferably, the MOS transistors Q13 ˜ Q14 and the MOS transistors Q15 ˜ Q16 constitute two groups of PMOS differential input pair transistors, and the MOS transistors Q17 ˜ Q18 constitute one group of NMOS differential input pair transistors.

[0017] Preferably, the MOS transistors Q21 to Q24 constitute two groups of PMOS cascode current mirrors, and the MOS transistors Q25 to Q28 constitute two groups of NMOS cascode current mirrors.

[0018] Preferably, the output stage module includes: MOS tubes T1-T18; the source ends of the MOS tubes T1-T2, MOS tubes T13-T14 and one end of the current source I9 are all connected to the power supply end; the gate ends of the MOS tube T1 and the MOS tube T2 are connected to the bias voltage Vb3, the drain end of the MOS tube T1 is connected to the source end of the MOS tube T3 and the node N1, the drain end of the MOS tube T2 is connected to the source end of the MOS tube T4, the node N2 and one end of the compensation capacitor Cc2, and the other end of the compensation capacitor Cc2 is connected The rail-to-rail output signal OUT is connected; the gate terminals of the MOS transistors T3 and T4 are connected to the bias voltage Vb1, the drain terminal of the MOS transistor T4 is connected to the source terminal of the MOS transistor T6, the drain terminal of the MOS transistor T8 and the gate terminal of the MOS transistor T17 and is connected to the differential signal OUT+; the drain terminal of the MOS transistor T6 is connected to the source terminal of the MOS transistor T8, the drain terminal of the MOS transistor T10 and the gate terminal of the MOS transistor T18 and is connected to the differential signal OUT-; the drain terminal of the MOS transistor T3 is connected to the drain terminal of the MOS transistor T9, the drain terminal of the MOS transistor T10 and the gate terminal of the MOS transistor T18 and is connected to the differential signal OUT-. The gate ends of the MOS transistors T11 and T12, and the gate ends of the MOS transistors T9 and T10 are connected to the bias voltage Vb2; the source end of the MOS transistor T9 is connected to the node P1 and the drain end of the MOS transistor T11, the source ends of the MOS transistors T11, T12, T16 and T18, and one end of the current source I8 are all grounded, the drain end of the MOS transistor T12 is connected to the node P2, the source end of the MOS transistor T10 and one end of the compensation capacitor Cc1, and the other end of the compensation capacitor Cc1 is connected to the node P2, the source end of the MOS transistor T10 and one end of the compensation capacitor Cc1. The other end of the current source I8 is connected to the gate end of the MOS tube T6, the drain end and the gate end of the MOS tube T14, and the source end of the MOS tube T14 is connected to the drain end and the gate end of the MOS tube T13; the other end of the current source I9 is ​​connected to the gate end of the MOS tube T8, the drain end and the gate end of the MOS tube T15, and the source end of the MOS tube T15 is connected to the drain end and the gate end of the MOS tube T16; the drain ends of the MOS tubes T17 and T18 are connected and connected to the rail-to-rail output signal OUT.

[0019] Compared with the prior art, the present invention has the following beneficial effects:

[0020] The input stage module of the present invention adopts a N-type MOSFET and a P-type MOSFET differential pair connected in parallel to form a complementary structure, realizing rail-to-rail input common mode signal range, the intermediate stage module provides a driving signal for the output stage while providing a certain gain, and the output stage module adopts a push-pull structure to provide a larger output current at a lower quiescent current to achieve rail-to-rail output. For the input stage module, the opening and closing of the input N-type MOSFET and P-type MOSFET differential pair are controlled by detecting the common mode input level to realize constant transconductance; the input offset voltage of the operational amplifier is eliminated by the fuse trimming module to meet the low offset requirement of the operational amplifier. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 The invention is a schematic diagram of a dual-channel chopper-stabilized operational amplifier circuit in the prior art.

[0022] Figure 2 It is a circuit diagram of a low offset rail-to-rail operational amplifier of the present invention.

[0023] Figure 3 It is a circuit diagram of the input stage module and the fuse trimming module of the present invention.

[0024] Figure 4 It is a circuit diagram of the common mode detection circuit of the present invention.

[0025] Figure 5 Schematic diagram of the circuit of the intermediate module of the present invention.

[0026] Figure 6 Schematic diagram of the circuit of the output stage module of the present invention. DETAILED DESCRIPTION

[0027] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the accompanying drawings are in very simplified form and in non-precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0028] like Figure 2 As shown, an embodiment of the present invention discloses a low offset rail-to-rail operational amplifier, comprising:

[0029] The three-stage main operational amplifier circuit is composed of an input stage module, an intermediate stage module and an output stage module connected in sequence; rail-to-rail input differential signals Vin+ and Vin- are input to the input stage module and the intermediate stage module, the input stage module outputs differential signals Vamp+ and Vamp- to the intermediate stage module, the intermediate stage module outputs differential signals OUT+ and OUT- to the output stage module, the output stage module outputs a rail-to-rail output signal OUT, and a Miller capacitor Cc is connected between the differential signal Vamp+ and the rail-to-rail output signal OUT;

[0030] like Figure 3 As shown, a fuse trimming module has one end connected to the rail-to-rail input differential signals Vin+ and Vin-, and the other end connected to the first end of the input stage module; wherein the fuse trimming module includes: switch tubes MD1-MD8; the drain ends of the switch tubes MD1-MD8 are connected to the input stage module, the gate ends of the switch tubes MD1-MD8 are connected to the control digital signals D1-D8 in sequence, the source ends of the switch tubes MD1-MD4 are connected to the grounded 8-fold current source I1, 4-fold current source I1, 2-fold current source I1 and current source I1 in sequence, and the source ends of the switch tubes MD5-MD8 are connected to the grounded 8-fold current source I1, 4-fold current source I1, 2-fold current source I1 and current source I1 in sequence; in order to reduce the operational amplifier offset, the output Vamp+ and Vamp- common mode levels are adjusted by controlling the load of the folded input stage through the fuse, thereby increasing the common mode rejection characteristics of the circuit. In the embodiment of the present invention, the control word signal obtained by fuse control is an 8-bit control digital signal D1~D8, which controls the opening and closing of NMOS switch tubes MD1~MD8 to achieve adjustment. In the embodiment of the present invention, the offset voltage adjustment step is 70μV, and the adjustable range is 1050μV.

[0031] like Figure 4As shown, in order to ensure a wide common-mode input range and a constant input stage transconductance, an embodiment of the present invention uses a common-mode detection circuit to realize the control of a complementary differential input pair of transistors, wherein one end of the common-mode detection circuit is connected to the rail-to-rail input differential signal Vin+ and the input reference voltage Vb, and the other end is connected to the second end of the input stage module and the first end of the intermediate stage module; wherein the common-mode detection circuit comprises: MOS transistors M1 to M11; the gate end of the MOS transistor M1 is connected to the rail-to-rail input differential signal Vin+, the source ends of the MOS transistors M1 to M2 are connected to a grounded reference current source Iref, the drain end of the MOS transistor M1 is connected to the drain end and the gate end of the MOS transistor M3 and the gate end of the MOS transistor M9, the drain end of the MOS transistor M9 is connected to the drain end of the MOS transistor M10, the gate end of the MOS transistor M10 is connected to the input reference voltage Vb, and the MOS transistor M10 is connected to the input reference voltage Vb. The source end of the MOS tube M11 is connected to the drain end and the gate end of the MOS tube M11 and generates an output current Iout1. The source end of the MOS tube M11 is grounded. The drain end of the MOS tube M2 is connected to the drain end and the gate end of the MOS tube M4 and the gate end of the MOS tube M5 and generates an output current Iout2. The drain end of the MOS tube M5 is connected to the gate end of the MOS tube M6 and the grounded reference current source Iref and generates a voltage V1. The drain end of the MOS tube M6 is connected to the resistor R, the drain end and the gate end of the MOS tube M7 and the gate end of the MOS tube M8 and the gate end of the MOS tube M2, and is connected to the input reference voltage Vb. The drain end of the MOS tube M8 is connected to the source end of the MOS tube M7. The source end of the MOS tube M8 is connected to the grounded reference current source Iref. The source ends of the MOS tube M9 and the MOS tubes M3 to M6, and the other end of the resistor R are all connected to the power supply end.

[0032] Common mode detection circuit such as Figure 4 As shown, the input reference level Vb signal is fixed, Vin+ is a rail-to-rail input signal, wherein the Vb signal is generated by PMOS tubes M6, M7, and M8 under the action of the reference current Iref. The common-mode level detection circuit is a differential operational amplifier structure, NMOS tubes M1 and M2 are differential input pairs, and the diode connects PMOS tubes M3 and M4 with PMOS tubes M9 and M10 to form a current mirror structure, and the output currents Iout1 and Iout2 provide bias currents for the PMOS differential input pairs and NMOS differential input pairs, respectively.

[0033] The specific working principle of the common mode detection circuit is as follows: when the input common mode signal Vin+ is low, Vin+ is much smaller than Vb, then the current Iref flows through the M2 tube, and outputs the current Iout1 through the M3 and M9 current mirrors, that is, the current mirror output current is 0, and the M4 and M5 current mirrors output the current Iout2 as the current Iref, at this time, the NMOS input pair is closed, and the PMOS input pair is turned on. As Vin+ increases, the M1 tube is turned on, and the current Iout1 can continue to flow. Since the current flowing through the M2 tube is less than the current Iref, that is, the current flowing through the M5 tube is lower than the current Iref, the voltage V1 decreases, the current of the M6 ​​tube increases, and the voltage Vb will rise slightly. When Vin+ continues to increase, the voltage Vb can no longer increase due to resistance limitation, then the M2 tube is closed, and all the current flows through the M1 tube. The current Iout1 flows through the current Iref, and the current Iout2 flows through the current 0, that is, at this time, under high common mode, the PMOS pair of tubes mirrored by the current Iout2 is closed, and the NMOS pair of tubes mirrored by the current Iout1 is opened. Thus, the NMOS input differential pair and the PMOS input differential pair are opened respectively under different high and low common mode conditions to achieve the function of constant transconductance.

[0034] When the input common-mode voltage is less than the common-mode detection threshold, the PMOS input differential pair works, and the total transconductance of the op amp input is:

[0035]

[0036] When the input common-mode voltage is less than the common-mode detection threshold, the NMOS input differential pair works, and the total transconductance of the op amp input is:

[0037]

[0038] If you want to use different input common mode ranges m,tot If they are equal,

[0039] u n C ox (W / L) n I n =u p C ox (W / L) p I p ;

[0040] In the above formula, u n 、u p are the electron mobility of NMOS input differential pair and PMOS input differential pair, C ox is the MOSFET gate oxide capacitance, (W / L) n and (W / L)p are the width-to-length ratios of the NMOS input differential pair and the PMOS input differential pair, respectively.n and I p are the tail current sources of the NMOS input differential pair and the PMOS input differential pair, respectively. In the embodiment of the present invention, the uC ox The value of the PMOS tube is ox Compared with NMOS tubes, the width-to-length ratio of the PMOS input differential pair is set to 1000 / 1, and that of the NMOS tube is 480 / 1. The tail current of the PMOS tube is 64Iref, and that of the NMOS tube is 50Iref. Under the condition of VDD=5V, the input common mode is 0V~3.88V, the PMOS input differential pair is turned on, and the NMOS input differential pair is turned on under the input common mode of 3.88V~5V, which can achieve the effect of constant transconductance. Since the noise performance of the PMOS input differential pair is lower than that of the NMOS input differential pair, it is hoped that the PMOS input differential pair is in a working state more often. However, when the flip level Vb is too high, the gate-source voltage of the PMOS input differential pair is too small, and the tail current source enters the linear region, reducing the common mode rejection ratio CMRR of the op amp.

[0041] like Figure 3As shown, the main function of the input stage module is to amplify the input rail-to-rail differential signal. This stage adopts a high-gain folding structure to achieve this, and at the same time compensates for the impact of the offset voltage caused by the device process or packaging through the tail current controlled by the digital signal. The input stage module includes: MOS transistors MC1-MC12 and resistors RC1-RC4; the gate terminals of the MOS transistors MC2 and MOS transistors MC1 are respectively connected to rail-to-rail input differential signals Vin+ and Vin-, the source terminals of the MOS transistors MC1 and MOS transistors MC2 are connected to a 64-fold current source I2, the drain terminal of the MOS transistor MC1 is connected to the source terminal of the MOS transistor MC11 and the grounded resistor RC1; the drain terminal of the MOS transistor MC2 is connected to the source terminal of the MOS transistor MC12 and the grounded resistor RC2; the gate terminal of the MOS transistor MC11 is connected to the gate terminal and drain terminal of the MOS transistor MC12, the drain terminal of the MOS transistor MC10 and the differential signal Vamp-, the drain terminal of the MOS transistor MC11 is connected to the drain terminal of the MOS transistor MC9 and the differential signal Vamp+, the gate terminals of the MOS transistors MC9 and MOS transistors MC10 are connected to the bias voltage VC3; the source terminal of the MOS transistor MC9 is connected to the gate terminal of the MOS transistor MC11, and the gate terminal of the MOS transistor MC10 is connected to the bias voltage VC4; the source terminal of the MOS transistor MC9 is connected to the gate terminal of the MOS transistor MC11. The gate end of the MOS transistor MC3 is connected to the rail-to-rail input differential signal Vin-, the source ends of the MOS transistor MC3 and the MOS transistor MC4 are connected to the grounded 50 times current source I1, the gate end of the MOS transistor MC4 is connected to the rail-to-rail input differential signal Vin+, the drain end of the MOS transistor MC4 is connected to the source end of the MOS transistor MC10 and the drain end of the MOS transistor MC8, and the gate ends of the MOS transistor MC7 and the MOS transistor MC8 are connected to the bias voltage VC2; the source end of the MOS transistor MC7 is connected to the drain end of the MOS transistor MC5 and the resistor RC3, and the gate ends of the MOS transistor MC5 and the MOS transistor MC6 are connected to the bias voltage VC1; the source end of the MOS transistor MC8 is connected to the drain end of the MOS transistor MC6 and the resistor RC4, and the other ends of the resistors RC3-RC4, the source ends of the MOS transistors MC5-MC6 and the other end of the 64 times current source I2 are all connected to the power supply end.

[0042] The MOS transistors MC1-MC2 constitute a PMOS complementary differential input pair of transistors, and the MOS transistors MC3-MC4 constitute a NMOS complementary differential input pair of transistors.

[0043] The MOS transistors MC5-MC10 and the resistors RC3-RC4 form two groups of PMOS cascode current mirrors.

[0044] The bias current of the complementary differential input pair is provided by the common mode detection circuit, so as to realize the constant transconductance of the input stage and achieve the goal of constant transconductance; then the input stage gain can be expressed as:

[0045] A V1 =gmtot {gm c10 r 0c10 [(gm c8 r 0c8 (r 0c6 / / R c4 ))] / / gm c12 r oc12 (r d,tot / / R c2 / / r 0c2 )};

[0046] In the above formula, gm tot is the equivalent input total transconductance, gm c10 and gm c12 are the transconductance of PMOS tube MC10 and NMOS tube MC12, r 0c10 and r oc12 The equivalent output impedance of the PMOS tube MC10 and the NMOS tube MC12, r 0c6 、r 0c8 、r 0c2 are the equivalent output impedances of PMOS tube MC6, PMOS tube MC8, and PMOS tube MC2, respectively. d,tot is the equivalent impedance of the fuse trimming control module, R C2 and R C4 is the resistance value of resistor RC2 and resistor RC4, and “ / / ” is the resistor parallel operation symbol.

[0047] like Figure 5As shown, the main function of the intermediate stage module is to provide a high gain stage, and this stage directly drives the output stage. The intermediate stage module includes: MOS transistors Q13 to Q28; the gate terminals of the MOS transistors Q13 and Q14 are respectively connected to the differential signals Vamp+ and Vamp-, the source terminals of the MOS transistors Q13 and Q14 are connected to the current source I3, the drain terminal of the MOS transistor Q13 is connected to the drain terminals of the MOS transistors Q15 and Q27 and the source terminal of the MOS transistor Q25 and is connected to the node P1, the drain terminal of the MOS transistor Q14 is connected to the drain terminals of the MOS transistors Q16 and Q28 and is connected to the node P1. and the source end of the MOS transistor Q26 and connected to the node P2; the gate ends of the MOS transistor Q16 and the MOS transistor Q15 are respectively connected to the rail-to-rail input differential signals Vin+ and Vin-, and the source ends of the MOS transistor Q16 and the MOS transistor Q15 are connected to the current source I4; the source ends of the MOS transistor Q27 and the MOS transistor Q28 are grounded, and the gate ends of the MOS transistor Q27 and the MOS transistor Q28 are connected to the drain ends of the MOS transistor Q25 and the MOS transistor Q23; the gate ends of the MOS transistor Q25 and the MOS transistor Q26 are connected The bias voltage Vb7 is connected to the gate terminals of the MOS transistors Q23 and Q24, and the source terminals of the MOS transistors Q24 and Q26 are connected to the differential signals OUT+ and OUT-, respectively; the source terminal of the MOS transistor Q23 is connected to the drain terminals of the MOS transistors Q21, Q17 and Q19 and connected to the node N1, and the gate terminals of the MOS transistors Q21 and Q22 are connected to the bias voltage Vb5; the source terminal of the MOS transistor Q24 is connected to the drain terminals of the MOS transistors Q21, Q17 and Q19 and connected to the node N1; the gate terminals of the MOS transistors Q21 and Q22 are connected to the bias voltage Vb5; the source terminal of the MOS transistor Q24 is connected to the drain terminals of the MOS transistors Q21, Q17 and Q19 and connected to the node N1; 22. The drain terminals of the MOS transistors Q20 and Q18 are connected to the node N2, the gate terminals of the MOS transistors Q19 and Q20 are connected to the bias voltage Vb4, the gate terminals of the MOS transistors Q18 and Q17 are respectively connected to the rail-to-rail input differential signals Vin+ and Vin-, the source terminals of the MOS transistors Q17 and Q18 are connected to the grounded current source I5; the other terminals of the current source I3 and the current source I4, and the source terminals of the MOS transistors Q19 to Q22 are all connected to the power supply terminal.

[0048] The MOS transistors Q13-Q14 and MOS transistors Q15-Q16 form two groups of PMOS differential input pairs, and the MOS transistors Q17-Q18 form a group of NMOS differential input pairs. Among the three differential input pairs, the common mode level of the PMOS transistor Q13 and the PMOS transistor Q14 differential pair is half of the power supply voltage, and the common mode is fixed. The common mode levels of the other two groups of PMOS differential input pairs, PMOS transistors Q15 and PMOS transistors Q16, and NMOS differential input pairs, NMOS transistors Q17 and NMOS transistors Q18, change with the input voltage, and their bias currents are also controlled and provided by the above common mode detection circuit.

[0049] The MOS transistors Q21 to Q24 form two groups of PMOS cascode current mirrors, and the MOS transistors Q25 to Q28 form two groups of NMOS cascode current mirrors.

[0050] Bias tubes PMOS tube Q19 and PMOS tube Q20 provide loads for NMOS differential input pairs NMOS tube Q17 and NMOS tube Q18. This stage has differential output, and the outputs are OUT+ and OUT-. The gain of this stage is A V2 The expression is:

[0051] A V2 =(gm tot +gm 13,14 ){gm 26 r 026 (r 028 / / r 024 / / r 016 ) / / gm 24 r o24 (r 022 / / r 020 / / r 018 )};

[0052] In the above formula, gm tot is the equivalent input impedance of the complementary differential input pair, gm 13,14 are the equivalent transconductance of PMOS tubes Q13 and Q14, gm 24 , gm 26 are the equivalent transconductances of Q24 and Q26, r 026 ,

[0053] r 028 、r 024 、r 016 、r 022 、r 020 and r 018 They are the equivalent output impedances of Q26, Q28, Q24, Q16, Q22, Q20 and Q18 respectively, and “ / / ” is the resistor parallel operation symbol.

[0054] like Figure 2 and Figure 6As shown, the output OUT+ and OUT- of the intermediate stage drive the output power tubes to be PMOS tube T17 and NMOS tube T18 to realize common source amplification, and finally realize the differential to single-ended output OUT. The output stage module includes: MOS tubes T1~T18; the source ends of the MOS tubes T1~T2, MOS tubes T13~T14 and one end of the current source I9 are all connected to the power supply end; the gate ends of the MOS tube T1 and MOS tube T2 are connected to the bias voltage Vb3, the drain end of the MOS tube T1 is connected to the source end of the MOS tube T3 and the node N1, the drain end of the MOS tube T2 is connected to the source end of the MOS tube T4, the node N2 and one end of the compensation capacitor Cc2, and the other end of the compensation capacitor Cc2 is connected to the rail pair The gate terminals of the MOS transistors T3 and T4 are connected to the bias voltage Vb1, the drain terminal of the MOS transistor T4 is connected to the source terminal of the MOS transistor T6, the drain terminal of the MOS transistor T8 and the gate terminal of the MOS transistor T17 and is connected to the differential signal OUT+; the drain terminal of the MOS transistor T6 is connected to the source terminal of the MOS transistor T8, the drain terminal of the MOS transistor T10 and the gate terminal of the MOS transistor T18 and is connected to the differential signal OUT-; the drain terminal of the MOS transistor T3 is connected to the drain terminal of the MOS transistor T9, the drain terminal of the MOS transistor T10 and the gate terminal of the MOS transistor T18 and is connected to the differential signal OUT-. 11 and the gate end of the MOS tube T12, the gate ends of the MOS tube T9 and the MOS tube T10 are connected to generate a bias voltage Vb2; the source end of the MOS tube T9 is connected to the node P1 and the drain end of the MOS tube T11, the source ends of the MOS tubes T11, MOS tubes T12, MOS tubes T16 and MOS tubes T18 and one end of the current source I3 are all grounded, the drain end of the MOS tube T12 is connected to the node P2, the source end of the MOS tube T10 and one end of the compensation capacitor Cc1, and the other end of the compensation capacitor Cc1 is connected to the node P2, the source end of the MOS tube T10 and one end of the compensation capacitor Cc1. The rail-to-rail output signal OUT is connected; the other end of the current source I3 is connected to the gate end of the MOS tube T6, the drain end and the gate end of the MOS tube T14, and the source end of the MOS tube T14 is connected to the drain end and the gate end of the MOS tube T13; the other end of the current source I8 is connected to the gate end of the MOS tube T8, the drain end and the gate end of the MOS tube T15, and the source end of the MOS tube T15 is connected to the drain end and the gate end of the MOS tube T16; the drain ends of the MOS tubes T17 and T18 are connected and connected to the rail-to-rail output signal OUT.

[0055] The gate bias voltage of the output power tube T18 is generated by the bias current I9, the diode connected NMOS tubes T15 and T16 and the NMOS tube T8, wherein the bias current I9 and the diode connected NMOS tubes T15 and T16 generate the bias voltage VBN, then VBN is connected to the gate of the NMOS tube T8, and the output drain voltage provides the gate bias voltage for T18; the gate bias voltage of the output power tube T17 is generated by the bias current I8, the diode connected PMOS tubes T13 and T14 and the PMOS tube T6, wherein the bias current I8 and the diode connected PMOS tubes T13 and T14 generate the bias voltage VBP, then VBP is connected to the gate of the PMOS tube T6, and the output drain voltage provides the gate bias voltage for T17. The size of the static current in the output pair tube is determined by the two current loops of T17, T6, T13, T14 and T18, T8, T15, T16, and the bias loop has:

[0056] V GS13 +V GS14 =V GS6 +V GS17 ;

[0057] V GS15 +V GS16 =V GS8 +V GS18 ;

[0058] Properly adjust T6, T14, T8, T15 so that their gate-source voltage V GS Yes |V GS13 |=V GS6 , V GS16 =V GS8 When the relationship is:

[0059]

[0060] If the loop current I q13 =I q16 ,at the same time Then there is

[0061]

[0062] In this way, the bias circuit can determine the output quiescent current and will not change due to changes in the common-mode input voltage. 10 The drain node of the output stage is short-circuited and in high impedance state, and the gain of the input stage is maintained. V3 The expression is:

[0063]

[0064] In the above formula, gm 17 , gm18 are the equivalent transconductances of the output power tubes PMOS tube T17 and NMOS tube T18, r 018 、r 017 are the equivalent output impedances of T18 and T17 respectively.

[0065] In summary, the total voltage gain of the rail-to-rail amplifier of the present invention is:

[0066] A V =A V1 ·A V2 ·A V3

[0067] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A low offset rail-to-rail operational amplifier, characterized in that: include: The three-stage main operational amplifier circuit is composed of an input stage module, an intermediate stage module and an output stage module connected in sequence; rail-to-rail input differential signals Vin+ and Vin- are input to the input stage module and the intermediate stage module, the input stage module outputs differential signals Vamp+ and Vamp- to the intermediate stage module, the intermediate stage module outputs differential signals OUT+ and OUT- to the output stage module, the output stage module outputs a rail-to-rail output signal OUT, and a Miller capacitor Cc is connected between the differential signal Vamp+ and the rail-to-rail output signal OUT; A fuse trimming module, one end of which is connected to the rail-to-rail input differential signals Vin+ and Vin-, and the other end of which is connected to the first end of the input stage module; The fuse trimming module includes: switch tubes MD1-MD8; the drain ends of the switch tubes MD1-MD8 are connected to the input stage module, the gate ends of the switch tubes MD1-MD8 are connected to the control digital signals D1-D8 in sequence, the source ends of the switch tubes MD1-MD8 are connected to the grounded 8-fold current source I1, 4-fold current source I1, 2-fold current source I1 and current source I1 in sequence, and the source ends of the switch tubes MD1-MD8 are connected to the grounded 8-fold current source I1, 4-fold current source I1, 2-fold current source I1 and current source I1 in sequence; A common mode detection circuit, one end of which is connected to the rail-to-rail input differential signal Vin+ and the input reference voltage Vb, and the other end of which is connected to the second end of the input stage module and the first end of the intermediate stage module; wherein the common mode detection circuit comprises: MOS tubes M1~M11; the gate end of the MOS tube M1 is connected to the rail-to-rail input differential signal Vin+, the source ends of the MOS tubes M1~M2 are connected to the grounded reference current source Iref, the drain end of the MOS tube M1 is connected to the drain end and the gate end of the MOS tube M3 and the gate end of the MOS tube M9, the drain end of the MOS tube M9 is connected to the drain end of the MOS tube M10, the gate end of the MOS tube M10 is connected to the input reference voltage Vb, the source end of the MOS tube M10 is connected to the drain end and the gate end of the MOS tube M11 and generates an output current I out1, the source end of the MOS tube M11 is grounded, the drain end of the MOS tube M2 is connected to the drain end and gate end of the MOS tube M4 and the gate end of the MOS tube M5 and generates an output current Iout2, the drain end of the MOS tube M5 is connected to the gate end of the MOS tube M6 and the grounded reference current source Iref and generates a voltage V1, the drain end of the MOS tube M6 is connected to the resistor R, the drain end and gate end of the MOS tube M7 and the gate end of the MOS tube M8 and the gate end of the MOS tube M2, and is connected to the input reference voltage Vb, the drain end of the MOS tube M8 is connected to the source end of the MOS tube M7, the source end of the MOS tube M8 is connected to the grounded reference current source Iref, the source ends of the MOS tube M9 and the MOS tubes M3 to M6, and the other end of the resistor R are all connected to the power supply end.

2. A low offset rail-to-rail operational amplifier as claimed in claim 1, characterized in that: The input stage module includes: MOS transistors MC1~MC12 and resistors RC1~RC4; the gate ends of the MOS transistors MC2 and MOS transistors MC1 are respectively connected to rail-to-rail input differential signals Vin+ and Vin-, the source ends of the MOS transistors MC1 and MOS transistors MC2 are connected to a 64-fold current source I2, the drain end of the MOS transistor MC1 is connected to the source end of the MOS transistor MC11 and the grounded resistor RC1; the drain end of the MOS transistor MC2 is connected to the source end of the MOS transistor MC12 and the grounded resistor RC2; the gate end of the MOS transistor MC11 is connected to the gate end and the drain end of the MOS transistor MC12, and the drain end and the differential signal Vamp- of the MOS transistor MC10, the drain end of the MOS transistor MC11 is connected to the drain end and the differential signal Vamp+ of the MOS transistor MC9, and the gate ends of the MOS transistors MC9 and MOS transistors MC10 are connected to the bias voltage VC3; the source end of the MOS transistor MC9 is connected to the gate end of the MOS transistor MC11, and the gate end of the MOS transistor MC10 is connected to the bias voltage VC4; the source end of the MOS transistor MC9 is connected to the gate end of the MOS transistor MC11, and the gate end of the MOS transistor MC11 is connected to the gate end and the drain end of the MOS transistor MC12, and the drain end and the differential signal Vamp- of the MOS transistor MC10, and the drain end of the MOS transistor MC11 is connected to the drain end and the differential signal Vamp+ of the MOS transistor MC9, and the gate ends of the MOS transistor MC10 are connected to the bias voltage VC3; the source end of the MOS transistor MC9 is connected to the gate end of the MOS transistor MC11. The gate end of the MOS transistor MC3 is connected to the rail-to-rail input differential signal Vin-, the source ends of the MOS transistor MC3 and the MOS transistor MC4 are connected to the grounded 50 times current source I1, the gate end of the MOS transistor MC4 is connected to the rail-to-rail input differential signal Vin+, the drain end of the MOS transistor MC4 is connected to the source end of the MOS transistor MC10 and the drain end of the MOS transistor MC8, and the gate ends of the MOS transistor MC7 and the MOS transistor MC8 are connected to the bias voltage VC2; the source end of the MOS transistor MC7 is connected to the drain end of the MOS transistor MC5 and the resistor RC3, and the gate ends of the MOS transistor MC5 and the MOS transistor MC6 are connected to the bias voltage VC1; the source end of the MOS transistor MC8 is connected to the drain end of the MOS transistor MC6 and the resistor RC4, and the other end of the resistors RC3~RC4, the source ends of the MOS transistors MC5~MC6 and the other end of the 64 times current source I2 are all connected to the power supply end.

3. A low offset rail-to-rail operational amplifier as claimed in claim 2, characterized in that: The MOS transistors MC1 and MC2 form a PMOS complementary differential input pair of transistors, and the MOS transistors MC3 and MC4 form an NMOS complementary differential input pair of transistors.

4. A low offset rail-to-rail operational amplifier as claimed in claim 2, characterized in that: The MOS transistors MC5 - MC10 form two groups of PMOS cascode current mirrors, and the MOS transistors MC11 - MC12 form two groups of NMOS cascode current mirrors.

5. A low offset rail-to-rail operational amplifier as claimed in claim 1, characterized in that: The MOS transistor M1 and the MOS transistor M2 are NMOS differential input pair transistors, and the MOS transistors M3 - M4 and the MOS transistors M9 - M10 form a PMOS current mirror structure.

6. A low offset rail-to-rail operational amplifier as claimed in claim 1, characterized in that: The intermediate module includes: MOS transistors Q13 to Q28; the gate terminals of the MOS transistors Q13 and Q14 are connected to differential signals Vamp+ and Vamp-, respectively; the source terminals of the MOS transistors Q13 and Q14 are connected to a current source I3; the drain terminal of the MOS transistor Q13 is connected to the drain terminals of the MOS transistors Q15 and Q27 and the source terminal of the MOS transistor Q25 and is connected to a node P1; the drain terminal of the MOS transistor Q14 is connected to the drain terminals of the MOS transistors Q16 and Q28 and is connected to a node P2. and the source end of the MOS transistor Q26 and connected to the node P2; the gate ends of the MOS transistor Q16 and the MOS transistor Q15 are respectively connected to the rail-to-rail input differential signals Vin+ and Vin-, and the source ends of the MOS transistor Q16 and the MOS transistor Q15 are connected to the current source I4; the source ends of the MOS transistor Q27 and the MOS transistor Q28 are grounded, and the gate ends of the MOS transistor Q27 and the MOS transistor Q28 are connected to the drain ends of the MOS transistor Q25 and the MOS transistor Q23; the gate ends of the MOS transistor Q25 and the MOS transistor Q26 are connected The bias voltage Vb7 is connected to the gate terminals of the MOS transistors Q23 and Q24, and the source terminals of the MOS transistors Q24 and Q26 are connected to the differential signals OUT+ and OUT-, respectively; the source terminal of the MOS transistor Q23 is connected to the drain terminals of the MOS transistors Q21, Q17 and Q19 and connected to the node N1, and the gate terminals of the MOS transistors Q21 and Q22 are connected to the bias voltage Vb5; the source terminal of the MOS transistor Q24 is connected to the drain terminals of the MOS transistors Q21, Q17 and Q19 and connected to the node N1; the gate terminals of the MOS transistors Q21 and Q22 are connected to the bias voltage Vb5; the source terminal of the MOS transistor Q24 is connected to the drain terminals of the MOS transistors Q21, Q17 and Q19 and connected to the node N1; 22. The drain ends of the MOS transistors Q20 and Q18 are connected to the node N2, the gate ends of the MOS transistors Q19 and Q20 are connected to the bias voltage Vb4, the gate ends of the MOS transistors Q18 and Q17 are respectively connected to the rail-to-rail input differential signals Vin+ and Vin-, and the source ends of the MOS transistors Q17 and Q18 are connected to the grounded current source I5; the other ends of the current source I3 and the current source I4, and the source ends of the MOS transistors Q19 to Q22 are all connected to the power supply end.

7. A low offset rail-to-rail operational amplifier as claimed in claim 6, characterized in that: The MOS transistors Q13 - Q14 and the MOS transistors Q15 - Q16 form two groups of PMOS differential input pair transistors, and the MOS transistors Q17 - Q18 form a group of NMOS differential input pair transistors.

8. A low offset rail-to-rail operational amplifier as claimed in claim 6, characterized in that: The MOS transistors Q21 to Q24 form two groups of PMOS cascode current mirrors, and the MOS transistors Q25 to Q28 form two groups of NMOS cascode current mirrors.

9. A low offset rail-to-rail operational amplifier as claimed in claim 1, characterized in that: The output stage module includes: MOS transistors T1~T18; the source ends of the MOS transistors T1~T2, MOS transistors T13~T14 and one end of the current source I9 are all connected to the power supply end; the gate ends of the MOS transistors T1 and T2 are connected to the bias voltage Vb3, the drain end of the MOS transistor T1 is connected to the source end of the MOS transistor T3 and the node N1, the drain end of the MOS transistor T2 is connected to the source end of the MOS transistor T4, the node N2 and one end of the compensation capacitor Cc2, and the other end of the compensation capacitor Cc2 is connected to the rail The gate terminals of the MOS transistors T3 and T4 are connected to the bias voltage Vb1, the drain terminal of the MOS transistor T4 is connected to the source terminal of the MOS transistor T6, the drain terminal of the MOS transistor T8 and the gate terminal of the MOS transistor T17 and is connected to the differential signal OUT+; the drain terminal of the MOS transistor T6 is connected to the source terminal of the MOS transistor T8, the drain terminal of the MOS transistor T10 and the gate terminal of the MOS transistor T18 and is connected to the differential signal OUT-; the drain terminal of the MOS transistor T3 is connected to the drain terminal of the MOS transistor T9, the drain terminal of the MOS transistor T10 and the gate terminal of the MOS transistor T18 and is connected to the differential signal OUT-. The gate ends of the MOS transistor T11 and the MOS transistor T12, the gate ends of the MOS transistor T9 and the MOS transistor T10 are connected to the bias voltage Vb2; the source end of the MOS transistor T9 is connected to the node P1 and the drain end of the MOS transistor T11, the source ends of the MOS transistors T11, T12, T16 and T18 and one end of the current source I8 are all grounded, the drain end of the MOS transistor T12 is connected to the node P2, the source end of the MOS transistor T10 and one end of the compensation capacitor Cc1, and the other end of the compensation capacitor Cc1 is connected to the ground. The rail-to-rail output signal OUT is connected; the other end of the current source I8 is connected to the gate end of the MOS tube T6, the drain end and the gate end of the MOS tube T14, and the source end of the MOS tube T14 is connected to the drain end and the gate end of the MOS tube T13; the other end of the current source I9 is ​​connected to the gate end of the MOS tube T8, the drain end and the gate end of the MOS tube T15, and the source end of the MOS tube T15 is connected to the drain end and the gate end of the MOS tube T16; the drain ends of the MOS tubes T17 and T18 are connected and connected to the rail-to-rail output signal OUT.

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