A communication synchronization method, device and computer storage medium

Abstract

The application provides a communication synchronization method and device and a computer storage medium, and applies to the technical field of communication. The method comprises the following steps: obtaining N power delay profiles (PDPs) of a target channel in sequence according to a measurement time interval; determining a first clock deviation value according to a target relative time delay of a first PDP among the N PDPs, a target relative time delay of an Nth PDP, and a time interval between the first PDP and the Nth PDP; correcting the relative time delay in each PDP according to the first clock deviation value; and controlling a sending end and a receiving end of the target channel to perform communication synchronization based on the corrected relative time delay. The method corrects the relative time delay in each PDP obtained based on the first clock deviation value calculated in a period of time, so as to obtain an accurate relative time delay, realize communication synchronization of the sending end and the receiving end, and improve the synchronization precision of the communication synchronization method.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a communication synchronization method, device, and computer storage medium. Background Art

[0002] With the development of communication technology, terahertz communication is becoming increasingly widely used. Methods for synchronizing terahertz communication transmission and reception employ a communication synchronization source, which involves introducing two separate communication synchronization sources capable of generating trigger signals at both the transmitting and receiving ends of the communication system. However, the use of two separate communication synchronization sources can introduce synchronization errors, causing the delay at the maximum power point of the power delay profile (PDP) measured in the channel to decay uniformly over time. This results in an offset in the measured relative delay, resulting in low synchronization accuracy for existing terahertz communication synchronization methods. Summary of the Invention

[0003] Embodiments of the present application provide a communication synchronization method, device, and computer storage medium to solve the problem of low synchronization accuracy in existing communication synchronization methods.

[0004] In order to solve the above technical problems, this application is implemented as follows:

[0005] In a first aspect, an embodiment of the present application provides a communication synchronization method. The method includes:

[0006] Obtain N power delay profiles PDP of the target channel in sequence according to the measurement time interval;

[0007] Determine a first clock offset value according to a target relative delay of a first PDP and a target relative delay of an Nth PDP among the N PDPs, and a time interval between the first PDP and the Nth PDP;

[0008] Correcting the relative delay in each of the PDPs according to the first clock offset value;

[0009] Based on the corrected relative delay, the transmitting end and the receiving end of the target channel are controlled to perform communication synchronization, where N is a positive integer greater than or equal to 2.

[0010] Optionally, sequentially acquiring N power delay profiles PDP of the target channel according to the measurement time interval includes:

[0011] Determining a first difference value in sequence according to measurement time intervals, where the first difference value is a difference between the target relative delays of the PDP in every two adjacent time intervals;

[0012] In a case where the number of target first difference values ​​is greater than a preset value, the N PDPs are determined, the target first difference value is a first difference value not equal to zero, and the preset value is determined according to the bandwidth.

[0013] Optionally, the target relative delay of each PDP is the relative delay corresponding to the maximum power in its corresponding PDP.

[0014] Optionally, the target relative delay of each PDP includes m sub-target relative delays, where the m sub-target relative delays are relative delays corresponding to the m target powers in the PDP, and the m target powers are first m powers of all powers in the PDP arranged in descending order;

[0015] Determining a first clock deviation value according to a target relative delay of a first PDP among the N PDPs and the target relative delay of an N-th PDP, and a time interval between the first PDP and the N-th PDP, includes:

[0016] Determining m second clock offset values ​​accordingly according to the m sub-target relative delays of a first PDP among the N PDPs and the m sub-target relative delays of an N-th PDP, and a time interval between the first PDP and the N-th PDP;

[0017] An average value of the m second clock deviation values ​​is determined as the first clock deviation value.

[0018] Optionally, sequentially acquiring N power delay profiles PDP of the target channel according to the measurement time interval includes:

[0019] According to the measurement time interval, cyclic correlation processing is performed on the transmission data of the target channel to obtain the N PDPs.

[0020] Optionally, before sequentially acquiring N power delay profiles PDP of the target channel in measurement time sequence, the method further includes:

[0021] Set the period of the clock synchronization source trigger signal of the target channel.

[0022] In a second aspect, an embodiment of the present application further provides a communication synchronization device. The communication synchronization device includes:

[0023] A first acquisition module is used to sequentially acquire N power delay profiles PDP of the target channel according to a measurement time interval;

[0024] A first determining module is configured to determine a first clock deviation value according to a target relative delay of a first PDP and a target relative delay of an Nth PDP among the N PDPs, and a time interval between the first PDP and the Nth PDP;

[0025] a first correction module, configured to correct the relative delay in each of the PDPs according to the first clock deviation value;

[0026] The first control module is used to control the transmitting end and the receiving end of the target channel to perform communication synchronization based on the corrected relative delay, where N is a positive integer greater than or equal to 2.

[0027] Optionally, the first acquisition module includes:

[0028] A first determining unit is configured to determine, in sequence according to measurement time intervals, a first difference value, where the first difference value is a difference between the target relative delays of the PDPs in every two adjacent time intervals;

[0029] The second determining unit is configured to determine the N PDPs when the number of target first difference values ​​is greater than a preset value, wherein the target first difference value is a first difference value not equal to zero, and the preset value is determined according to the bandwidth.

[0030] Optionally, the target relative delay of each PDP is the relative delay corresponding to the maximum power in its corresponding PDP.

[0031] Optionally, the target relative delay of each PDP includes m sub-target relative delays, where the m sub-target relative delays are relative delays corresponding to the m target powers in the PDP, and the m target powers are first m powers of all powers in the PDP arranged in descending order;

[0032] The first determining module includes:

[0033] a third determining unit, configured to determine m second clock offset values ​​correspondingly according to the m sub-target relative delays of a first PDP among the N PDPs and the m sub-target relative delays of an N-th PDP, and a time interval between the first PDP and the N-th PDP;

[0034] The fourth determining unit is configured to determine an average value of the m second clock deviation values ​​as the first clock deviation value.

[0035] Optionally, the first acquisition module includes:

[0036] The first acquiring unit is configured to perform cyclic correlation processing on the transmission data of the target channel according to a measurement time interval to obtain the N PDPs.

[0037] Optionally, the device further comprises:

[0038] The first setting module is used to set the period of the clock synchronization source trigger signal of the target channel.

[0039] In a third aspect, an embodiment of the present application further provides an electronic device comprising a processor, a memory, and a computer program stored in the memory and executable on the processor, wherein the computer program implements the steps of the above-mentioned communication synchronization method when executed by the processor.

[0040] In a fourth aspect, an embodiment of the present application further provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the above-mentioned communication synchronization method are implemented.

[0041] The communication synchronization method of an embodiment of the present application includes sequentially acquiring N power delay profiles (PDPs) of a target channel according to a measurement time interval; determining a first clock deviation value based on the target relative delay of the first PDP and the target relative delay of the Nth PDP among the N PDPs, as well as the time interval between the first PDP and the Nth PDP; correcting the relative delay in each of the PDPs based on the first clock deviation value; and controlling the transmitting end and the receiving end of the target channel to perform communication synchronization based on the corrected relative delay, where N is a positive integer greater than or equal to 2. The method corrects the relative delay in each acquired PDP based on the calculated first clock deviation value within a period of time, thereby obtaining an accurate relative delay, achieving communication synchronization between the transmitting end and the receiving end, and improving the synchronization accuracy of the communication synchronization method. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments of the present application. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0043] Figure 1 This is one of the PDP schematic diagrams of the communication synchronization method provided in the embodiment of the present application;

[0044] Figure 2 This is one of the overall delay fading graphs of the communication synchronization method provided in the embodiment of the present application;

[0045] Figure 3 This is the second overall delay attenuation diagram of the communication synchronization method provided in an embodiment of the present application;

[0046] Figure 4 This is the second PDP diagram of the communication synchronization method provided in an embodiment of the present application;

[0047] Figure 5 This is a flow chart of the communication synchronization method provided by an embodiment of the present application;

[0048] Figure 6 This is the third PDP diagram of the communication synchronization method provided in an embodiment of the present application;

[0049] Figure 7 This is the third overall delay attenuation diagram of the communication synchronization method provided in an embodiment of the present application;

[0050] Figure 8 is a structural diagram of a communication synchronization device provided by another embodiment of the present application;

[0051] Figure 9 This is a structural diagram of an electronic device provided in another embodiment of the present application. DETAILED DESCRIPTION

[0052] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0053] In existing clock synchronization source-based communication methods, two clock synchronization sources (two in total) are introduced at the transmitting and receiving ends of the communication system to trigger the signal. However, it has been found that the use of two separate clock synchronization sources will result in a certain degree of synchronization error, causing the delay at the maximum power of the power delay profile (PDP) measured by the channel to uniformly decay. Figure 1 The PDP diagram shows the delay of the multipath in the current channel and the power corresponding to the multipath. For a static channel, the delay of the multipath does not change with the length of the measurement time. The multipath with the highest power in the PDP is selected for observation. The peak point of maximum power is shown in the box. The delay corresponding to the peak within a certain period of time is recorded, which is the index on the horizontal axis, and the delay value is plotted according to the observation time to obtain the delay. Figure 2 It can be found that the peak delay decays linearly with time.

[0054] However, by zooming in on the overall fading graph, such as Figure 3 As shown in the figure, it can be seen that the decay rate of the peak delay is constant over a period of time. We use T to represent the time interval during which the peak delay remains constant.S In the case of terahertz communication, the relative time deviation is easily reflected on the PDP due to the large bandwidth, high sampling rate and large time delay resolution of terahertz, resulting in errors. In the case where the receiving end and the sending end are 6m apart, as shown in Figure 4 (a), when the bandwidth is 100MHz and the sampling rate is 100MHz, the time delay resolution is 3m, the corresponding time delay X is 2, and X is 2 in the PDP, and the small time delay attenuation is not enough to be reflected in the PDP; as shown in Figure 4 (b), when the bandwidth is 1GHz and the sampling rate is 1GHz, the time delay resolution is 0.3m, the corresponding time delay X should be 20, but it is shown as 19 in the PDP, and thus an error is shown, so that the relative time delay is not accurate enough. Therefore, in the case of large bandwidth terahertz communication, the embodiment of the present application provides a communication synchronization method. Referring to Figure 5 , Figure 5 FIG. 1 is a flowchart of a communication synchronization method provided by the embodiment of the present application, as shown in Figure 5 FIG. 1, the method comprises the following steps:

[0055] Step 501, N power delay profiles (PDPs) of a target channel are obtained in sequence according to a measurement time interval.

[0056] In this step, the sending end of the target channel sends a pseudo-random sequence or other sequence with good autocorrelation, and the receiving end of the target channel collects data transmitted by the target channel according to the measurement time interval. Each time the data is collected, a cyclic correlation process is performed to obtain a PDP. After the cyclic correlation process is performed on the collected multiple data, N PDPs are obtained.

[0057] Step 502, a first clock deviation value is determined according to a target relative time delay of a first PDP and a target relative time delay of an Nth PDP in the N PDPs, and a time interval between the first PDP and the Nth PDP.

[0058] In this step, the target relative time delay can be the relative time delay corresponding to the maximum power in each PDP. According to the time sequence, the target relative time delay τ1 of the first PDP and the target relative time delay τN of the Nth PDP are obtained. N The difference is calculated, and the average value of the difference is calculated to obtain the first clock deviation value , that is, the average time delay attenuation value in a period of time. For example, 3600 PDPs are obtained, the first PDP is shown in Figure 6 (a), and the target relative time delay τ1 thereof is 958; the 3600th PDP is shown in Figure 6 (b), and the target relative time delay τN thereof is 958. 3600=1007, and τ1=958 and τ 3600 =1007, and the resulting difference is calculated by averaging the number of observations to obtain the first clock deviation value in the 3599 data time intervals.

[0059] Step 503: Correct the relative delay in each of the PDPs according to the first clock offset value.

[0060] In this step, the PDP relative delay measured at the nth moment is taken as the standard relative delay of all PDPs, and the PDP at the mth moment is corrected (note that m here does not have to be less than the observation time T), and the shift amount is τ shift,m = Floor(Δτ·(mn)). The Floor(·) function represents rounding down. This is because the calculated Δτ may not be an integer, and the resolution of the delay is limited by the sampling rate. Its accuracy may deviate from the calculated accuracy of Δτ, so rounding down is required. For example, the 3600th PDP needs to be rounded down. shift,n = Floor (0.0136 (3600-1)) = 49-bit correction, for the 4001st PDP, τ shift,n =Floor(0.0136·(4001-1))=54-bit correction, thereby obtaining the accurate relative delay.

[0061] Step 104: Based on the corrected relative delay, control the transmitting end and the receiving end of the target channel to perform communication synchronization, where N is a positive integer greater than or equal to 2.

[0062] In this step, communication synchronization between the transmitting end and the receiving end is achieved based on the accurate relative delay obtained after correction.

[0063] In the communication synchronization method of the embodiment of the present application, based on the calculated first clock deviation value within a period of time, the relative delay in each PDP obtained is corrected, thereby obtaining an accurate relative delay, achieving communication synchronization between the sending end and the receiving end, and improving the synchronization accuracy of the communication synchronization method.

[0064] Optionally, sequentially acquiring N power delay profiles PDP of the target channel according to the measurement time interval includes:

[0065] Determining a first difference value in sequence according to measurement time intervals, where the first difference value is a difference between the target relative delays of the PDP in every two adjacent time intervals;

[0066] In a case where the number of target first difference values ​​is greater than a preset value, the N PDPs are determined, the target first difference value is a first difference value not equal to zero, and the preset value is determined according to the bandwidth.

[0067] In the communication synchronization method of the embodiment of the present application, a target relative delay set S is defined. n , put the target relative delay of the first n PDPs measured into the set S n , S n ={τ1,τ2,...,τ n}, where τ n Represents the target relative delay of the nth PDP. Through continuous measurement, the set S n Continuously expand the set S n Analysis can obtain T S , T S It is the maximum time period during which the relative delay remains constant.

[0068] First, the set S n With S n+1 The target relative delay in is processed differentially to obtain the differential set, namely D n ={d1,d2,...,d n}={τ2-τ1,τ3-τ2,...,τ n+1 -τ n}, d n =τ n+1 -τ n , record D n The number K of non-zero elements in and the sequence number of non-zero elements. As the measurement time increases, the set S n With S n+1 The number of elements in D is also increasing. n The number of non-zero elements K in the matrix is ​​also increasing. When K=2, the difference between the serial numbers of two non-zero elements is used to obtain the maximum time period T during which the relative delay remains unchanged. S , the results are as follows Figure 7 shown.

[0069] The measurement is continued until the number of target first differences is greater than a preset value, and then the measurement is stopped. The aforementioned target first differences are the non-zero elements in the difference set, and the number of target first differences is the number K of the aforementioned non-zero elements. It should be noted that T s It is inversely proportional to the bandwidth. Assuming that the bandwidths are B1 and B2 respectively, the sampling is X times the bandwidth. The time periods for keeping the relative delay unchanged are T s 1. T s 2, then there exists: Therefore, the setting of the preset value here is related to the bandwidth. For example, when the bandwidth is greater than 50 MHz, the preset value can be set to 10; when the bandwidth is less than 50 MHz, the preset value can be set to 3. When the measurement is stopped, N PDPs can be obtained.

[0070] The communication synchronization method according to the embodiments of the present application determines the number of target first difference values according to the bandwidth, thereby determining the time for stopping obtaining N PDPs, which is beneficial to shorten the time for the whole process of correcting the relative time delay.

[0071] Optionally, the target relative time delay of each PDP is the relative time delay corresponding to the maximum power in the corresponding PDP.

[0072] In the communication synchronization method according to the embodiments of the present application, if the strongest path can be determined, i.e., the paths corresponding to the maximum power of each PDP are the same, the target relative time delay of each PDP is the relative time delay corresponding to the maximum power in the corresponding PDP. Because the path corresponding to the maximum power is the direct path, it will not change basically. The first clock bias value calculated according to the relative time delay corresponding to the maximum power in the PDP can correct other relative time delays in the PDP, which can improve the accuracy of the correction of the relative time delay.

[0073] Optionally, the target relative time delay of each PDP includes m sub-target relative time delays, the m sub-target relative time delays are the relative time delays corresponding to the m target powers in the PDP, and the m target powers are the first m powers in the PDP arranged in descending order.

[0074] The determination of the first clock bias value according to the target relative time delay of the first PDP and the target relative time delay of the Nth PDP in the N PDPs and the time interval between the first PDP and the Nth PDP includes:

[0075] Correspondingly, the determination of the m second clock bias values according to the m sub-target relative time delays of the first PDP and the m sub-target relative time delays of the Nth PDP in the N PDPs and the time interval between the first PDP and the Nth PDP.

[0076] The average of the m second clock bias values is determined as the first clock bias value.

[0077] In the communication synchronization method according to the embodiments of the present application, if the strongest path cannot be determined, i.e., the paths corresponding to the greater powers in each PDP are different. For example, the first three powers arranged in descending order in each PDP can be taken, and the relative time delays corresponding to the first three powers in each PDP are placed in the set The m second clock bias values are determined according to the determination method of the foregoing embodiments. The average of the m second clock bias values is taken and determined as the first clock bias value.

[0078] In the case that the strongest path cannot be determined, the first clock offset value is determined according to the relative time delay corresponding to the first m powers arranged in descending order in each PDP, which is beneficial to improve the accuracy of the subsequent correction of the relative time delay.

[0079] Optionally, the N power-time delay spectrums (PDPs) of the target channel are sequentially obtained according to the measurement time interval, and the method comprises the following steps of:

[0080] The transmission data of the target channel is cyclically correlated according to the measurement time interval, and the N PDPs are obtained.

[0081] In the communication synchronization method, the occurrence end of the target channel sends a pseudo-random sequence or other sequence with good autocorrelation, and the receiving end of the target channel collects the data transmitted by the target channel according to the measurement time interval. Each time the data is collected, a cyclic correlation processing is performed to obtain a PDP. Through the cyclic correlation processing of the collected multiple data, N PDPs are obtained. In the embodiment of the application, the data obtained by each measurement is cyclically correlated to obtain a PDP, which is beneficial to subsequent determination of the target relative time delay in the PDP.

[0082] Optionally, before the N power-time delay spectrums (PDPs) of the target channel are sequentially obtained according to the measurement time sequence, the method further comprises the following steps of:

[0083] The period of the clock synchronization source trigger signal of the target channel is set.

[0084] In the communication synchronization method, some preparatory work needs to be done before the measurement starts. For example, the transmitting end and the receiving end of the terahertz channel measurement system are built. First, the PN code, frequency, power, code rate, modulation mode, filter and local oscillator signal frequency and power of the transmitting radio frequency signal are set. At the same time, the period of the clock synchronization source trigger signal of the transmitting end and the receiving end is set, which is a prerequisite for subsequent collection of relatively synchronized data groups. Exemplarily, the specific steps can be as follows:

[0085] (1) The measurement uses the following modules: spectrum analyzer, vector network analyzer, up-down conversion local oscillator signal generator, amplifier, low noise amplifier, transceiver antenna, clock synchronization source. For the radio frequency signal generator vector signal source in the transmitting end, the signal radio frequency is set to 6GHz, and the power is set to 0dBm. The baseband signal uses a pseudo-random sequence PN9, the code rate is set to 600MHz, BPSK modulation is used, and the raised cosine filter with alpha 1 is used. The frequency of the local oscillator signal in the local oscillator signal source of the transmitting end and the receiving end is set to 21GHz, and the power is set to 10dBm.

[0086] (2) The period of the impulse response sent by the clock synchronization source is set to a common multiple of 1 / 10 MHz of the baseband signal PN code period. The baseband signal period is 511 / 600 MHz. Therefore, the period of the impulse response sent by the clock synchronization source is set to 51.1 μs to ensure that the sampling rate is as fast as possible.

[0087] In the embodiment of the present application, setting the period of the clock synchronization source trigger signal of the target channel is beneficial to the subsequent measurement process.

[0088] See also Figure 8 , Figure 8 This is a structural diagram of a communication synchronization device provided in another embodiment of the present application.

[0089] like Figure 8 As shown, the communication synchronization device 800 includes:

[0090] The first acquisition module 801 is configured to sequentially acquire N power delay profiles PDP of the target channel according to a measurement time interval;

[0091] A first determining module 802 is configured to determine a first clock offset value based on a target relative delay of a first PDP and a target relative delay of an Nth PDP among the N PDPs, and a time interval between the first PDP and the Nth PDP;

[0092] A first correction module 803 is configured to correct the relative delay in each of the PDPs according to the first clock offset value;

[0093] The first control module is used to control the transmitting end and the receiving end of the target channel to perform communication synchronization based on the corrected relative delay, where N is a positive integer greater than or equal to 2.

[0094] Optionally, the first acquisition module includes:

[0095] A first determining unit is configured to determine, in sequence according to measurement time intervals, a first difference value, where the first difference value is a difference between the target relative delays of the PDPs in every two adjacent time intervals;

[0096] The second determining unit is configured to determine the N PDPs when the number of target first difference values ​​is greater than a preset value, wherein the target first difference value is a first difference value not equal to zero, and the preset value is determined according to the bandwidth.

[0097] Optionally, the target relative delay of each PDP is the relative delay corresponding to the maximum power in its corresponding PDP.

[0098] Optionally, the target relative delay of each PDP includes m sub-target relative delays, where the m sub-target relative delays are relative delays corresponding to the m target powers in the PDP, and the m target powers are first m powers of all powers in the PDP arranged in descending order;

[0099] The first determining module includes:

[0100] a third determining unit, configured to determine m second clock offset values ​​correspondingly according to the m sub-target relative delays of a first PDP among the N PDPs and the m sub-target relative delays of an N-th PDP, and a time interval between the first PDP and the N-th PDP;

[0101] The fourth determining unit is configured to determine an average value of the m second clock deviation values ​​as the first clock deviation value.

[0102] Optionally, the first acquisition module includes:

[0103] The first acquiring unit is configured to perform cyclic correlation processing on the transmission data of the target channel according to a measurement time interval to obtain the N PDPs.

[0104] Optionally, the device further comprises:

[0105] The first setting module is used to set the period of the clock synchronization source trigger signal of the target channel.

[0106] See Figure 9 , Figure 9 This is a structural diagram of an electronic device provided in an embodiment of the present application, such as Figure 9 As shown, the electronic device includes: a processor 900, a memory 920, and a program or instruction stored in the memory 920 and executable on the processor 900, the processor 900 is used to read the program or instruction in the memory 920; the electronic device also includes a bus interface and a transceiver 910.

[0107] The transceiver 910 is configured to receive and send data under the control of the processor 900 .

[0108] Among them, Figure 9In the embodiment, the bus architecture may include any number of interconnected buses and bridges, specifically linking together various circuits of one or more processors represented by processor 900 and memory represented by memory 920. The bus architecture may also link together various other circuits such as peripheral devices, voltage regulators, and power management circuits, which are all well known in the art and therefore will not be described further herein. The bus interface provides an interface. The transceiver 910 may be a plurality of components, i.e., a transmitter and a transceiver, providing a unit for communicating with various other devices on a transmission medium. The processor 900 is responsible for managing the bus architecture and general processing, and the memory 920 may store data used by the processor 900 when performing operations.

[0109] The processor 900 is configured to read the program or instruction in the memory 920 and execute the following steps:

[0110] Obtain N power delay profiles PDP of the target channel in sequence according to the measurement time interval;

[0111] Determine a first clock offset value according to a target relative delay of a first PDP and a target relative delay of an Nth PDP among the N PDPs, and a time interval between the first PDP and the Nth PDP;

[0112] Correcting the relative delay in each of the PDPs according to the first clock offset value;

[0113] Based on the corrected relative delay, the transmitting end and the receiving end of the target channel are controlled to perform communication synchronization, where N is a positive integer greater than or equal to 2.

[0114] Optionally, the processor 900 is configured to read a program or instruction in the memory 920 and perform the following steps:

[0115] Determining a first difference value in sequence according to measurement time intervals, where the first difference value is a difference between the target relative delays of the PDP in every two adjacent time intervals;

[0116] In a case where the number of target first difference values ​​is greater than a preset value, the N PDPs are determined, the target first difference value is a first difference value not equal to zero, and the preset value is determined according to the bandwidth.

[0117] Optionally, the target relative delay of each PDP is the relative delay corresponding to the maximum power in its corresponding PDP.

[0118] Optionally, the target relative delay of each PDP includes m sub-target relative delays, where the m sub-target relative delays are relative delays corresponding to the m target powers in the PDP, and the m target powers are first m powers of all powers in the PDP arranged in descending order;

[0119] The processor 900 is configured to read the program or instruction in the memory 920 and execute the following steps:

[0120] Determining m second clock offset values ​​accordingly according to the m sub-target relative delays of a first PDP among the N PDPs and the m sub-target relative delays of an N-th PDP, and a time interval between the first PDP and the N-th PDP;

[0121] An average value of the m second clock deviation values ​​is determined as the first clock deviation value.

[0122] Optionally, the processor 900 is configured to read a program or instruction in the memory 920 and perform the following steps:

[0123] According to the measurement time interval, cyclic correlation processing is performed on the transmission data of the target channel to obtain the N PDPs.

[0124] Optionally, the processor 900 is configured to read a program or instruction in the memory 920 and perform the following steps:

[0125] Set the period of the clock synchronization source trigger signal of the target channel.

[0126] The present application also provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the various processes of the above-mentioned communication synchronization method embodiment are implemented, and the same technical effects are achieved. To avoid repetition, the details are not described here. The computer-readable storage medium is, for example, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0127] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0128] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus the necessary general hardware platform, and of course can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for enabling a terminal (which can be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in each embodiment of the present application.

[0129] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of this application, ordinary technicians in this field can also make many forms without departing from the purpose of this application and the scope of protection of the claims, all of which are within the protection of this application.

Claims

1. A communication synchronization method, characterized in that: The method comprises: Obtain N power delay profiles PDP of the target channel in sequence according to the measurement time interval; Determine a first clock offset value according to a target relative delay of a first PDP and a target relative delay of an Nth PDP among the N PDPs, and a time interval between the first PDP and the Nth PDP; Correcting the relative delay in each of the PDPs according to the first clock offset value; Based on the corrected relative delay, controlling the transmitting end and the receiving end of the target channel to perform communication synchronization, where N is a positive integer greater than or equal to 2; The obtaining, in sequence according to the measurement time interval, N power delay profiles PDP of the target channel includes: Determining a first difference value in sequence according to measurement time intervals, where the first difference value is a difference between the target relative delays of the PDP in every two adjacent time intervals; When the number of target first differences is greater than a preset value, the N PDPs are determined, where the target first difference is a first difference whose value is not equal to zero, the preset value is determined according to the bandwidth, and the target relative delay of each of the PDPs is the relative delay corresponding to the maximum power in its corresponding PDP.

2. The communication synchronization method according to claim 1, characterized in that: The target relative delay of each PDP includes m sub-target relative delays, where the m sub-target relative delays are relative delays corresponding to the m target powers in the PDP, and the m target powers are the first m powers of all powers in the PDP arranged in descending order; Determining a first clock deviation value according to a target relative delay of a first PDP among the N PDPs and the target relative delay of an N-th PDP, and a time interval between the first PDP and the N-th PDP, includes: Determining m second clock offset values ​​accordingly according to the m sub-target relative delays of a first PDP among the N PDPs and the m sub-target relative delays of an N-th PDP, and a time interval between the first PDP and the N-th PDP; An average value of the m second clock deviation values ​​is determined as the first clock deviation value.

3. The communication synchronization method according to claim 1, wherein: The obtaining, in sequence according to the measurement time interval, N power delay profiles PDP of the target channel includes: According to the measurement time interval, cyclic correlation processing is performed on the transmission data of the target channel to obtain the N PDPs.

4. The communication synchronization method according to claim 3, wherein: Before sequentially acquiring N power delay profiles PDP of the target channel in the order of measurement time, the method further includes: Set the period of the clock synchronization source trigger signal of the target channel.

5. A communication synchronization device, characterized in that: The device comprises: A first acquisition module is used to sequentially acquire N power delay profiles PDP of the target channel according to a measurement time interval; A first determining module is configured to determine a first clock offset value according to a target relative delay of a first PDP and the target relative delay of an N-th PDP among the N PDPs, and a time interval between the first PDP and the N-th PDP; a first correction module, configured to correct the relative delay in each of the PDPs according to the first clock deviation value; A first control module is configured to control the transmitting end and the receiving end of the target channel to perform communication synchronization based on the corrected relative delay, where N is a positive integer greater than or equal to 2; The first acquisition module includes: A first determining unit is configured to sequentially determine a plurality of first difference values ​​according to a measurement time interval, wherein the first difference value is a difference between the target relative delays of the PDP in every two adjacent time intervals; The second determining unit is configured to determine the N PDPs when the number of target first differences is greater than a preset value, the target first difference being a first difference whose value is not equal to zero, the preset value being determined according to the bandwidth, and the target relative delay of each of the PDPs being the relative delay corresponding to the maximum power in its corresponding PDP.

6. An electronic device, characterized in that: The method comprises a processor, a memory, and a computer program stored in the memory and executable on the processor, wherein the computer program implements the steps of the communication synchronization method according to any one of claims 1 to 4 when executed by the processor.

7. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, which, when executed by a processor, implements the steps of the communication synchronization method according to any one of claims 1 to 4.

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